CN119201803A - A single-channel multi-data source transmission system and method based on SRIO - Google Patents
A single-channel multi-data source transmission system and method based on SRIO Download PDFInfo
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- G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
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- G06F13/4282—Bus transfer protocol, e.g. handshake; Synchronisation on a serial bus, e.g. I2C bus, SPI bus
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Abstract
一种基于SRIO的单通道多数据源传输系统及方法，属于数据传输技术领域，包括FPGA子系统和DSP子系统；FPGA子系统包括FPGA预处理模块、SRIO发送模块、SRIO复位模块和SRIO接收模块；DSP子系统包括DSP接收模块、DSP发送驱动层、DSP发送接口层、DSP发送应用层和EMIF设置模块；通过SRIO发送模块，将前级多个通道的FPGA数据预处理模块封装好的SRIO包，进行排序发送即可。SRIO进行无应答传输，相对于现有技术中对于短包数据的处理，大大提高了传输效率和实时性；加入片循环操作，对比之前单缓存或者乒乓操作，增加了存储空间，前级传输无需等待后级的处理反馈时间，直接进行大批量连续存储，这种连续存储解决了等待的延时问题。
A single-channel multi-data source transmission system and method based on SRIO, belonging to the field of data transmission technology, includes an FPGA subsystem and a DSP subsystem; the FPGA subsystem includes an FPGA preprocessing module, an SRIO sending module, an SRIO reset module and an SRIO receiving module; the DSP subsystem includes a DSP receiving module, a DSP sending driver layer, a DSP sending interface layer, a DSP sending application layer and an EMIF setting module; through the SRIO sending module, the SRIO packets encapsulated by the FPGA data preprocessing module of the previous multiple channels can be sorted and sent. SRIO performs non-response transmission, which greatly improves the transmission efficiency and real-time performance compared with the processing of short packet data in the prior art; adding a slice loop operation, compared with the previous single cache or ping-pong operation, increases the storage space, and the previous stage transmission does not need to wait for the processing feedback time of the subsequent stage, and directly performs large-scale continuous storage, which solves the waiting delay problem.
Description
Technical Field
The invention belongs to the technical field of data transmission, and particularly relates to a single-channel multi-data-source transmission system and method based on SRIO.
Background
The existing data processing system is usually developed by using an embedded platform, a DSP and an FPGA are made into a PCB, the DSP processes and processes the total data message, the FPGA expands a hardware interface, the DSP and an internal communication core of the FPGA use SRIO (Serial Rapid IP) and EMIF (External Memory Interface) external memories, SRIO is a high-speed serial communication interface protocol, the topology structure is simple and flexible and changeable, serial hardware buses are few, and the embedded high-speed serial communication system is an embedded high-reliability high-performance packet-switching-based high-speed interconnection technology. EMIF is a common parallel communication connection mode between a DSP chip and an FPGA, has excellent performance and great convenience and flexibility.
In the existing data transmission system, an interface data transmission mode with uncertain time length such as serial port and spi is commonly adopted, and an SRIO (serial input output) is adopted for large-batch continuous data transmission, so that the problems of low EMIF rate and poor timeliness exist, or an SRIO mode is adopted for transmitting data packets with a stream mode of less than or equal to 256 bytes, so that the utilization of SRIO bandwidth is low, and the overall transmission efficiency of data is influenced.
Disclosure of Invention
The invention aims to solve the problems of the data transmission using different interfaces and different formats, the rapid and efficient data transmission using SRIO uniformly, the problem of rapid and continuous mass storage of short packets by adding a slice circulation polling mode, and the delay waiting in the transmission process is shortened synchronously.
In a first aspect, the invention provides an SRIO-based single-channel multi-data-source transmission system, which comprises an FPGA subsystem and a DSP subsystem;
The FPGA subsystem comprises an interface channel module, an FPGA preprocessing module, an SRIO sending module, an EMIF state module, an SRIO reset module and an SRIO receiving module;
The system comprises an interface channel module, an FPGA preprocessing module, an SRIO sending module, an EMIF state module, an SRIO reset module, an SRIO receiving module and a data storage module, wherein the interface channel module is used for externally connecting hardware of a plurality of interfaces, the FPGA preprocessing module is used for preprocessing data from an external interface, the SRIO sending module is used for sending a data packet and a doorbell packet, the EMIF state module is used for storing the latest state result of a current interface channel, the SRIO reset module is used for resetting when an SRIO link is initialized or abnormal, and the SRIO receiving module is used for receiving an SRIO data packet;
the DSP subsystem comprises a DSP receiving module, a DSP doorbell module, a DSP sending driving layer, a DSP sending interface layer, a DSP sending application layer and an EMIF setting module;
The DSP receiving module is used for receiving and writing data into a memory of the DSP, the DSP doorbell module is used for identifying an interrupt source of doorbell interrupt, the DSP sending application layer is used for processing data to be sent by each interface, the DSP sending interface layer is used for starting the DSP sending driving layer to send SRIO packets in batches according to data quantity time-sharing and sub-packaging, the EMIF setting module is provided with storage performance and is used for making SRIO protocol conventions and setting a slice circulation address, a slice circulation size, a slice circulation number, a data length of doorbell interrupt and the number of data packets of doorbell interrupt of each channel.
Furthermore, according to the SRIO-based single-channel multi-data-source transmission system, the interface channel module receives data or transmits the data according to sampling clocks of all interfaces, the number of receiving interfaces is 64 at most, the number of transmitting interfaces is 2×32 at most, and the sum of interface bandwidths is smaller than or equal to the SRIO bandwidth.
Further, in the single-channel multi-data-source transmission system based on SRIO, when the FPGA preprocessing module performs data preprocessing, packaging data is performed according to the SRIO protocol of the EMIF setting module and internal chip circulation, the packaging data comprises a packet header, a packet and a doorbell packet, and the data packet after packaging is transmitted to the SRIO transmitting module.
In the SRIO-based single-channel multi-data-source transmission system, when the SRIO reset module resets, the counting, FIFO and status words related to the SRIO in the FPGA are cleared and reset, the FPGA subsystem detects the link state of the SRIO in real time, and when the link or port is abnormal, the FPGA subsystem notifies the DSP subsystem through the EMIF state module to reset and reconnect.
In the SRIO-based single-channel multi-data-source transmission system, the DSP doorbell module identifies the interrupt source of doorbell interrupt, and uses DoorBell interrupt to inform the DSP subsystem, after the DSP subsystem enters the doorbell interrupt, firstly searches which interface channel is the interrupt according to DoorBell doorbell interrupt, and then identifies the address area of piece cyclic polling and the effective byte length of each piece of address area through the EMIF state module.
Furthermore, in the SRIO-based single-channel multi-data-source transmission system, after the FPGA preprocessing module finishes packaging the data and before the SRIO sending module sends the doorbell packet, the FPGA subsystem updates the latest state result of the current interface channel and stores the latest state result through the EMIF state module, so that the state result query is conveniently carried out after the doorbell is interrupted by the DSP, the chip cyclic polling result is identified, and the data is completely accessed.
In a second aspect, the present invention provides a transmission method of the SRIO-based single channel multi-data source transmission system according to the first aspect, including a data uplink process and a data downlink process;
The data uplink process comprises the steps that an FPGA subsystem receives data from hardware of a plurality of interfaces, performs data preprocessing through an FPGA preprocessing module, processes and packages the data of each interface channel according to a preset doorbell interrupt protocol and a slice cycle protocol, then sends data packets and doorbell packets to a DSP subsystem through an SRIO sending module, sends the previous-stage multipath data to the DSP through an SRIO channel, and performs data caching through DDR3 of the DSP;
After receiving doorbell interruption, the SRIO bottom layer of the DSP verifies the current interruption source identification channel a priori, then inquires an EMIF state module of the channel, inquires the first address of the current interruption piece circulation and the first address of the last piece circulation of the current channel, and the interfaces with short packet complements can simultaneously identify the number of bytes of effective data of each piece address, then extracts the effective data between the two interruption times, and subsequently carries out application layer processing;
The data downlink process comprises the steps of carrying out time-sharing batch transmission when the DSP subsystem transmits data, packaging according to a contracted interface channel protocol, identifying packet head address information in the packaging by the FPGA subsystem, judging which interface channel is the data, extracting the data, and directly putting the data into a corresponding interface FIFO according to the sequence of receiving the packaging for external transmission.
Because the transmission speed of the SRIO is far greater than the speed of the external interface, only the protocol for data transmission is required to be agreed, and priority processing is not required. The downlink time sequence of the data is actively controlled by the DSP. Only the data transmission is considered to be not too fast, so that the quantity of FIFO buffers of the FPGA is exceeded, and the data is lost. Meanwhile, because the FPGAs are parallel, doorbell interruption does not need to be sent to the FPGAs, and the problem of real-time response of the FPGAs does not need to be considered. Meanwhile, the doorbell is not limited, so that the number of data channels sent to the FPGA by the DSP is far more than 64, and 2×16 channel data can be achieved.
Furthermore, according to the SRIO-based single-channel multi-data-source transmission method, the doorbell interrupt protocol agrees with the interrupt data quantity of each channel, one channel data quantity sent by the FPGA reaches one, two or more packets, one doorbell interrupt notification DSP needs to be sent (how many packets of DSPs are set to the FPGA according to the hardware interface characteristics), the packet header address protocol in one doorbell is accumulated according to the chip cycle first address at the time, and the next doorbell needs to be accumulated with a new chip cycle first address.
Furthermore, the single-channel multi-data source transmission method based on SRIO is characterized in that the slice circulation protocol agrees with how many times of doorbell interruption and the single-time doorbell interruption data length are stored continuously in one channel, new data need to deviate from a header address according to the slice circulation protocol after one doorbell is sent, continuous arrangement of data areas can be guaranteed according to the length of the doorbell, meanwhile, after the DSP is closed and interrupted and is opened again, the DSP inquires a state register value of FPGA slice circulation through an EMIF state module, an interval area of two times of interruption is detected, cache data in DDR3 can be completely identified, and the doorbell interruption protocol and the slice circulation protocol are restrained by changing EMIF communication between the DSP and the FPGA. The DSP can conveniently read the data in the middle after actively closing the interrupt.
Furthermore, the single-channel multi-data source transmission method based on SRIO is characterized in that when short packet data is processed according to a slice circulation protocol, the FPGA needs to conduct data packet breaking processing on discontinuous short packet type data, broken packets are judged according to time, data with inconsistent lengths are processed in a complement or subpackaging or doorbell breaking mode, and continuous data wait to meet 256 bytes and are packaged into SWRITE packets. The method for supplementing the number is that when a single data packet is < =256 bytes, fixed data 0x80 is supplemented to 256 bytes, the specific number of bytes is updated through a state register of an EMIF, the packetizing mode is that when single packet data is >256 bytes, the number of the single packet data is still supplemented to 256 bytes according to 256 bytes when the last packet is insufficient to 256 bytes, the doorbell is set according to the requirement of a hardware interface, a doorbell interrupt is set according to one packet for a short packet data interface, after the packetizing or supplementing the number, the doorbell interrupt of each interface is set separately, a doorbell is sent after the multi-packet data for a large number of continuous data interfaces, such as a serial port is set with one doorbell packet after the single packet data, and a doorbell, such as a video, a picture and a doorbell interrupt can be added for the large number of continuous data.
According to the SRIO-based single-channel multi-data-source transmission system and the SRIO-based single-channel multi-data-source transmission method, SRIO packets packaged by the FPGA data preprocessing modules of the front-stage multiple channels are sequenced and sent out through the SRIO sending module. Compared with the prior art for processing short packet data, the SRIO processing method greatly improves the transmission efficiency and the real-time performance, adds the slice circulation operation, increases the storage space compared with the prior single buffer or ping-pong operation, does not need to wait for the processing feedback time of the later stage in the former stage transmission, directly carries out mass continuous storage, and solves the waiting delay problem in the continuous storage.
Drawings
FIG. 1 is a schematic diagram of a single channel multi-data source transmission system based on SRIO according to an embodiment of the present invention;
FIG. 2 is a communication flow chart of a single channel multi-data source transmission system based on SRIO according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of a data uplink process according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of a data downlink process according to an embodiment of the present invention;
fig. 5 is a schematic diagram of a transmission flow of a single-channel piece circulation doorbell according to an embodiment of the present invention;
fig. 6 is a schematic diagram of an SRIO doorbell header protocol of the DSP according to an embodiment of the present invention;
Fig. 7 is a schematic diagram of an SRIO doorbell header protocol of the DSP according to an embodiment of the present invention.
Detailed Description
The single-channel multi-data source transmission system and method based on SRIO of the invention are described in detail below through the drawings and the embodiments.
Example 1
The embodiment discloses a single-channel multi-data-source transmission system based on SRIO, which comprises an FPGA subsystem and a DSP subsystem, wherein the FPGA subsystem comprises an interface channel module, an FPGA preprocessing module, an SRIO transmitting module, an EMIF state module, an SRIO resetting module and an SRIO receiving module, and the DSP subsystem comprises a DSP receiving module, a DSP doorbell module, a DSP transmitting driving layer, a DSP transmitting interface layer, a DSP transmitting application layer and an EMIF setting module.
In the disclosed embodiment, a 4x SRIO and an EMIF16 interface are connected between the FPGA subsystem and the DSP subsystem. An EMIF16 interface is used, the memory characteristic of the EMIF is considered, the protocol convention of SRIO is carried out by using the EMIF, and the chip circulation address, the chip circulation times and the doorbell interrupt data length of each channel can be flexibly configured. The FPGA feeds back real-time status via the EMIF16 in real-time. The SRIO only carries out transmission of stream mode and doorbell interrupt, and the actual use of the SRIO can simultaneously reach the bandwidth speed of 1.1 GB/s.
The interface channel module is connected with the hardware of a plurality of external interfaces and is used for inputting and outputting system communication data. The interface channel module receives data in or sends data out according to the sampling clock of each interface. Up to 64 receiving interfaces, up to 2×32 transmitting interfaces, and the sum of the interface bandwidths is less than or equal to the SRIO bandwidth. When the number of the interface data reaches a certain value or a certain time condition, the preprocessing module starts processing.
The FPGA preprocessing module is used for processing data from an external interface, and packaging the data of the interface according to the SRIO protocol of the EMIF setting module and the internal chip cycle counting result. The packed data mainly comprises a packet header, a packet header and a doorbell packet. And transmitting the data packet after the packaging is completed to an SRIO transmitting module.
After the packing of the FPGA and the processing module is completed, the latest state result of the current interface channel is updated by the FPGA before the doorbell packet is sent by the SRIO sending module of the FPGA, so that the state result inquiry is conveniently carried out after the doorbell is interrupted by the DSP, the chip circulation result is identified, and the data is completely accessed.
The SRIO reset module is used for carrying out reset when the SRIO link is initialized or abnormal, and the reset can clear and reset the count, FIFO, status word and the like of the SRIO in the FPGA. The FPGA can detect the link state of the SRIO in real time, and when the link or port is abnormal, the FPGA informs the DSP through the EMIF16 to carry out reset reconnection.
The DSP receiving module, the DSP receiving is simple, the SRIO bottom layer judges the protocol packet type according to the packet head, as shown in fig. 6 and 7, the stream mode packet carrying the data word, and the DMA is used for writing the data into the memory of the DSP according to the DSP memory address agreed by the packet head and the data length of the packet.
And the DSP doorbell module is used for identifying an interrupt source of doorbell interrupt and informing the DSP by using DoorBell interrupt in order that the DSP can rapidly process data in real time. After entering the doorbell interrupt, the DSP searches for which interface channel is the interrupt according to the DoorBell doorbell interrupt, and then identifies the address area of the slice cyclic poll and the valid byte length of each slice address area through the EMIF16 status module.
The three modules are used for the DSP to send data to the FPGA. The DSP transmitting application layer processes the data to be transmitted by each interface, and the DSP transmitting interface layer starts the DSP transmitting driving layer to transmit the SRIO packets according to the time-sharing batch subpackaging of the data quantity. And the SRIO receiving module of the FPGA receives the data packet of the SRIO and distributes the data packet to each sending interface module according to a packet header protocol, and each interface sequentially sends out the data.
Considering a storage performance of EMIF, using EMIF interface to make SRIO protocol convention, EMIF setting module flexibly and conveniently sets slice circulation address, slice circulation size, slice circulation times, data length of doorbell interrupt, number of data packets of doorbell interrupt, etc. of SRIO of each channel.
In the embodiment of the disclosure, the internal communication core of the DSP and the FPGA uses the SRIO and the EMIF external memory, and the SRIO protocol agreement between the DSP and the FPGA and the feedback of the status result of the chip circulation are very convenient through the EMIF interface. The system has the assistance of EMIF, and the link of SRIO only transmits the data packet in the streaming mode and the doorbell packet without data, thereby greatly improving the transmission efficiency of SRIO.
The transmission of the SRIO mainly comprises two transmission types of IO and Message, under the two transmission types, a plurality of protocol packet formats are provided, and based on the use requirement of a system, the technical scheme only applies two types of SWRITE packets (stream mode) and DOORBELL packets (doorbell interrupt packet). The streaming mode is used for data transmission and the doorbell is used for informing an interrupt.
SWRITE packets, which specify that the protocol packet consists of a 64bit packet header and 1 to 256 bytes of data, the packet header carries an ID, packet mode, packet data length, receiver destination address. The receiving party analyzes the packet header and transmits the data with the corresponding length in the packet to the designated address. In this embodiment, the length of data carried by SWRITE is 256 bytes, so that the service efficiency of SRIO is very high.
DOORBELL packets, a 64bit packet header carries a data protocol, wherein a16 bit info section carries an interrupt message, and the DSP can receive at most 64 DOORBELL doorbell interrupts. With these 64 interrupts, the interrupt source can be identified. After the data is sent by using the streaming mode, the FPGA sends DOORBELL interrupt to the DSP to inform the DSP that the data is completed, and the subsequent processing is timely carried out.
The system is externally connected with data from multiple interfaces, the FPGA is a parallel processor, and the FPGA receives and transmits data from different clock domains, different data lengths, different data bit degrees and different time periods in real time. And continuously storing the data in the memory of the DSP through a 4xSRIO interface, and notifying the DSP through SRIO doorbell interrupt when a certain number or time is reached, and carrying out data processing by the DSP.
Example two
Based on the SRIO-based single-channel multi-data-source transmission system disclosed in the first embodiment, the present embodiment discloses an SRIO-based single-channel multi-data-source transmission method, as shown in fig. 1, 3 and 4, two bidirectional communication interfaces, a parallel EMIF16 interface, a high-speed serial 4x SRIO interface, and an EMIF interface performs SRIO protocol constraint, are connected between two subsystems FPGA and DSP subsystem. The memory of the DSP is expanded by 2GB DDR3, and data caching can be performed in a large batch.
There are two directions for data transmission, namely data downlink (the DSP sends to the FPGA) and data uplink (the FPGA sends to the DSP). Due to the difference between the two processors, there is a slight difference between the schemes used for data uplink and data downlink. The specific data transmission process is as follows:
Data uplink:
The data comes in from the external hardware interface of the FPGA and reaches the dual-port RAM of the external interface of the FPGA, and the FPGA preprocessing module performs data preprocessing and uses the DSP to perform expansion caching. Because the FPGA code is compiled once to take effect once, the number of FIFOs per channel of the FPGA is limited. Preprocessing data of each channel, processing and packaging according to a set doorbell interrupt protocol and a slice cycle protocol, then sending the data, entering a memory DDR3 of the DSP, and caching the data by the DDR3 of the DSP to realize the function of expanding cache. The doorbell interrupt protocol agrees with the interrupt data quantity of each channel, one channel data quantity sent by the FPGA reaches one packet, two packets or multiple packets, a doorbell interrupt notification DSP needs to be sent once (how many packets of DSP are set to the FPGA according to the hardware interface characteristics), the packet header address protocol in one doorbell is accumulated according to the chip cycle head address at this time, and the next doorbell needs to be accumulated with a new chip cycle head address.
The slice circulation protocol agrees that a channel continuously stores the data length of the doorbell interrupt for more than one time and the single doorbell interrupt, and after the doorbell is sent once, new data needs to offset the header address according to the slice circulation protocol, so that the data areas are ensured to be continuous and can be continuously arranged according to the length of the doorbell. Meanwhile, the application of the DSP has the requirement of closing the interrupt, after the DSP is closed and the interrupt is opened again, the DSP queries the state register value of the circulating poll of the FPGA chip through the EMIF state module, detects the interval area of the two interrupts, and can completely identify the cache data in the DDR 3. The doorbell interrupt protocol and the slice loop protocol are constrained by the EMIF communication between the DSP and the FPGA. The DSP can conveniently read the data in the middle after actively closing the interrupt.
The short packet data needs special treatment in the chip circulation polling processing, and the FPGA has a data packet breaking function for discontinuous short packet type data such as serial ports, SPI and the like, judges the broken packet according to time, and considers the broken packet as one packet of data after the specific proportion time such as the baud rate is exceeded. Because the data lengths of serial ports and the like are inconsistent, the real-time performance of the system is considered, and operation processing modes such as complement, subcontracting, doorbell interruption and the like can exist. The complement is not needed for continuous image, AD and other data, and only the package SWRITE of the 256-byte packaging process is waited to be met.
The complement processing mode is that in the data single packet < = 256 bytes, the complement fixed data 0x80 is complemented to 256 bytes, and the specific byte number is updated through the state register of the EMIF. The packetization is performed in such a way that, in case of single packet data >256 bytes, it is necessary to packetize the data in 256 bytes, and if the last packet is not 256 enough, it is still padded to 256 bytes. The doorbell interrupt processing mode is that the doorbell is set according to the requirement of a hardware interface, and the doorbell interrupt is set according to one packet for a short packet data interface, and after the packet is divided or complemented, the short packet interface needs to be added with a doorbell interrupt. The doorbell interrupt for each interface is separate. For a large number of consecutive data interfaces, a doorbell is sent after multiple packets of data. For example, a serial port is provided with a single-packet data primary doorbell, so that a doorbell packet needs to be added behind the single-packet data. For large volumes or continuous data, one more doorbell, such as a video, one picture with one doorbell break, may be wrapped.
After being packaged by a chip circulation protocol of the preprocessing module, the chip circulation protocol enters a post-stage FPGA sending module, the module mainly sends the multi-path data of the front stage to the DSP through an SRIO channel, and the speed of the module is far greater than the packaging speed of the preprocessing module of the front stage. When there are two or more paths of data to be transmitted, the data packets are sequentially transmitted according to the channel number. The method is directly cached to the internal memory of the DSP, the redundant caching of the FPGA is not needed, and the FPGA only processes the package in real time and actively uploads the package. And the SRIO sending module sends out the data packet and the doorbell packet.
After receiving the data, the SRIO bottom layer of the DSP starts the DMA to carry out data movement, and stores the data into the corresponding memory area of the DSP one by one according to the address and the length of the SRIO packet header protocol. After receiving doorbell interruption, the current interruption source identification channel is verified a priori, then an EMIF state module of the channel is queried, the first address of the current interruption piece circulation and the first address of the last piece circulation of the current channel are queried, the interfaces with short packet complements can simultaneously identify the number of bytes of effective data of each piece address, then effective data between two interruption is extracted, and application layer processing is performed subsequently.
And (3) data downlink:
The data downlink is simpler, the FPGA decodes the SRIO serial stream mode data of the DSP by the packet header protocol, distributes the decoded data to the respective channel FIFO and sends the decoded data to the hardware interface. Because the transmission speed of the SRIO is far greater than the speed of the external interface, only the protocol of data transmission is agreed, and priority processing is not needed. The downlink time sequence of the data is actively controlled by the DSP. Only the data transmission is considered to be not too fast, so that the quantity of FIFO buffers of the FPGA is exceeded, and the data is lost. Meanwhile, because the FPGAs are parallel, doorbell interruption does not need to be sent to the FPGAs, and the problem of real-time response of the FPGAs does not need to be considered. Meanwhile, the doorbell is not limited, so that the number of data channels sent to the FPGA by the DSP is far more than 64, and 2×16 channel data can be achieved from theoretical design (only 39 are used in an actual system).
When the DSP transmits data, time constraint is carried out, and data exceeding the FIFO buffer quantity can not be transmitted to the interface within the time limited by the hardware interface, so that the DSP interface layer carries out time-sharing batch transmission. According to the agreed interface channel protocol package, mainly the address information of the package head, the FPGA identifies the address information of the package head, judges which interface channel is the data of which interface channel, extracts the data, and according to the sequence of the package, directly puts the data into the corresponding interface FIFO for external transmission.
In the embodiment of the disclosure, an EMIF16 interface is used, and an SRIO module is combined to provide double guarantee for communication of the system, and the FPGA monitors link and port link states of the SRIO link in real time, and notifies the DSP to perform SRIO reset reconnection when abnormal, so that transmission of the system is more stable and reliable. In the initialization process, the EMIF is used for carrying out protocol constraint of SRIO between the DSP and the FPGA, for example, the initial address of a first picture of a video in a format of a protocol convention SDI (1920 x 1080 x 2 byte) is 0x90000000, the doorbell interrupt packet number of the convention SDI is 1920 x 1080 x 2/256=16200, and the number of the convention slice cycle polling times is 50. The practical effect is that SDI video data are continuously arranged according to the data byte stream of video frames, when one picture is transmitted, the FPGA adds a doorbell interrupt to inform the DSP that one picture is completely reached, and 50 pieces of video data are continuously stored. And waiting for 50 pieces of storage to be full, returning to the address of 0x90000000 for continuous storage, storing 50 pieces of storage, and continuously returning to the address of 0x90000000 for continuous caching. The EMIF state update is mainly to update the first address of the doorbell interrupt and inform the DSP where the first address of the picture is. If the data is short packet data such as serial port, the DSP is informed of the effective byte number of the data, because the serial port short packet has the complement operation, the DSP is informed of the effective byte number of the packet through EMIF.
Based on the communication example of SRIO multichannel control between the DSP and the FPGA, data are segmented according to the largest SRIO data packet, a slice circulation polling mode is added, and a doorbell is added to interrupt operation. The operation of the broken package and the doorbell+256 bytes SWRITE package of the interface module greatly improves the real-time performance of the system transmission and transmission processing data, and can completely process the communication requirement in time by the broken package and the doorbell operation in consideration of the fact that the DSP can not always process the data. As shown in the flowcharts of fig. 2 and 5, through the slice circulation polling mode, the data control flow of the FPGA has no DSP participation, so that the work of the FPGA is greatly simplified, the feedback problem is not required to be considered when the FPGA is in data uplink, the FPGA only needs to consider that the received data packet is sent, and a large amount of cache data is executed by the DSP memory.
The receiving of the DSP is also independent of the DSP program flow, and is automatically executed by an SRIO module and a DMA module, a slice circulation protocol and a channel protocol attached to the SRIO are adopted, the SRIO bottom layer moves the data of SWRITE packets to the memory area by using the DMA according to the 32-bit address in the packet header and the length information of 8 bits in the packet header, and the DMA is a high-speed access peripheral, so that the program flow control of the DSP is not required for moving the data. For the serial CPU such as the DSP, the serial CPU can be completed without occupying program time, and a great amount of time is saved.
When the DSP sends data to the FPGA, the sending protocol is well regulated when the SRIO protocol is initialized, the FPGA extracts address information corresponding to the packet header protocol, identifies which channel is the data of which channel, extracts the data and forwards the data to the corresponding interface channel.
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