CN119170083B

CN119170083B - A test circuit and memory

Info

Publication number: CN119170083B
Application number: CN202310706738.9A
Authority: CN
Inventors: 庄勇; 孙凯
Original assignee: Changxin Memory Technologies Inc
Current assignee: Changxin Memory Technologies Inc
Priority date: 2023-06-13
Filing date: 2023-06-13
Publication date: 2025-10-03
Anticipated expiration: 2043-06-13
Also published as: CN119170083A

Abstract

The disclosure provides a test circuit and a memory, wherein the test circuit comprises a first control module, a state decoding module and a second control module, the first control module generates and outputs a parity indication signal, a turnover indication signal and a topology indication signal based on address jump pulses, the state decoding module counts and decodes the topology indication signal to obtain an intermediate decoding signal, and the second control module generates and outputs a first state signal and a second state signal based on the parity indication signal, the turnover indication signal and the intermediate decoding signal.

Description

Test circuit and memory

Technical Field

The disclosure relates to the technical field of semiconductor memories, and in particular relates to a test circuit and a memory.

Background

Dynamic random access memory (Dynamic Random Access Memory, DRAM) is widely used in various electronic products as a semiconductor memory, particularly, the 5th generation DDR (5th Double Data Rate,DDR5) because of its high performance and low cost. The most commonly used test method for the Memory is a Memory built-in self test (Memory Build IN SELF TEST, MBIST) method, an MBIST circuit aims at the Memory, a test circuit of the Memory is automatically generated, and certain defects in the Memory are detected by executing a specific test algorithm.

Disclosure of Invention

The present disclosure provides a test circuit and a memory.

The technical scheme of the present disclosure is realized as follows:

in a first aspect, an embodiment of the present disclosure provides a test circuit for performing a read-write test on a storage array using a plurality of preset data topologies, the test circuit comprising:

the first control module is configured to generate and output a parity indication signal, a turnover indication signal and a topology indication signal based on the received address jump pulse, wherein the address jump pulse indicates that the count value of the row address of the executed target operation reaches an even highest order or an odd highest order, and the target operation is a read operation or a write operation;

the state decoding module is connected with the first control module and is configured to count and decode the topology indication signal to obtain an intermediate decoding signal;

the second control module is connected with the first control module and the state decoding module and is configured to generate and output a first state signal and a second state signal based on the parity indication signal, the turnover indication signal and the intermediate decoding signal;

the first status signal is used for selecting one of a first data sequence and a second data sequence as a target data sequence, the second status signal indicates whether each data of the target data sequence is overturned, and the target data sequence or the overturned target data sequence is used for forming the preset data topology.

In some embodiments, the preset data topologies have a set a, each set of the preset data topologies comprising a first data topology and a second data topology, each of the first data topology and the second data topology comprising an odd data topology and an even data topology;

the odd-even indication signal indicates that the row address of the storage unit corresponding to the target operation is an odd row address or an even row address, and generates the corresponding odd data topology or even data topology;

The topology indication signal indicates a group number of the preset data topology corresponding to the target operation, and the flip indication signal indicates the first data topology or the second data topology corresponding to the target operation.

In some embodiments, the first control module is further configured to generate and output a read-write indication signal based on receiving the address jump pulse, wherein the read-write indication signal indicates a read operation or a write operation.

In some embodiments, the test circuit further comprises a test module;

the test module is connected with the first control module and the second control module and is configured to receive the read-write indication signal, the first state signal and the second state signal, write the corresponding preset data topology into the storage array based on the first state signal and the second state signal when the read-write indication signal indicates a write operation, or read the data of the storage array when the read-write indication signal indicates a read operation, and compare the read data based on the first state signal and the second state signal.

In some embodiments, the first control module is specifically configured to control the level state of the parity indicator signal to flip once every 1 address jump pulse is received, control the level state of the read-write indicator signal to flip once every 2 address jump pulses are received, control the level state of the flip indicator signal to flip once every 4 address jump pulses are received, and generate 1 topology indicator signal every 8 address jump pulses are received.

In some embodiments, the first control module comprises:

A first signal unit configured to sample an inverted signal of the parity indication signal using the address jump pulse, generating a new parity indication signal;

The second signal unit is connected with the first signal unit and is configured to logically process the parity indication signal and the read-write indication signal to generate a first intermediate signal, and sample the first intermediate signal based on the address jump pulse to generate a new read-write indication signal;

the third signal unit is connected with the second signal unit and is configured to logically process the parity indication signal, the read-write indication signal and the turning indication signal to generate a second intermediate signal, and sample the second intermediate signal based on the address jump pulse to generate a new turning indication signal;

The fourth signal unit is connected with the third signal unit and is configured to logically process the parity indication signal, the read-write indication signal and the turnover indication signal to obtain a third intermediate signal, and the topology indication signal is generated based on the third intermediate signal, the address jump pulse and a preset system clock signal.

In some embodiments, the state coding module includes a counting unit and C coding units, the number of the intermediate coding signals being C;

The counting unit is connected with the first control module and is configured to count the pulses of the topology indication signal to generate a first count value;

The j-th decoding unit is connected with the counting unit and is configured to control the j-th intermediate decoding signal to be in a first state when the first count value accords with the j-th decoding condition, and control the j-th intermediate decoding signal to be in a second state when the first count value does not accord with the j-th decoding condition, wherein j is an integer which is more than or equal to 1 and less than or equal to C, C is less than or equal to A, the first count value comprises a B-bit subparameter, and 2B is more than or equal to A.

In some embodiments, the second control module comprises:

the first logic unit is configured to perform logic processing on the C intermediate decoding signals and output a first state even signal, a first state odd signal, a second state even signal and a second state odd signal;

A second logic unit configured to output one of the first state even signal and the first state odd signal as a first pre-selected signal based on the parity indication signal, and to output one of the second state even signal and the second state odd signal as a second pre-selected signal based on the parity indication signal;

And outputting one of the second pre-selected signal and an inverted signal of the second pre-selected signal as the second state signal based on the flip instruction signal.

In some embodiments, the first logic unit includes:

The preprocessing unit is configured to perform logic processing on the C intermediate decoding signals and output a first selection even signal, a first selection odd signal, a second selection even signal and a second selection odd signal;

A selection unit configured to output one of a standard 0 signal and a standard 1 signal as the first state even signal based on the first selection even signal;

outputting one of a standard 0 signal and a standard 1 signal as the first state odd signal based on the first selection odd signal;

Outputting one of a standard 0 signal and a standard 1 signal as the second state even signal based on the second selection even signal;

based on the second select odd signal, one of a standard 0 signal and a standard 1 signal is output as the second state odd signal.

In some embodiments, the first signal unit comprises a first trigger, wherein the clock end of the first trigger receives the address jump pulse, the input end of the first trigger is connected with the inverting output end of the first trigger, and the non-inverting output end of the first trigger outputs the parity indication signal;

the first input end of the first exclusive-or gate receives the odd-even indication signal, the second input end of the first exclusive-or gate is connected with the normal phase output end of the second trigger, the output end of the first exclusive-or gate outputs the first intermediate signal, the input end of the second trigger receives the first intermediate signal, the clock end of the second trigger receives the address jump pulse, and the normal phase output end of the second trigger outputs the read-write indication signal;

the first input end of the first AND gate receives the read-write indication signal, the second input end of the first AND gate receives the parity indication signal, the output end of the first AND gate is connected with the first input end of the second XOR gate, the second input end of the second XOR gate is connected with the positive phase output end of the third trigger, the output end of the second XOR gate outputs the second intermediate signal, the input end of the third trigger receives the second intermediate signal, the clock end of the third trigger receives the address jump pulse, and the positive phase output end of the third trigger outputs the turning indication signal;

the fourth signal unit comprises a second AND gate, a third XOR gate, a fourth trigger, a fifth trigger and a fourth XOR gate, wherein a first input end of the second AND gate is connected with an output end of the first AND gate, a second input end of the second AND gate receives the turning indication signal, an output end of the second AND gate is connected with a first input end of the third XOR gate, a second input end of the third XOR gate is connected with a non-inverting output end of the fourth trigger, an output end of the third XOR gate outputs the third intermediate signal, an input end of the fourth trigger receives the third intermediate signal, a clock end of the fourth trigger receives the address jump pulse, a non-inverting output end of the fourth trigger is connected with an input end of the fifth trigger, a clock end of the fifth trigger receives the preset system clock signal, a non-inverting output end of the fifth trigger is connected with a fourth input end of the fourth XOR gate, and a fourth input end of the fourth trigger is connected with a fourth input end of the fourth XOR gate, and a fourth output end of the fourth trigger is connected with a topology indication signal.

In some embodiments, in the case of 2a=12, b=3, c=5;

correspondingly, the counting unit comprises a sixth trigger, a fifth exclusive-OR gate, a seventh trigger, a third AND gate, a sixth exclusive-OR gate and an eighth trigger;

The clock ends of the sixth trigger, the seventh trigger and the eighth trigger receive the topology indication signal, the input end of the sixth trigger is connected with the inverted output end of the sixth trigger, the positive output end of the sixth trigger is connected with the first input end of the fifth exclusive-OR gate, the second input end of the fifth exclusive-OR gate is connected with the positive output end of the seventh trigger, the output end of the fifth exclusive-OR gate is connected with the input end of the seventh trigger, the positive output end of the seventh trigger is connected with the first input end of the third AND gate, the second input end of the third AND gate is connected with the positive output end of the sixth trigger, the output end of the third AND gate is connected with the first input end of the sixth exclusive-OR gate, the second input end of the sixth exclusive-OR gate is connected with the positive output end of the eighth trigger, and the output end of the sixth exclusive-OR gate is connected with the input end of the eighth trigger; the positive phase output end of the sixth trigger outputs the 1 st bit sub-parameter of the first count value, the positive phase output end of the seventh trigger outputs the 2 nd bit sub-parameter of the first count value, and the positive phase output end of the eighth trigger outputs the 3 rd bit sub-parameter of the first count value.

In some embodiments, the preprocessing unit includes a first logic, a second logic, a third logic, and a fourth logic;

The input end of the first logic device receives part of signals of the C intermediate decoding signals, and the output end of the first logic device outputs the first selection even signal;

the input end of the second logic device receives part of signals of the C intermediate decoding signals, and the output end of the second logic device outputs the first selection odd signals;

The input end of the third logic device receives part of signals of the C intermediate decoding signals, and the output end of the third logic device outputs the second selection even signal;

The input end of the fourth logic device receives part of signals of the C intermediate decoding signals, and the output end of the fourth logic device outputs the second selection odd signals;

Wherein the first select even signal, the first select odd signal, the second select even signal, and the second select even signal are not identical when the intermediate decoded signals are different.

In some embodiments, the selection unit includes a first selector, a second selector, a third selector, and a fourth selector;

A first input end of the first selector receives the standard 1 signal, a second input end of the first selector receives the standard 0 signal, a control end of the first selector receives the first select even signal, and an output end of the first selector outputs the first state even signal;

The first input end of the second selector receives the standard 1 signal, the second input end of the second selector receives the standard 0 signal, the control end of the second selector receives the first selection odd signal, and the output end of the second selector outputs the first state odd signal;

A first input end of the third selector receives the standard 0 signal, a second input end of the first selector receives the standard 1 signal, a control end of the third selector receives the second select even signal, and an output end of the third selector outputs the second state even signal;

the first input end of the fourth selector receives the standard 0 signal, the second input end of the fourth selector receives the standard 1 signal, the control end of the fourth selector receives the second selection odd signal, and the output end of the fourth selector outputs the second state odd signal.

In some embodiments of the present invention, in some embodiments,

The second logic unit comprises a fifth selector and a sixth selector, wherein a first input end of the fifth selector receives the first state even signal, a second input end of the fifth selector receives the first state odd signal, a control end of the fifth selector receives the parity indication signal, an output end of the fifth selector outputs the first preselected signal, a first input end of the sixth selector receives the second state even signal, a second input end of the sixth selector receives the second state odd signal, a control end of the sixth selector receives the parity indication signal, and an output end of the sixth selector outputs the second preselected signal;

The output unit comprises a buffer, a third NOT gate and a seventh selector, wherein the input end of the buffer receives the first preselected signal, the output end of the buffer outputs the first state signal, the input end of the third NOT gate receives the second preselected signal, the output end of the third NOT gate is connected with the first input end of the seventh selector, the second input end of the seventh selector receives the second preselected signal, the control end of the seventh selector receives the turning indication signal, and the output end of the seventh selector outputs the second state signal.

In some embodiments, all reset terminals of the first to eighth flip-flops receive a start signal, and if the start signal indicates that the test circuit starts to operate, the first to eighth flip-flops perform a reset operation.

In a second aspect, embodiments of the present disclosure provide a memory comprising a test circuit as claimed in any one of the first aspects.

The embodiment of the disclosure provides a test circuit and a memory, wherein the test circuit can automatically complete the read-write operation of a preset data topology after receiving address jump pulse, odd-even indication signals, turning indication signals and topology indication signals, and can change input data when odd or even counts reach the highest level, change the read-write state after address traversal, realize the test of another preset data topology by turning test data after the test of one preset data topology is completed, and circularly control until all the preset data topologies are tested.

Drawings

FIG. 1 is a schematic diagram of a data topology provided by an embodiment of the present disclosure;

fig. 2 is a schematic diagram of a composition structure of a test circuit according to an embodiment of the disclosure;

FIG. 3 is a schematic diagram of a structure of another test circuit according to an embodiment of the disclosure;

FIG. 4 is a control schematic diagram of a test circuit according to an embodiment of the disclosure;

FIG. 5 is a first signal timing diagram according to an embodiment of the present disclosure;

FIG. 6 is a second signal timing diagram according to an embodiment of the disclosure;

fig. 7 is a schematic structural diagram of a first control module according to an embodiment of the disclosure;

fig. 8 is a schematic diagram of a composition structure of a state decoding module according to an embodiment of the disclosure;

fig. 9 is a schematic structural diagram of a counting unit according to an embodiment of the disclosure;

Fig. 10 is a schematic structural diagram of a decoding unit according to an embodiment of the disclosure;

fig. 11 is a schematic structural diagram of a second control module according to an embodiment of the disclosure;

Fig. 12 is a schematic structural diagram of a first logic unit according to an embodiment of the disclosure;

fig. 13 is a schematic structural diagram of a preprocessing unit according to an embodiment of the present disclosure;

Fig. 14 is a schematic structural diagram of a selection unit according to an embodiment of the present disclosure;

Fig. 15 is a schematic structural diagram of a second logic unit according to an embodiment of the present disclosure

Fig. 16 is a schematic structural diagram of an output unit according to an embodiment of the disclosure;

fig. 17 is a schematic structural diagram of a memory according to an embodiment of the present disclosure.

Detailed Description

The technical solutions in the embodiments of the present disclosure will be clearly and completely described below with reference to the drawings in the embodiments of the present disclosure. It is to be understood that the specific embodiments described herein are merely illustrative of the application and not limiting of the application. It should be noted that, for convenience of description, only a portion related to the related application is shown in the drawings.

Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this disclosure belongs. The terminology used herein is for the purpose of describing embodiments of the present disclosure only and is not intended to be limiting of the present disclosure.

In the following description, reference is made to "some embodiments" which describe a subset of all possible embodiments, but it is to be understood that "some embodiments" can be the same subset or different subsets of all possible embodiments and can be combined with one another without conflict.

It should be noted that the term "first/second/third" in relation to embodiments of the present disclosure is used merely to distinguish similar objects and does not represent a particular ordering of the objects, it being understood that the "first/second/third" may be interchanged with a particular order or sequencing, if permitted, to enable embodiments of the present disclosure described herein to be implemented in an order other than that illustrated or described herein.

Testable technologies for memories include direct testing, testing with embedded CPUs, and built-in self-test technology (MBIST). Compared with other two technologies, the MBIST has a plurality of advantages, firstly, the MBIST can realize the automation of testability design and automatically realize a general memory test algorithm to achieve the purposes of high test quality and low test cost, secondly, the MBIST circuit can utilize a system clock to perform full-speed test, thereby covering more generation defects and reducing test time, and finally, the MBIST circuit can provide self-diagnosis and self-repair functions for each memory unit. Furthermore, the initialization test vector of MBIST can be performed on very low cost test equipment. Therefore, MBIST is the dominant technology of current embedded memory test design from the standpoint of high test quality and low test cost.

For DDR5, the Joint Electron engineering development Association (JEDEC, joint Electron DEVICE ENGINEERING) specifies that MBIST is activated by the mode register MR23:OP [4] and the guard key (guard key) of group 4 MR24, and then MBIST operation is performed. The DDR5 self test time (TSELFTEST) with the storage capacity of 8/16 gigabytes (Gigabyte, gb) is no more than 9 seconds at maximum, and the data topology tested during the self test time is designed by a designer according to the actual requirement.

The MBIST of the present design includes the 12 Data topology (Data topo) structure shown in fig. 1 at host end runtime. When the MBIST receives the enable signal from host, the MBIST automatically performs the 12 data topology write and read operations of fig. 1. The Data in two adjacent Data topos in the 12 Data topologies are inverted from each other. For example, for Data topo2, the Data corresponding to each memory cell is obtained by inverting the Data corresponding to the corresponding memory cell in Data topo 1. It should be understood that WL in fig. 1 represents a word line, BL represents a bit line, and the intersection of the bit line and the corresponding word line is a memory cell, and each memory cell stores "0" or "1".

That is, referring to fig. 1, when MBIST receives the enable signal issued by host, it first performs a test using Data topo1 and Data topo2, and the specific procedure is as follows:

(1) The even row addresses are counted and the even Data topology in Data topo1 (i.e., 00000000 corresponding to WL0/WL2WL4/WL6 in Data topo 1) is written to even row addresses such as WL0/WL2WL4/wl6.

(2) After counting to the even most significant bit, counting starts for the odd row address and the odd Data topology in Data topo1 (i.e., 10101010 corresponding to WL1/WL3WL5/WL76 in Data topo 1) is written to the odd row address such as WL1/WL3WL5/WL7.

(3) After the odd row address counts to the highest bit, a read operation is started and the read data and the written data are compared;

(4) The even row addresses are counted and the even Data topology in Data topo2 (i.e., 11111111 corresponding to WL0/WL2WL4/WL6 in Data topo 2) is written to even row addresses such as WL0/WL2WL4/WL6.

(5) After counting to the even most significant bit, counting starts for the odd row address and the odd Data topology in Data topo2 (i.e., 01010101 corresponding to WL1/WL3WL5/WL76 in Data topo 2) is written to the odd row address such as WL1/WL3WL5/WL7.

(6) After the odd row address counts to the highest bit, a read operation starts to be performed and the read Data and the written Data are compared, thereby completing the test of Data topo1 and Data topo 2.

The test of Data topo3 and Data topo4, the test of Data topo6 and Data topo6, the test of Data topo7 and Data topo8, the test of Data topo9 and Data topo10, and the test of Data topo11 and Data topo12 are continued to be completed according to the above steps.

Based on this, the embodiment of the disclosure provides a test circuit, which can automatically complete the read-write operations of the 12 Data topos after receiving the enable signal of the host end, can switch to an even row address when the odd row address counts to the highest bit or change the odd row address count when the even row address counts to the highest bit, and change the corresponding input Data, and change the read-write state after the row address traversal of 1 Data topo until all the Data topos are tested. Therefore, the test time can be saved, and the test efficiency can be improved.

In one embodiment of the present disclosure, as shown in fig. 2, a composition structure of a test circuit 10 is shown, the test circuit 10 performs a read-write test on a memory array by using a plurality of preset Data topologies Data topo, the test circuit 10 includes:

A first control module 11 configured to generate and output a parity indication signal, a flip indication signal, and a topology indication signal based on a received address jump pulse, wherein the address jump pulse indicates that a count value of a row address on which a target operation has been performed reaches an even-numbered highest order or an odd-numbered highest order, and the target operation is a read operation or a write operation;

the state decoding module 12 is connected with the first control module 11 and is configured to count and decode the topology indication signal to obtain an intermediate decoding signal;

A second control module 13, connected to the first control module 11 and the state decoding module 12, configured to generate and output a first state signal and a second state signal based on the parity indication signal, the flip indication signal, and the intermediate decoding signal;

the first status signal is used for selecting one of the first Data sequence and the second Data sequence as a target Data sequence, the second status signal indicates whether each Data of the target Data sequence is overturned, and the target Data sequence or the overturned target Data sequence is used for forming a preset Data topology Data topo.

The embodiment of the disclosure relates to a built-in self-test circuit design of a memory in an integrated circuit design, in particular to a state machine design of a 16Gb DDR5 built-in self-test circuit when a host end operates, and the design is applied to automatic generation and change of control signals when various data topology tests are carried out in a 16Gb DDR5 chip, but the invention is not limited to the range, and other command planning and generating circuits and counting time sequence control circuits can all adopt the design.

It should be noted that the first status signal and the second status signal jointly determine the type of the data sequence. Specifically, the first state signal has a first state and a second state, the first state corresponds to the first data sequence, the second state corresponds to the second data sequence, the first data sequence or the second data sequence is selected as a target data sequence according to the state of the first state signal to test, the second state signal has a third state and a fourth state, when the second state signal is in the third state, the target data sequence is unchanged, and when the second state signal is in the fourth state, the target data sequence is turned over. Therefore, the automatic Data overturning can be realized, and the read-write test of the Data topo can be more efficiently completed.

In some embodiments, the preset Data topologies have a group a, each group of preset Data topologies Data topo comprises a first Data topology and a second Data topology, each of the first Data topology and the second Data topology comprises an odd Data topology and an even Data topology, the parity indication signal indicates that a row address of a storage unit corresponding to the execution target operation is an odd row address or an even row address and generates a corresponding odd Data topology or an even Data topology, the topology indication signal indicates a group number of the preset Data topology corresponding to the execution target operation, and the flip indication signal indicates the first Data topology or the second Data topology corresponding to the execution target operation.

It should be noted that, the parity signal may select to perform a read operation on the odd row address or the even row address according to the level state. For example, when the parity signal is in the first level state, the target operation is performed on the Data array with even row address in the Data topo, and when the target operation is performed on the last even row address in the Data topo, the parity signal is changed from the first level state to the second level state, and the target operation is continuously performed on the Data array with odd row address in the Data topo.

In short, the parity indication signal corresponds to a switch between an odd Data topology and an even Data topology in the same preset Data topology, the flip indication signal corresponds to a switch between a first Data topology and a second Data topology in the same set of preset Data topologies, and the topology indication signal corresponds to a switch between different sets of preset Data topology sets Data topo.

Referring to fig. 1, since the Data of every two Data topos are in a flipped relationship, two Data topos are taken as one group, and 6 groups of Data topos are total, i.e., a=6.

In some embodiments, referring to FIG. 4, the first control module 11 is further configured to generate and output a read-write indication signal (WR_RD) based on receiving the address jump pulse, wherein the read-write indication signal (WR_RD) indicates a read operation or a write operation.

It should be noted that, in the embodiment of the present disclosure, a JUMP addressing (JUMP) manner is adopted, when the first control module 11 receives an address JUMP pulse, it indicates that the count value of the odd line address or the even line address in a certain Data topo has reached the highest level, the input target Data sequence will be changed at this time, and when all line addresses of a Data topo have been traversed, the read-write state will be changed by the read-write indication signal. That is, the data sequences of the odd row address and the even row address are different.

In some embodiments, as shown in FIG. 3, the test circuit 10 further includes a test module 14;

the test module 14 is connected to the first control module 11 and the second control module 13, and is configured to receive a read-write indication signal, a first status signal and a second status signal, write corresponding Data topo to the storage array based on the first status signal and the second status signal when the read-write indication signal indicates a write operation, or read Data of the storage array when the read-write indication signal indicates a read operation, and perform comparison processing on the read Data based on the first status signal and the second status signal.

During the test, it is determined whether to write Data topo into the memory array or read the Data in the memory array according to the read/write instruction signal. Specifically, when the read-write instruction signal is in a first level state, the corresponding Data topo is written into the memory array, and when the read-write instruction signal is in a second level state, the Data in the memory array is read. Meanwhile, by comparing the written data with the read data, the error of which data is specific can be judged, so that the data can be processed in time, and the testing efficiency is improved.

In some embodiments, referring to fig. 4 to 6, the first control module 11 is specifically configured to control the level state of the parity indication signal data_change to be flipped once every 1 address jump pulse even_odd is received, control the level state of the read/write indication signal wr_rd to be flipped once every 2 address jump pulses even_odd is received, control the level state of the flip indication signal index to be flipped once every 4 address jump pulses even_odd is received, and generate 1 topology indication signal s_clk every 8 address jump pulses even_odd is received.

It should be noted that fig. 4 shows the different signals to be controlled when the state machine performs the test. Wherein DATA <0> is a first preselected signal, DATA <1> is a second preselected signal, and the first preselected signal DATA <0> and the second preselected signal DATA <1> together determine what DATA is input into the DATA topo. The first preselected signal DATA <0> is the first state signal, and the second preselected signal DATA <0> is the second state signal after being inverted. ADDR represents the addressing control signal, default is the state machine default. As can be seen from the above description, the addressing methods adopted in the embodiments of the present disclosure are JUMP addressing (JUMP) with parity differentiation.

According to the different values of the control signals shown in fig. 4, taking Data topo1 and Data topo2 in fig. 1 as examples, the corresponding timing diagrams are shown in fig. 5:

(1) The flip indication signal=0 (not flipped), the read-write indication signal wr_rd=0 (write phase), the parity indication signal data_change=0, and the input preselected signal Data <1:0> is 00 at this time, so that the corresponding even Data topology is written into the even row address;

(2) The inversion indication signal=0 (no inversion), the read-write indication signal wr_rd=0 (write phase), and the parity indication signal data_change=1, the input preselected signal Data <1:0> is 01, so as to write the corresponding odd Data topology into the odd row address, so that a complete Data topo is written;

(3) The flip indication signal=0 (not flipped), the read-write indication signal wr_rd=1 (read phase), the parity indication signal data_change=0, the Data of even row address is read out at this time, and the read Data is compared with the even Data topology corresponding to the preselected signal Data <1:0> being 00;

(4) The inversion indication signal=0 (not inverted), the read-write indication signal wr_rd=1 (read phase), the parity indication signal data_change=1, the Data of the odd row address is read out at this time, and the read Data is compared with the odd Data topology corresponding to the preselected signal Data <1:0> being 01, so as to complete the test of the Data topo.

(5) The flip indication signal=1 (flip), the read-write indication signal wr_rd=0 (write phase), the parity indication signal data_change=0, and the input preselected signal Data <1:0> is 11 at this time, so that the corresponding even Data topology is written into the even row address;

(6) The inversion indication signal=1 (inversion), the read-write indication signal wr_rd=0 (writing phase), and the parity indication signal data_change=1, when the input preselected signal Data <1:0> is 10, so as to write the corresponding odd Data topology into the odd row address;

(7) The flip signal=1 (flip), the read-write indication signal wr_rd=1 (read phase), thereby reading out the corresponding DATA result, the two sets of pre-selected signals DATA <1:0> are 11, the parity indication signal data_change=0, at this time, the DATA of even row addresses are read out, and the read-out DATA are compared with the even DATA topology corresponding to the pre-selected signals DATA <1:0> being 11;

(4) The Data of the odd row address is read out at this time, and the read Data is compared with the odd Data topology corresponding to the preselected signal Data <1:0> of 10 to complete the test of the Data topo, and simultaneously complete the test of the group of Data topo.

It should be noted that, since the address skip pulse even_odd indicates that the count value of the row address on which the target operation has been performed reaches the EVEN-numbered highest bit or the ODD-numbered highest bit, once the first control module 11 receives the 1 address skip pulse even_odd, it indicates that the test circuit 10 has completed counting the EVEN-numbered row address of Data topo, and if the previous parity indication signal data_change is in the first level state, the parity indication signal data_change is switched to the second level state at this time, and the test of the memory cell corresponding to the ODD-numbered row address starts to be performed.

When the first control module 11 receives 2 address skip pulses even_odd, it indicates that writing of a certain Data topo is completed, and at this time, the level state of the read/write instruction signal is switched from the original write operation to the read operation. That is, when the first control module 11 receives 2 address skip pulses even_odd, it indicates that the writing operation is completed for one Data topo, and when the first control module 11 receives 4 address skip pulses even_odd, the reading operation is completed for the Data topo. In other words, when the first control module 11 receives the 4 address skip pulses even_odd, the test on the Data topo is completed, and at this time, the test on the next Data topo is required. Since the Data between two adjacent Data topos (a group of Data topos) are inverted, the inversion indication signal INVERT INVERTs the Data of the previous Data topo to obtain the next Data topo.

As described above, when the first control module 11 receives the 4 address skip pulses even_odd, the test for the Data topo is completed. Then, when the first control module 11 receives 8 address skip pulses even_odd, it indicates that the test on the two adjacent Data topos is completed, and at this time, 1 topology indication signal s_clk is generated. Therefore, as shown in FIG. 6, the pre-selection signal DATA <1:0> needs to be controlled to be changed once every two Data topos, so a counter is added after the Data flip signal INVERT to flip once every 8 address jump pulses EVEN_ODD (i.e. one group of Data topos), the topology indication signal S_CLK is generated after shifting, and the number of groups of Data topos (one group for every two Data topos) is counted. Thus, one topology indication signal S_CLK indicates that 2 adjacent Data topo tests are complete. The embodiment of the disclosure is to group the 12 Data topos two by two, and when the test circuit 10 generates the 6 topology indication signals s_clk, it is indicated that the test is completed for all the 12 Data topos.

Therefore, the control of the host terminal can be realized more conveniently by splitting the signals to be controlled layer by layer, and the control is easy to adjust.

In some embodiments, as shown in fig. 7, the first control module 11 includes:

A first signal unit 111 configured to sample an inverted signal of the parity indication signal data_change using the address skip pulse even_odd to generate a new parity indication signal;

A second signal unit 112 connected to the first signal unit 111 and configured to logically process the parity indication signal data_change and the read/write indication signal wr_rd to generate a first intermediate signal, and sample the first intermediate signal based on the address skip pulse even_odd to generate a new read/write indication signal;

A third signal unit 113 connected to the second signal unit 112 and configured to logically process the parity indication signal data_change, the read/write indication signal wr_rd, and the flip indication signal INVERT to generate a second intermediate signal;

The fourth signal unit 114, connected to the third signal unit 113, is configured to perform logic processing on the parity indication signal data_change, the read/write indication signal wr_rd and the flip indication signal INVERT to obtain a third intermediate signal, and generates a topology indication signal s_clk based on the third intermediate signal, the address skip pulse even_odd and the preset system clock signal bist_clk.

Specifically, with continued reference to fig. 7, the first signal unit 111 includes a first flip-flop 21, wherein a clock terminal CLK of the first flip-flop 21 receives the address skip pulse even_odd, an input terminal of the first flip-flop 21 is connected to an inverting output terminal thereof, and a non-inverting output terminal of the first flip-flop 21 outputs the parity indication signal data_change;

The second signal unit 112 includes a first exclusive-or gate 22 and a second trigger 23, wherein a first input end of the first exclusive-or gate 22 receives the parity indication signal data_change, a second input end of the first exclusive-or gate 22 is connected with a non-inverting output end of the second trigger 23, an output end of the first exclusive-or gate 22 outputs a first intermediate signal, an input end of the second trigger 23 receives the first intermediate signal, a clock end CLK of the second trigger 23 receives the address jump pulse EVEN_ODD, and a non-inverting output end of the second trigger 23 outputs a read/write indication signal WR_RD;

The third signal unit 113 includes a first and gate 24, a second exclusive-or gate 25, and a third flip-flop 26, where a first input terminal of the first and gate 24 receives a read-write indication signal wr_rd, a second input terminal of the first and gate 24 receives a parity indication signal data_change, an output terminal of the first and gate 24 is connected to a first input terminal of the second exclusive-or gate 25, a second input terminal of the second exclusive-or gate 25 is connected to a positive output terminal of the third flip-flop 26, an output terminal of the second exclusive-or gate 25 outputs a second intermediate signal, an input terminal of the third flip-flop 26 receives the second intermediate signal, a clock terminal CLK of the third flip-flop 26 receives an address skip pulse even_odd, and a positive output terminal of the third flip-flop 26 outputs a flip-flop indication signal INVERT;

The fourth signal unit 114 includes a second and gate 27, a third exclusive-or gate 28, a fourth flip-flop 29, a fifth flip-flop 30, and a fourth exclusive-or gate 31, where a first input terminal of the second and gate 27 is connected to an output terminal of the first and gate 24, a second input terminal of the second and gate 27 receives the flip-flop indication signal INVERT, an output terminal of the second and gate 27 is connected to a first input terminal of the third exclusive-or gate 28, a second input terminal of the third exclusive-or gate 28 is connected to a non-inverting output terminal of the fourth flip-flop 29, an output terminal of the third exclusive-or gate 28 outputs a third intermediate signal, an input terminal of the fourth flip-flop 29 receives the third intermediate signal, a clock terminal CLK of the fourth flip-flop 29 receives the address skip pulse even_odd, a non-inverting output terminal of the fourth flip-flop 29 is connected to an input terminal of the fifth flip-flop 30, a clock terminal of the fifth flip-flop 30 receives the preset system clock signal bist_clk, a non-inverting output terminal of the fifth flip-flop 30 is connected to a first input terminal of the fourth exclusive-or gate 31, and an output terminal of the fourth exclusive-or gate 31 outputs a topology indication signal.

It should be noted that, the first signal unit 111, the second signal unit 112, the third signal unit 113 and the fourth signal unit 114 together form a synchronous counter, and each signal unit 111 outputs a corresponding indication signal. The first signal unit 111 outputs the parity indication signal data_change, the second signal unit 112 outputs the read/write indication signal wr_rd, the third signal unit 113 outputs the flip indication signal INVERT, and the fourth signal unit 114 outputs the topology indication signal s_clk.

It should be noted that, the address skip pulse even_odd and the preset system clock signal bist_clk are not both sampling the third intermediate signal, and the preset system clock signal bist_clk is sampling the output of the previous stage flip-flop (fourth flip-flop 29).

In some embodiments, as shown in fig. 8, the state decoding module 12 includes a counting unit 121 and C decoding units 122, where the number of intermediate decoding signals is C;

A counting unit 121, connected to the first control module 11, configured to count pulses of the topology indication signal s_clk, generating a first count value;

The jth decoding unit 122 is connected to the counting unit 121 and configured to control the jth intermediate decoding signal to be in the first state when the first count value meets the jth decoding condition, and to control the jth intermediate decoding signal to be in the second state when the first count value does not meet the jth decoding condition, wherein j is an integer greater than or equal to 1 and less than or equal to C, C is less than or equal to A, and the first count value includes a B-bit subparameter, 2B is greater than or equal to A.

It should be noted that the first count value is the number of topology indication signals s_clk, and thus if the first count value includes B as a sub-parameter, B topology indication signals s_clk are generated. And 1 topology indication signal S_CLK is generated for every two Data topos, so 2B must be greater than or equal to the number A of Data topos to ensure that all Data topos are tested.

Specifically, as shown in fig. 9, in the case of 2a=12, b=3, c=5;

Correspondingly, the counting unit 121 includes a sixth flip-flop 32, a fifth exclusive-or gate 33, a seventh flip-flop 34, a third and gate 35, a sixth exclusive-or gate 36, and an eighth flip-flop 37;

The clock terminals CLK of the sixth flip-flop 32, the seventh flip-flop 34 and the eighth flip-flop 37 receive the topology indication signal S_CLK, the input terminal of the sixth flip-flop 32 is connected with the inverting output terminal thereof, the non-inverting output terminal of the sixth flip-flop 32 is connected with the first input terminal of the fifth exclusive-OR gate 33, the second input terminal of the fifth exclusive-OR gate 33 is connected with the non-inverting output terminal of the seventh flip-flop 34, the non-inverting output terminal of the seventh flip-flop 34 is connected with the first input terminal of the third AND gate 35, the second input terminal of the third AND gate 35 is connected with the non-inverting output terminal of the sixth flip-flop 32, the output terminal of the third AND gate 35 is connected with the first input terminal of the sixth exclusive-OR gate 36, the second input terminal of the sixth exclusive-OR gate 36 is connected with the non-inverting output terminal of the eighth flip-flop 37, the output terminal of the sixth exclusive-OR gate 36 is connected with the input terminal of the eighth flip-flop 37, the non-inverting output terminal of the sixth flip-flop 32 is connected with the input terminal of the seventh flip-flop 34, the non-inverting output terminal of the sixth flip-flop 32 outputs the first count value 1S < 1-bit value < S2 > and the first output terminal of the positive count value <1> S <3> of the first output terminal of the seventh flip-flop.

It should be noted that the value of the first count value S <2:0> is also the state in which the state machine is located. The first control module 11 and the counting unit 121 in the embodiment of the present disclosure all use synchronous counters, which have faster counting speed and better clock synchronism. Of course, in other embodiments, the related functions may be implemented by using asynchronous counters, which are determined according to the circuit design and actual needs.

In some embodiments, as shown in fig. 10, the jth decoding unit 122 includes a first nor gate 38, a first nor gate 39, a first nand gate 40, and a second nor gate 41, where the second input terminal of the first nor gate 38 receives the 1 st bit sub-parameter S <0> of the first count value, the first input terminal of the first nor gate 38 receives the 2 nd bit sub-parameter S <1> of the first count value, the input terminal of the first nor gate 39 receives the 3 rd bit sub-parameter S <2> of the first count value, the first input terminal of the first nand gate 40 is connected to the output terminal of the first nor gate 39, the second input terminal of the first nand gate 40 is connected to the output terminal of the first nor gate 38, the output terminal of the first nand gate 40 is connected to the input terminal of the second nor gate 41, and the output terminal of the second nor gate 41 outputs the jth intermediate decoding signal.

Note that, when 2a=12, i.e., a=6, the value of the corresponding topology indication signal s_clk is at most 6. When b=3, the first count value is 8 at maximum, and the range that the counting unit 121 can count is 000 to 111. From the above, the topology indication signal s_clk indicates the group number of the Data topo corresponding to the execution target operation, and the Data topo in 12 of fig. 1 can obtain 6 preset Data topology groups, so that the first count value can be used to represent the state of the state machine. The state machine is IN the relationship with DATA_IN <1:0> as shown IN Table 1:

TABLE 1

It should be appreciated that TOPO CNT is the state machine S <2:0>, and S <2:0> is the first count value. Since the disclosed embodiments have a total of 6 sets of Data topos, table 1 lists the 6 states of state machine S <2:0 >. Where DATA_IN <0> is the first state signal and DATA_IN <1> is the second state signal. The first state signal DATA_IN <0> is the first preselected signal, and the second state signal DATA_IN <1> is the inverted second preselected signal DATA <1>.

Now, the example of row 1 in table 1 is described, and other rows can be understood with reference to row 1.

Line 1 is the first set of Data topo, which is also the 1 st state in which the state machine is located. When DATA_IN <1:0> is 00/01/00/01, it corresponds to DATA topo1 IN FIG. 1, wherein the first two 00/01 correspond to DATA topo1 write operations and the second two 00/01 correspond to DATA topo1 read operations, so that the testing of DATA topo1 is completed. Then, the high bit of DATA_IN <1:0> is flipped by the flip indication signal INVERT to obtain 10/11/10/11, which is DATA_IN <1:0> corresponding to DATA topo2, and similarly, the first two 10/11 write operations corresponding to DATA topo2 and the second two 10/11 read operations corresponding to DATA topo 2. Row 1 in table 1 thus completes the testing of Data topo1 and Data topo 2. During this time, the automatic flipping of Data topo is completed.

Still referring to the 1 st example IN Table 1, a simple explanation is made as to how the first state signal DATA_IN <0> and the second state signal DATA_IN <1> are obtained for the corresponding DATA topo. Referring to FIG. 4 and Table 1, when DATA_IN <1:0> is 00, i.e., the first state signal DATA_IN <0> and the second state signal DATA_IN <1> are both 0, the corresponding DATA sequence is 00000000, when DATA_IN <1:0> is 01, i.e., the first state signal DATA_IN <0> is 1, the second state signal DATA_IN <1> is 0, the corresponding DATA sequence is 10101010. Referring to fig. 1, data topo having an even Data sequence of 00000000 and an odd Data sequence of 10101010 is Data topo1. Similarly, when the first state signal DATA_IN <0> is 0 and the second state signal DATA_IN <1> is 1, the DATA sequence corresponding to DATA_IN <0> is flipped when DATA_IN <1> is 1, the DATA sequence corresponding to DATA_IN <0> is 00000000 when DATA_IN <0> is 0, the DATA sequence corresponding to DATA_IN <1:0> is 11111111 when DATA_IN <1:0> is 10, the DATA sequence corresponding to DATA_IN <0> and DATA_IN <1> is 1, and the DATA topo corresponding to even DATA sequence of 11111111 and the DATA sequence corresponding to 01010101 is DATA topo2 when DATA_IN <1:0> is 11.

That is, the disclosed embodiments control the automatic input and testing of 12 kinds of DATA topos by controlling the first state signal data_in <0> and the second state signal data_in <0 >.

In other words, referring to Table 1, the state machine can be considered to have 6 states TOPO CNT0, TOPO CNT1, TOPO CNT2, TOPO CNT3, TOPO CNT4, TOPO CNT5.

IN one design, the state of the state machine can be found when (1) DATA_IN <1> =0, DATA_IN <0> =0, and the states TOPO CNT 0-TOPO CNT5 need to be determined at this time;

IN another design, the state of the state machine can be found when (1) DATA_IN <1> =0, DATA_IN <0> =1, and the states TOPO CNT 0-TOPO CNT5 need to be determined at this time;

IN yet another design, the state of the state machine can be found when (1) DATA_IN <1> =1, DATA_IN <0> =1, and the states TOPO CNT 0-TOPO CNT5 are also determined.

IN yet another design, the state of the state machine can be found when (1) DATA_IN <1> =1, DATA_IN <0> =0, where the states TOPO CNT0, TOPO CNT1, TOPO CNT2, TOPO CNT3, TOPO CNT5 need to be determined as well, and the state of TOPO CNT4 need not be found, which can be defined inversely by other states.

Therefore, with the last design, only 5 states of the state machine need to be found, and the number of decoding devices is reduced.

Specifically, as shown IN FIG. 10, the state of the state machine is found IN Table 1 with DATA_IN <0> being 0 and DATA_IN <1> being 1 and decoded to generate intermediate decoded signals DATA0 (indicating whether the state machine is IN the TOPO CNT0 state), DATA1 (indicating whether the state machine is IN the TOPO CNT1 state), DATA2 (indicating whether the state machine is IN the TOPO CNT2 state), DATA3 (indicating whether the state machine is IN the TOPO CNT3 state) and DATA5 (indicating whether the state machine is IN the TOPO CNT5 state) for subsequent generation of the preselected signals DATA <1:0>.

In some embodiments, as shown in fig. 11 to 14, the second control module 13 includes:

a first logic unit 131 configured to logically process the C intermediate decoding signals (DATA 0, DATA1, DATA2, DATA3, and DATA 5), and output a first state EVEN signal data0_even, a first state ODD signal data0_odd, a second state EVEN signal data1_even, and a second state ODD signal data1_odd;

A second logic unit 132 configured to output one of the first state EVEN signal DATA0_EVEN and the first state ODD signal DATA0_ODD as a first pre-selected signal DATA <0> based on the parity indication signal Data_change, and to output one of the second state EVEN signal DATA1_EVEN and the second state ODD signal DATA1_ODD as a second pre-selected signal DATA <1> based on the parity indication signal Data_change;

an output unit 133 configured to output the first preselected signal DATA <0> as a first state signal DATA_IN <0>, and to output one of the second preselected signal DATA <1> and an inverted signal of the second preselected signal as a second state signal DATA_IN <1> based on the inversion indication signal INVERT.

Specifically, referring to fig. 12, the first logic unit 131 includes:

A preprocessing unit 1311 configured to logically process the C intermediate decoding signals (DATA 0, DATA1, DATA2, DATA3, and DATA 5), outputting a first selection EVEN signal even_data0_en, a first selection ODD signal odd_data0_en, a second selection EVEN signal even_data1_en, and a second selection ODD signal odd_data1_en;

a selection unit 1312 configured to output one of the standard 0 signal and the standard 1 signal as the first state EVEN signal data0_even based on the first selection EVEN signal even_data0_en;

Outputting one of the standard 0 signal and the standard 1 signal as the first state ODD signal data0_odd based on the first selection ODD signal odd_data0_en;

Outputting one of the standard 0 signal and the standard 1 signal as the second state EVEN signal data1_even based on the second select EVEN signal even_data1_en;

Based on the second selection ODD signal odd_data1_en, one of the standard 0 signal and the standard 1 signal is output as the second state ODD signal data1_odd.

As shown in fig. 13, the preprocessing unit 1311 includes a first logic 42, a second logic 43, a third logic 44, and a fourth logic 45;

an input terminal of the first logic 42 receives a partial signal of the C intermediate decoded signals, and an output terminal of the first logic 42 outputs a first select EVEN signal even_data0_en;

An input terminal of the second logic 43 receives part of the signals of the C intermediate decoding signals, and an output terminal of the second logic 43 outputs a first selection ODD signal odd_data0_en;

An input terminal of the third logic 44 receives a partial signal of the C intermediate decoded signals, and an output terminal of the third logic 44 outputs a second select EVEN signal even_data1_en;

the input terminal of the fourth logic 45 receives part of the signals of the C intermediate decoded signals, and the output terminal of the fourth logic 45 outputs the second selection ODD signal odd_data1_en;

When the intermediate decoding signals are different, the first selection EVEN signal even_data0_en, the first selection ODD signal odd_data0_en, the second selection EVEN signal even_data1_en, and the second selection EVEN signal odd_data1_en are not identical.

In fig. 13, the first logic unit 42, the second logic unit 43, and the third logic unit 44 are all or gates, and the fourth logic unit 45 is a 2-not gate, however, other logic gates or logic circuit combinations may be used instead of or gates in a specific design.

It should be noted that, taking the first EVEN selection signal even_data0_en as an example, which indicates that the first state signal data_in <0> is 0 during EVEN addressing, a value that makes the first state signal data_in <0> be 0 is found from the intermediate decoding signals DATA0, DATA1, DATA2, DATA3 and DATA5, the first EVEN selection signal even_data0_en can be generated by or logic, and the first EVEN selection signal odd_data0_en, the second EVEN selection signal even_data1_en and the second ODD selection signal odd_data1_en are generated IN the same way. Since column 1 of DATA_IN <1:0> IN Table 1 corresponds to the even DATA sequence IN DATA topo, column 2 corresponds to the odd DATA sequence IN DATA topo, and subsequent columns are sequentially recursively. Take columns 1 and 2 in table 1 as examples:

IN the EVEN addressing (column 1 of table 1), that is, the values for which the first state signal data_in <0> is 0 are found out from the intermediate decoding signals DATA0, DATA1, DATA2, DATA3 and DATA5, and are DATA0, DATA1 and DATA3, the first select EVEN signal even_data0_en is generated by or logic, and the values for which the second state signal data_in <1> is 1 are found out, and the second select EVEN signal even_data1_en is generated by or logic.

Similarly, when ODD addressing is performed (column 2 of table 1), the first selection ODD signal odd_data0_en is generated by or logic by finding out the value for making the first state signal data_in <0> 0 from among the intermediate decoding signals DATA0, DATA1, DATA2, DATA3 and DATA5, and the second selection ODD signal odd_data1_en is generated by inverting the value for making the second state signal data_in <1> 1 to DATA3 twice.

It will be appreciated that the data written when traversing the odd and even row addresses is different, and that parity is required here as the address addressing is parity-split. In this way, the addressing mode is unified, and the control logic is clear.

Accordingly, as shown in fig. 14, the selection unit 1312 includes a first selector 46, a second selector 47, a third selector 48, and a fourth selector 49;

A first input terminal of the first selector 46 receives the standard 1 signal, a second input terminal of the first selector 46 receives the standard 0 signal, a control terminal of the first selector 46 receives the first select EVEN signal even_data0_en, and an output terminal of the first selector 46 outputs the first state EVEN signal data0_even;

A first input terminal of the second selector 47 receives the standard 1 signal, a second input terminal of the second selector 47 receives the standard 0 signal, a control terminal of the second selector 47 receives the first selection ODD signal odd_data0_en, and an output terminal of the second selector 47 outputs the first state ODD signal data0_odd;

a first input terminal of the third selector 48 receives the standard 0 signal, a second input terminal of the first selector 48 receives the standard 1 signal, a control terminal of the third selector 48 receives the second selection EVEN signal data1_even, and an output terminal of the third selector 48 outputs the second state EVEN signal data1_even;

A first input terminal of the fourth selector 49 receives the standard 0 signal, a second input terminal of the fourth selector 49 receives the standard 1 signal, a control terminal of the fourth selector 49 receives the second selection ODD signal data1_odd, and an output terminal of the fourth selector 49 outputs the second state ODD signal data1_odd.

It should be noted that, the first selection EVEN signal even_data0_en, the first selection ODD signal odd_data0_en, the second selection EVEN signal data1_even, and the second selection ODD signal data1_odd generated by the and processing unit 1311 are used to select the values of the first state EVEN signal data0_even, the first state ODD signal data0_odd, the second state EVEN signal data1_even, and the second state ODD signal data1_odd. Illustratively, when the first select EVEN signal even_data0_en is 1, the first state EVEN signal data0_even takes 0 and vice versa takes 1. The other three are understood by reference and will not be described in detail herein.

In some embodiments, as shown in fig. 15, the second logic unit 132 includes a fifth selector 50 and a sixth selector 51, a first input terminal of the fifth selector 50 receives the first state EVEN signal data0_even, a second input terminal of the fifth selector 50 receives the first state ODD signal data0_odd, a control terminal of the fifth selector 50 receives the parity indication signal datachange, an output terminal of the fifth selector 50 outputs the first preselected signal data0 >, a first input terminal of the sixth selector 51 receives the second state EVEN signal data1_even, a second input terminal of the sixth selector 51 receives the second state ODD signal data1_odd, a control terminal of the sixth selector 51 receives the parity indication signal datachange, and an output terminal of the sixth selector 51 outputs the second preselected signal data1 >.

As shown IN fig. 16, the output unit 133 includes a buffer 52, a third not gate 53 and a seventh selector 54, wherein an input terminal of the buffer 52 receives a first preselected signal DATA <0>, an output terminal of the buffer 52 outputs a first state signal data_in <0>, an input terminal of the third not gate 53 receives a second preselected signal DATA <1>, an output terminal of the third not gate 53 is connected to a first input terminal of the seventh selector 54, a second input terminal of the seventh selector 54 receives the second preselected signal DATA <1>, a control terminal of the seventh selector 54 receives a flip indication signal INVERT, and an output terminal of the seventh selector 54 outputs the second state signal data_in <1>.

It should be noted that the buffer 52 is formed by two NOT gates, that is, the first preselected signal DATA <0> is inverted twice to obtain the first state signal DATA_IN <0>. That is, IN the disclosed embodiment, the first preselected signal DATA <0> is the first state signal DATA_IN <0>, and the second state signal DATA_IN <1> is the inverse of the second preselected signal DATA <1 >.

Meanwhile, whether DATA <1:0> at a specific output is an odd row address or an even row address can be selected through the parity indication signal Data_change, and whether the value of DATA <1> needs to be flipped is determined through the flip indication signal INVERT.

For the state machine, when the test starts, the state machine S <2:0> is 0, and the decoding unit 122 decodes that DATA0 is 1, DATA2, DATA3, and DATA5 are 0, and since DATA0 is 1, the first selection EVEN signal even_data0_en obtained by the preprocessing unit 1311 is 1, the first selection ODD signal odd_data0_en, the second selection EVEN signal even_data1_en, and the second selection ODD signal odd_data1_en are all 0, and then the selection unit 1312 selects the first state EVEN signal data0_even to be 0, the first state ODD signal data0_odd to be 1, the second state EVEN signal data1_even to be 0, and the second state ODD signal data1_odd to be 0. At this time, the parity indication signal data_change and the inversion indication signal INVERT maintain initialized values, the first pre-selected signal Data <0> is selected as the first state EVEN signal data0_even, the second pre-selected signal Data <1> is the second state EVEN signal data1_even, the second state signal data1 > is the second pre-selected signal data1_even, no inversion occurs, i.e., data1:0 > is 00, when the EVEN address reaches a maximum value, the parity indication signal data_change is inverted, the inversion indication signal INVERT is unchanged, the first pre-selected signal data0 > is selected as the first state ODD signal data0_odd, the second pre-selected signal data1 > is selected as the second state ODD signal data1_odd, and the second state signal data1 > is selected as the second pre-selected signal data1_in, i.e., data1:0 > is 01. So far, the odd row address and the even row address of one Data topo are traversed, namely the full address is written, then the full address reading operation is carried out, and the Data change is the same. When the read-write operation of one Data topo is completed, the next Data topo is written and read, at this time, the flip indication signal INVERT is flipped, and the rest changes are unchanged, so that DATA_IN <1:0> changes to 10/11/10/11, the 2 nd Data topo is read-write traversed, and the first control module 11 and the counting unit 121 are used for enabling the topology indication signal S_CLK to generate a pulse, so that the state of the state machine changes from 0 to 1, and the corresponding written Data also generates the same change as the state 0, so that the cycle is performed until 6 states, namely 12 Data topos, are traversed.

In some embodiments, all reset terminals of the first flip-flops 21 to 37 receive the start signal Rst, wherein if the start signal Rst indicates the test circuit 10 starts to operate, all the first flip-flops 21 to 37 perform the reset operation.

In addition, the reset signal is also generated when the first count value counts to 110 (the next state after DATA 5) so as to start the next cycle.

That is, in order to achieve the foregoing test requirements, the presently disclosed embodiments provide a test circuit 10, the test circuit 10 needs to include the following functions as shown in fig. 4:

1. the addressing mode is controlled. When the MBIST receives the enable signal sent by the host, it selects whether to read or write the Data sequence corresponding to the even row address or the odd row address in the Data topo by using the Data-change of the parity indication signal in a jump addressing mode.

2. Control the selection of the test input DATA (preselected signals DATA <1:0 >). The first preselected signal DATA <0> and the second preselected signal DATA <1> together determine the DATA sequence that is input to the MBIST circuit each time. For example, the DATA sequence is 00000000 when the first preselected signal DATA <0> =0 and the second preselected signal DATA <1> =0, 11111111 when the first preselected signal DATA <0> =0 and the second preselected signal DATA <1> =1, 10101010 when the first preselected signal DATA <0> =1 and the second preselected signal DATA <1> =0, and 01010101 when the first preselected signal DATA <0> =1 and the second preselected signal DATA <1> =1.

3. And controlling a read-write (wr_rd) command. The MBIST circuit is tested with the data sequence changed each time the odd or even row address reaches the top bit. In other words, for one Data topo, a write operation (WR) is performed first, then a read operation (RD) is performed, and when the read and write operations in the Data topo are all completed, the flip indication signal INVERT is activated. It should be appreciated that the inversion indication signal INVERT is used to control the input of the next DATA topo, and the inversion indication signal INVERT is different from the second pre-selected signal DATA <1>, wherein INVERT is used to control the input of the same DATA topo.

In yet another embodiment of the present disclosure, as shown in fig. 17, a memory 60 provided by an embodiment of the present disclosure is shown, the memory 60 including the test circuit 10 of any one of the previous embodiments.

The foregoing is merely a preferred embodiment of the present disclosure, and is not intended to limit the scope of the present disclosure.

It should be noted that in this disclosure, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises the element.

The foregoing embodiment numbers of the present disclosure are merely for description and do not represent advantages or disadvantages of the embodiments.

The methods disclosed in the several method embodiments provided in the present disclosure may be arbitrarily combined without collision to obtain a new method embodiment.

The features disclosed in the several product embodiments provided in the present disclosure may be combined arbitrarily without conflict to obtain new product embodiments.

The features disclosed in the several method or apparatus embodiments provided in the present disclosure may be arbitrarily combined without any conflict to obtain new method embodiments or apparatus embodiments.

The foregoing is merely a specific embodiment of the disclosure, but the protection scope of the disclosure is not limited thereto, and any person skilled in the art can easily think about changes or substitutions within the technical scope of the disclosure, and it should be covered in the protection scope of the disclosure. Therefore, the protection scope of the present disclosure shall be subject to the protection scope of the claims.

Claims

1. A test circuit is characterized in that the test circuit performs read-write test on a storage array by utilizing a plurality of preset data topologies, and the test circuit comprises:

The first state signal is used for selecting one of a first data sequence and a second data sequence as a target data sequence, the second state signal indicates whether each data of the target data sequence is overturned, and the target data sequence or the overturned target data sequence is used for forming the preset data topology;

the first control module is further configured to generate and output a read-write indication signal based on the received address jump pulse, wherein the read-write indication signal indicates a read operation or a write operation;

the test circuit further comprises a test module;

2. The test circuit of claim 1, wherein the test circuit comprises a plurality of test circuits,

The preset data topologies have A groups, each group of the preset data topologies comprises a first data topology and a second data topology, and each of the first data topology and the second data topology comprises an odd data topology and an even data topology;

3. The test circuit of claim 1, wherein the test circuit comprises a plurality of test circuits,

The first control module is specifically configured to control the level state of the parity indicating signal to turn over once every 1 address jump pulse is received, control the level state of the read-write indicating signal to turn over once every 2 address jump pulses are received, control the level state of the turning over indicating signal to turn over once every 4 address jump pulses are received, and generate 1 topology indicating signal every 8 address jump pulses are received.

4. The test circuit of claim 1, wherein the first control module comprises:

5. The test circuit of claim 4, wherein the state decoding module comprises a counting unit and C decoding units, the number of intermediate decoding signals being C;

6. The test circuit of claim 5, wherein the second control module comprises:

7. The test circuit of claim 6, wherein the first logic unit comprises:

8. The test circuit of claim 5, wherein the first signal unit comprises a first flip-flop, a clock terminal of the first flip-flop receiving the address jump pulse, an input terminal of the first flip-flop being connected to an inverting output terminal thereof, a non-inverting output terminal of the first flip-flop outputting the parity indication signal;

9. The test circuit of claim 8, wherein in the case of 2a=12, b=3, c=5;

10. The test circuit of claim 7, wherein the preprocessing unit comprises a first logic, a second logic, a third logic, and a fourth logic;

11. The test circuit of claim 7, wherein the selection unit comprises a first selector, a second selector, a third selector, and a fourth selector;

12. The test circuit of claim 6, wherein the test circuit comprises a plurality of test circuits,

13. The test circuit of claim 9, wherein all reset terminals of the first flip-flop through the eighth flip-flop receive a start signal;

And if the starting signal indicates that the test circuit starts working, the first trigger to the eighth trigger execute reset operation.

14. A memory comprising the test circuit of any of claims 1-13.