CN119165806A - Battery simulator synchronization method, device and storage medium - Google Patents
Battery simulator synchronization method, device and storage medium Download PDFInfo
- Publication number
- CN119165806A CN119165806A CN202411654374.5A CN202411654374A CN119165806A CN 119165806 A CN119165806 A CN 119165806A CN 202411654374 A CN202411654374 A CN 202411654374A CN 119165806 A CN119165806 A CN 119165806A
- Authority
- CN
- China
- Prior art keywords
- simulator
- module
- output
- battery
- modules
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B19/00—Programme-control systems
- G05B19/02—Programme-control systems electric
- G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
- G05B19/042—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using digital processors
- G05B19/0423—Input/output
-
- G—PHYSICS
- G05—CONTROLLING; REGULATING
- G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
- G05B2219/00—Program-control systems
- G05B2219/20—Pc systems
- G05B2219/21—Pc I-O input output
- G05B2219/21137—Analog to digital conversion, ADC, DAC
Landscapes
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Automation & Control Theory (AREA)
- Charge And Discharge Circuits For Batteries Or The Like (AREA)
Abstract
The application discloses a battery simulator synchronization method, a device and a storage medium, wherein control modules of a plurality of battery simulators CAN be connected together through a CAN bus or a CANFD bus, so that output adjustment parameters required by each output channel module CAN be accurately transmitted to the corresponding battery simulator, and simultaneously, the synchronous output control of all the output channel modules CAN be realized by designing a first clock line, a second clock line, a first enabling line and a second enabling line and skillfully utilizing the change of enabling signals and the change of clock signals.
Description
Technical Field
The present application relates to the field of source-based systems, and in particular, to a method and apparatus for synchronizing a battery simulator, and a storage medium.
Background
At present, when a plurality of battery simulators are needed to be connected in parallel or in series and synchronous output is carried out on a plurality of output channels, a large output synchronous error is often caused due to inconsistent time of receiving data by each channel, and synchronous control cannot be formed due to the existence of the error, so that the requirements under a synchronous application scene cannot be met.
Disclosure of Invention
The application aims to provide a battery simulator synchronization method, a device and a storage medium, which improve the synchronization of battery simulators in the parallel or serial process.
According to the battery simulator synchronization method of the embodiment of the first aspect of the application, the battery simulators in the multichannel battery simulator platform are synchronized, each battery simulator comprises a control module, an FPGA module and a plurality of output channel modules, the control modules are in communication connection with the FPGA module, serial communication lines, first enabling lines and first clock lines are connected between the FPGA module and each output channel module, the battery simulators are sequentially arranged, a second enabling line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators, the FPGA modules output synchronous clock signals to the corresponding output channel modules through the first clock lines and the second clock lines, and the control modules of the battery simulators are connected through CAN buses or CANFD buses;
The battery simulator synchronization method is applied to a control module of the first simulator, and comprises the following steps:
Acquiring setting data, wherein the setting data comprises output adjustment parameters of a plurality of output channel modules in each battery simulator;
Transmitting output adjustment parameters corresponding to a plurality of output channel modules in the first simulator to an FPGA module in the first simulator;
Transmitting output adjustment parameters corresponding to a plurality of output channels in each second simulator to the FPGA module in the corresponding second simulator, so that a control module in each second simulator feeds back a slave response signal to a control module of the first simulator;
Under the condition that the slave response signals returned by each second simulator are received, the first enabling lines and each second enabling line are adjusted to be high level, and output adjustment parameters corresponding to a plurality of output channel modules in each battery simulator are transmitted to each output channel module, so that each output channel module returns channel response signals to the corresponding control module;
And under the condition that the channel response signals returned by each output channel transmission in the first simulator are received, the first enabling line and the second enabling line are adjusted to be low level, so that each output channel module responds to the trigger edge signals in the corresponding first clock line or the second clock line under the condition that the falling edge signals in the corresponding first enabling line or the second enabling line are detected, and output operation is executed according to the received output adjustment parameters.
According to the battery simulator synchronization device, a plurality of battery simulators in a multi-channel battery simulator platform are synchronized, each battery simulator comprises a control module, an FPGA module and a plurality of output channel modules, the control modules are in communication connection with the FPGA module, serial communication lines, first enabling lines and first clock lines are connected between the FPGA module and each output channel module, the battery simulators are sequentially arranged, a second enabling line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators, the FPGA modules output synchronous clock signals to the corresponding output channel modules through the first clock lines and the second clock lines, the control modules of the battery simulators are connected through CAN buses or CANFD buses, the battery simulators in the first position are first simulators, and the rest battery simulators are second simulators;
The battery simulator synchronization device, applied to the control module of the first simulator, comprises:
the setting data acquisition module is used for acquiring setting data, wherein the setting data comprises output adjustment parameters of a plurality of output channel modules in each battery simulator;
The first data sending module is used for transmitting output adjustment parameters corresponding to the output channel modules in the first simulator to the FPGA module in the first simulator;
The second data sending module is used for transmitting output adjustment parameters corresponding to a plurality of output channels in each second simulator to the FPGA module in the corresponding second simulator so that the control module in each second simulator feeds back a slave machine response signal to the control module of the first simulator;
The first synchronous control module is used for adjusting the first enabling line and each second enabling line to be in a high level under the condition that the slave machine response signal returned by each second simulator is received, and transmitting output adjustment parameters corresponding to a plurality of output channel modules in each battery simulator to each output channel module so that each output channel module returns a channel response signal to the corresponding control module;
and the second synchronous control module is used for adjusting the first enabling line and the second enabling line to be low level under the condition that the channel response signal returned by each output channel transmission in the first simulator is received, so that each output channel module responds to the trigger edge signal in the corresponding first clock line or the second clock line under the condition that the falling edge signal in the corresponding first enabling line or the second enabling line is detected, and output operation is executed according to the received output adjustment parameters.
According to an embodiment of the third aspect of the present application, there is stored computer-executable instructions for performing the battery simulator synchronization method as described in the embodiment of the first aspect.
According to the battery simulator synchronization method, device and storage medium, the control modules of the battery simulators CAN be connected together through the CAN bus or the CANFD bus, so that output adjustment parameters required by each output channel module CAN be accurately transmitted to the corresponding battery simulator, and meanwhile, the change of an enabling signal and the change of a clock signal are ingeniously utilized through designing the first clock line, the second clock line, the first enabling line and the second enabling line, so that the transmission of each output adjustment parameter to the corresponding output channel module CAN be realized, and the synchronous output control of all the output channel modules is completed.
Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application.
Drawings
The foregoing and/or additional aspects and advantages of the application will become apparent and may be better understood from the following description of embodiments taken in conjunction with the accompanying drawings in which:
FIG. 1 is a schematic diagram of a multi-channel battery simulator platform according to an embodiment of the present application;
FIG. 2 is a flowchart of a method for synchronizing a battery simulator according to an embodiment of the present application;
fig. 3 is a schematic structural diagram of a synchronization device for a battery simulator according to an embodiment of the application.
Reference numerals:
a control module 110, an FPGA module 120, and an output channel module 130.
Detailed Description
Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.
In the description of the present application, the description of first, second, etc. is for the purpose of distinguishing between technical features only and should not be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated or implicitly indicating the precedence of the technical features indicated.
In the description of the present application, it should be understood that the direction or positional relationship indicated with respect to the description of the orientation, such as up, down, etc., is based on the direction or positional relationship shown in the drawings, is merely for convenience of describing the present application and simplifying the description, and does not indicate or imply that the apparatus or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as limiting the present application.
In the description of the present application, unless explicitly defined otherwise, terms such as arrangement, installation, connection, etc. should be construed broadly and the specific meaning of the terms in the present application can be determined reasonably by a person skilled in the art in combination with the specific content of the technical solution.
The following description of the embodiments of the present application will be made with reference to the accompanying drawings, in which it is apparent that the embodiments described below are some, but not all embodiments of the application.
In order to better describe the battery simulator synchronization method, device and storage medium of the embodiments of the present invention, a multi-channel battery simulator platform is proposed herein, as shown in fig. 1, where the multi-channel battery simulator platform includes a plurality of battery simulators, each battery simulator includes a control module 110, an FPGA (Field Programmable GATE ARRAY ) module 120, a plurality of output channel modules 130, the control module 110 is communicatively connected with the FPGA module 120, a serial communication line, a first enable line and a first clock line are connected between the FPGA module 120 and each output channel module 130, the plurality of battery simulators are sequentially arranged, a second enable line and a second clock line are arranged between the FPGA modules 120 of two adjacent battery simulators, the plurality of FPGA modules 120 output synchronous clock signals to the corresponding output channel modules 130 through the first clock line and the second clock line, and the control module 110 of the plurality of battery simulators is connected with a CAN (Controller Area Network ) bus or a CAN (CAN with Flexible Data rate, CAN bus with flexible data transmission rate;
the control module 110 and the FPGA module 120 are connected through fsmc (Flexible Static Memory Controller, variable static memory controller) buses.
The control modules 110 of the plurality of battery simulators are connected through a CAN bus or a CANFD bus, so that data transmission collision CAN be avoided, and each data frame CAN be transmitted to a designated battery simulator during transmission.
The plurality of battery simulators are sequentially arranged, the battery simulator at the first position is set as a first simulator, the host equipment can be understood, the other battery simulators are set as second simulators, and the slave equipment can be understood.
After the FPGA module 120 in the first simulator is started, clock signals can be sent through the first clock line and the second clock line all the time, and when the FPGA module 120 in each second simulator detects the clock signal sent by the second clock line, the FPGA module 120 in each second simulator outputs the clock signal synchronized with the clock signal output by the FPGA module 120 in the first simulator to the second simulator in the next bit through the second clock line until all the FPGA modules 120 in the battery simulators can output the synchronized clock signals.
The serial communication line can realize data transmission between the FPGA module 120 and the output channel.
The output channel module 130 is built with a controller, and realizes data interaction with the FPGA module 120 and control of output of the output channel module 130 through the controller.
The method, the device and the storage medium for controlling the synchronous output of the parallel operation of the power supply in the embodiment of the invention are described below on the basis of the power supply system.
Referring to fig. 2, fig. 2 is a flowchart of a battery simulator synchronization method according to an embodiment of the present application, which is applied to a control module 110 of a first simulator, and includes:
Acquiring setting data, wherein the setting data comprises output adjustment parameters of a plurality of output channel modules 130 in each battery simulator;
transmitting output adjustment parameters corresponding to the plurality of output channel modules 130 in the first simulator to the FPGA module 120 in the first simulator;
Transmitting output adjustment parameters corresponding to the plurality of output channels in each second simulator to the FPGA module 120 in the corresponding second simulator, so that the control module 110 in each second simulator feeds back a slave response signal to the control module 110 of the first simulator;
In the case of receiving the slave response signal returned from each second simulator, adjusting the first enable line and each second enable line to be at a high level, and transmitting output adjustment parameters corresponding to the plurality of output channel modules 130 in each battery simulator to each output channel module 130, so that each output channel module 130 returns a channel response signal to the corresponding control module 110;
And when the channel response signal returned by each output channel transmission in the first simulator is received, the first enabling line and the second enabling line are adjusted to be low level, so that each output channel module 130 responds to the trigger edge signal in the corresponding first clock line or the second clock line when the falling edge signal in the corresponding first enabling line or the second enabling line is detected, and output operation is performed according to the received output adjustment parameters.
In the embodiment of the present application, the control modules 110 of the plurality of battery simulators are connected together through the CAN bus or the CANFD bus, so that the output adjustment parameters required by each output channel module 130 CAN be accurately transmitted to the corresponding battery simulator, and meanwhile, by designing the first clock line, the second clock line, the first enable line and the second enable line, and skillfully utilizing the variation of the enable signal and the variation of the clock signal, the transmission of each output adjustment parameter to the corresponding output channel module 130 CAN be realized, and the synchronous output control of all the output channel modules 130 CAN be completed.
The setting data can be manually input through an interactive interface on the platform, and can also be directly issued by an upper computer to obtain the setting data.
When the synchronization control is required, the setting data may include an output adjustment parameter corresponding to each output channel module 130 in each battery simulator, and each output channel module 130 may complete the output control according to the received output adjustment parameter.
After obtaining the setting data, the control module 110 in the first simulator may analyze the output adjustment parameters required by the self output channel module 130, and transmit the output adjustment parameters to the FPGA module 120 in the first simulator through the Fsmc bus, where the FPGA module 120 temporarily stores the output adjustment parameters.
After the above-mentioned control module 110 in the first simulator obtains the setting data, the output adjustment parameters required by the output channel module 130 in each second simulator CAN be resolved, and then CAN be transmitted to the control module 110 in each second simulator through the CAN bus or the CANFD bus, and further transmitted to the FPGA module 120 by the control module 110 in each second simulator for temporary storage.
After transmitting the output adjustment parameters to the FPGA module 120 for temporary storage, the control module 110 in each of the second simulators generates a slave response signal, and transmits the slave response signal back to the first simulator through the CAN bus or CANFD bus.
After receiving the slave response signal returned by each second simulator, the first simulator can determine that the FPGA module 120 in each second simulator has completed temporary storage of the output adjustment parameters, at this time, the first enable line and each second enable line can be adjusted to be at a high level, and each battery simulator can transmit the output adjustment parameters temporarily stored in the FPGA module 120 to the corresponding output channel module 130 when detecting the high level signal.
The first simulator can sequentially transmit the output adjustment parameters to the control modules of the corresponding battery simulators from the second position to the last position.
After each of the output channel modules 130 receives the output adjustment parameters, the feedback channel response signals are sent to the corresponding control module 110, and the control module 110 can determine whether there is data missing transmission or false transmission according to the feedback channel response signals, for example, if there is a certain output channel module 130 without feedback channel response signals to the corresponding control module 110, it can determine that there is missing transmission, and at this time, the synchronous control output is meaningless, and an alarm can be generated to inform the operator.
After the first simulator receives the channel response signals fed back by the corresponding multiple output channel modules 130, it can determine that substantially all output channel modules 130 have received the output adjustment parameters, at this time, the first enable line and each second enable line may be adjusted to be low level, when each battery simulator detects the low level signal, each output channel module 130 may wait for a transition of the clock signal in the first clock line or the second clock line, for example, wait for a rising edge, and when the rising edge of the clock signal is identified, finish outputting according to the received output adjustment parameters.
It should be noted that, the clock signals in the first clock line or the second clock line are synchronous, and thus, the plurality of output channel modules 130 can complete synchronous output control.
It should be further noted that, although the plurality of battery simulators are generally of the same model, and there may be a slight difference in data transmission time between the two battery simulator internal control modules 110, the FPGA module 120 and the output channel module 130 due to the manufacturing process problem, the first simulator needs to perform the level adjustment control of the first enable line and each second enable line after the channel response signal, and this short time is enough to compensate for the foregoing time error, and the output channel module 130 will output without the second simulator, and the channel response signal will not be fed back yet.
In some embodiments, the transmitting the output adjustment parameters corresponding to the plurality of output channels in each second simulator to the FPGA module 120 in the corresponding second simulator includes:
Transmitting output adjustment parameters corresponding to the plurality of output channels in each second simulator to the corresponding control module 110 in the second simulator, so that the control module 110 in each second simulator transmits the received output adjustment parameters to the corresponding FPGA module 120, and after the FPGA module 120 receives the output adjustment parameters, transmits a slave response signal to the control module 110 of the first simulator;
And the first simulator sends the output adjustment parameters corresponding to the next second simulator under the condition that the first simulator receives the slave response signal returned by one second simulator.
The transmission of the output adjustment parameters corresponding to the plurality of output channels in each second simulator to the control module 110 in the corresponding second simulator may be accomplished through a CAN bus and a CANFD bus.
After receiving the output adjustment parameters corresponding to the plurality of output channels, the control module 110 in each of the second simulators may transmit the output adjustment parameters corresponding to the plurality of output channels to the FPGA module 120 through the Fsmc bus. After the transmission of the output adjustment parameter is completed, the control module 110 in the second simulator generates a slave response signal, and feeds back the slave response signal to the first simulator.
Under the condition that the first simulator receives the slave machine response signal returned by one second simulator, the first simulator can send the output adjustment parameter corresponding to the next second simulator, so that the conflict between the feedback of the slave machine response signal and the output adjustment parameter sent by the second simulator is avoided, and the integrity and the accuracy of the whole flow are ensured.
In some embodiments, transmitting output adjustment parameters corresponding to a plurality of output channels in each second simulator to the corresponding second simulator control module 110 includes:
Generating a slave control data frame according to the output adjustment parameters corresponding to the plurality of output channel modules 130 in each second simulator, wherein the slave control data frame comprises the output adjustment parameters corresponding to the plurality of output channels in the corresponding second simulator and register address data, each control module 110 in each second simulator comprises a plurality of registers, and the register address data of the plurality of registers in the plurality of control modules 110 are different;
the slave control data frame is transmitted to the second simulator control module 110 of the register address data corresponding register through the CAN bus or CANFD bus.
Each battery simulator can comprise a plurality of registers, each register can be allocated with a unique register address, and for convenience of control, the register addresses of the registers in each battery simulator are continuously set, and the plurality of battery simulators sequentially keep the addresses continuous.
The register address data has uniqueness, so that the register address data can be used as a target address in the slave control data frame, and the slave control data frame can be transmitted to the control module 110 of the battery simulator corresponding to the register address data.
In some embodiments, the control module 110 in each second simulator transmits the received output adjustment parameters to the corresponding FPGA module 120 by:
Responding to the data receiving interruption, analyzing the slave control data frame to obtain corresponding output adjustment parameters;
the received output adjustment parameters are transmitted to the corresponding FPGA module 120.
In this embodiment, the multiple battery simulators are connected by using a CAN bus or a CANFD bus, so that the analysis of the slave control data frame and the transmission of the output adjustment parameters CAN be completed by directly using a CAN interrupt mode, and the judgment by using the calculation force of the control module 110 is not needed, i.e. the integrity of data transmission is improved, and the control module 110 CAN better execute other tasks.
In some embodiments, the plurality of registers of each control module 110 includes a synchronous control register and an independent control register, and in the event that register address data in the slave control data frame indicates the synchronous control register, each battery simulator performs an output operation according to the received output adjustment parameter after triggering the edge signal in response to the corresponding first clock line or second clock line;
the battery simulator synchronization method further comprises the steps of:
under the condition that register address data in the slave control data frame indicates an independent control register, analyzing the slave control data frame to obtain a corresponding output adjustment parameter;
transmitting the corresponding output adjustment parameters to the corresponding output channel module 130;
the plurality of output channel modules 130 are enabled to perform output operations according to the received output adjustment parameters.
In this embodiment, the plurality of registers of each control module 110 include a synchronous control register and an independent control register, and because each register corresponds to unique register address data, only the register address data needs to be judged to determine whether synchronous control is needed, when the register address data is determined to be the independent control register, synchronous control is not needed, the output channel module 130 directly receives the output adjustment parameter and completes output control according to the received output adjustment parameter, when the register is determined to be the synchronous control register, synchronous control is needed, and at this time, the first simulator needs to wait for a synchronous control signal transmitted by a clock line and an enable line, and then completes corresponding operation.
In some embodiments, adjusting the first enable line and each of the second enable lines to a high level includes:
Sending a write enabling signal to the FPGA module 120 in the first simulator, so that the FPGA module 120 in the first simulator adjusts the first enabling line to be high level, and adjusts the second enabling line connected with the adjacent FPGA module 120 to be high level;
The FPGA module 120 in each second simulator synchronously adjusts the second enable line connected to the next FPGA module 120 to be high level.
When the first simulator receives the slave response signal returned by each second simulator, the first simulator sends a write-in enabling signal to the FPGA module 120 in the first simulator, and the FPGA module 120 can adjust the first enabling line to be high level, and synchronously adjust the second enabling line connected with the adjacent FPGA module 120 to be high level. The FPGA module 120 in each second simulator can adjust the enable line connected to the next FPGA module 120 to be high level synchronously.
In this embodiment, the characteristics of the FPGA module 120 are utilized to realize synchronous transmission of the corresponding enable signal.
In some embodiments, transmitting output adjustment parameters corresponding to a plurality of output channel modules 130 in each battery simulator to each output channel module 130 includes:
In the first simulator, when the FPGA module 120 adjusts the first enable line to a high level, the corresponding output adjustment parameter is sent to the corresponding output channel module 130;
In the case that the FPGA module 120 in each second simulator detects a rising edge signal of the second enable line, the FPGA module 120 in each second simulator sends the corresponding output adjustment parameter to the corresponding output channel module 130;
After each output channel module 130 receives the corresponding output adjustment parameter, the corresponding FPGA module 120 returns a channel response signal to the corresponding control module 110.
In this real-time manner, the FPGA module 120 in the first simulator can synchronously reach all the second simulators through the high level output by the second enable line, based on this, when each second simulator detects the rising edge signal of the second enable line, the corresponding output adjustment parameter can be synchronously sent to the corresponding output channel module 130, and when the first enable line is adjusted to the high level, the FPGA module 120 in the first simulator can also send the corresponding output adjustment parameter to the corresponding output channel module 130, so as to realize synchronous control of receiving the output adjustment parameters by all the output channel modules 130.
In some embodiments, adjusting the first enable line and the second enable line to low levels includes:
Sending an output enable signal to the FPGA module 120 in the first simulator, so that the FPGA module 120 in the first simulator adjusts the first enable line of the corresponding output channel module 130 to a low level, and adjusts the second enable line connected to the adjacent FPGA module 120 to a low level;
The FPGA module 120 in each second simulator adjusts the second enable line connected to the next FPGA module 120 to be low level.
In this embodiment, the FPGA module 120 in the first simulator can synchronously reach all the second simulators through the low level output by the second enable line, and then synchronously reach the output channel module 130 of each battery simulator, so that all the output channel modules 130 can synchronously detect the change of the level from the high level to the low level, and then can make the rising edges of subsequently detected clock signals be the same rising edge, thereby realizing high synchronization.
According to the battery simulator synchronization method provided by the embodiment of the application, the execution main body can be a battery simulator synchronization device. In the embodiment of the application, a method for executing the synchronization of the battery simulator by using the synchronization device of the battery simulator is taken as an example, and the synchronization device of the battery simulator provided by the embodiment of the application is described.
Referring to fig. 3, an embodiment of the present application further provides a battery simulator synchronization device, including:
A setting data obtaining module, configured to obtain setting data, where the setting data includes output adjustment parameters of the plurality of output channel modules 130 in each battery simulator;
The first data sending module is configured to transmit output adjustment parameters corresponding to the plurality of output channel modules 130 in the first simulator to the FPGA module 120 in the first simulator;
The second data sending module is configured to transmit output adjustment parameters corresponding to the plurality of output channels in each second simulator to the FPGA module 120 in the corresponding second simulator, so that the control module 110 in each second simulator feeds back the slave response signal to the control module 110 of the first simulator;
the first synchronous control module is configured to adjust the first enable line and each second enable line to a high level when receiving the slave response signal returned by each second simulator, and transmit output adjustment parameters corresponding to the plurality of output channel modules 130 in each battery simulator to each output channel module 130, so that each output channel module 130 returns a channel response signal to the corresponding control module 110;
And the second synchronous control module is used for adjusting the first enabling line and the second enabling line to be low level under the condition that a channel response signal returned by each output channel transmission in the first simulator is received, so that each output channel module 130 responds to the trigger edge signal in the corresponding first clock line or the second clock line under the condition that the falling edge signal in the corresponding first enabling line or the second enabling line is detected, and output operation is executed according to the received output adjustment parameters.
Furthermore, an embodiment of the present application provides a computer-readable storage medium storing computer-executable instructions that are executed by a processor or control module to cause the processor to perform the battery simulator synchronization method in the above embodiment, for example, to perform the method described above.
Those of ordinary skill in the art will appreciate that all or some of the steps, systems, and methods disclosed above may be implemented as software, firmware, hardware, and suitable combinations thereof. Some or all of the physical components may be implemented as software executed by a processor, such as a central processing unit, digital signal processor, or microprocessor, or as hardware, or as an integrated circuit, such as an application specific integrated circuit. Such software may be distributed on computer readable media, which may include computer storage media or non-transitory media and communication media or transitory media. The term computer storage media includes both volatile and nonvolatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable instructions, data structures, program modules or other data, as known to those skilled in the art. Computer storage media includes, but is not limited to, RAM, ROM, EEPROM, flash memory or other memory technology, CD-ROM, digital versatile disk DVD or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by the computer. Furthermore, as is well known to those of ordinary skill in the art, communication media typically embodies computer readable instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media.
The embodiments of the present application have been described in detail with reference to the accompanying drawings, but the present application is not limited to the above embodiments, and various changes can be made within the knowledge of one of ordinary skill in the art without departing from the spirit of the present application.
Claims (10)
1. The battery simulator synchronization method is characterized by comprising the steps of synchronizing a plurality of battery simulators in a multichannel battery simulator platform, wherein each battery simulator comprises a control module, an FPGA module and a plurality of output channel modules, the control module is in communication connection with the FPGA module, a serial port communication line, a first enabling line and a first clock line are connected between the FPGA module and each output channel module, the plurality of battery simulators are sequentially arranged, a second enabling line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators, the plurality of FPGA modules output synchronous clock signals to the corresponding output channel modules through the first clock line and the second clock line, the control modules of the plurality of battery simulators are connected through a CAN bus or a CANFD bus, the battery simulator at the first position is the first simulator, and the rest battery simulators are the second simulators;
The battery simulator synchronization method is applied to a control module of the first simulator, and comprises the following steps:
Acquiring setting data, wherein the setting data comprises output adjustment parameters of a plurality of output channel modules in each battery simulator;
Transmitting output adjustment parameters corresponding to a plurality of output channel modules in the first simulator to an FPGA module in the first simulator;
Transmitting output adjustment parameters corresponding to a plurality of output channels in each second simulator to the FPGA module in the corresponding second simulator, so that a control module in each second simulator feeds back a slave response signal to a control module of the first simulator;
Under the condition that the slave response signals returned by each second simulator are received, the first enabling lines and each second enabling line are adjusted to be high level, and output adjustment parameters corresponding to a plurality of output channel modules in each battery simulator are transmitted to each output channel module, so that each output channel module returns channel response signals to the corresponding control module;
And under the condition that the channel response signals returned by each output channel transmission in the first simulator are received, the first enabling line and the second enabling line are adjusted to be low level, so that each output channel module responds to the trigger edge signals in the corresponding first clock line or the second clock line under the condition that the falling edge signals in the corresponding first enabling line or the second enabling line are detected, and output operation is executed according to the received output adjustment parameters.
2. The method according to claim 1, wherein the transmitting the output adjustment parameters corresponding to the plurality of output channels in each of the second simulators to the FPGA modules in the corresponding second simulators includes:
Transmitting output adjustment parameters corresponding to a plurality of output channels in each second simulator to a corresponding control module in the second simulator, so that the control module in each second simulator transmits the received output adjustment parameters to a corresponding FPGA module, and after the FPGA module receives the output adjustment parameters, the control module sends the slave response signals to the control module of the first simulator;
And the first simulator sends the output adjustment parameter corresponding to the next second simulator under the condition that the first simulator receives the slave response signal returned by one second simulator.
3. The method according to claim 2, wherein the transmitting the output adjustment parameters corresponding to the plurality of output channels in each of the second simulators to the corresponding control modules in the second simulators includes:
Generating a slave control data frame according to the output adjustment parameters corresponding to the output channel modules in each second simulator, wherein the slave control data frame comprises the output adjustment parameters corresponding to the output channels in the second simulator and register address data, and each control module in the second simulator comprises a plurality of registers, and the register address data of the registers in the control modules are different;
and transmitting the slave control data frame to the control module in the second simulator of the register address data corresponding register through the CAN bus or the CANFD bus.
4. A method of synchronizing battery simulators according to claim 3, wherein the control module in each of the second simulators transmits the received output adjustment parameters to the corresponding FPGA module by:
responding to the data receiving interruption, analyzing the slave control data frame to obtain the corresponding output adjustment parameter;
and transmitting the received output adjustment parameters to the corresponding FPGA modules.
5. The battery simulator synchronization method of claim 3, wherein the plurality of registers of each of the control modules comprises a synchronization control register and an independent control register, wherein each of the battery simulators performs the performing an output operation according to the received output adjustment parameter after the triggering of an edge signal in the response to the corresponding one of the first clock line or the second clock line in a case where the register address data in the slave control data frame is indicated as the synchronization control register;
The battery simulator synchronization method further comprises the following steps:
under the condition that the register address data in the slave control data frame indicates the independent control register, analyzing the slave control data frame to obtain the corresponding output adjustment parameter;
transmitting the corresponding output adjustment parameters to the corresponding output channel modules;
enabling a plurality of output channel modules to execute output operation according to the received output adjustment parameters.
6. The battery simulator synchronization method of claim 1, wherein the adjusting the first enable line and each of the second enable lines to a high level comprises:
sending a write-in enabling signal to an FPGA module in the first simulator so that the FPGA module in the first simulator adjusts the first enabling line to be high level, and adjusts a second enabling line connected with adjacent FPGA modules to be high level;
And the FPGA module in each second simulator synchronously adjusts a second enabling line connected with the next FPGA module to be high level.
7. The method of claim 1, wherein transmitting the output adjustment parameters corresponding to the plurality of output channel modules in each battery simulator to each of the output channel modules comprises:
Under the condition that the FPGA module adjusts the first enabling line to be in a high level in the first simulator, the corresponding output adjusting parameter is sent to the corresponding output channel module;
under the condition that the FPGA module in each second simulator detects the rising edge signal of the second enabling line, the FPGA module in each second simulator sends the corresponding output adjustment parameters to the corresponding output channel modules;
And after each output channel module receives the corresponding output adjustment parameter, returning the channel response signal to the corresponding control module through the corresponding FPGA module.
8. The battery simulator synchronization method of claim 1, wherein the adjusting the first and second enable lines to a low level comprises:
Sending an output enabling signal to an FPGA module in the first simulator so that the FPGA module in the first simulator adjusts a first enabling line corresponding to the output channel module to be low level, and adjusts a second enabling line connected with adjacent FPGA modules to be low level;
And the FPGA module in each second simulator adjusts a second enabling line connected with the next FPGA module to be low level.
9. The battery simulator synchronization device is characterized by being used for synchronizing a plurality of battery simulators in a multichannel battery simulator platform, wherein each battery simulator comprises a control module, an FPGA module and a plurality of output channel modules, the control module is in communication connection with the FPGA module, a serial port communication line, a first enabling line and a first clock line are connected between the FPGA module and each output channel module, the plurality of battery simulators are sequentially arranged, a second enabling line and a second clock line are arranged between the FPGA modules of two adjacent battery simulators, the plurality of FPGA modules output synchronous clock signals to the corresponding output channel modules through the first clock line and the second clock line, the control modules of the plurality of battery simulators are connected through a CAN bus or a CANFD bus, the battery simulator at the first position is the first simulator, and the rest battery simulators are the second simulators;
The battery simulator synchronization device, applied to the control module of the first simulator, comprises:
the setting data acquisition module is used for acquiring setting data, wherein the setting data comprises output adjustment parameters of a plurality of output channel modules in each battery simulator;
The first data sending module is used for transmitting output adjustment parameters corresponding to the output channel modules in the first simulator to the FPGA module in the first simulator;
The second data sending module is used for transmitting output adjustment parameters corresponding to a plurality of output channels in each second simulator to the FPGA module in the corresponding second simulator so that the control module in each second simulator feeds back a slave machine response signal to the control module of the first simulator;
The first synchronous control module is used for adjusting the first enabling line and each second enabling line to be in a high level under the condition that the slave machine response signal returned by each second simulator is received, and transmitting output adjustment parameters corresponding to a plurality of output channel modules in each battery simulator to each output channel module so that each output channel module returns a channel response signal to the corresponding control module;
and the second synchronous control module is used for adjusting the first enabling line and the second enabling line to be low level under the condition that the channel response signal returned by each output channel transmission in the first simulator is received, so that each output channel module responds to the trigger edge signal in the corresponding first clock line or the second clock line under the condition that the falling edge signal in the corresponding first enabling line or the second enabling line is detected, and output operation is executed according to the received output adjustment parameters.
10. A computer-readable storage medium having stored thereon computer-executable instructions for causing a computer to perform the battery simulator synchronization method of claim 1 to 8.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411654374.5A CN119165806B (en) | 2024-11-19 | 2024-11-19 | Battery simulator synchronization method, device and storage medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411654374.5A CN119165806B (en) | 2024-11-19 | 2024-11-19 | Battery simulator synchronization method, device and storage medium |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN119165806A true CN119165806A (en) | 2024-12-20 |
| CN119165806B CN119165806B (en) | 2025-03-21 |
Family
ID=93878921
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411654374.5A Active CN119165806B (en) | 2024-11-19 | 2024-11-19 | Battery simulator synchronization method, device and storage medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119165806B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020111696A1 (en) * | 2000-11-29 | 2002-08-15 | Kai Albrecht | Method and device for synchronizing processes which are performed on a plurality of units |
| CN103543679A (en) * | 2013-10-28 | 2014-01-29 | 深圳万讯自控股份有限公司 | Intelligent type resistance signal isolated gate |
| DE102019102992A1 (en) * | 2019-02-06 | 2020-08-06 | Auto-Intern GmbH | Device and method for recording and processing and outputting synchronized measurement data, and computer program product and use |
| CN112052593A (en) * | 2020-09-07 | 2020-12-08 | 北京交通大学 | A kind of battery operation characteristics and fault simulation simulation operation platform and operation method thereof |
| CN216771895U (en) * | 2021-11-03 | 2022-06-17 | 武汉精能电子技术有限公司 | Power supply management system |
| US20240094299A1 (en) * | 2022-09-21 | 2024-03-21 | Renesas Electronics Corporation | Battery simulator |
-
2024
- 2024-11-19 CN CN202411654374.5A patent/CN119165806B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20020111696A1 (en) * | 2000-11-29 | 2002-08-15 | Kai Albrecht | Method and device for synchronizing processes which are performed on a plurality of units |
| CN103543679A (en) * | 2013-10-28 | 2014-01-29 | 深圳万讯自控股份有限公司 | Intelligent type resistance signal isolated gate |
| DE102019102992A1 (en) * | 2019-02-06 | 2020-08-06 | Auto-Intern GmbH | Device and method for recording and processing and outputting synchronized measurement data, and computer program product and use |
| CN112052593A (en) * | 2020-09-07 | 2020-12-08 | 北京交通大学 | A kind of battery operation characteristics and fault simulation simulation operation platform and operation method thereof |
| CN216771895U (en) * | 2021-11-03 | 2022-06-17 | 武汉精能电子技术有限公司 | Power supply management system |
| US20240094299A1 (en) * | 2022-09-21 | 2024-03-21 | Renesas Electronics Corporation | Battery simulator |
Also Published As
| Publication number | Publication date |
|---|---|
| CN119165806B (en) | 2025-03-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| KR101018542B1 (en) | controller | |
| CN109977435B (en) | Factory operation simulation method, factory operation simulation device and computer storage medium | |
| US20140149805A1 (en) | Slave device, master device, and communication method | |
| CN113507337B (en) | Method, device, medium and equipment for determining clock synchronization precision | |
| US10659536B2 (en) | Method of controlling inverters | |
| CN112598895A (en) | System and method for preventing multi-channel conflict during electric energy meter verification | |
| US20190253497A1 (en) | Control device, control system, control method, and non-transitory computer-readable storage medium | |
| US20170033886A1 (en) | Communication apparatus, lens apparatus and image pickup apparatus including the same | |
| CN108271018B (en) | Space camera electronics emulation test system | |
| CN110727452A (en) | System and method for realizing BMS (battery management system) upgrading through serial port | |
| CN119165806B (en) | Battery simulator synchronization method, device and storage medium | |
| WO2025228461A1 (en) | Address allocation method, battery management system and electronic device | |
| EP4468139A1 (en) | Method and apparatus for synchronizing images from multiple channels, and electronic device | |
| CN117792574B (en) | A method and device for adjusting power line signal transmission rate | |
| CN120091485A (en) | Lighting control system, lighting control method, electronic equipment, medium and product | |
| CN109525347B (en) | Time synchronization method and device | |
| CN106325606A (en) | Signal scanning method and device of infrared touch equipment and touch equipment | |
| CN119544134A (en) | Ethernet-based battery simulator synchronization method, device and storage medium | |
| CN112447040B (en) | Queue order detection method and device, electronic equipment and medium | |
| JP3192890B2 (en) | Parallel test equipment | |
| CN119147802B (en) | Soc synchronous control method, device, equipment and storage medium | |
| CN113820160A (en) | Detection method, detection device and detection system of OBD (on-Board diagnostics) equipment | |
| CN117724447B (en) | Data processing method of simulation device, test simulation device and simulation system | |
| CN119728071B (en) | Chip testing method and device for asynchronous half-duplex communication protocol and testing machine | |
| CN120498999B (en) | Firmware upgrading method and storage medium |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |