CN119152813A - Scan driving circuit, display device and control method of scan driving circuit - Google Patents
Scan driving circuit, display device and control method of scan driving circuit Download PDFInfo
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- CN119152813A CN119152813A CN202411624305.XA CN202411624305A CN119152813A CN 119152813 A CN119152813 A CN 119152813A CN 202411624305 A CN202411624305 A CN 202411624305A CN 119152813 A CN119152813 A CN 119152813A
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- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
- G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
- G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
- G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
- G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
- G09G3/3208—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED] organic, e.g. using organic light-emitting diodes [OLED]
- G09G3/3266—Details of drivers for scan electrodes
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Abstract
本申请涉及一种扫描驱动电路、显示装置及扫描驱动电路控制方法，扫描驱动电路包括多个级联的栅极扫描驱动电路，栅极扫描驱动电路包括：控制单元、独立驱动单元、第一输出单元、第二输出单元和下拉单元；控制单元连接第一输出单元、独立驱动单元和下拉单元；独立驱动单元连接第一输出单元和第二输出单元；下拉单元连接第一输出单元和第二输出单元。该扫描驱动电路的独立驱动单元能够在控制单元作用下，控制第一输出单元和第二输出单元输出两个重叠的扫描信号，使输出的扫描信号能够在输出期间内独立工作，提高扫描驱动电路运行稳定性，并且，由于第一输出单元和第二输出单元共用一个控制单元，可以减小电路面积。
The present application relates to a scanning drive circuit, a display device and a scanning drive circuit control method, wherein the scanning drive circuit includes a plurality of cascaded gate scanning drive circuits, and the gate scanning drive circuit includes: a control unit, an independent driving unit, a first output unit, a second output unit and a pull-down unit; the control unit is connected to the first output unit, the independent driving unit and the pull-down unit; the independent driving unit is connected to the first output unit and the second output unit; the pull-down unit is connected to the first output unit and the second output unit. Under the action of the control unit, the independent driving unit of the scanning drive circuit can control the first output unit and the second output unit to output two overlapping scanning signals, so that the output scanning signals can work independently during the output period, thereby improving the operation stability of the scanning drive circuit, and since the first output unit and the second output unit share a control unit, the circuit area can be reduced.
Description
Technical Field
The present application relates to the field of display technologies, and in particular, to a scan driving circuit, a display device, and a control method of the scan driving circuit.
Background
An Active-matrix organic light-emitting diode (AMOLED) compensation technology is a series of technological innovation strategies designed for solving the defects of uneven brightness, residual image appearance and the like encountered in the manufacturing and using stages of an AMOLED display screen. The technologies comprehensively use a software and hardware method, and aim to optimize the luminous efficiency of each pixel, so that the overall image quality of the display screen is obviously improved.
The compensation strategy is subdivided into two main classes, internal and external. The external compensation strategy is commonly used in commercial organic light emitting semiconductor OLED televisions, and is specially used for correcting the threshold Voltage (VTH) of an IGZO TFT (indium gallium zinc oxide thin film transistor), and the scheme simplifies the design of a pixel circuit, but requires additional driving system support, so that the production cost is increased. On the other hand, the internal compensation circuit technology based on IGZO TFT requires a special structure built in the scan driving circuit to avoid potential problems, which inevitably increases the overall area of the circuit, contrary to the current pursuing of high resolution reduction of available circuit area to create a narrow bezel display product. Therefore, how to ensure stable operation of the system without increasing the circuit area is a problem to be solved.
Disclosure of Invention
The application provides a scanning driving circuit, a display device and a scanning driving circuit control method, which are used for solving the technical problem of how to ensure stable operation of a system and not increase the circuit area.
In a first aspect, the application provides a scan driving circuit, which comprises a plurality of cascaded gate scan driving circuits, wherein the gate scan driving circuits comprise a control unit, an independent driving unit, a first output unit, a second output unit and a pull-down unit;
The control unit is connected with the first output unit, the independent driving unit and the pull-down unit, the independent driving unit is connected with the first output unit and the second output unit, and the pull-down unit is connected with the first output unit and the second output unit;
The independent driving unit controls the first output unit and the second output unit to output two overlapped scanning signals under the action of the control unit.
Optionally, the independent driving unit comprises a clock signal unit and a driving switch;
the first output unit outputs a first scanning signal based on a first clock signal of the clock signal unit under the action of the driving switch;
the second output unit outputs a second scanning signal based on a second clock signal of the clock signal unit under the action of the driving switch;
Wherein the first scan signal and the second scan signal at least partially overlap.
Optionally, the control unit includes a first thin film transistor, a second thin film transistor, a third thin film transistor, a fourth thin film transistor, a fifth thin film transistor, a sixth thin film transistor, a seventh thin film transistor, an eighth thin film transistor, a ninth thin film transistor, and a tenth thin film transistor;
The first end of the first thin film transistor is connected with a first-stage grid scanning signal, the second end of the first thin film transistor is connected with the first end of the second thin film transistor, the first end of the fourth thin film transistor, the grid of the sixth thin film transistor, the grid of the seventh thin film transistor, the grid of the eighth thin film transistor and the first sampling node of the first output unit, and the second end of the second thin film transistor is connected with the first end of the third thin film transistor, the second end of the fourth thin film transistor, the first end of the fifth thin film transistor and the second end of the sixth thin film transistor;
The grid electrode of the fourth thin film transistor is connected with the grid electrode of the fifth thin film transistor, the first end of the seventh thin film transistor, the second end of the tenth thin film transistor and a second sampling node, and the second sampling node is connected with the grid electrode of the ninth thin film transistor and the pull-down unit;
a second end of the seventh thin film transistor is connected with the first end of the eighth thin film transistor and the first end of the ninth thin film transistor;
A first end of the sixth thin film transistor, a first end of the tenth thin film transistor and a second end of the ninth thin film transistor are commonly connected with a high level; the second end of the third thin film transistor, the second end of the fifth thin film transistor and the second end of the eighth thin film transistor are commonly connected with a low level;
The grid electrode of the second thin film transistor is connected with the grid electrode of the third thin film transistor and the level transmission signal of the next level;
and the grid electrode of the tenth thin film transistor is connected with the control end of the driving switch and the fourth clock signal.
Optionally, the first output unit includes an eleventh thin film transistor and a first capacitor;
The first end of the eleventh thin film transistor is connected with the first clock signal, the grid electrode of the eleventh thin film transistor, the first end of the first capacitor and the first end of the driving switch are connected with the first sampling node together, the second end of the eleventh thin film transistor is connected with the second end of the first capacitor, and the second end of the eleventh thin film transistor is used for outputting a first scanning signal.
Optionally, the second output unit includes a thirteenth thin film transistor and a second capacitor;
The first end of the thirteenth thin film transistor is connected with the second clock signal, the grid electrode of the thirteenth thin film transistor, the first end of the second capacitor and the second end of the driving switch are commonly connected with the third sampling node of the second output unit, the second end of the thirteenth thin film transistor is connected with the second end of the second capacitor, and the second end of the thirteenth thin film transistor is used for outputting a second scanning signal.
Optionally, the pull-down unit includes a twelfth thin film transistor and a fourteenth thin film transistor;
A first end of the twelfth thin film transistor is connected with a second end of the eleventh thin film transistor, a grid electrode of the twelfth thin film transistor and a grid electrode of the fourteenth thin film transistor are commonly connected with the second sampling node, and a second end of the twelfth thin film transistor and a second end of the fourteenth thin film transistor are commonly connected with a low level;
The first end of the fourteenth thin film transistor is connected with the second end of the thirteenth thin film transistor.
Optionally, the gate scan driving circuit further includes a stage transfer-out unit including a fifteenth thin film transistor and a sixteenth thin film transistor;
A first end of the fifteenth thin film transistor is connected with the first end of the thirteenth thin film transistor, a grid electrode of the fifteenth thin film transistor is connected with the grid electrode of the thirteenth thin film transistor, a second end of the fifteenth thin film transistor is connected with the first end of the sixteenth thin film transistor, a grid electrode of the sixteenth thin film transistor is connected with the grid electrode of the fourteenth thin film transistor, and a second end of the sixteenth thin film transistor is connected with a low level;
The second end of the fifteenth thin film transistor and the first end of the sixteenth thin film transistor commonly output the level transmission signal of the current level.
Optionally, the driving switch includes a seventeenth thin film transistor;
the first end of the seventeenth thin film transistor is connected with the grid electrode of the eleventh thin film transistor, the second end of the seventeenth thin film transistor is connected with the third sampling node, and the grid electrode of the seventeenth thin film transistor is connected with the grid electrode of the tenth thin film transistor.
In a second aspect, the present application provides a display device including a display panel and a driving circuit;
The display panel comprises a pixel unit array, and the driving circuit is used for driving the pixel unit and comprises the scanning driving circuit in any one of the first aspect.
In a third aspect, the present application provides a scan driving circuit control method applied to the scan driving circuit according to any one of the first aspects, the scan driving circuit control method comprising:
The first output unit and the second output unit are controlled by the independent driving unit to output two overlapped scanning signals.
Compared with the prior art, the technical scheme provided by the embodiment of the application has the advantages that the scanning driving circuit comprises a plurality of cascaded grid scanning driving circuits, wherein each grid scanning driving circuit comprises a control unit, an independent driving unit, a first output unit, a second output unit and a pull-down unit, the control unit is connected with the first output unit, the independent driving unit and the pull-down unit, the independent driving unit is connected with the first output unit and the second output unit, and the pull-down unit is connected with the first output unit and the second output unit. The independent driving unit of the scanning driving circuit can control the first output unit and the second output unit to output two overlapped scanning signals under the action of the control unit, so that the output scanning signals can independently work in the output period, the operation stability of the scanning driving circuit is improved, and the circuit area can be reduced because the first output unit and the second output unit share one control unit.
Drawings
The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments consistent with the application and together with the description, serve to explain the principles of the application.
In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, and it will be obvious to a person skilled in the art that other drawings can be obtained from these drawings without inventive effort.
One or more embodiments are illustrated by way of example and not limitation in the figures of the accompanying drawings, in which like references indicate similar elements, and in which the figures of the drawings are not to be taken in a limiting sense, unless otherwise indicated.
FIG. 1 is a schematic diagram of a scan driving circuit according to an embodiment of the present application;
FIG. 2 is a schematic diagram of a scan driving circuit according to an embodiment of the present application;
FIG. 3 is a timing diagram of a signal according to an embodiment of the present application;
FIG. 4 is a schematic diagram of a reset phase according to an embodiment of the present application;
FIG. 5 is a schematic diagram of a precharge phase provided by an embodiment of the present application;
Fig. 6 is a schematic diagram of a precharge voltage holding phase according to an embodiment of the present application.
The reference numerals are as follows:
101-control unit, 102-independent driving unit, 103-first output unit, 104-second output unit, 105-pull-down unit, 106-stage transmission unit;
T1-first thin film transistor, T2-second thin film transistor, T3-third thin film transistor, T4-fourth thin film transistor, T5-fifth thin film transistor, T6-sixth thin film transistor, T7-seventh thin film transistor, T8-eighth thin film transistor, T9-ninth thin film transistor, T10-tenth thin film transistor, T11-eleventh thin film transistor, T12-twelfth thin film transistor, T13-thirteenth thin film transistor, T14-fourteenth thin film transistor, T15-fifteenth thin film transistor, T16-sixteenth thin film transistor, T17-seventeenth thin film transistor;
C1-first capacitor, C2-second capacitor, VGH-high level, VGL-low level;
gout (2 n-3) -the upper stage gate scan signal, cout (2 n-4) -the upper stage transfer signal, cout (2n+2) -the lower stage transfer signal, cout (2 n) -the present stage transfer signal, gout (2 n-1) -the first scan signal, gout (2 n) -the second scan signal, CLK 1-the first clock signal, CLK 2-the second clock signal, CLK 4-the fourth clock signal;
q [ n ] -first sampling node, QB [ n ] -second sampling node, QA [ n ] -third sampling node.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
The following disclosure provides many different embodiments, or examples, for implementing different structures of the application. In order to simplify the present disclosure, components and arrangements of specific examples are described below. They are, of course, merely examples and are not intended to limit the application. Furthermore, the present application may repeat reference numerals and/or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself dictate a relationship between the various embodiments and/or configurations discussed.
In order to solve the technical problem of how to ensure stable operation of a system and not increase the circuit area in the prior art, the application provides a scanning driving circuit, a display device and a scanning driving circuit control method, which can enable an output scanning signal to independently work in an output period, improve the operation stability of the scanning driving circuit and reduce the circuit area.
Example 1
The first embodiment of the present application provides a scan driving circuit, which includes a plurality of cascaded gate scan driving circuits, as shown in fig. 1, and the gate scan driving circuit includes a control unit 101, an independent driving unit 102, a first output unit 103, a second output unit 104, and a pull-down unit 105.
The connection relationship is such that the control unit 101 connects the first output unit 103, the independent driving unit 102, and the pull-down unit 105, the independent driving unit 102 connects the first output unit 103 and the second output unit 104, and the pull-down unit 105 connects the first output unit 103 and the second output unit 104.
The independent driving unit 102 controls the first output unit 103 and the second output unit 104 to output two overlapped scan signals under the action of the control unit 101.
The independent driving unit of the scanning driving circuit can control the first output unit and the second output unit to output two overlapped scanning signals under the action of the control unit, so that the output scanning signals can independently work in the output period, the running stability of the scanning driving circuit is improved, and the circuit area can be reduced because the first output unit and the second output unit share one control unit.
In one embodiment, the independent drive unit 102 includes a clock signal unit and a drive switch. As shown in fig. 2, the driving switch may be a seventeenth thin film transistor T17, and the clock signal unit may output a clock signal.
The first output unit outputs a first scanning signal based on a first clock signal of the clock signal unit under the action of the driving switch, and the second output unit outputs a second scanning signal based on a second clock signal of the clock signal unit under the action of the driving switch, wherein the first scanning signal and the second scanning signal are at least partially overlapped, for example, can be overlapped by 50%, and the running stability of the system is ensured during the overlapped output period.
In a specific embodiment, the structure of the scan driving circuit is schematically shown in fig. 2, and the control unit includes a first thin film transistor T1, a second thin film transistor T2, a third thin film transistor T3, a fourth thin film transistor T4, a fifth thin film transistor T5, a sixth thin film transistor T6, a seventh thin film transistor T7, an eighth thin film transistor T8, a ninth thin film transistor T9, and a tenth thin film transistor T10.
The connection relationship is as follows:
The first end of the first thin film transistor T1 is connected with the previous stage of grid scanning signal Gout (2 n-3), the second end of the first thin film transistor T1 is connected with the first end of the second thin film transistor T2, the first end of the fourth thin film transistor T4, the grid of the sixth thin film transistor T6, the grid of the seventh thin film transistor T7, the grid of the eighth thin film transistor T8 and the first sampling node Q [ n ] of the first output unit, the second end of the second thin film transistor T2 is connected with the first end of the third thin film transistor T3, the second end of the fourth thin film transistor T4, the first end of the fifth thin film transistor T5 and the second end of the sixth thin film transistor T6;
A gate electrode of the fourth thin film transistor T4 is connected to a gate electrode of the fifth thin film transistor T5, a first end of the seventh thin film transistor T7, a second end of the tenth thin film transistor T10, and a second sampling node QB [ n ], and the second sampling node QB [ n ] is connected to a gate electrode of the ninth thin film transistor T9 and the pull-down unit 105;
The second end of the seventh thin film transistor T7 is connected with the first end of the eighth thin film transistor T8 and the first end of the ninth thin film transistor T9;
The first end of the sixth thin film transistor T6, the first end of the tenth thin film transistor T10 and the second end of the ninth thin film transistor T9 are commonly connected with the high level VGH, and the second end of the third thin film transistor T3, the second end of the fifth thin film transistor T5 and the second end of the eighth thin film transistor T8 are commonly connected with the low level VGL;
The grid electrode of the first thin film transistor T1 is connected with the stage signal Cout (2 n-4) of the upper stage, and the grid electrode of the second thin film transistor T2 is connected with the grid electrode of the third thin film transistor T3 and the stage signal Cout (2n+2) of the lower stage;
The gate of the tenth thin film transistor T10 is connected to the control terminal of the driving switch and the fourth clock signal CLK4.
The first output unit includes an eleventh thin film transistor T11 and a first capacitor C1.
The connection relationship is as follows:
The first end of the eleventh thin film transistor T11 is connected to the first clock signal CLK1, the gate electrode of the eleventh thin film transistor T11, the first end of the first capacitor C1 and the first end of the driving switch are commonly connected to the first sampling node qn, the second end of the eleventh thin film transistor T11 is connected to the second end of the first capacitor C1, and the second end of the eleventh thin film transistor T11 is configured to output the first scan signal Gout (2 n-1).
The second output unit includes a thirteenth thin film transistor T13 and a second capacitor C2.
The connection relationship is as follows:
the first end of the thirteenth thin film transistor T13 is connected to the second clock signal CLK2, the gate of the thirteenth thin film transistor T13, the first end of the second capacitor C2 and the second end of the driving switch are commonly connected to the third sampling node QA [ n ] of the second output unit, the second end of the thirteenth thin film transistor T13 is connected to the second end of the second capacitor C2, and the second end of the thirteenth thin film transistor T13 is used for outputting the second scan signal Gout (2 n).
The pull-down unit includes a twelfth thin film transistor T12 and a fourteenth thin film transistor T14.
The connection relationship is as follows:
The first end of the twelfth thin film transistor T12 is connected with the second end of the eleventh thin film transistor T11, the grid electrode of the twelfth thin film transistor T12 and the grid electrode of the fourteenth thin film transistor T14 are commonly connected with the second sampling node QB [ n ], and the second end of the twelfth thin film transistor T12 and the second end of the fourteenth thin film transistor T14 are commonly connected with the low level VGL;
the first terminal of the fourteenth thin film transistor T14 is connected to the second terminal of the thirteenth thin film transistor T13.
The gate scan driving circuit further includes a stage transfer-out unit 106, and the stage transfer-out unit 106 includes a fifteenth thin film transistor T15 and a sixteenth thin film transistor T16.
The connection relationship is as follows:
The first end of the fifteenth thin film transistor T15 is connected with the first end of the thirteenth thin film transistor T13, the grid electrode of the fifteenth thin film transistor T15 is connected with the grid electrode of the thirteenth thin film transistor T13, the second end of the fifteenth thin film transistor T15 is connected with the first end of the sixteenth thin film transistor T16, the grid electrode of the sixteenth thin film transistor T16 is connected with the grid electrode of the fourteenth thin film transistor T14, the second end of the sixteenth thin film transistor T16 is connected with the low level VGL, and the second end of the fifteenth thin film transistor T15 and the first end of the sixteenth thin film transistor T16 jointly output a level transmission signal Cout (2 n) of the current level.
Specifically, the driving switch includes a seventeenth thin film transistor T17. The first end of the seventeenth thin film transistor T17 is connected to the gate electrode of the eleventh thin film transistor T11, the second end of the seventeenth thin film transistor T17 is connected to the third sampling node QA n, and the gate electrode of the seventeenth thin film transistor T17 is connected to the gate electrode of the tenth thin film transistor T10.
In the present embodiment, the scanning driving circuit is composed of 17 thin film transistors TFT (T1 to T17) and two capacitors (C1, C2). The circuit operates in eight periods t1 to t8, the timing chart of the signals is shown in fig. 3, 6 (three in a single stage) clock signals are used by the circuit, 2 direct current signals VGL, VGH, and next, the operation of the scanning driving circuit for the eight periods will be described in detail.
T1 reset phase
As shown in fig. 4, when Cout (2 n-4) and CLKL4 signals become high level voltages, low level voltages of Gout (2 n-3) are applied to Q (n) and QA (n) through T1 and T17. Therefore, the nodes Q (n) and QA (n) are reset to VGL. Meanwhile, as CLK4 turns on T10, the voltage of QB (n) is reset to VGH.
T2 precharge phase
As shown in fig. 5, the schematic diagram of the precharge phase is shown in fig. 5, during the precharge period, T1 is turned on by the Cout (2 n-4) signal, and when the Gout (2 n-3) signal becomes the high level voltage of VGH, the voltage of Q (n) is charged to the high level voltage. CLK4 turns on T17 so node QA (n) is also charged to the high level voltage of Q (n). Since T7, T8 and T10 are turned on at the same time, the voltage of QB (n) connection VGL, QB (n) is discharged to VGL. VGH applies a high voltage through T6 to the source node of T4, the gate-source Voltage (VGS) of T4 is lower than VTH, and T4 is turned off. Therefore, the nodes Q (n) and QA (n) can maintain a high level voltage. The voltages of Gout (2 n-1) and Gout (2 n) and Cout (2 n) are determined by the CLK signal and are VGL.
T3 precharge voltage holding stage
As shown in fig. 6, the precharge voltage holding stage is schematically shown in which T1 is turned off when the Cout (2 n-4) signal becomes a low level voltage, and the nodes Q (n) and QA (n) are in a floating state. Since T2 and T4 are completely turned off by applying VGH to the source node through T6, the voltage drop of Q (n) due to the leakage current is prevented. Thus, Q (n) and QA (n) maintain the voltage level during precharge through C1 and C2. When CLK4 goes to a low level voltage, T10 is turned off and QB (n) is discharged to VGL through T7 and T8.
T4:Q (n) bootstrap phase
During this period, node Q (n) is in a floating state because T1, T2, T4, and T17 are all turned off. When the CLK1 signal goes to a high voltage, Q (n) is bootstrapped by the capacitor C1. Subsequently, the low level voltage of QB (n) turns off T12, and T11 outputs Gout (2 n-1) signal. Since the closed T17 independent driving structure is used, the voltage of QA (n) is kept at the bootstrap voltage at this stage.
T5:QA (n) bootstrap phase
When the CLK2 signal goes to a high voltage, QA (n) is bootstrapped by the capacitor C2, similar to the case of Q (n) in the previous period. T13 and T15 output Gout (2 n) and Cout (2 n), respectively. At this point, the voltage of Q (n) is not affected by QA (n) bootstrap, since T17 is still off and the independent drive structure disconnects nodes Q (n) and QA (n). At this stage, gout (2 n) and Gout (2 n-1) output independent scan signals, respectively.
T6:gout (2 n-1) discharge stage
When the CLK1 signal becomes a low level voltage, the voltage of Q (n) falls close to VGH due to the coupling effect of C1. Since the voltage of CLK4 is still VGL, causing T17 to turn off, nodes Q (n) and QA (n) are controlled separately. Therefore, QA (n) and Gout (2 n) are not affected by the change of the Q (n) voltage, and the bootstrap voltage and VGH are maintained, respectively.
T7:Gout (2 n) discharge sustain stage
When the Cout (2n+2) and CLK4 signals become high level voltages of VGH, T2, T3, T10, and T17 are turned on. Nodes Q (n) and QA (n) discharge through T2 and T3 to VGL. T2, T3 and Cout (2n+2) act together to significantly reduce the gate-source Voltage (VGS) of T7 and T8, thereby charging QB (n) through T10 to VGH. Thus, T4 and T5 are also turned on, and Q (n) and QA (n) are discharged at the same time. Meanwhile, the high voltage of QB (n) turns on T12, T14, and T16, discharging the output signal node to the low level voltage VGL.
T8 holding stage
During this period, node QB (n) is in a floating state because CLK4 is a low level voltage, turning off T10. The leakage path T7 of QB (n) is completely closed by applying VGH to the source node of T7, and QB (n) can maintain VGH. Therefore, the voltages of Q (n) and QA (n) are maintained at VGL by the discharge of T4 and T5. Meanwhile, since the high voltage of QB (n) turns on T12, T14 and T16, the output signal can be maintained at a low voltage.
In the above 8 stages, if T17 is not used, during bootstrap, nodes Q (n) and QA (n) are connected to and affected by CLK1 and CLK2, respectively, by capacitive coupling of C1 and C2, and as CLK1 becomes a high level voltage, the voltage of Q (n) increases, and then, when CLK2 becomes VGH, the voltage of Q (n) increases again, and thus, the voltage of Q (n) does not directly reach the bootstrap voltage level. In addition, when T17 is not used, the degree to which the node Q (n) is charged by CLK1 or CLK2 is low because these signals charge C1 and C2 at the same time, and when CLK1 becomes a low level voltage after Gout (2 n) is output, the node Q (n) cannot be maintained at a bootstrap voltage level due to capacitive coupling of C1, and thus two scan signals having an overlap ratio of 50% and being stable cannot be stably output in the T5 stage.
The present embodiment can maintain the bootstrap voltage at the nodes Q (n) and QA (n) during the output of Gout (2 n-1) and Gout (2 n) due to the use of the T17 independent driving structure. When the bootstrap voltage level of Q (n) or QA (n) is higher than VGH, T17 is turned off, and thus the nodes Q (n) and QA (n) can have sufficiently high voltages during bootstrap of each output signal. During capacitor precharge and bootstrap, the voltage of QB (n) is VGL, so that the pull-down TFTs (T12, T14, and T16) are in an off state. Thus, by using a separate driving structure, the proposed scan driving circuit generates two stable output signals with an overlap ratio of 50%. Also, the scan driving circuit can reduce a circuit area because two output signals Gout (2 n-1) and Gout (2 n) of adjacent gate lines share one control unit, and the shift register operation can be successfully demonstrated through the above 8 stages, and thus, with the independent driving structure, the scan driving circuit can exhibit stable operation under a plurality of overlapped output signals.
It should be understood that the scan driving circuit according to the embodiment of the present application may also appropriately adjust the signal timing and the circuit scheme according to the output signals to generate a plurality of output signals having different timings, which is not limited.
Example 2
Based on the same technical concept, a second embodiment of the present application provides a display device including a display panel and a driving circuit;
the display panel includes a pixel cell array, and a driving circuit for driving the pixel cells, including the scan driving circuit of any one of the first embodiments.
The driving circuit of the display device can output two independent and overlapped scanning signals, so that the output scanning signals can independently work in the output period, the running stability of the system is improved, and the circuit area of the display device can be reduced because the first output unit and the second output unit share one control unit.
Example 3
A scan driving circuit control method, which is applied to the scan driving circuit according to any one of the first embodiments, comprising:
The first output unit and the second output unit are controlled by the independent driving unit to output two overlapped scanning signals.
According to the method, the first output unit and the second output unit can be controlled by the independent driving unit to output two overlapped scanning signals, so that the running stability of the system is improved.
The apparatus embodiments described above are merely illustrative, wherein the elements illustrated as separate elements may or may not be physically separate, and the elements shown as elements may or may not be physical elements, may be located in one place, or may be distributed over a plurality of network elements. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
From the above description of embodiments, it will be apparent to those skilled in the art that the embodiments may be implemented by means of software plus a general purpose hardware platform, or may be implemented by hardware. Based on such understanding, the foregoing technical solution may be embodied essentially or in a part contributing to the related art in the form of a software product, which may be stored in a computer readable storage medium, such as ROM/RAM, a magnetic disk, an optical disk, etc., including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform the method described in the respective embodiments or some parts of the embodiments.
It is to be understood that the terminology used herein is for the purpose of describing particular example embodiments only, and is not intended to be limiting. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. The terms "comprises," "comprising," "includes," "including," and "having" are inclusive and therefore specify the presence of stated features, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components, and/or groups thereof. The method steps, processes, and operations described herein are not to be construed as necessarily requiring their performance in the particular order described or illustrated, unless an order of performance is explicitly stated. It should also be appreciated that additional or alternative steps may be used.
It should be understood that the specific embodiments described herein are for purposes of illustration only and are not intended to limit the scope of the application. In the description, suffixes such as "module", "part" or "unit" for representing elements are used only for facilitating the description of the present application, and have no specific meaning per se. Thus, "module," "component," or "unit" may be used in combination.
The foregoing is only a specific embodiment of the application to enable those skilled in the art to understand or practice the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (10)
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411624305.XA CN119152813A (en) | 2024-11-14 | 2024-11-14 | Scan driving circuit, display device and control method of scan driving circuit |
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| Application Number | Priority Date | Filing Date | Title |
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| CN202411624305.XA CN119152813A (en) | 2024-11-14 | 2024-11-14 | Scan driving circuit, display device and control method of scan driving circuit |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| CN111210757A (en) * | 2020-02-26 | 2020-05-29 | 深圳市华星光电半导体显示技术有限公司 | Gate drive circuit and display panel |
| CN113689833A (en) * | 2021-07-30 | 2021-11-23 | 惠科股份有限公司 | Drive circuit, multistage drive circuit and display panel |
| CN114267307A (en) * | 2021-11-30 | 2022-04-01 | 惠科股份有限公司 | Drive circuit, gate drive circuit and display panel |
| CN114333720A (en) * | 2021-12-10 | 2022-04-12 | 长沙惠科光电有限公司 | Drive circuit, gate drive circuit and display panel |
| WO2024178814A1 (en) * | 2023-03-01 | 2024-09-06 | 武汉华星光电半导体显示技术有限公司 | Gate driving circuit and display panel |
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2024
- 2024-11-14 CN CN202411624305.XA patent/CN119152813A/en not_active Withdrawn
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN111210757A (en) * | 2020-02-26 | 2020-05-29 | 深圳市华星光电半导体显示技术有限公司 | Gate drive circuit and display panel |
| CN113689833A (en) * | 2021-07-30 | 2021-11-23 | 惠科股份有限公司 | Drive circuit, multistage drive circuit and display panel |
| CN114267307A (en) * | 2021-11-30 | 2022-04-01 | 惠科股份有限公司 | Drive circuit, gate drive circuit and display panel |
| CN114333720A (en) * | 2021-12-10 | 2022-04-12 | 长沙惠科光电有限公司 | Drive circuit, gate drive circuit and display panel |
| WO2024178814A1 (en) * | 2023-03-01 | 2024-09-06 | 武汉华星光电半导体显示技术有限公司 | Gate driving circuit and display panel |
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