CN119125851A - Integrated circuit pull-off test method and system based on ATE equipment - Google Patents
Integrated circuit pull-off test method and system based on ATE equipment Download PDFInfo
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- CN119125851A CN119125851A CN202411586291.7A CN202411586291A CN119125851A CN 119125851 A CN119125851 A CN 119125851A CN 202411586291 A CN202411586291 A CN 202411586291A CN 119125851 A CN119125851 A CN 119125851A
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- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2832—Specific tests of electronic circuits not provided for elsewhere
- G01R31/2834—Automated test systems [ATE]; using microprocessors or computers
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2855—Environmental, reliability or burn-in testing
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Abstract
本发明涉及集成电路技术领域，具体涉及一种基于ATE设备的集成电路拉偏测试方法及系统，包括以下步骤：上位机通过GPIB与ATE设备连接，启动上位机软件，启动相应的测试项目；控制ATE设备进行电压拉偏测试，得到芯片的最低和最高运行电压，同时进行频率拉偏测试，得到芯片最高运行频率；在芯片最低和最高运行电压的之间选取固定的电压步进值进行频率拉偏测试；根据拉偏的结果绘制组合拉偏二维结果图，得到芯片的最佳工作电压和频率范围。本发明能确定集成电路的电源电压和时钟频率的极限值，探测其边界和冗余情况。通过可靠性试验前后的拉偏测试，可评估性能退化。
The present invention relates to the technical field of integrated circuits, and in particular to a method and system for testing an integrated circuit deviation based on an ATE device, comprising the following steps: a host computer is connected to the ATE device via a GPIB, the host computer software is started, and the corresponding test items are started; the ATE device is controlled to perform a voltage deviation test to obtain the minimum and maximum operating voltages of the chip, and a frequency deviation test is performed at the same time to obtain the maximum operating frequency of the chip; a fixed voltage step value is selected between the minimum and maximum operating voltages of the chip to perform a frequency deviation test; a combined deviation two-dimensional result diagram is drawn according to the deviation result to obtain the optimal operating voltage and frequency range of the chip. The present invention can determine the limit values of the power supply voltage and clock frequency of the integrated circuit, and detect its boundaries and redundancy. Performance degradation can be evaluated through deviation tests before and after reliability tests.
Description
Technical Field
The invention relates to the technical field of integrated circuits, in particular to an integrated circuit bias testing method and system based on ATE equipment.
Background
Before integrated circuits enter the market, the wafer (CP) and finished product (FT) must be tested on Automated Test Equipment (ATE). Conventional ATE testing typically evaluates integrated circuits using standard supply voltages and clock frequencies at normal or extreme temperature conditions. However, this approach does not cover all possible combinations of voltage and clock frequencies and therefore does not determine the normal operating boundary conditions of the integrated circuit under these combinations. In the aging test of the reliability test, the finished product (FT) is only tested on ATE equipment before and after aging, and whether the chip can normally work under the standard power supply voltage and the clock frequency can only be judged, so that the highest clock frequency which can be born by the integrated circuit under different voltage conditions and the degradation condition of the highest clock frequency before and after aging can not be known.
In the prior art, there are problems that are somewhat reflected in the patent application CN 202410510482.9. The method described in this patent application is mainly focused on the testing technique of integrated circuits, however, it only provides a testing method, which has a certain limitation in practical application. In particular, this approach does not cover all possible voltage and clock frequency combinations, and therefore does not ensure the chip's normal operation under various extreme conditions during testing.
Since this method fails to take into account the impact of different voltage and clock frequency combinations on chip performance, the performance of the chip at the limiting voltage and clock frequency cannot be sufficiently verified in practical applications. This means that although this method can test the functionality of the chip to some extent, it is still an unknown whether the chip can remain in a stable and reliable operating state under extreme operating conditions. Such limitations may lead to unforeseen problems in practical applications, affecting the stability and reliability of the overall system.
Disclosure of Invention
Aiming at the defects of the prior art, the invention discloses an integrated circuit bias testing method and system based on ATE equipment, which are used for solving the problems.
The invention is realized by the following technical scheme:
In a first aspect, the present invention provides a method for testing pull bias of an integrated circuit based on ATE equipment, comprising the steps of:
The upper computer is connected with ATE equipment through GPIB, and starts up the upper computer software to start up the corresponding test items;
Controlling ATE equipment to perform voltage bias test to obtain the lowest and highest operating voltages of the chip, and performing frequency bias test to obtain the highest operating frequency of the chip;
Selecting a fixed voltage stepping value between the lowest and highest running voltages of the chip to perform a frequency bias test;
and drawing a combined pulling bias two-dimensional result graph according to the pulling bias result to obtain the optimal working voltage and frequency range of the chip.
Further, in the method, when the voltage bias is performed, the method includes the following steps:
the ATE equipment provides the input clock frequency and the power supply voltage of a nominal value for the tested device according to an integrated circuit data manual;
The ATE equipment provides test vectors for the tested device, runs the test vectors and judges the test result of the tested device;
If the test result is passing, the upper computer guides the ATE equipment to gradually reduce the power supply voltage, and the test steps are repeated until the result is not passing, so that the lowest working voltage of the integrated circuit is determined and recorded;
the upper computer gradually increases the power supply voltage of the ATE equipment, repeats the testing steps until failure, and records the maximum operating voltage of the integrated circuit.
Further, in the method, when the frequency is biased, the method comprises the following steps:
the ATE equipment provides the input clock frequency and the power supply voltage of a nominal value for the tested device according to an integrated circuit data manual;
The ATE equipment provides test vectors for the tested device, runs the test vectors and judges the test result of the tested device;
If the test result is passed, the upper computer will gradually increase the input clock frequency of the ATE equipment, repeat the test steps until the result fails, and then calculate and record the maximum working frequency of the integrated circuit under the input clock frequency.
Furthermore, in the implementation of the method, when the combined bias operation is performed, an upper computer is used to control Automatic Test Equipment (ATE) at the same time, so that the frequency bias operation is performed on each voltage point in the whole range from the lowest operation voltage to the highest operation voltage of the integrated circuit. This process helps to fully evaluate the performance of an integrated circuit under different voltage conditions.
Furthermore, in the process of drawing the combined bias two-dimensional graph, the upper computer plays a vital role and is responsible for generating a two-dimensional result graph of the integrated circuit power supply voltage and clock frequency boundary conditions. In this figure, the X-axis represents different voltage values, while the Y-axis represents different frequency values. To intuitively display the test results, results that meet the test criteria PASS will be marked green, while results that FAIL the test criteria FAIL will be marked red. In this way, the boundary conditions of the integrated circuit at different supply voltage and clock frequency combinations can be clearly seen.
Furthermore, in the process of carrying out the combined bias, the upper computer software also has the function of automatically adjusting the test parameters according to the test result. Specifically, the upper computer software dynamically adjusts the step values of the voltage and the frequency according to the previous test result. The self-adaptive adjustment mechanism can improve the efficiency and accuracy of the test and ensure that the performance limit of the integrated circuit is found in the shortest time.
Furthermore, in the whole test process, the upper computer software can record the voltage, frequency and test result data of each test point in real time. These data include not only the instantaneous values during the test, but also the final test results. All of this data is stored in a database for subsequent analysis and querying. In this way, the integrity and traceability of the test data can be ensured, providing powerful data support for performance evaluation and fault diagnosis of the integrated circuit.
In a second aspect, the present invention provides an integrated circuit bias testing system based on ATE equipment, where the system is configured to implement the integrated circuit bias testing method based on ATE equipment according to the first aspect, and the system includes
The upper computer is connected with the GPIB and the ATE equipment, operates the GPIB to carry out voltage and frequency bias test, evaluates the tested device, records and counts the result, and generates a two-dimensional result graph;
The ATE equipment is used for providing a bias power supply and a clock signal for the DUT, inputting a test vector and evaluating the result to confirm that the device functions normally;
And the DUT is used for providing a biased power supply voltage for the ATE equipment, running a test vector under a biased input clock and outputting a test result to the ATE equipment.
Still further, the system also includes a database module, the primary function of which is to store and manage test data. The database module is closely connected with the upper computer software and can receive and store the voltage, frequency and test result data of each test point in real time. Moreover, the database module has strong historical test data query and analysis functions, and a user can easily search and analyze past test data through the functions, so that the performance and the historical performance of the equipment are better known.
Furthermore, the system also comprises a user interface module which is closely connected with the upper computer software and is used for displaying real-time data and a two-dimensional result graph in the test process. The design of the user interface module is very humanized, provides rich interaction functions, and allows a user to flexibly adjust the stepping values of voltage and frequency according to the needs and preferences of the user. In addition, the user can select different test items and conditions through the module so as to meet various different test requirements. The design not only improves the flexibility and convenience of the test, but also greatly improves the user experience.
The beneficial effects of the invention are as follows:
The present invention provides an efficient method for accurately determining the minimum and maximum supply voltage thresholds of an integrated circuit under normal operating conditions. In addition, it can identify the maximum clock frequency that the integrated circuit can withstand, as well as the highest operating limit at a particular supply voltage and clock frequency combination. In this way, we can detect in detail the performance boundaries of the integrated circuit in terms of supply voltage and clock frequency.
Furthermore, the invention can also reveal the redundancy condition of the integrated circuit in terms of voltage and frequency, namely, the integrated circuit can still keep stable operation under the condition of exceeding the normal working range. The detection of such redundancy is of great importance for evaluating the reliability of integrated circuits and for designing redundancy protection measures.
Before and after some reliability tests are performed, the invention can help us know the performance degradation condition of the integrated circuit after long-time operation or operation under severe environment by executing the pull bias test. Such testing helps to evaluate the stability and lifetime of the integrated circuit in practical applications, thereby providing an important reference for the design and optimization of the integrated circuit. By the method, the reliability and stability of the integrated circuit under various working conditions can be ensured, and the performance and safety of the whole system are further improved.
Drawings
In order to more clearly illustrate the embodiments of the invention or the technical solutions in the prior art, the drawings that are required in the embodiments or the description of the prior art will be briefly described, it being obvious that the drawings in the following description are only some embodiments of the invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a general flow chart of an integrated circuit bias test method based on ATE equipment of the present invention;
FIG. 2 is a voltage bias flow chart according to an embodiment of the present invention;
FIG. 3 is a frequency offset flow chart of an embodiment of the present invention;
FIG. 4 is a voltage and frequency combining rate bias flow chart of an embodiment of the present invention;
FIG. 5 is a graph of voltage and frequency for an example ADP32F035 chip of the present invention;
fig. 6 is a schematic diagram of an integrated circuit bias test system based on ATE equipment according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
In one embodiment, referring to fig. 1, an integrated circuit bias testing method based on ATE equipment is disclosed, comprising the following steps:
The upper computer is connected with ATE equipment through GPIB, and starts up the upper computer software to start up the corresponding test items;
Controlling ATE equipment to perform voltage bias test to obtain the lowest and highest operating voltages of the chip, and performing frequency bias test to obtain the highest operating frequency of the chip;
Selecting a fixed voltage stepping value between the lowest and highest running voltages of the chip to perform a frequency bias test;
and drawing a combined pulling bias two-dimensional result graph according to the pulling bias result to obtain the optimal working voltage and frequency range of the chip.
In this embodiment, first, the GPIB connection between the host computer and the ATE device is ensured to be correct and correct, and the communication protocols of both parties are consistent. And starting the upper computer software, and opening the corresponding test item. In the upper computer software, a voltage bias test program is selected and executed. The program automatically controls the ATE equipment to bias the voltage across the chip, starting from the nominal voltage of the chip, and gradually decreasing and increasing the voltage until the minimum and maximum operating voltage thresholds of the chip are reached.
The performance of the chip at different voltages, in particular the performance data at the lowest and highest operating voltages, is recorded in this example. These data will serve as reference standards for subsequent testing. Next, a frequency pull bias test is performed. And selecting a frequency bias test program in the upper computer software, and setting the running voltage of the chip to be the lowest and highest voltage values recorded before. The ATE equipment will test the chip in a set frequency range to determine the highest operating frequency of the chip.
The present implementation records the performance of the chip at different frequencies, particularly the data at the highest operating frequency. These data will be used for subsequent voltage & frequency combination bias tests. In the upper computer software, a voltage step value is set for performing a voltage & frequency combination bias test between the lowest and highest operating voltages of the chip. In general, the smaller the step value, the more accurate the test result, but the test time increases accordingly.
The present embodiment performs a voltage & frequency combination bias test. And the ATE equipment comprehensively tests the chip according to the set voltage stepping value and the frequency range, and records the performance of the chip under different voltage and frequency combinations.
After the test of this embodiment is completed, the upper computer software will collect and sort all the test data. Using these data, a combined pull bias two-dimensional result map is generated. The figure will show the performance of the chip at different voltage and frequency combinations, helping engineers evaluate the stability and reliability of the chip.
The present embodiment analyzes the two-dimensional result map to determine the optimum operating voltage and frequency range of the chip. These data are of great significance for chip design optimization, production process control and quality assurance of the final product.
The embodiment sorts the test results and the analysis report into a document for reference by related engineers and management personnel. Ensuring that all relevant personnel know the performance characteristics and potential risks of the chip so as to take corresponding measures in subsequent design, production and application.
In one embodiment, as shown in fig. 2, when the voltage bias is performed, the method includes the following steps:
the ATE equipment provides the input clock frequency and the power supply voltage of a nominal value for the tested device according to an integrated circuit data manual;
The ATE equipment provides test vectors for the tested device, runs the test vectors and judges the test result of the tested device;
If the test result is passing, the upper computer guides the ATE equipment to gradually reduce the power supply voltage, and the test steps are repeated until the result is not passing, so that the lowest working voltage of the integrated circuit is determined and recorded;
the upper computer gradually increases the power supply voltage of the ATE equipment, repeats the testing steps until failure, and records the maximum operating voltage of the integrated circuit.
In one embodiment, as shown in fig. 3, when the frequency is biased, the method includes the following steps:
the ATE equipment provides the input clock frequency and the power supply voltage of a nominal value for the tested device according to an integrated circuit data manual;
The ATE equipment provides test vectors for the tested device, runs the test vectors and judges the test result of the tested device;
If the test result is passed, the upper computer will gradually increase the input clock frequency of the ATE equipment, repeat the test steps until the result fails, and then calculate and record the maximum working frequency of the integrated circuit under the input clock frequency.
In the process of executing the method, when the combined bias operation is involved, an upper computer is used to control Automatic Test Equipment (ATE). The purpose of this operation is to ensure that the frequency pull-bias operation is performed for each voltage point over the entire range of the lowest operating voltage to the highest operating voltage of the integrated circuit. This process is of great importance for the overall evaluation and review of the performance of integrated circuits under different voltage conditions.
In this embodiment, the upper computer plays a vital role in the process of drawing the combined pull-bias two-dimensional graph. It is responsible for generating a two-dimensional result map of the integrated circuit supply voltage versus clock frequency boundary conditions. In this graph, the X-axis represents different voltage values, and the Y-axis represents different frequency values. In order to make the test results more intuitive and easy to understand, results that meet the test criteria PASS will be marked green, while results that FAIL the test criteria FAIL will be marked red. In this way we can clearly observe the boundary conditions of an integrated circuit at different supply voltage and clock frequency combinations, thereby better assessing its performance and stability.
In an embodiment, referring to fig. 4, the voltage and frequency combination frequency bias current process is as follows, and the upper computer software further has a function of automatically adjusting the test parameters according to the test result in the process of executing the combination bias current. Specifically, the upper computer software dynamically adjusts the step values of the voltage and the frequency according to the previous test result. The self-adaptive adjustment mechanism can remarkably improve the efficiency and accuracy of the test and ensure that the performance limit of the integrated circuit is found in the shortest time. By the mode, the upper computer software can intelligently optimize the testing process, and the tedious and inefficient manual parameter adjustment is avoided. The voltage and frequency stepping values can be flexibly adjusted according to actual test conditions, so that the optimal working state of the integrated circuit is more rapidly approximated. The intelligent testing method not only improves the testing efficiency, but also greatly reduces the time required by the testing, so that the whole testing process is more efficient and accurate.
In this embodiment, the upper computer software records the voltage, frequency and test result data of each test point in real time during the whole test process. These data include not only the instantaneous values during the test, but also the final test results. All of this data is stored in a database for subsequent analysis and querying. In this way, the integrity and traceability of the test data can be ensured, providing powerful data support for performance evaluation and fault diagnosis of the integrated circuit. In addition, the upper computer software can also classify and mark the data in detail so as to quickly locate and retrieve relevant information when needed. The real-time recording and detailed classifying method not only improves the data processing efficiency, but also enhances the data reliability, thereby providing more accurate and comprehensive reference basis for engineers in integrated circuit design and optimization.
In one embodiment, as shown in FIG. 5, using an ADP32F035 chip as an example, ATE equipment is of the CHROMA3380 type. First, the highest and lowest operating voltages of the ADP32F035 chip were determined by the voltage bias test. The test results showed that the highest operating voltage of the chip was 1.9 volts and the lowest operating voltage was 1.6 volts. Next, we obtained the highest clock frequency of the chip, with a result of 107 mhz, through the frequency pull-out test. And finally, drawing a two-dimensional result graph of the combined bias by the upper computer through a combined bias test of voltage and frequency. In this figure, the X-axis represents voltage and the Y-axis represents frequency. In this way, we can intuitively see the test results at different voltage and frequency combinations.
From fig. 5 we can observe that ADP32F035 chip has a highest input clock period of 58 ns at a lowest operating voltage of 1.6 volts, corresponding to a frequency of 17.24 mhz. Since the PLL (phase locked loop) inside the chip is fixed to 6 times the frequency, at 1.6 volts, the highest clock frequency is 17.24 times 6, i.e. 103.44 mhz. While at a maximum operating voltage of 1.9 volts, the highest clock frequency of the chip reaches 107.14 megahertz. The nominal VDD voltage for the ADP32F035 chip was 1.8 volts and the clock frequency was 60 mhz. From fig. 5 we can see the performance of the ADP32F035 integrated circuit under different operating conditions. At nominal voltage and clock frequencies, the highest clock frequency of the ADP32F035 integrated circuit has a redundancy of 47 megahertz, whereas the voltage redundancy ranges between 1.6 volts and 1.9 volts.
In one embodiment, an ATE device-based integrated circuit bias test system is provided, comprising
The upper computer is connected with the GPIB and the ATE equipment, operates the GPIB to carry out voltage and frequency bias test, evaluates the tested device, records and counts the result, and generates a two-dimensional result graph;
The ATE equipment is used for providing a bias power supply and a clock signal for the DUT, inputting a test vector and evaluating the result to confirm that the device functions normally;
And the DUT is used for providing a biased power supply voltage for the ATE equipment, running a test vector under a biased input clock and outputting a test result to the ATE equipment.
In one embodiment of the system, a database module is included, among other components. The primary function of this database module is to store and manage test data. The test device is closely connected with upper computer software, and can receive and store the voltage, frequency and test result data of each test point in real time. Moreover, the database module has strong historical test data query and analysis functions, and a user can easily search and analyze past test data through the functions, so that the performance and the historical performance of the equipment are better known. In this way, the user can track and evaluate the operation of the device in detail, and make more informed decisions.
In another embodiment, the system further comprises a user interface module. The module is closely connected with upper computer software and is used for displaying real-time data and a two-dimensional result graph in the test process. The design of the user interface module is very humanized, provides rich interaction functions, and allows a user to flexibly adjust the stepping values of voltage and frequency according to the needs and preferences of the user. In addition, the user can select different test items and conditions through the module so as to meet various different test requirements. The design not only improves the flexibility and convenience of the test, but also greatly improves the user experience. The user can easily make various settings and adjustments so that the test process is more efficient and intuitive. Through the friendly user interface, the user can more intuitively understand the test result, so that more accurate judgment and decision can be made.
In summary, the present invention provides an efficient method for accurately determining the minimum and maximum supply voltage thresholds of an integrated circuit under normal operating conditions. In addition, it can identify the maximum clock frequency that the integrated circuit can withstand, as well as the highest operating limit at a particular supply voltage and clock frequency combination. In this way, we can detect in detail the performance boundaries of the integrated circuit in terms of supply voltage and clock frequency.
The invention also reveals the redundancy of the integrated circuit in terms of voltage and frequency, i.e. the integrated circuit can still maintain stable operation in case of exceeding the normal operating range. The detection of such redundancy is of great importance for evaluating the reliability of integrated circuits and for designing redundancy protection measures.
Before and after some reliability tests are performed, the invention can help us know the performance degradation condition of the integrated circuit after long-time operation or operation under severe environment by executing the pull bias test. Such testing helps to evaluate the stability and lifetime of the integrated circuit in practical applications, thereby providing an important reference for the design and optimization of the integrated circuit. By the method, the reliability and stability of the integrated circuit under various working conditions can be ensured, and the performance and safety of the whole system are further improved.
The foregoing embodiments are merely for illustrating the technical solution of the present invention, but not for limiting the same, and although the present invention has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that modifications may be made to the technical solution described in the foregoing embodiments or equivalents may be substituted for parts of the technical features thereof, and that such modifications or substitutions do not depart from the spirit and scope of the technical solution of the embodiments of the present invention in essence.
Claims (10)
1. An integrated circuit bias testing method based on ATE equipment is characterized by comprising the following steps:
The upper computer is connected with ATE equipment through GPIB, and starts up the upper computer software to start up the corresponding test items;
Controlling ATE equipment to perform voltage bias test to obtain the lowest and highest operating voltages of the chip, and performing frequency bias test to obtain the highest operating frequency of the chip;
Selecting a fixed voltage stepping value between the lowest and highest running voltages of the chip to perform a frequency bias test;
and drawing a combined pulling bias two-dimensional result graph according to the pulling bias result to obtain the optimal working voltage and frequency range of the chip.
2. The method for testing the pull bias of the integrated circuit based on the ATE equipment according to claim 1, wherein the method comprises the following steps when voltage pull bias is carried out:
the ATE equipment provides the input clock frequency and the power supply voltage of a nominal value for the tested device according to an integrated circuit data manual;
The ATE equipment provides test vectors for the tested device, runs the test vectors and judges the test result of the tested device;
If the test result is passing, the upper computer guides the ATE equipment to gradually reduce the power supply voltage, and the test steps are repeated until the result is not passing, so that the lowest working voltage of the integrated circuit is determined and recorded;
the upper computer gradually increases the power supply voltage of the ATE equipment, repeats the testing steps until failure, and records the maximum operating voltage of the integrated circuit.
3. The method for testing the bias of the integrated circuit based on the ATE equipment according to claim 1, wherein the method comprises the following steps when the frequency is biased:
the ATE equipment provides the input clock frequency and the power supply voltage of a nominal value for the tested device according to an integrated circuit data manual;
The ATE equipment provides test vectors for the tested device, runs the test vectors and judges the test result of the tested device;
If the test result is passed, the upper computer will gradually increase the input clock frequency of the ATE equipment, repeat the test steps until the result fails, and then calculate and record the maximum working frequency of the integrated circuit under the input clock frequency.
4. The method according to claim 1, wherein in the combined bias process, the upper computer is controlled to control the ATE test equipment simultaneously, so as to ensure that the frequency bias operation is performed for each voltage point in the range from the lowest voltage to the highest voltage of the integrated circuit.
5. The method for testing the pull bias of the integrated circuit based on the ATE equipment according to claim 1, wherein in the method, in the process of drawing a combined pull bias two-dimensional graph, an upper computer is responsible for generating a two-dimensional result graph of the boundary condition of the power supply voltage and the clock frequency of the integrated circuit, wherein in the two-dimensional result graph, an X axis represents a voltage value and a Y axis represents a frequency value.
6. The method according to claim 1, wherein in the method, in the process of performing combined bias, the upper computer software can also automatically adjust the test parameters according to the test result, and dynamically adjust the step values of the voltage and the frequency according to the previous test result.
7. The method according to claim 1, wherein the upper computer software records the voltage, frequency and test result data of each test point in real time during the test, and stores the data in the database.
8. An ATE device-based integrated circuit bias testing system for implementing the ATE device-based integrated circuit bias testing method according to any one of claims 1-7, comprising
The upper computer is connected with the GPIB and the ATE equipment, operates the GPIB to carry out voltage and frequency bias test, evaluates the tested device, records and counts the result, and generates a two-dimensional result graph;
The ATE equipment is used for providing a bias power supply and a clock signal for the DUT, inputting a test vector and evaluating the result to confirm that the device functions normally;
And the DUT is used for providing a biased power supply voltage for the ATE equipment, running a test vector under a biased input clock and outputting a test result to the ATE equipment.
9. The ATE equipment-based integrated circuit bias test system of claim 8, further comprising a database module for storing and managing test data, the database module being connected to the host software, the database module being capable of receiving and storing in real time the voltage, frequency and test result data of each test site, and the database module providing a query and analysis function for historical test data.
10. The ATE-device-based integrated circuit bias test system of claim 8, further comprising a user interface module coupled to the host software for displaying real-time data and two-dimensional results during the test, wherein the user interface module further provides interactive functionality allowing a user to adjust the step values of voltage and frequency as desired, and to select different test items and conditions.
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