CN119105635A - A mainboard timing control circuit - Google Patents
A mainboard timing control circuit Download PDFInfo
- Publication number
- CN119105635A CN119105635A CN202411571189.XA CN202411571189A CN119105635A CN 119105635 A CN119105635 A CN 119105635A CN 202411571189 A CN202411571189 A CN 202411571189A CN 119105635 A CN119105635 A CN 119105635A
- Authority
- CN
- China
- Prior art keywords
- resistor
- field effect
- effect transistor
- diode
- control circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
- G06F1/24—Resetting means
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/22—Modifications for ensuring a predetermined initial state when the supply voltage has been applied
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K17/00—Electronic switching or gating, i.e. not by contact-making and –breaking
- H03K17/51—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used
- H03K17/56—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices
- H03K17/687—Electronic switching or gating, i.e. not by contact-making and –breaking characterised by the components used by the use, as active elements, of semiconductor devices the devices being field-effect transistors
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
- Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Amplifiers (AREA)
Abstract
本发明公开了一种主板时序控制电路，所述控制电路包括反馈单元，反馈单元包括第一位移寄存器、第十九电阻、第二十电阻、第二十二电阻、第二十三电阻、第一连接器；本发明能够在第一个模块上电后自动建立响应期，对该模块的响应速度进行检测，在响应期内，如果未能收到被检测模块的上电完成信号反馈，电路会自动对下一个模块的上电信号进行限制，确保所有模块都能按照预设顺序稳定启动，能够在任一模块因环境温度因素影响其响应速度时，对下一个模块进行上电限制的同时为被检测模块建立延时期，从而避免错误的报警、复位操作，以及上电信号反馈时间不准确的情况发生。
The present invention discloses a mainboard timing control circuit, the control circuit comprises a feedback unit, the feedback unit comprises a first shift register, a nineteenth resistor, a twentieth resistor, a twenty-second resistor, a twenty-third resistor, and a first connector; the present invention can automatically establish a response period after a first module is powered on, and detect the response speed of the module; within the response period, if the power-on completion signal feedback of the detected module is not received, the circuit will automatically limit the power-on signal of the next module, ensuring that all modules can be stably started in a preset order; when the response speed of any module is affected by the environmental temperature factor, the next module can be powered on and a delay period can be established for the detected module, thereby avoiding the occurrence of erroneous alarms, reset operations, and inaccurate power-on signal feedback time.
Description
Technical Field
The present invention relates to the field of circuit design technologies, and in particular, to a motherboard timing control circuit.
Background
The voltage or current required by starting each module in the main board is different, so that the power-on time sequence control is particularly important, and a reasonable and stable power-on time sequence control scheme can ensure that each component of the computer works cooperatively when the computer is started, so that the problems of hardware conflict or damage and the like are effectively avoided. However, the existing timing control circuit can provide a power-on signal for each module step by step based on the feedback of a clock signal and a preset power-on sequence after receiving a power-on signal, but cannot automatically establish a response period after the first module is powered on and detect the response speed of the module based on the power-on signal, and cannot prevent the problem that the feedback time of the power-on signal is inaccurate when any module affects the response speed of the module due to the ambient temperature, so that the main board timing control circuit is provided, and can automatically establish the response period after the first module is powered on and detect the response speed of the module.
Disclosure of Invention
In view of the above technical problems, an object of the present invention is to provide a timing control circuit for a motherboard, the control circuit includes a feedback unit, the feedback unit includes a first shift register U1, a nineteenth resistor R19, a twentieth resistor R20, a twenty second resistor R22, a twenty third resistor R23, and a first connector P1;
The first pin of the first shift register U1, the second pin of the first shift register U1 and one end of a twenty-third resistor R20 are connected with a power supply, the ninth pin of the first shift register U1 is connected with one end of a nineteenth resistor R19 and the other end of the twentieth resistor R20, the eighth pin of the first shift register U1 is connected with one end of a twenty-second resistor R22 and one end of a twenty-third resistor R23, the other end of the twenty-second resistor R22 is connected with the end of a first connector P1, and the other end of the nineteenth resistor R19 and the other end of the twenty-third resistor R23 are connected with a grounding end.
Further, the control circuit further includes a conversion unit, where the conversion unit includes a second triode Q2, a third triode Q3, a fourth field effect transistor Q4, a seventh triode Q7, a third diode D3, a fifth diode D5, a first capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fourteenth resistor R14, a sixteenth resistor R16, and a seventeenth resistor R17;
The collector of the second triode Q2 is connected with one end of the second resistor R2, one end of the fourth resistor R4 and one end of the sixth resistor R6, the base of the second triode Q2 is connected with one end of the first resistor R1, one end of the fourth triode Q4 is connected with the other end of the first resistor R1, one end of the third resistor R3 is connected, the base of the third triode Q3 is connected with the other end of the fourth resistor R4, the drain of the fourth triode Q4 is connected with one end of the first capacitor C1, the other end of the second resistor R2, the grid of the fourth triode Q4 is connected with the cathode of the third diode D3, one end of the fifth resistor R5 is connected, the collector of the seventh triode Q7 is connected with the anode of the third diode D3, the base of the seventh triode Q7 is connected with the cathode of the fifth diode D5, one end of the seventeenth resistor R17 is connected with one end of the fourteenth resistor R14, one end of the fifth resistor R16, the anode of the fifth diode D5 is connected with the other end of the first connector P1, the other end of the third resistor R3, the sixteenth resistor R6, the sixteenth resistor R14, the other end of the third resistor R2 is connected with the other end of the sixteenth resistor R1, the other end of the third resistor R2 is connected with the sixteenth resistor R5, the other end of the sixteenth resistor R2 is connected with the other end of the power source.
Further, the control circuit further comprises a limiting unit, wherein the limiting unit comprises a second operational amplifier U2, a third operational amplifier U3, a first field effect transistor Q1, a second diode D2, an eighth resistor R8, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12;
The same phase end of the second operational amplifier U2 is connected with one end of an eighth resistor R8, one end of a tenth resistor R10 and the cathode of a second diode D2, the output end of the second operational amplifier U2 is connected with the grid electrode of the first field effect transistor Q1, the same phase end of the third operational amplifier U3 is connected with one end of a third resistor R3, the opposite phase end of the third operational amplifier U3 is connected with one end of an eleventh resistor R11 and one end of a twelfth resistor R12, the output end of the third operational amplifier U3 is connected with the anode of the second diode D2, the drain electrode of the first field effect transistor Q1 is connected with the eighth pin of the first displacement register U1, the other end of the eighth resistor R8, the other end of the eleventh resistor R11 are connected with a power supply, and the source electrode of the first field effect transistor Q1, the other end of the tenth resistor R10, the other end of the twelfth resistor R12 are connected with a grounding end.
Further, the control circuit further comprises a reset unit, wherein the reset unit comprises a ninth field effect transistor Q9, a sixth diode D6, a seventh resistor R7, a ninth resistor R9 and a second connector P2;
The grid electrode of the ninth field effect transistor Q9 is connected with the anode of the sixth diode D6 and the end of the second connector P2, the cathode of the sixth diode D6 is connected with one end of the seventh resistor R7, one end of the ninth resistor R9 and the inverting end of the second operational amplifier U2, the other end of the ninth resistor R9 is connected with a power supply, and the other end of the seventh resistor R7 and the source electrode of the ninth field effect transistor Q9 are connected with a grounding end.
Further, the control circuit further comprises a delay unit, wherein the delay unit comprises a fifth field effect transistor Q5, a sixth field effect transistor Q6, an eighth field effect transistor Q8, a first diode D1, a fourth diode D4, an eighteenth resistor R18 and a twenty-first resistor R21;
The grid electrode of the fifth field effect tube Q5 is connected with the anode of the first diode D1 and the grid electrode of the first field effect tube Q1, the source electrode of the fifth field effect tube Q5 is connected with the grid electrode of the eighth field effect tube Q8, one end of the twenty-first resistor R21 and the end of the third connector P3, the drain electrode of the fifth field effect tube Q5 is connected with the drain electrode of the sixth field effect tube Q6 and one end of the eighteenth resistor R18, the grid electrode of the sixth field effect tube Q6 is connected with the output end of the third operational amplifier U3, the source electrode of the sixth field effect tube Q6 is connected with the cathode of the fourth diode D4, the drain electrode of the eighth field effect tube Q8 is connected with the ninth pin of the first shift register U1, the cathode of the first diode D1 is connected with the same-phase end of the second operational amplifier U2, the anode of the fourth diode D4 is connected with the end of the first connector P1, and the source electrode of the eighth field effect tube Q8, the other end of the eighteenth resistor R18 and the other end of the twenty-first resistor R21 are connected with the ground.
Further, the control circuit further comprises a reset unit, and the reset unit further comprises a twenty-fourth resistor R24;
One end of the twenty-fourth resistor R24 is connected with the grid electrode of the ninth field effect transistor Q9, and the other end of the twenty-fourth resistor R24 is connected with the grounding end.
Further, the control circuit further comprises a delay unit, and the delay unit further comprises a thirteenth resistor R13 and a fifteenth resistor R15;
One end of the thirteenth resistor R13 is connected with the grid electrode of the sixth field effect transistor Q6, one end of the fifteenth resistor R15 is connected with the grid electrode of the fifth field effect transistor Q5, and the other end of the thirteenth resistor R13 and the other end of the fifteenth resistor R15 are connected with the ground terminal.
Compared with the prior art, the invention has the beneficial effects that:
The invention can automatically establish a response period after the first module is electrified, detect the response speed of the module, automatically limit the electrifying signal of the next module if the electrifying completion signal feedback of the detected module is not received in the response period, ensure that all modules can be stably started according to a preset sequence, and establish a delay period for the detected module when any module is electrified to limit the response speed of the next module due to the environmental temperature factor, thereby avoiding false alarm and reset operations and the occurrence of inaccurate electrifying signal feedback time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the following description will briefly explain the drawings needed in the prior art and the embodiments, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings can be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a circuit configuration diagram provided by the present invention.
FIG. 2 is an enlarged view of a first shift register according to the present invention
Detailed Description
In order that the objects and advantages of the invention will become more readily apparent, a more particular description of the invention will be rendered by reference to specific embodiments thereof which are illustrated in the appended drawings, it being understood that the following text is only intended to describe one or more specific embodiments of the invention and is not intended to limit the scope of the invention as defined in the appended claims.
The invention discloses a main board time sequence control circuit, which comprises a feedback unit, wherein the feedback unit comprises a first displacement register U1, a nineteenth resistor R19, a twentieth resistor R20, a twenty second resistor R22, a twenty third resistor R23 and a first connector P1;
The first pin of the first shift register U1, the second pin of the first shift register U1 and one end of a twenty-third resistor R20 are connected with a power supply, the ninth pin of the first shift register U1 is connected with one end of a nineteenth resistor R19 and the other end of the twentieth resistor R20, the eighth pin of the first shift register U1 is connected with one end of a twenty-second resistor R22 and one end of a twenty-third resistor R23, the other end of the twenty-second resistor R22 is connected with the end of a first connector P1, and the other end of the nineteenth resistor R19 and the other end of the twenty-third resistor R23 are connected with a grounding end.
Specifically, the control circuit further includes a conversion unit, where the conversion unit includes a second triode Q2, a third triode Q3, a fourth field effect transistor Q4, a seventh triode Q7, a third diode D3, a fifth diode D5, a first capacitor C1, a first resistor R1, a second resistor R2, a third resistor R3, a fourth resistor R4, a fifth resistor R5, a sixth resistor R6, a fourteenth resistor R14, a sixteenth resistor R16, and a seventeenth resistor R17;
The collector of the second triode Q2 is connected with one end of the second resistor R2, one end of the fourth resistor R4 and one end of the sixth resistor R6, the base of the second triode Q2 is connected with one end of the first resistor R1, one end of the fourth triode Q4 is connected with the other end of the first resistor R1, one end of the third resistor R3 is connected, the base of the third triode Q3 is connected with the other end of the fourth resistor R4, the drain of the fourth triode Q4 is connected with one end of the first capacitor C1, the other end of the second resistor R2, the grid of the fourth triode Q4 is connected with the cathode of the third diode D3, one end of the fifth resistor R5 is connected, the collector of the seventh triode Q7 is connected with the anode of the third diode D3, the base of the seventh triode Q7 is connected with the cathode of the fifth diode D5, one end of the seventeenth resistor R17 is connected with one end of the fourteenth resistor R14, one end of the fifth resistor R16, the anode of the fifth diode D5 is connected with the other end of the first connector P1, the other end of the third resistor R3, the sixteenth resistor R6, the sixteenth resistor R14, the other end of the third resistor R2 is connected with the other end of the sixteenth resistor R1, the other end of the third resistor R2 is connected with the sixteenth resistor R5, the other end of the sixteenth resistor R2 is connected with the other end of the power source.
Specifically, the control circuit further comprises a limiting unit, wherein the limiting unit comprises a second operational amplifier U2, a third operational amplifier U3, a first field effect transistor Q1, a second diode D2, an eighth resistor R8, a tenth resistor R10, an eleventh resistor R11 and a twelfth resistor R12;
The same phase end of the second operational amplifier U2 is connected with one end of an eighth resistor R8, one end of a tenth resistor R10 and the cathode of a second diode D2, the output end of the second operational amplifier U2 is connected with the grid electrode of the first field effect transistor Q1, the same phase end of the third operational amplifier U3 is connected with one end of a third resistor R3, the opposite phase end of the third operational amplifier U3 is connected with one end of an eleventh resistor R11 and one end of a twelfth resistor R12, the output end of the third operational amplifier U3 is connected with the anode of the second diode D2, the drain electrode of the first field effect transistor Q1 is connected with the eighth pin of the first displacement register U1, the other end of the eighth resistor R8, the other end of the eleventh resistor R11 are connected with a power supply, and the source electrode of the first field effect transistor Q1, the other end of the tenth resistor R10, the other end of the twelfth resistor R12 are connected with a grounding end.
Specifically, the control circuit further comprises a reset unit, wherein the reset unit comprises a ninth field effect transistor Q9, a sixth diode D6, a seventh resistor R7, a ninth resistor R9 and a second connector P2;
The grid electrode of the ninth field effect transistor Q9 is connected with the anode of the sixth diode D6 and the end of the second connector P2, the cathode of the sixth diode D6 is connected with one end of the seventh resistor R7, one end of the ninth resistor R9 and the inverting end of the second operational amplifier U2, the other end of the ninth resistor R9 is connected with a power supply, and the other end of the seventh resistor R7 and the source electrode of the ninth field effect transistor Q9 are connected with a grounding end.
Specifically, the control circuit further comprises a delay unit, wherein the delay unit comprises a fifth field effect transistor Q5, a sixth field effect transistor Q6, an eighth field effect transistor Q8, a first diode D1, a fourth diode D4, an eighteenth resistor R18 and a twenty-first resistor R21;
The grid electrode of the fifth field effect tube Q5 is connected with the anode of the first diode D1 and the grid electrode of the first field effect tube Q1, the source electrode of the fifth field effect tube Q5 is connected with the grid electrode of the eighth field effect tube Q8, one end of the twenty-first resistor R21 and the end of the third connector P3, the drain electrode of the fifth field effect tube Q5 is connected with the drain electrode of the sixth field effect tube Q6 and one end of the eighteenth resistor R18, the grid electrode of the sixth field effect tube Q6 is connected with the output end of the third operational amplifier U3, the source electrode of the sixth field effect tube Q6 is connected with the cathode of the fourth diode D4, the drain electrode of the eighth field effect tube Q8 is connected with the ninth pin of the first shift register U1, the cathode of the first diode D1 is connected with the same-phase end of the second operational amplifier U2, the anode of the fourth diode D4 is connected with the end of the first connector P1, and the source electrode of the eighth field effect tube Q8, the other end of the eighteenth resistor R18 and the other end of the twenty-first resistor R21 are connected with the ground.
Specifically, the control circuit further comprises a reset unit, and the reset unit further comprises a twenty-fourth resistor R24;
One end of the twenty-fourth resistor R24 is connected with the grid electrode of the ninth field effect transistor Q9, and the other end of the twenty-fourth resistor R24 is connected with the grounding end.
Specifically, the control circuit further comprises a delay unit, and the delay unit further comprises a thirteenth resistor R13 and a fifteenth resistor R15;
One end of the thirteenth resistor R13 is connected with the grid electrode of the sixth field effect transistor Q6, one end of the fifteenth resistor R15 is connected with the grid electrode of the fifth field effect transistor Q5, and the other end of the thirteenth resistor R13 and the other end of the fifteenth resistor R15 are connected with the ground terminal.
Referring to fig. 1, a clock unit is set in the control circuit, the first connector P1 end is used for receiving a clock signal, the clock signal is fed back by the clock unit, the 1 pin and the 2 pin of the first shift register U1 are input pins, the 3-6 pin and the 10-13 pin are output pins, the 8 pin is the input pin of the clock signal, the 9 pin is a reset pin, the signal of the first connector P1 end is fed back to the ground end through a twenty-second resistor R22 and a twenty-third resistor R23, the signal of the twenty-third resistor R23 end is fed back to the 8 pin of the first shift register U1, when the 8 pin of the first shift register U1 obtains a rising edge signal, the output pin of the first shift register U1 is sequentially output, the signals of the 3 pin, the 4 pin, the 5 pin, the 6 pin, the 10 pin, the 11 pin, the 12 pin and the 13 pin are sequentially, the signals of the output pin of the first shift register U1 are the upper electric signals for controlling each module, the corresponding upper electric module obtains a power supply signal when the output pin is at a high level, the power supply voltage of each module is adjusted by a DC-DC module, and when the power supply voltage of each module is more than the power supply voltage of the corresponding upper electric module is fed back to the nineteenth end through the nineteenth resistor R19, and the nineteenth electric resistor R19 is fed back to the ninth electric resistor when the power module is more than the upper electric module is required to be controlled by the upper electric module.
Referring to fig. 1, in an initial state, a power signal is fed back to a gate of a fourth field effect transistor Q4 through a fourteenth resistor R14 and a sixteenth resistor R16, the signal of the sixteenth resistor R16 is fed back to a ground terminal through a seventh triode Q7 emitter, a seventh triode Q7 base, a seventeenth resistor R17 and the ground terminal, the power signal is positively biased between the seventh triode Q7 emitter and the seventh triode Q7 base, the seventh triode Q7 is conducted, the signal of the sixteenth resistor R16 is fed back to a gate of the fourth field effect transistor Q4 through the seventh triode Q7 and a third diode D3, a fifth resistor R5 is used for discharging parasitic capacitance of the gate of the fourth field effect transistor Q4, the difference between the gate of the fourth field effect transistor Q4 and the source of the fourth field effect transistor Q4 is higher than a conduction threshold, the fourth field effect transistor Q4 is conducted, the power signal is enabled to rise in potential through a sixth resistor R6 and a second resistor R2, the power signal is fed back to a third triode Q2 through a third resistor R3 and a third resistor R1, and the third triode Q2 are grounded, and the power signal is enabled to rise in potential through the third capacitor C1 and the third resistor Q3 and the third resistor R2, the third capacitor is enabled to rise in potential, the third capacitor is enabled to rise in the potential, and the third transistor is enabled to be the potential, and the third transistor is enabled to rise through the third capacitor C1, and the third resistor 3 is enabled to rise in potential, and the third capacitor is enabled to rise to be the third potential.
Referring to fig. 1, when the first connector P1 receives a first clock signal, the first connector P1 signal is at a rising edge of the clock signal, the first connector P1 signal is fed back to the ground through the fifth diode D5 and the seventeenth resistor R17, the base terminal of the seventh triode Q7 obtains the signal feedback of the first connector P1, the seventh triode Q7 is turned off, the fourth fet Q4 is turned off, the potential of the first capacitor C1 continues to rise, the collector terminal potential of the second triode Q2 is pulled high, when the first connector P1 signal is at a falling edge of the first clock signal, the fourth fet Q4 is turned on, the first capacitor C1 signal is fed through the drain of the fourth fet Q4, the source of the fourth fet Q4, the base of the second triode Q2, and the emitter of the second triode Q2 to the ground, the second triode Q2 is conducted, the potential of the first capacitor C1 is reduced to the potential of the base electrode end of the second triode Q2, the potential of the collector electrode end of the second triode Q2 is pulled down, the third triode Q3 is cut off, the potential of the collector electrode end of the third triode Q3 is pulled up, at the moment, the first connector P1 end receives a first clock signal, when the signal of the first connector P1 end is from rising edge to falling edge again, the potential of the collector electrode end of the third triode Q3 is reduced from high to low, the conversion unit restores to an initial state, at the moment, the first connector P1 end receives a second clock signal, so that when the first connector P1 end receives a clock signal, the collector electrode end level of the third triode Q3 is converted, and a signal basis is provided for the limiting unit and the delay unit.
Referring to fig. 1, a power signal is fed back to an inverting terminal of a third operational amplifier U3 through an eleventh resistor R11 and a twelfth resistor R12 to a ground terminal, a collector terminal signal of the third triode Q3 is fed back to an in-phase terminal of the third operational amplifier U3, the power signal is fed back to a ground terminal through an eighth resistor R8 and a tenth resistor R10 to an in-phase terminal of a second operational amplifier U2, when a first clock signal is received by a first connector P1, the third triode Q3 collector terminal is high, the third operational amplifier U3 outputs, an output terminal signal of the third operational amplifier U3 clamps a voltage signal of the in-phase terminal of the second operational amplifier U2 through a second diode D2 and a tenth resistor R10, and simultaneously the second operational amplifier U2 outputs, an output terminal signal of the second operational amplifier U2 is fed back to a gate of a first field effect transistor Q1, a gate of the first field effect transistor Q1 and a source terminal signal of the first field effect transistor Q1 are higher than a threshold voltage difference, when a first clock signal is high, a first signal is fed back to a drain terminal of the first transistor Q1, and a first signal is immediately shifted up to a drain terminal of the first operational amplifier Q1, and a drain terminal of the first operational amplifier is shifted up to a first resistor Q1 is shifted up, and a first signal is shifted to a drain terminal of the first signal is immediately up to a first ground terminal 1.
Referring to fig. 1, the second connector P2 is configured to receive a power-on completion signal fed back by the power-on module, each module to be powered on feeds back the power-on completion signal to the control circuit once after power-on is completed, when the module to obtain the power-on signal does not feed back the power-on completion signal, the module is a detected module, the time from the first module to the second module before power-on is the response period of the power-on completion signal, when the first connector P1 receives the second clock signal, the second connector P2 obtains the power-on completion signal feedback of the detected module (in the response period), the second connector P2 obtains the signal, and is at a high level, otherwise, is at a low level, the signal at the second connector P2 feeds back to the gate of the ninth field effect transistor Q9, the fourth resistor R24 is configured to bleed the parasitic capacitance of the gate of the ninth field effect transistor Q9, when the second connector P2 is at a high level, the voltage difference between the grid electrode of the ninth field effect tube Q9 and the source electrode of the ninth field effect tube Q9 is higher than the conduction threshold, the ninth field effect tube Q9 is conducted, the collector end signal of the third triode Q3 is conducted to the ground end through the drain electrode of the ninth field effect tube Q9 and the source electrode of the ninth field effect tube Q9, the collector end signal of the third triode Q3 is pulled down, the conversion unit is reset to the initial state, the third operational amplifier U3 is cut off, the power supply signal is conducted to the ground end through a ninth resistor R9 and a seventh resistor R7, the signal at the end of the seventh resistor R7 is fed back to the inverting end of the second operational amplifier U2, meanwhile, the signal at the end of the second connector P2 is conducted to the ground end through a sixth diode D6 and a seventh resistor R7, when the end of the second connector P2 is at a high level, the voltage signal at the inverting end of the second operational amplifier U2 is clamped through the sixth diode D6 and the seventh resistor R7, the signal at the end of the seventh resistor R7 is higher than the signal at the end of the tenth resistor R10, meanwhile, the second operational amplifier U2 is cut off, the first field effect transistor Q1 is cut off, when a control circuit obtains a power-on completion signal of a detected module in a response period, the power-on signal of the next module is released to limit, so that the feedback of the power-on signal can be normally obtained, a response period is automatically built after the first module is powered on, the response speed of the module is detected, and in the response period, if the power-on completion signal feedback of the detected module is not received, the circuit can automatically limit the power-on signal of the next module, and therefore all modules can be stably started according to a preset sequence.
Referring to fig. 1, considering that when any module affects its response speed due to ambient temperature, the module controlled by the whole timing circuit will encounter the problem of inaccurate feedback time of the power-up signal, so that it is necessary to establish a delay period for the detected module while performing power-up restriction on the next module, so as to avoid erroneous alarm and reset operations and inaccurate feedback time of the power-up signal, when the first connector P1 end completes the reception of the first clock signal, the third operational amplifier U3 outputs, the second operational amplifier U2 outputs, the signal at the output end of the third operational amplifier U3 is fed back to the gate of the sixth field effect transistor Q6, the thirteenth resistor R13 is used for discharging the parasitic capacitance of the gate of the sixth field effect transistor Q6, the differential pressure between the gate of the sixth field effect transistor Q6 and the source of the sixth field effect transistor Q6 is higher than the on threshold, the sixth field effect transistor Q6 is turned off, meanwhile, the signal of the output end of the second operational amplifier U2 is fed back to the grid electrode of the fifth field effect transistor Q5, the fifteenth resistor R15 is used for discharging parasitic capacitance of the grid electrode of the fifth field effect transistor Q5, the voltage difference between the grid electrode of the fifth field effect transistor Q5 and the source electrode of the fifth field effect transistor Q5 is higher than a conducting threshold value, the fifth field effect transistor Q5 is conducted, when the first connector P1 end finishes receiving a second clock signal, the third operational amplifier U3 is cut off, the signal of the output end of the second operational amplifier U2 clamps the same phase end of the signal through the first diode D1 and the tenth resistor R10 to enable the second operational amplifier U2 to output all the time, at the moment, the sixth field effect transistor Q6 is conducted, the fifth field effect transistor Q5 is conducted, the time from the rising edge of the second clock signal to the rising edge of the third clock signal is a delay period, if the second connector P2 end obtains signal feedback in the delay period, the third operational amplifier U3 and the second operational amplifier U2 are both in the off state, the switching unit and the limiting unit are reset to the initial state, at this time, the first connector P1 end can normally enable the next module to obtain the power-on signal when receiving the clock signal again, if the second connector P2 end still does not obtain the signal feedback during the delay period, the first connector P1 end obtains the clock signal again, at this time, the signal at the first connector P1 end is at the rising edge of the clock signal, the signal at the first connector P1 end is higher than the on threshold value through the fourth diode D4, the source electrode of the sixth field effect tube Q6, the drain electrode of the sixth field effect tube Q6, the eighteenth resistor R18 to the ground end, the signal at the eighteenth resistor R18 is connected to the ground end through the drain electrode of the fifth field effect tube Q5, the source electrode of the fifth field effect tube Q5, the twenty-first resistor R21 to the ground end, the signal feedback at the twenty-first resistor R21 is fed back to the gate electrode of the eighth field effect tube Q8, the difference between the gate electrode of the eighth field effect tube Q8 and the source electrode of the eighth field effect tube Q8 is higher than the on threshold value, the signal at the eighth field effect tube Q8 is higher than the on threshold value, the signal is set up through the nineteenth resistor R19 and the alarm unit is reset to the alarm unit, and the alarm unit is further connected to the ground potential signal through the clock signal feedback unit, the alarm unit is reset to the alarm unit, and the alarm unit is further set to the alarm unit is reset to the ground.
It will be evident to those skilled in the art that the invention is not limited to the details of the foregoing illustrative embodiments, and that the present invention may be embodied in other specific forms without departing from the spirit or essential characteristics thereof. The present embodiments are, therefore, to be considered in all respects as illustrative and not restrictive, the scope of the invention being indicated by the appended claims rather than by the foregoing description, and all changes which come within the meaning and range of equivalency of the claims are therefore intended to be embraced therein. Any reference sign in a claim should not be construed as limiting the claim concerned.
Claims (7)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411571189.XA CN119105635B (en) | 2024-11-06 | 2024-11-06 | A mainboard timing control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411571189.XA CN119105635B (en) | 2024-11-06 | 2024-11-06 | A mainboard timing control circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN119105635A true CN119105635A (en) | 2024-12-10 |
| CN119105635B CN119105635B (en) | 2025-02-11 |
Family
ID=93710688
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411571189.XA Active CN119105635B (en) | 2024-11-06 | 2024-11-06 | A mainboard timing control circuit |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119105635B (en) |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060190746A1 (en) * | 2005-02-24 | 2006-08-24 | Boerstler David W | System and method for automatic calibration of a reference voltage |
| CN105096792A (en) * | 2014-05-12 | 2015-11-25 | 北京大学深圳研究生院 | Adaptive voltage source, shift register and unit thereof, and display |
| US9367711B1 (en) * | 2008-09-04 | 2016-06-14 | Intelleflex Corporation | Battery assisted RFID tag with square-law receiver and optional part time active behavior |
| CN206569078U (en) * | 2017-02-28 | 2017-10-20 | 上海申涪机电科技有限公司 | A kind of train passenger compartment illumination intelligent controller |
| US20230187922A1 (en) * | 2021-12-13 | 2023-06-15 | Stmicroelectronics S.R.L. | Electronic fuse systems and devices |
| CN118212891A (en) * | 2024-05-21 | 2024-06-18 | 惠科股份有限公司 | Display panel and display device |
-
2024
- 2024-11-06 CN CN202411571189.XA patent/CN119105635B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US20060190746A1 (en) * | 2005-02-24 | 2006-08-24 | Boerstler David W | System and method for automatic calibration of a reference voltage |
| US9367711B1 (en) * | 2008-09-04 | 2016-06-14 | Intelleflex Corporation | Battery assisted RFID tag with square-law receiver and optional part time active behavior |
| CN105096792A (en) * | 2014-05-12 | 2015-11-25 | 北京大学深圳研究生院 | Adaptive voltage source, shift register and unit thereof, and display |
| CN206569078U (en) * | 2017-02-28 | 2017-10-20 | 上海申涪机电科技有限公司 | A kind of train passenger compartment illumination intelligent controller |
| US20230187922A1 (en) * | 2021-12-13 | 2023-06-15 | Stmicroelectronics S.R.L. | Electronic fuse systems and devices |
| CN118212891A (en) * | 2024-05-21 | 2024-06-18 | 惠科股份有限公司 | Display panel and display device |
Also Published As
| Publication number | Publication date |
|---|---|
| CN119105635B (en) | 2025-02-11 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101825916B (en) | Computer system | |
| CN102403988B (en) | Power on reset circuit | |
| CN101923146A (en) | Power Test Control | |
| CN103576816B (en) | Switching on and shutting down control circuit | |
| CN119105635B (en) | A mainboard timing control circuit | |
| WO2022156833A2 (en) | Display hot plugging detection circuit, working method, integrated circuit and electronic device | |
| CN105759929A (en) | Power supply sequence circuit and laptop comprising same | |
| CN118054655A (en) | Power supply circuit, control method thereof and electronic equipment | |
| CN101872229A (en) | Computer power supply and power state signal generation circuit on it | |
| US20110252246A1 (en) | Timing control circuit and power supply using the same | |
| CN113541121B (en) | Hot plug protection circuit, plug device and electronic equipment | |
| CN101751102A (en) | Starting-up signal generating device | |
| CN105448271A (en) | GOA unit, GOA circuit, display device and grid driving method | |
| CN216561698U (en) | Switching on and shutting down circuit and electronic equipment | |
| JP7434344B2 (en) | current limit circuit | |
| CN213547473U (en) | Hardware-based one-key quick startup and shutdown circuit | |
| CN104460920A (en) | Switching circuit and computer device with the same | |
| CN222691711U (en) | A test device for pulse modulator and radio frequency power amplifier | |
| CN108462227B (en) | Control system for realizing DC and Micro USB double charging | |
| CN101996143B (en) | Reset Circuits for Electronic Devices | |
| CN207706423U (en) | A kind of power amplifier and sound equipment applied to sound equipment | |
| CN115754428B (en) | A voltage detection circuit, backup power supply system, smart meter and method | |
| CN218471299U (en) | Signal source insertion detection circuit and device | |
| CN219758719U (en) | Solid state disk clock switching circuit | |
| US9746891B2 (en) | Computer |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| GR01 | Patent grant | ||
| GR01 | Patent grant |