CN119070953B

CN119070953B - FPGA (field programmable gate array) speed reduction bridge, speed adaptation method, electronic equipment and medium

Info

Publication number: CN119070953B
Application number: CN202411163822.1A
Authority: CN
Inventors: 周滔顺; 杜欣; 周书; 蒋辉煌; 陈涛; 袁志明; 郭栋; 鲁东豪
Original assignee: Wuxi Zhongxing Microsystem Technology Co ltd
Current assignee: Wuxi Zhongxing Microsystem Technology Co ltd
Priority date: 2024-08-22
Filing date: 2024-08-22
Publication date: 2025-07-15
Anticipated expiration: 2044-08-22
Also published as: CN119070953A

Abstract

The application provides an FPGA (field programmable gate array) speed reduction bridge, a speed adaptation method, electronic equipment and a medium, wherein the FPGA speed reduction bridge comprises an FPGA multi-speed Ethernet interface, a speed adaptation module, a speed adaptation control module and a protocol adaptation module; the multi-rate Ethernet interface can be configured into one of a plurality of different configuration rates, is connected with external Ethernet equipment and is in data communication with the Ethernet equipment at the configuration rate, the rate adaptation module is connected with the multi-rate Ethernet interface and comprises an asynchronous FIFO for caching Ethernet message data received by the multi-rate Ethernet interface from the Ethernet equipment, the protocol adaptation module is connected with the rate adaptation module and comprises a MAC layer codec module and a PCS layer codec module, and the rate adaptation control module is used for adapting the configuration rate of the multi-rate Ethernet interface and outputting clock signals used by the MAC layer codec module and the PCS layer codec module based on the adapted configuration rate.

Description

FPGA (field programmable gate array) speed reduction bridge, speed adaptation method, electronic equipment and medium

Technical Field

The application belongs to the technical field of chips, and particularly relates to an FPGA (field programmable gate array) speed reduction bridge, a speed adaptation method, electronic equipment and a medium.

Background

With the increasing size of ASIC (Application-SPECIFIC INTEGRATED Circuit, application specific integrated Circuit), it is necessary to fully verify before streaming, and besides the verification means such as EDA/EMU, FPGA (Field-Programmable gate array) prototype verification is becoming an indispensable means for accelerating convergence of verification for a large SOC chip.

The Ethernet interface rate is higher and higher, and the highest rate of an ETH interface standard single 1ink based on the IEEE 802.3 protocol reaches 1.6Tbps. Meanwhile, in order to enable the ASIC chip to be capable of more scenes, the interface is often enabled to support multiple rates, and multiple rates are generally compatible downwards, for example, the rate of a single link of the Ethernet interface supports multiple rate modes of 400G/200G/100G/50G/25G/10G/1G, so that the application scenes are richer. However, since ASIC logic is generally complex, it is generally only possible to run to tens of MHz on FPGA platforms, so that it is necessary to down-convert ASIC logic.

Disclosure of Invention

The application aims to provide an FPGA (field programmable gate array) speed reduction bridge, a speed adaptation method, electronic equipment and a medium, and aims to solve the problems of protocol adaptation, speed adaptation, lossless transmission and the like.

The application provides an FPGA (field programmable gate array) speed-reducing bridge, which comprises an FPGA multi-rate Ethernet interface, a rate adaptation module, a rate adaptation control module and a protocol adaptation module, wherein,

The FPGA multi-rate Ethernet interface can be configured into one of a plurality of different configuration rates, is connected with external Ethernet equipment and is in data communication with the Ethernet equipment at the configured configuration rate;

The rate adaptation module is connected with the FPGA multi-rate Ethernet interface and comprises an asynchronous FIFO for caching Ethernet message data received by the FPGA multi-rate Ethernet interface from the Ethernet equipment;

The protocol adaptation module is connected with the rate adaptation module and comprises an MAC layer encoding and decoding module and a PCS layer encoding and decoding module, wherein the MAC layer encoding and decoding module is used for carrying out MAC layer encoding on Ethernet message data stored by the asynchronous FIFO, and the PCS layer encoding and decoding module is used for carrying out PCS layer encoding on encoded data output by the MAC layer encoding and decoding module;

The rate adaptation control module is used for adapting the configuration rate of the FPGA multi-rate Ethernet interface and outputting clock signals used by the MAC layer encoding and decoding module and the PCS layer encoding and decoding module based on the adapted configuration rate.

In an alternative implementation manner, the FPGA multi-rate ethernet interface includes a first DRP dynamic configuration module, a first memory, a first QPLL frequency synthesizer and a first register, where the first memory is configured to store configuration parameters corresponding to one or more configuration rates, the first DRP dynamic configuration module receives a first configuration signal from external software through a software control interface, configures the first QPLL frequency synthesizer according to the configuration parameters corresponding to the configuration rate specified by the first configuration signal, after the first QPLL frequency synthesizer is configured, the configuration parameters corresponding to the configuration rate specified by the first configuration signal are written into the first register, and the configuration rate specified by the first configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the first memory or the configuration rate specified by the external software.

In an alternative implementation manner, the rate adaptation control module comprises a second DRP dynamic configuration module, a second memory, a second QPLL frequency synthesizer, a CPLL frequency synthesizer and a second register, wherein the second memory is used for storing configuration parameters corresponding to one or more configuration rates, the second DRP dynamic configuration module receives a second configuration signal from external software through a software control interface, configures the second QPLL frequency synthesizer and the CPLL frequency synthesizer according to the configuration parameters corresponding to the configuration rates specified by the second configuration signal, after the second QPLL frequency synthesizer and the CPLL frequency synthesizer are configured, the configuration parameters corresponding to the configuration rates specified by the second configuration signal are written into the second register, and the configuration rate specified by the second configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the second memory or the configuration rate specified by the external software.

In an alternative embodiment, the rate adaptation control module further comprises a first clock buffer, a second clock buffer and a third clock buffer;

The second register is provided with a user configuration frequency division interface, the user configuration frequency division interface is configured to be used for 32 frequency division to obtain a 32 frequency division clock signal, the 32 frequency division clock signal is stored in the first clock buffer to obtain a 32 frequency division clock signal output to the PCS layer encoding and decoding module, the 32 frequency division clock signal is stored in the second clock buffer after being turned off every 32 cycles to obtain a 33 frequency division clock signal output to the MAC layer encoding and decoding module, the 32 frequency division clock signal is turned off every 1 cycle and is stored in the third clock buffer after being turned off every 32 cycles to obtain a 66 frequency division clock signal output to the PCS layer encoding and decoding module.

In an alternative implementation manner, an asynchronous FIFO in the rate adaptation module is provided with a full alarm waterline threshold, a null alarm waterline threshold and a read start waterline threshold, when the data volume in the asynchronous FIFO is greater than or equal to the full alarm waterline threshold, the configuration value of the minimum average frame interval of the MAC layer codec module is triggered to be reduced, and when the data volume in the asynchronous FIFO is less than or equal to the null alarm waterline threshold, the configuration value of the read start waterline threshold is triggered to be increased.

In an alternative embodiment, the asynchronous FIFO in the rate adaptation module is provided with a full alarm waterline threshold, a null alarm waterline threshold and a read start waterline threshold;

When the data amount in the asynchronous FIFO is larger than or equal to the full alarm waterline threshold value, triggering the MAC layer codec module to periodically delete the inter-frame interval of Ethernet message data if the rate adaptation module is configured into an adaptive inter-frame interval adjustment mode until the data amount in the asynchronous FIFO is smaller than or equal to the full alarm waterline threshold value;

When the data volume in the asynchronous FIFO is smaller than or equal to the empty alarm waterline threshold value, if the rate adaptation module is configured into a self-adaptive inter-frame interval adjustment mode, the MAC layer encoding and decoding module is triggered to periodically insert an inter-frame interval into Ethernet message data until the data volume in the asynchronous FIFO is larger than or equal to the empty alarm waterline threshold value, and if the accumulated times of the empty alarm waterline threshold value is larger than or equal to a second set threshold value, the read starting waterline threshold value is regulated.

In an alternative embodiment, the thresholds are ordered from big to small by full alarm watermark threshold, clear full alarm watermark threshold, read enable watermark threshold, clear empty alarm watermark threshold, empty alarm watermark threshold.

The second aspect of the present application provides a rate adaptation method, which is implemented by using the FPGA speed reduction bridge of the first aspect, and includes:

configuring the FPGA multi-rate ethernet interface to one of a plurality of different configuration rates;

And the rate adaptation control module is used for adapting the configuration rate of the FPGA multi-rate Ethernet interface and outputting clock signals used by the MAC layer encoding and decoding module and the PCS layer encoding and decoding module, and the configuration rate adapted by the rate adaptation control module has a preset adaptation relation with the configuration rate of the FPGA multi-rate Ethernet interface.

In an alternative embodiment, configuring the FPGA multi-rate ethernet interface to one of a plurality of different configuration rates includes:

the first DRP dynamic configuration module of the rate adaptation control module receives a first configuration signal received by external software through a software control interface;

Configuring a first QPLL frequency synthesizer of the rate adaptation control module according to configuration parameters corresponding to a configuration rate specified by the first configuration signal;

if the first QPLL frequency synthesizer is configured, writing configuration parameters corresponding to the configuration rate specified by the first configuration signal into a first register of the rate adaptation control module, wherein the configuration rate specified by the first configuration signal is one of the configuration rates corresponding to the configuration parameters stored in a first memory of the rate adaptation control module or the configuration rate specified by the external software.

In an alternative embodiment, the rate adaptation control module is used to adapt the configuration rate at which the FPGA multi-rate ethernet interface is configured, and output clock signals used by the MAC layer codec module and the PCS layer codec module, including:

the second DRP dynamic configuration module of the rate adaptation control module receives a second configuration signal from external software through a software control interface;

Configuring a second QPLL frequency synthesizer and a CPLL frequency synthesizer of the rate adaptation control module according to configuration parameters corresponding to the configuration rate specified by the second configuration signal;

If the second QPLL frequency synthesizer and the CPLL frequency synthesizer are configured, writing configuration parameters corresponding to the configuration rate appointed by the second configuration signal into a second register of the rate adaptation control module, wherein the configuration rate appointed by the second configuration signal is one of the configuration rates corresponding to the configuration parameters stored in a second memory of the rate adaptation control module or the configuration rate appointed by external software.

In an alternative embodiment, the method further comprises:

configuring a user-configured frequency division interface of the second register to be 32 frequency division, so as to obtain a 32 frequency division clock signal;

Storing the 32 frequency division clock signals to a first clock buffer to obtain 32 frequency division clock signals output to the PCS layer encoding and decoding module;

turning off one 32-period of the 32-frequency-division clock signal and storing the 32-period-division clock signal into a second clock buffer to obtain a 33-frequency-division clock signal output to the MAC layer encoding and decoding module;

and turning off one 32 frequency division clock signal every 1 period, turning off 2 frequency division clock signals every 32 periods, and storing the clock signals into a third clock buffer to obtain 66 frequency division clock signals which are output to the PCS layer encoding and decoding module.

In an alternative embodiment, the method further comprises:

setting a full alarm waterline threshold, an empty alarm waterline threshold and a read start waterline threshold for an asynchronous FIFO in the rate adaptation module;

if the data volume in the asynchronous FIFO is detected to be greater than or equal to the full alarm waterline threshold, triggering external software to reconfigure a configuration value of the minimum average frame interval of the MAC layer codec module so as to reduce the configuration value;

and if the data quantity in the asynchronous FIFO is detected to be smaller than or equal to the alarm waterline threshold to be empty, triggering external software to reconfigure the read starting waterline threshold so as to increase the read starting waterline threshold.

In an alternative embodiment, the method further comprises:

Setting a full alarm waterline threshold, a null alarm waterline threshold and a read start waterline threshold for an asynchronous FIFO in the rate adaptation module;

If the data amount in the asynchronous FIFO is detected to be greater than or equal to the full alarm waterline threshold value, and the rate adaptation module is configured to be in a self-adaptive inter-frame interval adjustment mode, triggering the MAC layer encoding and decoding module to periodically delete the inter-frame interval of the Ethernet message data until the data amount in the asynchronous FIFO is less than or equal to the full alarm waterline threshold value;

if the accumulated times of the threshold value of the full alarm waterline is larger than or equal to a first set threshold value, reducing the configuration value of the minimum average frame interval of the MAC layer encoding and decoding module;

If the data amount in the asynchronous FIFO is detected to be smaller than or equal to the empty alarm waterline threshold value, and the rate adaptation module is configured to be in a self-adaptive inter-frame interval adjustment mode, triggering the MAC layer encoding and decoding module to periodically insert an inter-frame interval into Ethernet message data until the data amount in the asynchronous FIFO is larger than or equal to the empty alarm waterline threshold value;

And if the accumulated times of the empty alarm waterline threshold value is larger than or equal to a second set threshold value, the read starting waterline threshold value is regulated to be high.

A third aspect of the application provides an electronic device comprising a processor and a memory, the memory storing a plurality of instructions, the processor being for reading the instructions and performing the method of the first aspect.

A fourth aspect of the application provides a computer readable storage medium storing a plurality of instructions readable by a processor and carrying out the method of the first aspect.

Compared with the related art, the technical scheme of the application has at least the following advantages:

The method solves the problem that the flow of the Ethernet test equipment is not transmitted at the line speed through the FPGA speed reduction bridge in a lossless manner by combining the speed adaptation and the frequency offset adaptation, also solves the problem that the FPGA speed reduction bridge cannot test the real PFC/PAUSE of the ASIC DUT by controlling the matching speed of the real Ethernet test equipment in the related art, further improves the connection speed with the real Ethernet test equipment by up to 10Gbps, accelerates the verification efficiency, improves the convergence speed of prototype verification, realizes the multi-speed connection of the FPGA speed reduction bridge and the real Ethernet test equipment, and solves the problem of multi-speed switching.

Additional features and advantages of the application will be set forth in the description which follows, and in part will be obvious from the description, or may be learned by practice of the application. The objectives and other advantages of the application may be realized and attained by the structure and flow of the instrumentalities and methods pointed out in the specification and drawings.

Drawings

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the related art, the drawings that are required to be used in the embodiments or the related technical descriptions will be briefly described, and it is obvious that the drawings in the following description are some embodiments of the present application, and other drawings may be obtained according to the drawings without any inventive effort for a person skilled in the art.

Fig. 1 is a block diagram of an implementation structure of an FPGA speed bump according to the related art.

FIG. 2 is a block diagram of one implementation of an FPGA speed reduction bridge according to an exemplary embodiment of the present application.

Fig. 3 is a block diagram of the structure of an FPGA multi-rate ethernet interface according to an exemplary embodiment of the present application.

Fig. 4 is a rate adaptation flow chart of an FPGA multi-rate ethernet interface according to an exemplary embodiment of the present application.

Fig. 5 is a block diagram of the structure of a rate adaptation control module according to an exemplary embodiment of the present application.

Fig. 6 is a rate adaptation flow chart of a rate adaptation control module according to an exemplary embodiment of the application.

Fig. 7 is an equivalent frequency division structure block diagram of a rate adaptation control module according to an exemplary embodiment of the present application.

Fig. 8 is a block diagram of a structure of a frequency offset adaptation according to an exemplary embodiment of the present application.

Fig. 9 is a diagram showing the various pipeline high and low effects provided for asynchronous FIFOs, according to an illustrative embodiment of the present application.

Detailed Description

In order to make the objects, technical solutions and advantages of the embodiments of the present application more apparent, the technical solutions of the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application, and it is apparent that the described embodiments are some embodiments of the present application, but not all embodiments of the present application. All other embodiments, which are derived by a person skilled in the art from the embodiments according to the application without creative efforts, fall within the protection scope of the application.

The method provided by the application can be implemented in a terminal environment that can include one or more of a processor, a memory, and a display screen. Wherein the memory stores at least one instruction that is loaded and executed by the processor to implement the method described in the embodiments below.

The processor may include one or more processing cores. The processor connects various parts within the overall terminal using various interfaces and lines, performs various functions of the terminal and processes data by executing or executing instructions, programs, code sets, or instruction sets stored in the memory, and invoking data stored in the memory.

The Memory may include random access Memory (Random Access Memory, RAM) or Read-Only Memory (ROM). The memory may be used to store instructions, programs, code, sets of codes, or instructions.

The display screen is used for displaying a user interface of each application program.

In addition, it will be appreciated by those skilled in the art that the structure of the terminal described above is not limiting and that the terminal may include more or fewer components, or may combine certain components, or a different arrangement of components. For example, the terminal further includes components such as a radio frequency circuit, an input unit, a sensor, an audio circuit, a power supply, and the like, which are not described herein.

In combination with the related state of the art mentioned in the background, in order to be able to connect with a real test meter, a speed reduction bridge needs to be added before the ASIC test logic to match the real test meter and the speed of the ASIC after the speed reduction.

The inventor discovers that the speed reduction bridge needs to solve the core problems:

1. rate adaptation, essentially solves the problem of clock matching.

2. Protocol adaptation, which is quite different from the lower Ethernet interface protocol of the real meter connection and the real ASIC DUT high-speed Ethernet interface protocol, is the adaptation of 1G to 10G/100G high-speed Ethernet protocol.

As an auxiliary verification means in ASIC verification, the inventor of the application finds through search that the related technology is directly connected with the DUT after being coded by the MAC layer, and in the FPGA speed reduction bridge structure of the related technology shown in figure 1, some functions are not realized, and only the problem of flow existence is solved.

Therefore, the FPGA speed bump in the related art has the following drawbacks:

Protocol adaptation is only coded to the MAC layer, PCS logic of the ASIC cannot be tested and covered, and possible reasons are that the rate adaptation problem cannot be solved, so that testing of PCS on an FPGA prototype is abandoned;

the interface connected with the tester only supports 1G rate, and cannot cover a scene of multi-rate switching;

During rate adaptation, the tester is paused to send packets through the state violent packet loss of the FIFO or through sending the PAUSE flow control frame, so that the ASIC DUT (application specific integrated circuit) such as ROCE and other nondestructive transmission scenes cannot be tested, a plurality of extreme cases in a line speed scene cannot be effectively covered on the FPGA prototype, and the pressure test cannot be effectively tested on the FPGA prototype, so that the functional test can be only carried out.

Based on the analysis, in order to solve the problems in the related art, the application provides an FPGA (field programmable gate array) speed reduction bridge and a speed adaptation method, which solve the problem of speed matching after real Ethernet test equipment is subjected to frequency reduction with an ASIC (application specific integrated circuit) DUT (device under test), and solve the problem of lossless line speed transparent transmission of the flow of the Ethernet test equipment through the FPGA speed reduction bridge in a mode of combining the speed adaptation and the frequency offset adaptation; the method also solves the problem that the FPGA speed reduction bridge cannot test the real PFC/PAUSE of the ASIC DUT by controlling the matching speed of the real Ethernet test equipment in the related technology, improves the connection speed with the real Ethernet test equipment to be as high as 10Gbps, accelerates the verification efficiency, improves the convergence speed of prototype verification, realizes the multi-speed connection of the FPGA speed reduction bridge and the real Ethernet test equipment, and solves the problem of multi-speed switching.

Referring to fig. 2, the application exemplarily proposes an FPGA speed-down bridge, which comprises an FPGA multi-rate ethernet interface, a rate adaptation module, a rate adaptation control module, and a protocol adaptation module, wherein,

In an alternative embodiment of the present application, the FPGA multi-rate ethernet interface includes a first DRP dynamic configuration module, a first memory, a first QPLL frequency synthesizer, and a first register, where the first memory is configured to store configuration parameters corresponding to one or more configuration rates, the first DRP dynamic configuration module receives a first configuration signal from external software through a software control interface, configures the first QPLL frequency synthesizer according to the configuration parameters corresponding to the configuration rate specified by the first configuration signal, and after the first QPLL frequency synthesizer is configured, the configuration parameters corresponding to the configuration rate specified by the first configuration signal are written into the first register, and the configuration rate specified by the first configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the first memory or the configuration rate specified by the external software.

In some embodiments, the first register is FPGA SERDES, such as a GTY. In this embodiment, the first QPLL frequency synthesizer is located within the GTY.

As an alternative implementation, referring to fig. 3, external software configures DRP (Dynamic Reconfiguration Port, dynamic configuration port) of the FPGA multi-rate ethernet interface through APB (ADVANCED PERIPHERAL Bus) software control interface. The first memory of the FPGA multi-rate ethernet interface may be a ROM that may store configuration parameters for multiple configuration rates, such as Serdes configuration parameters for four configuration rates, 1G/2.5G/5G/10G. After the external software can issue a switching rate command through the APB software control interface, the DRP dynamic configuration module reads the Serdes configuration parameters of the corresponding configuration rate from the ROM according to the exemplary flow shown in fig. 4, writes SERDES LANE (i.e. the first register) through the SERDES DRP interface, resets SERDES LANE after the configuration is completed, or the external software can drive the DRP dynamic configuration module through the APB software control interface to dynamically configure the Serdes configuration parameters corresponding to the configuration rate designated by the external software to SERDES LANE through the SERDES DRP interface so as to complete the cutting speed of the FPGA multi-rate ethernet interface.

Referring to fig. 4, an exemplary embodiment includes determining whether a configuration signal for performing rate switching is received if a CPLL clock lock signal or QPLL clock lock signal is detected, selecting a corresponding ROM address in the FPGA multi-rate ethernet interface according to a configuration rate specified in the configuration signal if the configuration signal is received, reading a corresponding second register (GTY, that is, FPGA SERDES) address, masking a field to be reconfigured of the second register after the DRP interface is ready, writing the field to be reconfigured to the second register, determining whether the second register is configured after the DRP interface is ready again, and resetting the GTY if the configuration is completed. If not, returning to wait for the next configuration.

In an alternative embodiment of the present application, the rate adaptation control module includes a second DRP dynamic configuration module, a second memory, a second QPLL frequency synthesizer, a CPLL frequency synthesizer, and a second register, where the second memory is configured to store configuration parameters corresponding to one or more configuration rates, the second DRP dynamic configuration module receives a second configuration signal from external software through a software control interface, configures the second QPLL frequency synthesizer and the CPLL frequency synthesizer according to the configuration parameters corresponding to the configuration rate specified by the second configuration signal, and after the second QPLL frequency synthesizer and the CPLL frequency synthesizer are configured, the configuration parameters corresponding to the configuration rate specified by the second configuration signal are written into the second register, and the configuration rate specified by the second configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the second memory or the configuration rate specified by the external software.

The configuration rate specified by the second configuration signal has a preset adaptation relation with the configuration rate specified by the first configuration signal for configuring the configuration rate of the FPGA multi-rate Ethernet interface.

In some embodiments, the second register is FPGA SERDES, such as a GTY. In this embodiment, the second QPLL frequency synthesizer and the CPLL frequency synthesizer are located within the GTY.

In another alternative embodiment of the present application, the rate adaptation control module further includes a first clock buffer, a second clock buffer, and a third clock buffer;

In the embodiment of the application, the adaptation between the speed of the Ethernet test equipment and the logic to be tested of the ASIC DUT is mainly completed through two steps of speed adaptation and frequency offset adaptation, and the multi-speed cut-off speed adaptation of the ASIC DUT is completed through the FPGA multi-speed Ethernet interface.

In the rate adaptation process, in an alternative embodiment of the application, after the frequency of the whole logic to be tested of the ASIC DUT is reduced by 10 times, the service logic clock is 50MHz, the logic frequency of the FPGA multi-rate Ethernet interface is 83.0125MHz, and the time sequence is easier to converge, so that a rate adaptation method of a two-part method is adopted in the embodiment:

In a first step, the transmission rate is adapted. The method solves the problem of Base-x to Base-R linear rate adaptation (1.25 Gbps (1G) < - >1.03125Gbps (after 10G down conversion)), 3.125Gbps (2.5G) < - >2.578125Gbps (after 25G down conversion)), rate adaptation of Base-R to Base-R RS-FEC (10.3125 Gbps (10G) < - >10.625 Gabs (after 100G RS-FEC 544 down conversion), and the like), and the method has the advantages that the linear rate of 1G/2.5G is higher than the linear rate after 10G/25G down conversion, but the linear rate of 1G/2.5G is 8b/10b coding, the coding efficiency is not higher than the 64b/66b coding of 10G/25G, and the total rate is matched.

And step two, frequency offset adaptation. In the Ethernet protocol, the jitter of plus or minus 100ppm can be processed, the speed-down bridge rate adaptation module can accurately match the rate, the frequency deviation of plus 100ppm is ensured not to be cut off, and the packet loss of minus 100ppm is ensured not to be generated.

Through the two steps, the FPGA speed reduction bridge can be used for nondestructively and thoroughly transmitting the flow of all Ethernet test equipment, so that various pressure tests can be carried out on the ASIC DUT logic to be tested after equivalent frequency reduction. Meanwhile, the problem that the related technical scheme cannot test PCS layer codes and cannot conduct nondestructive business test is solved, the constructed scene can effectively simulate various extreme cases of an ASIC actual scene digital logic part, particularly an Ethernet interface part, and the duty ratio of an ASIC generated clock is truly scaled and simulated.

The transmission rate adaptation is essentially achieved by matching the asynchronous FIFO read/write clock in the rate adaptation module with the clocks of the MAC layer codec module and the PCS layer codec module. Taking 1G < - >10G rate adaptation as an example, the recovered clock of the 1G Ethernet interface is 125MHz, the clock signals required by the 10G MAC layer, the PCS layer and the PMA layer are 312.5MHz, 156.25MHz and 322.265625MHz respectively, after 10 times of frequency reduction, 31.25MHz, 15.625MHz and 32.265625MHz respectively, obviously 32.2265625MHz cannot be obtained by simply frequency division of the recovered 125MHz clock, meanwhile, the FPGA does not suggest Serdes (deserializer) to recover the frequency division of a clock cascade PLL (phase locked loop), because the recovered clock jitter is larger, the PLL cannot be locked due to the fact that the threshold value of the recovered clock jitter is exceeded, unstable factors are additionally introduced, and the problem positioning difficulty is increased. Therefore, in an alternative embodiment of the present application, a rate adaptation control module as shown in fig. 5 is used, so as to obtain the line rate 32/33/66 frequency division clock required by the protocol adaptation module and the rate adaptation module.

The rate adaptation control module supports rate adaptation in two modes, namely a hardware automatic configuration mode and a software-hardware combined configuration mode.

In the hardware automatic configuration mode, the ROM serving as the second memory stores a plurality of configuration rates, such as a plurality of configuration rates of 10G/25G/50G/100G, for example, the plurality of configuration rates stored in the second memory can be in one-to-one correspondence with the plurality of configuration rates stored in the FPGA multi-rate Ethernet interface, and has a set adaptation relationship, such as the plurality of configuration rates of 10G/25G/50G/100G respectively adapt to the plurality of configuration rates stored in the FPGA multi-rate Ethernet interface, that is, the plurality of configuration rates of the Serdes configuration parameters stored in the second memory of the rate adaptation controller are Serdes configuration parameters of the plurality of configuration rates stored in the second memory of the FPGA multi-rate Ethernet interface.

When the external software can issue a cut-speed command through an APB (advanced peripheral bus) software control port during the adaptation, the DRP dynamic configuration module reads the Serdes configuration parameters with corresponding speed from the second memory ROM according to the exemplary process shown in FIG. 6, writes the Serdes configuration parameters into the second register Serdes through a SERDES DRP interface, and resets the second register Serdes after the configuration is completed.

Referring to fig. 6, an exemplary embodiment includes determining whether a configuration signal for rate switching is received if a CPLL clock lock signal or QPLL clock lock signal is detected, selecting a corresponding ROM address according to a configuration rate specified in the configuration signal if the configuration signal is received, reading a corresponding GTY (FPGA Serdes) address from the selected ROM address, configuring a VCO frequency of a second QPLL frequency synthesizer and a source clock and a frequency division ratio of the CPLL frequency synthesizer after a DRP interface is ready, determining whether the second QPLL frequency synthesizer or the CPLL frequency synthesizer is configured after the DRP interface is ready again, and resetting the GTY if the configuration is completed. If not, returning to wait for the next configuration.

In the software and hardware combined configuration mode, the second memory ROM only stores a limited number of Serdes configuration parameters, and for other 40G/200G/400G/800G and other speed reduction rates, external software can drive the DRP dynamic configuration module through the APB software control interface to write the corresponding Serdes configuration parameter flow into Serdes through the DRP interface.

Because of the limitation of the Serdes structure of the second register of the FPGA, the number of user configuration frequency dividing interfaces which are opened for users is only 1, the counter direct frequency division or cascading PLL is not friendly to the realization of the FPGA, in order to obtain three types of clocks of line speed 32/33/66 frequency division required by a protocol adaptation module through a unique one of the user configuration frequency dividing interfaces, the user configuration frequency dividing interfaces which are reserved by the Serdes of the FPGA are configured to be 32 frequency division, and then 33 frequency division and 66 frequency division clocks are obtained through the 32 frequency division clocks by using a gating clock equivalent frequency division method, as shown in figure 7.

The frequency division clock of 32 is directly obtained after the Serdes 32 frequency division clock passes through the first clock buffer BUFGCE;

the 33 frequency division clock is that after each 32 periods of the Serdes 32 frequency division clock, the clock of one period is turned off to obtain an equivalent line rate 33 frequency division clock;

66 divided clock, namely after each 1 period of the Serdes 32 divided clock, the clock of 1 period is turned off, and the clock of 2 periods is turned off every 32 periods, so that the equivalent line rate 66 divided clock is obtained.

The frequency offset adaptation is mainly used for matching the flow adaptation caused by the frequency offset of the FPGA multi-rate Ethernet interface receiving direction RX recovery clock and the frequency offset of the local frequency division clock sent by the FPGA speed reduction bridge to the ASIC DUT. The frequency offset refers to the offset of the crystal oscillator relative to the nominal center frequency, and the 802.3 protocol allows for frequency offset between the connection partners to be within plus or minus 100 ppm. As shown in fig. 8, for example, when the clock frequency offset in the receiving direction RX is recovered to be a positive frequency offset and the clock frequency offset in the local frequency division is a negative frequency offset, the data flow in the receiving direction in unit time is larger than the data flow that can be sent in the sending direction, which can cause the waterline of the asynchronous FIFO in the rate adaptation module to rise, and accumulate for a period of time, which can cause the problem that the asynchronous FIFO is full and the ethernet message data is discarded.

When the recovery clock frequency offset of the receiving direction is negative frequency offset and the local frequency division clock frequency offset is positive frequency offset, in unit time, the data flow of the receiving direction is smaller than the data flow which can be sent in the sending direction, the asynchronous FIFO waterline in the rate adaptation module is lowered, the asynchronous FIFO is accumulated for a period of time, the asynchronous FIFO is empty, if the asynchronous FIFO is empty during the process of transmitting one Ethernet message data, the message is cut off, and then the Ethernet message data received by the ASIC DUT is wrong.

To solve the above two problems, in an alternative embodiment of the present application, the frequency offset may be adapted by using a fine adjustment frame Interval (IPG) mode that combines coarse adjustment with adaptive adjustment of hardware and software.

In an alternative embodiment of the application, under the mode of combining software and hardware and coarse tuning, a full alarm waterline threshold, a null alarm waterline threshold and a read start waterline threshold can be set for an asynchronous FIFO in the rate adaptation module, when the data volume in the asynchronous FIFO is greater than or equal to the full alarm waterline threshold, the configuration value of the minimum average frame interval of the MAC layer codec module is triggered to be reduced, and when the data volume in the asynchronous FIFO is less than or equal to the null alarm waterline threshold, the configuration value of the read start waterline threshold is triggered to be reconfigured by the external software to be increased. In some embodiments, when the waterline of the asynchronous FIFO reaches a read enable waterline threshold, the read enable of the asynchronous FIFO is asserted, thereby enabling the flow of data out of the FIFO.

In some alternative embodiments, when the FIFO alarms on a full line, i.e. the amount of data in the asynchronous FIFO is greater than or equal to the threshold of the full alarm waterline, an interrupt may be triggered to report to the external software, which reconfigures the minimum average IPG value of the MAC layer decoding module, such as by subtracting 1, and clears the interrupt, and if the FIFO is triggered again to trigger an interrupt on a full line, the external software may continue to reconfigure the minimum average IPG value of the MAC layer decoding module, such as by subtracting 1. By the method, the problem that when the clock frequency deviation of the RX recovery in the receiving direction is positive frequency deviation and the clock frequency deviation of the local frequency division is negative frequency deviation, the data flow in the receiving direction in unit time is larger than the data flow which can be sent in the sending direction, and the asynchronous FIFO is full and the Ethernet message data is discarded can be solved.

In other alternative embodiments, when the FIFO alarms the empty pipeline, i.e. the amount of data in the asynchronous FIFO is less than or equal to the alarm-to-empty pipeline threshold, an interrupt is triggered to report to the external software, the external software configures the read-start pipeline threshold of the asynchronous FIFO to be increased by 1, and clears the interrupt, and if the FIFO is triggered again to interrupt the empty pipeline alarm, the external software continues to increase the read-start pipeline threshold of the asynchronous FIFO by 1. By the method, the problem that when the clock frequency deviation of the recovery clock in the receiving direction RX is negative frequency deviation and the clock frequency deviation of the local frequency division clock is positive frequency deviation, the data flow in the receiving direction is smaller than the data flow which can be sent in the sending direction in unit time, and the data error of the Ethernet message received by the ASIC DUT is caused can be solved.

In an optional embodiment of the present application, in a hardware adaptive fine tuning manner, a full alarm waterline threshold, a null alarm waterline threshold, and a read start waterline threshold may be set for an asynchronous FIFO in the rate adaptation module;

In some embodiments, when the asynchronous FIFO of the rate adaptation module reaches or falls below the empty alarm waterline, an alarm should be generated to alarm the empty alarm waterline, the rate adaptation module decides whether to perform adaptive IPG (inter-frame interval) adjustment according to the preset configuration of external software, if so, the MAC layer codec module periodically inserts an IPG into the ethernet message data based on a DIC (DEFICIT IDLE Count) algorithm until the FIFO waterline is greater than or equal to the empty alarm waterline threshold, and the MAC layer codec module stops inserting the IPG value and continues to transmit the IPG according to the DIC algorithm. In addition, the number of empty alarms can be counted, and when the counted number is larger than a first set threshold value, the read start waterline of the asynchronous FIFO of the rate adaptation module is adjusted to be high. By the method, the problem that when the clock frequency deviation of the RX recovery in the receiving direction is positive frequency deviation and the clock frequency deviation of the local frequency division is negative frequency deviation, the data flow in the receiving direction in unit time is larger than the data flow which can be sent in the sending direction, and the asynchronous FIFO is full and the Ethernet message data is discarded can be solved.

In other embodiments, when the asynchronous FIFO of the rate adaptation module reaches or is higher than the full alarm waterline, the FIFO is generated to be full, the rate adaptation module decides whether to perform adaptive IPG adjustment according to the pre-configuration of the external software, and the MAC layer codec module periodically deletes the IPG of the ethernet message data based on the DIC algorithm until the FIFO waterline is less than or equal to the full alarm waterline value. In addition, statistics may be performed on the number of times of full line alarms, and when the counted number of times is greater than a second set threshold, the configuration value of the minimum average frame interval may be reduced. When the IPG is periodically deleted, the requirement of the average minimum average frame interval of the 802.3 receiving end is met. By the method, the problem that when the clock frequency deviation of the recovery clock in the receiving direction RX is negative frequency deviation and the clock frequency deviation of the local frequency division clock is positive frequency deviation, the data flow in the receiving direction is smaller than the data flow which can be sent in the sending direction in unit time, and the data error of the Ethernet message received by the ASIC DUT is caused can be solved.

The software and hardware combined coarse adjustment mode and the hardware self-adaptive fine adjustment mode can be matched with each other, and complement each other to jointly complete frequency offset adaptation. Referring to FIG. 9, the thresholds are illustratively sorted from big to small by full alarm watermark threshold, clear full alarm watermark threshold, read enable watermark threshold, clear empty alarm watermark threshold, empty alarm watermark threshold.

Accordingly, the present application provides, illustratively, in a second aspect, a rate adaptation method implemented using the FPGA speed reduction bridge set forth in the first aspect, the method comprising:

In an alternative embodiment of the present application, configuring the FPGA multi-rate ethernet interface to one of a plurality of different configuration rates includes:

In an alternative embodiment of the present application, the adapting the configuration rate of the FPGA multi-rate ethernet interface by using a rate adaptation control module, and outputting clock signals used by a MAC layer codec module and a PCS layer codec module, includes:

In an alternative embodiment of the application, the method further comprises:

Specific implementation details of the rate adaptation method may be referred to the description in the embodiment of the first aspect, and will not be repeated here.

It is understood that the circuit structures, names and parameters described in the above embodiments are only examples. Those skilled in the art may also make and adjust the structural features of the above embodiments as desired without limiting the inventive concept to the specific details of the examples described above.

The application also provides an electronic device comprising a processor and a memory, the memory storing a plurality of instructions, the processor being for reading the instructions and performing any of the methods of the first aspect. Wherein the processor and the memory may be connected by a bus or otherwise, for example by a bus connection. The processor may be a central processing unit (Central Processing Unit, CPU). The processor may also be other general purpose processors, digital signal processors (Digital SignalProcessor, DSP), application SPECIFIC INTEGRATED Circuits (ASICs), field-Programmable gate arrays (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic devices, discrete gate or transistor logic devices, discrete hardware components, or a combination of the above.

The memory is used as a non-transitory computer readable storage medium for storing non-transitory software programs, non-transitory computer executable programs, and modules, such as program instructions/modules corresponding to the methods in embodiments of the present application. The processor executes various functional applications of the processor and data processing, i.e., implements the methods of the method embodiments described above, by running non-transitory software programs, instructions, and modules stored in memory.

The memory may include a storage program area that may store an operating system, application programs required for at least one function, and a storage data area that may store data created by the processor, etc. In addition, the memory may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid state storage device. In some embodiments, the memory may optionally include memory located remotely from the processor, the remote memory being connectable to the processor through a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Although the present application has been described in detail with reference to the foregoing embodiments, those skilled in the art will understand that modifications may be made to the technical solutions described in the foregoing embodiments or equivalents may be substituted for some of the technical features thereof, and these modifications or substitutions do not depart from the spirit and scope of the technical solutions of the embodiments of the present application in essence.

Claims

1. The FPGA speed reducing bridge is characterized by comprising an FPGA multi-rate Ethernet interface, a rate adaptation module, a rate adaptation control module and a protocol adaptation module, wherein,

the rate adaptation control module is used for adapting the configuration rate of the FPGA multi-rate Ethernet interface and outputting clock signals used by the MAC layer encoding and decoding module and the PCS layer encoding and decoding module based on the adapted configuration rate;

When the data amount in the asynchronous FIFO in the rate adaptation module is larger than the full alarm waterline threshold, the rate adaptation module decides whether to execute adaptive inter-frame space adjustment according to the pre-configuration of external software, and if the adaptive inter-frame space adjustment is performed, the MAC layer encoding and decoding module periodically deletes the inter-frame space of the Ethernet message data until the data amount of the FIFO is smaller than or equal to the full alarm waterline threshold.

2. The FPGA speed-down bridge of claim 1, wherein the FPGA multi-rate ethernet interface comprises a first DRP dynamic configuration module, a first memory, a first QPLL frequency synthesizer and a first register, wherein the first memory is configured to store configuration parameters corresponding to one or more configuration rates, the first DRP dynamic configuration module receives a first configuration signal from external software through a software control interface, configures the first QPLL frequency synthesizer according to the configuration parameters corresponding to the configuration rate specified by the first configuration signal, after the first QPLL frequency synthesizer is configured, the configuration parameters corresponding to the configuration rate specified by the first configuration signal are written into the first register, and the configuration rate specified by the first configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the first memory or the configuration rate specified by the external software.

3. The FPGA speed-down bridge of claim 1, wherein the rate adaptation control module comprises a second DRP dynamic configuration module, a second memory, a second QPLL frequency synthesizer, a CPLL frequency synthesizer and a second register, wherein the second memory is used for storing configuration parameters corresponding to one or more configuration rates, the second DRP dynamic configuration module receives a second configuration signal from external software through a software control interface, configures the second QPLL frequency synthesizer and the CPLL frequency synthesizer according to the configuration parameters corresponding to the configuration rate specified by the second configuration signal, and after the second QPLL frequency synthesizer and the CPLL frequency synthesizer are configured, the configuration parameters corresponding to the configuration rate specified by the second configuration signal are written into the second register, and the configuration rate specified by the second configuration signal is one of the configuration rates corresponding to the configuration parameters stored in the second memory or the configuration rate specified by the external software.

4. The FPGA speed reduction bridge of claim 3, wherein the rate adaptation control module further comprises a first clock buffer, a second clock buffer, and a third clock buffer;

5. The FPGA speed-down bridge of claim 1, wherein an asynchronous FIFO in the rate adaptation module is configured with a full alarm watermark threshold, a null alarm watermark threshold, and a read start watermark threshold, wherein when the amount of data in the asynchronous FIFO is greater than or equal to the full alarm watermark threshold, the external software is triggered to reconfigure the configuration value of the minimum average frame interval of the MAC layer codec module to decrease, and when the amount of data in the asynchronous FIFO is less than or equal to the null alarm watermark threshold, the external software is triggered to reconfigure the read start watermark threshold to increase.

6. The FPGA speed bump of claim 1 wherein the asynchronous FIFOs in the rate adaptation module are configured to flush the full alarm watermark threshold, to disengage the full alarm watermark threshold, to flush the empty alarm watermark threshold, to disengage the empty alarm watermark threshold, and to disengage the read launch watermark threshold;

7. The FPGA of claim 6 wherein the thresholds are ordered from large to small by full alarm watermark threshold, clear full alarm watermark threshold, read enable watermark threshold, clear alarm watermark threshold.

8. A rate adaptation method, characterized in that the method is implemented with the FPGA speed reduction bridge of any one of claims 1-7, the method comprising:

9. The rate adaptation method of claim 8, wherein configuring the FPGA multi-rate ethernet interface to one of a plurality of different configuration rates comprises:

10. The rate adaptation method according to claim 8, wherein adapting the configuration rate at which the FPGA multi-rate ethernet interface is configured with a rate adaptation control module and outputting clock signals used by a MAC layer codec module and a PCS layer codec module comprises:

11. The rate adaptation method according to claim 10, characterized in that the method further comprises:

12. The rate adaptation method according to claim 8, wherein the method further comprises:

13. The rate adaptation method according to claim 8, wherein the method further comprises:

14. An electronic device comprising a processor and a memory, the memory storing a plurality of instructions, the processor configured to read the instructions and perform the rate adaptation method of any one of claims 8-13.

15. A computer readable storage medium storing a plurality of instructions readable by a processor and executable by the processor to perform the rate adaptation method of any one of claims 8-13.