CN119068939A - Memory refresh method and device - Google Patents
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- CN119068939A CN119068939A CN202310619356.2A CN202310619356A CN119068939A CN 119068939 A CN119068939 A CN 119068939A CN 202310619356 A CN202310619356 A CN 202310619356A CN 119068939 A CN119068939 A CN 119068939A
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40622—Partial refresh of memory arrays
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40611—External triggering or timing of internal or partially internal refresh operations, e.g. auto-refresh or CAS-before-RAS triggered refresh
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/406—Management or control of the refreshing or charge-regeneration cycles
- G11C11/40615—Internal triggering or timing of refresh, e.g. hidden refresh, self refresh, pseudo-SRAMs
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Abstract
The present disclosure provides a memory refreshing method and device, and relates to the technical field of semiconductors, comprising the steps of obtaining refresh parameters corresponding to data lines in a memory; the refresh parameter is determined according to the data retention time of the memory cell connected with the data line, the refresh command response interval times corresponding to the data line are determined according to the refresh parameter corresponding to the data line, and the refresh operation is performed on the data line according to the refresh command response interval times. In the embodiment of the disclosure, when the memory executes the refresh command each time, only a part of the data lines are subjected to refresh operation according to the refresh parameters corresponding to the data lines, instead of all the data lines, and some data lines can be subjected to refresh operation once every a plurality of refresh commands, so that the power consumption of the memory can be reduced on the premise of not losing the data stored in the memory.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a memory refresh method and apparatus.
Background
Since the memory stores data in a capacitor, there is a characteristic that all data stored therein needs to be refreshed continuously for a limited time to prevent data loss.
At present, the refresh mode of the memory can be divided into an automatic refresh mode and a self-refresh mode, wherein in the automatic refresh mode, a refresh command is sent out by a controller periodically, the memory is responsible for executing the refresh command, and in the self-refresh mode, the controller is only responsible for sending a command for entering the self-refresh mode and a command for exiting the self-refresh mode, and after entering the self-refresh mode, the refresh command is generated by the memory itself periodically.
However, the existing memory requires at least one refresh operation per data line when each refresh command is executed, thereby resulting in a larger power consumption of the memory.
Disclosure of Invention
The invention provides a memory refreshing method and device, which can effectively reduce the power consumption of a memory.
In a first aspect, an embodiment of the present disclosure provides a memory refresh method, where the memory includes a plurality of data lines, the method including:
The method comprises the steps of obtaining a refresh parameter corresponding to a data line, wherein the refresh parameter is determined according to the data retention time of a storage unit connected with the data line;
Determining the response interval times of the refresh command corresponding to the data line according to the refresh parameter corresponding to the data line;
and carrying out refreshing operation on the data line according to the response interval times of the refreshing command corresponding to the data line.
In some embodiments, the refreshing operation on the data line according to the number of refresh command response intervals corresponding to the data line includes:
When the memory responds to a refresh command, determining the refresh times corresponding to the refresh command;
Determining whether the data line belongs to a data line to be refreshed or not according to the refresh times corresponding to the refresh command and the refresh command response interval times corresponding to the data line;
And when the data line belongs to the data line to be refreshed, carrying out refreshing operation on the data line, and when the data line does not belong to the data line to be refreshed, keeping the switching state of the data line unchanged.
In some embodiments, before the obtaining the refresh parameter corresponding to the data line, the method further includes:
detecting the data retention time of a storage unit connected with the data line;
And determining a refresh parameter corresponding to the data line according to the data retention time of the memory cell.
In some embodiments, the detecting the data retention time of the memory cell to which the data line is connected includes:
writing first data in the memory cell;
reading the second data stored in the storage unit for a plurality of times according to a preset interval duration;
Comparing the first data with the second data read each time, and determining the time when the memory cell first generates a read error;
And determining the time when the memory cell first generates a read error as the data retention time of the memory cell.
In some embodiments, the determining the refresh parameter corresponding to the data line according to the data retention time of the memory cell includes:
And determining the refresh parameters corresponding to the data lines according to the data retention time of the memory cells and the preset time intervals corresponding to the refresh parameters.
In some embodiments, after determining the refresh parameter corresponding to the data line, the method further includes:
and adjusting the state of at least one programmable logic device corresponding to the data line according to the refresh parameter corresponding to the data line.
In some embodiments, the acquiring the refresh parameter corresponding to the data line includes:
Reading the state of the at least one programmable logic device;
And obtaining the refresh parameter corresponding to the data line according to the state of the at least one programmable logic device.
In some embodiments, the determining the number of refresh command response intervals corresponding to the data line according to the refresh parameter corresponding to the data line includes:
And determining the refresh command response interval times corresponding to the data lines according to the refresh parameters corresponding to the data lines and the corresponding relation between each preset refresh parameter and the refresh command response interval times, wherein different refresh parameters correspond to different refresh command response interval times.
In some embodiments, further comprising:
and re-detecting the data retention time of the storage unit connected with the data line at intervals of preset time, and updating the refresh parameter corresponding to the data line according to the re-detected data retention time.
In a second aspect, embodiments of the present disclosure provide a memory refresh apparatus, the memory including a plurality of data lines, the apparatus comprising:
the device comprises an acquisition module, a data line and a storage unit, wherein the acquisition module is used for acquiring refresh parameters corresponding to the data line, and the refresh parameters are determined according to the data retention time of the storage unit connected with the data line;
the determining module is used for determining the response interval times of the refresh command corresponding to the data line according to the refresh parameter corresponding to the data line;
and the refreshing module is used for refreshing the data line according to the corresponding refreshing command response interval times of the data line.
In some embodiments, the refresh module is to:
When the memory responds to a refresh command, determining the refresh times corresponding to the refresh command;
Determining whether the data line belongs to a data line to be refreshed or not according to the refresh times corresponding to the refresh command and the refresh command response interval times corresponding to the data line;
And when the data line belongs to the data line to be refreshed, carrying out refreshing operation on the data line, and when the data line does not belong to the data line to be refreshed, keeping the switching state of the data line unchanged.
In some embodiments, the apparatus further comprises a detection module for:
detecting the data retention time of a storage unit connected with the data line;
And determining a refresh parameter corresponding to the data line according to the data retention time of the memory cell.
In some embodiments, the detection module is to:
writing first data in the memory cell;
reading the second data stored in the storage unit for a plurality of times according to a preset interval duration;
Comparing the first data with the second data read each time, and determining the time when the memory cell first generates a read error;
And determining the time when the memory cell first generates a read error as the data retention time of the memory cell.
In some embodiments, the detection module is to:
And determining the refresh parameters corresponding to the data lines according to the data retention time of the memory cells and the preset time intervals corresponding to the refresh parameters.
In some embodiments, the apparatus further comprises an adjustment module for:
and adjusting the state of at least one programmable logic device corresponding to the data line according to the refresh parameter corresponding to the data line.
In some embodiments, the acquisition module is to:
Reading the state of the at least one programmable logic device;
And obtaining the refresh parameter corresponding to the data line according to the state of the at least one programmable logic device.
In some embodiments, the determining module is to:
And determining the refresh command response interval times corresponding to the data lines according to the refresh parameters corresponding to the data lines and the corresponding relation between each preset refresh parameter and the refresh command response interval times, wherein different refresh parameters correspond to different refresh command response interval times.
In some embodiments, the system further comprises an update module for:
and re-detecting the data retention time of the storage unit connected with the data line at intervals of preset time, and updating the refresh parameter corresponding to the data line according to the re-detected data retention time.
In a third aspect, an embodiment of the present disclosure provides an electronic device comprising at least one processor and a memory;
the memory stores computer-executable instructions;
The at least one processor executes computer-executable instructions stored by the memory such that the at least one processor performs a memory refresh method as provided in the first aspect.
In a fourth aspect, embodiments of the present disclosure provide a computer-readable storage medium having stored therein computer-executable instructions that, when executed by a computer, implement a memory refresh method as provided in the first aspect.
According to the memory refreshing method and the memory refreshing device, the refreshing parameters corresponding to the data lines are determined according to the data retention time of the memory cells connected with the data lines, when the memory executes the refreshing command each time, only a part of the data lines are refreshed according to the refreshing parameters corresponding to the data lines, but not all the data lines are refreshed, and some data lines can be refreshed once every a plurality of refreshing commands, so that the power consumption of the memory can be reduced on the premise that the data stored in the memory is not lost.
Drawings
FIG. 1 is a schematic layout diagram of a memory according to an embodiment of the disclosure;
fig. 2 is a schematic structural diagram of a memory cell of a memory according to an embodiment of the disclosure;
FIG. 3 is a flowchart illustrating a memory refresh method according to an embodiment of the present disclosure;
FIG. 4 is a flowchart illustrating a refinement step of detecting a data retention time of a memory cell connected to a data line according to an embodiment of the disclosure;
FIG. 5 is a schematic diagram of a program module of a memory refresh device according to an embodiment of the present disclosure;
Fig. 6 is a schematic hardware structure of an electronic device according to an embodiment of the disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. Furthermore, while the disclosure has been presented by way of example only, it should be appreciated that various aspects of the disclosure may be separately implemented in a complete embodiment.
It should be noted that the brief description of the terms in the present disclosure is only for convenience in understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between similar or similar objects or entities and not necessarily for describing a particular sequential or chronological order, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to those elements expressly listed, but may include other elements not expressly listed or inherent to such product or apparatus.
The term "module" as used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware or/and software code that is capable of performing the function associated with that element.
The embodiments of the present disclosure relate to the field of semiconductor memory technology, and may be optionally applied to chip design of dynamic random access memory (Dynamic Random Access Memory, DRAM), including controlling the refresh mode of the DRAM.
It is understood that a memory generally includes a plurality of Bit Lines (BL), a plurality of Word Lines (WL), and a plurality of memory cells, wherein each memory cell is connected to a corresponding one of the WL and the BL.
Referring to fig. 1, fig. 1 is a schematic layout diagram of a memory according to an embodiment of the disclosure.
Taking one Bank in DRAM as an example, the plurality of bit lines may be divided into 128 bit line groups, each having 8 bit lines therein, and the bit lines in each bit line group are denoted as BL0, BL1, and BL2. The plurality of word lines may be divided into 8192 word line groups, each having 8 word lines therein, and the word lines in each word line group are denoted as WL0, WL1, WL2, WL7 for convenience of description below.
The memory cells P11-P88 are distributed in a matrix, wherein the memory cells of the first column are connected with the word line WL0, the memory cells of the second column are connected with the word line WL1, and so on, the memory cells of the eighth column are connected with the word line WL7, the memory cells of the first row are connected with the bit line BL0, the memory cells of the second row are connected with the bit line BL1, and so on, the memory cells of the eighth row are connected with the bit line BL7, so that each memory cell is connected with one WL and one BL.
Referring to fig. 2, fig. 2 is a schematic structural diagram of a memory cell of a memory according to an embodiment of the disclosure.
In some embodiments, each memory cell 10 includes a transistor 12 and a capacitor 11, where the gate of the transistor 12 is connected to WL, the source of the transistor 12 is connected to BL, the drain of the transistor 12 is connected to the capacitor 11, and it should be noted that the source of the transistor 12 may also be connected to the capacitor 11, and accordingly, the drain of the transistor 12 is connected to BL.
In some embodiments, BL may write a high signal "1" to capacitor 11 when the signal on WL turns on transistor 12, and the charge on capacitor 11 slowly leaks over time after the signal on WL turns off transistor 12. The time between the leakage of the capacitor 11 from the high level signal "1" to the low level signal "0" is the data holding time of the capacitor 11. The data retention time of the capacitor 11 needs to be longer than a preset time to realize the dynamic memory function of the dynamic random access memory.
Since DRAM stores data in a capacitor, it has a characteristic that all data stored therein needs to be refreshed continuously for a limited time to prevent data loss. In the refresh process of the DRAM, the original data is first read, the level of the capacitor 11 is compared with the reference level, and after the 1/0 value of the data is judged, the original data is written back. The capacitor 11 is fully charged during the write back process (if the data is 1), as compared to a single charge operation.
In some embodiments, the refresh mode of the memory can be divided into an auto-refresh mode in which a refresh command is issued periodically by the controller and the memory is responsible for executing the refresh command, and a self-refresh mode in which the controller is responsible for transmitting only a command to enter the self-refresh mode and a command to exit the self-refresh mode, the refresh command being generated periodically by the memory itself after entering the self-refresh mode. However, the existing memory requires at least one refresh operation per data line when each refresh command is executed, thereby resulting in a larger power consumption of the memory.
Taking the self-refresh mode as an example, when the system enters the deep sleep state to save power consumption, no DRAM read/write request is generated, and it is not necessary to use the controller to maintain the DRAM state at this time, so the controller may be turned off, and the external clock of the DRAM may be stopped, and the self-refresh state is used to maintain the data in the DRAM to save power. There are many kinds of power consumption of the DRAM, in which IDD6 refers to a consumption current at the time of self-refresh of the DRAM. Each self-refresh operation of the DRAM is to switch each WL at least once in a self-refresh time, and data is restored to the capacitor by the operation of the WL switch, and the generation of the loss current is mainly caused by the large number of switching operations of the WL.
In view of the above technical problems, the embodiments of the present disclosure provide a memory refresh method, which determines refresh parameters corresponding to each data line according to a data retention time of a memory cell connected to each data line, when a memory executes a refresh command each time, the memory may perform refresh operation on only a portion of the data lines, instead of performing refresh operation on all the data lines, and some data lines may perform refresh operation once every several refresh commands, so that power consumption of the memory may be reduced, and especially, a consumption current of the memory in a self-refresh state may be reduced on the premise that data stored in the memory is not lost. Reference is made to the following examples for details.
It should be noted that, the memory refresh method provided in the embodiments of the present disclosure may be applied to a self-refresh mode of a memory or an auto-refresh mode of a memory, which is not limited in the embodiments of the present disclosure.
Referring to fig. 3, fig. 3 is a flowchart illustrating steps of a memory refresh method according to an embodiment of the disclosure. In some embodiments of the present disclosure, the memory includes a plurality of data lines, and the memory refresh method includes:
S301, acquiring a refresh parameter corresponding to the data line, wherein the refresh parameter is determined according to the data retention time of the memory cell connected with the data line.
In some embodiments, the data retention time of the memory cell may be interpreted as the time between the capacitor leaking from the high level signal "1" to the low level signal "0" after the capacitor in the memory cell is charged, or as the effective time after the data is written in the memory cell, the memory cell retains the accuracy of the stored data without causing errors in reading the data.
In some embodiments, the refresh parameters corresponding to the data lines may be determined according to the data retention time of the memory cells connected to the data lines in the memory, and stored in a specific storage manner. After the memory is powered on, the refresh parameters corresponding to the pre-stored data lines are acquired.
Alternatively, the data line may be a word line in a memory.
S302, determining the response interval times of the refresh command corresponding to the data line according to the refresh parameter corresponding to the data line.
In the embodiment of the disclosure, the refresh command response interval times corresponding to each data line can be determined according to the refresh parameters corresponding to each data line and the preset corresponding relation between each refresh parameter and the refresh command response interval times, wherein different refresh parameters correspond to different refresh command response interval times.
In some embodiments, a correspondence between a preset refresh parameter and the number of refresh command response intervals may be obtained. For example, when the refresh parameter is 1 bit, the refresh command response interval number corresponding to the preset refresh parameter "0" is 0 times, the refresh command response interval number corresponding to the refresh parameter "1" is 1 time, and when the refresh parameter is 2 bits, the refresh command response interval number corresponding to the preset refresh parameter "00" is 0 times, the refresh command response interval number corresponding to the refresh parameter "01" is 1 time, the refresh command response interval number corresponding to the refresh parameter "10" is 2 times, and the refresh command response interval number corresponding to the refresh parameter "11" is 3 times.
Wherein the number of refresh command response intervals is 0, indicating that a refresh operation is performed for each refresh command.
In some embodiments, the number of refresh command response intervals corresponding to each data line may be determined according to a correspondence between the refresh parameter and the number of refresh command response intervals and the refresh parameter corresponding to each data line.
The longer the data retention time of the memory cell connected to the data line, the greater the number of refresh command response intervals corresponding to the data line.
S303, carrying out refreshing operation on the data line according to the corresponding refreshing command response interval times of the data line.
In the embodiment of the disclosure, when the memory executes the refresh command, the refresh operation may be performed on each data line according to the number of refresh command response intervals corresponding to each data line.
In some embodiments, when the memory responds to the refresh command, the refresh frequency corresponding to the refresh command is determined, whether each data line belongs to the data line to be refreshed is determined according to the refresh frequency corresponding to the refresh command and the refresh command response interval frequency corresponding to each data line, when a certain data line belongs to the data line to be refreshed, the refresh operation is performed on the data line, and when the certain data line does not belong to the data line to be refreshed, the switch state of the data line is kept unchanged.
For example, assume that the refresh parameter is 1 bit, and the refresh command response interval corresponding to the refresh parameter "0" is 0 times, and the refresh command response interval corresponding to the refresh parameter "1" is 1 times. Referring to table 1, table 1 illustrates a first example of a refresh method for a plurality of data lines in an embodiment of the present disclosure.
TABLE 1A schematic representation of a refresh mode for a plurality of data lines in an embodiment of the present disclosure
As shown in table 1, since the refresh parameter corresponding to the data lines WL0, WL3, WL4 is "0", the memory performs the refresh operation on the data lines WL0, WL3, WL4 each time the refresh command is performed, and since the refresh parameter corresponding to the data lines WL1, WL2, WL5 is "1", the memory does not perform the refresh operation on the data lines WL1, WL2, WL5 when the refresh command is performed the first time, and the memory performs the refresh operation on the data lines WL1, WL2, WL5 only when the refresh command is performed the second time.
It will be appreciated that the memories in table 1 perform refresh operations for only a portion of the data lines when performing the refresh commands 1,3, 5. Therefore, the number of WL switches when the refresh command is executed can be reduced, and the power consumption of the memory in the refresh process can be reduced, including the current loss of the memory in the self-refresh state.
According to the memory refreshing method provided by the embodiment of the disclosure, the refreshing parameters corresponding to the data lines are determined according to the data retention time of the memory unit connected with the data lines, when the memory executes the refreshing command each time, only a part of the data lines can be refreshed according to the refreshing parameters corresponding to the data lines, but not all the data lines, and some data lines can be refreshed once at intervals for a plurality of times of refreshing commands, so that the power consumption of the memory can be reduced on the premise that the data stored in the memory is not lost.
Based on the description of the foregoing embodiments, in some embodiments of the present disclosure, before the refresh parameters corresponding to the data lines are obtained, detecting the data retention time of the memory cells connected to the data lines, and determining the refresh parameters corresponding to the data lines according to the data retention time of the memory cells connected to the data lines.
In some embodiments, a built-In Self Test (MBIST) may be used to detect the data retention time of the Memory cells to which each data line is connected.
In some embodiments, since each of the data lines is connected to a plurality of memory cells, when detecting the data retention time of the memory cell to which the data line is connected, the data retention time of each of the memory cells to which the data line is connected may be detected, and the minimum value of the data retention times of the memory cells to which the data line is connected is determined as the data retention time of the memory cell to which the data line is connected.
In some embodiments, when detecting the data retention time of the memory cell connected to the data line, each memory cell connected to the data line may be set as one memory sequence, and the data retention time of the memory sequence may be determined to be the data retention time of the memory cell connected to the data line.
Referring to fig. 4, fig. 4 is a flowchart illustrating a refinement step of detecting a data retention time of a memory cell connected to a data line in an embodiment of the disclosure.
In some embodiments, the detecting the data retention time of the memory cell connected to the data line includes:
s401, writing first data in a memory cell connected with a data line.
S402, reading the second data stored in the storage unit.
S403, comparing whether the second data are consistent with the first data, if so, returning to execute the step S402 after a preset time interval, otherwise, executing the step S404.
It can be understood that if the second data is consistent with the first data, it can be determined that the memory cell has no read error currently, and if the second data is inconsistent with the first data, it can be determined that the memory cell has a read error.
S404, determining the time when the memory cell first generates the read error as the data holding time of the memory cell.
In some embodiments, the time interval corresponding to each refresh parameter may be preset based on the refresh window tREFW, the time interval tREFI, and other parameters of the memory.
In some embodiments, after determining the data retention time of the memory cell, the refresh parameter corresponding to the data line may be determined according to the data retention time of the memory cell and the preset time interval corresponding to each refresh parameter.
According to the memory refreshing method provided by the embodiment of the disclosure, the refreshing parameters corresponding to the data lines are determined according to the data retention time of the memory cells connected with the data lines, and when the memory executes the refreshing command each time, only a part of the data lines are refreshed according to the refreshing parameters corresponding to the data lines, instead of all the data lines, so that the power consumption of the memory can be reduced on the premise that the data stored in the memory is not lost.
Based on the foregoing description of the embodiments, in some embodiments of the present disclosure, after determining the refresh parameter corresponding to each data line, the state of at least one programmable logic device corresponding to each data line may be adjusted according to the refresh parameter corresponding to each data line.
Alternatively, the programmable logic device may be a one-time programmable (One Time Programmable, OTP) device based on Fuse (Fuse) technology (hereinafter referred to as Fuse device), or the programmable logic device may be a one-time programmable device based on antifuse (AntiFuse) technology (hereinafter referred to as antifuse device).
Wherein, the anti-fuse type device realizes '1' to '0' programming by breaking down an insulating layer between a polysilicon layer and an N+ diffusion layer of a programming tube, so that a resistance value between the two layers is changed (reduced), resulting in a change of an equivalent logic value. The fuse type device is programmed by blowing the fuse according to the electromigration characteristics, so that the resistance values at two ends of the fuse are changed.
Specifically, when the fuse memory cells of the fuse type device are shipped, the states of the fuses are the same, the fuse memory cells can be regarded as a small resistor or a wire, data "0" is stored at the time, when programming is performed, according to the data storage requirement, a current with a sufficient large data bit is given to some specific fuse memory cells to blow the fuses, and the fuse memory cells after blowing the fuses are equivalent to open or a large resistor, so that the fuse memory cells store "1".
The antifuse-type device corresponding to the fuse-type device may exhibit very large resistance of the antifuse in each antifuse memory cell at the time of shipment, and thus have good electrical isolation performance, and may be regarded as an open circuit, which stores data "0". In programming, a high programming voltage is applied to the data bits of certain specific anti-fuse memory cells according to the data storage requirement, so that the anti-fuses in the anti-fuse memory cells are broken down, the broken down anti-fuse memory cells show a small resistance, and the broken down anti-fuse memory cells store data '1'.
In some embodiments, after the memory is powered on, reading the state of the at least one programmable logic device, and obtaining the refresh parameter corresponding to the data line according to the state of the at least one programmable logic device.
Wherein the states of the programmable logic device include "0" and "1".
In some embodiments, the memory may include a refresh circuit, a refresh frequency counter, and programmable logic devices corresponding to each data line, where the refresh circuit reads a state of the programmable logic device corresponding to each data line when executing the refresh command, and determines, according to the state of the programmable logic device corresponding to each data line and a count result of the refresh frequency counter, a data line that needs to be refreshed and a data line that does not need to be refreshed.
In some embodiments, each data line may correspond to one or more programmable logic devices, the number of which may be selected according to the number of kinds of refresh parameters. For example, each data line may correspond to one programmable logic device when two refresh parameters are present, two programmable logic devices when three or four refresh parameters are present, three programmable logic devices when five to eight refresh parameters are present, and so on.
For example, assuming that four refresh parameters exist, the refresh command response interval number corresponding to the refresh parameter "00" is 0 times, the refresh command response interval number corresponding to the refresh parameter "01" is 1 time, the refresh command response interval number corresponding to the refresh parameter "10" is 2 times, and the refresh command response interval number corresponding to the refresh parameter "11" is 3 times. Referring to table 2, table 2 illustrates a second example of a refresh mode of the plurality of data lines in an embodiment of the present disclosure.
TABLE 2 schematic representation of the refresh mode of multiple data lines in an embodiment of the present disclosure
As shown in table 2, the Fuse state corresponding to the data line WL0 is "00", so that the memory performs a refresh operation on the data line WL0 every time a refresh command is executed, the Fuse state corresponding to the data line WL1, WL2 is "01", so that the memory performs no refresh operation on the data line WL1, WL2 when refresh commands are executed 1, 3,5, and m (a multiple of 3) times, the memory performs a refresh operation on the data line WL1, WL2 only when refresh commands are executed 2, 4, n (a multiple of 2) times, the Fuse state corresponding to the data line WL3 is "10", so that the memory performs no refresh operation on the data line WL3 when refresh commands are executed 1,2, 4,5, 7, and m (a multiple of 3) times, and the memory performs no refresh operation on the data line WL3 only when refresh commands are executed 3, 6, m (a multiple of 3) times, and the Fuse state corresponding to the data line WL4 is "11", and the Fuse state corresponding to the data line WL3, 4, and the Fuse state corresponding to the data line WL3, and the Fuse state corresponding to the data line WL4 are executed only when refresh commands are executed 4, and 3.
In some embodiments, multiple data lines may also correspond to the same one or more programmable logic devices.
For example, each two data lines may correspond to the same programmable logic device.
For example, assume that there are two refresh parameters, the refresh command response interval number corresponding to refresh parameter "0" is 0 times, and the refresh command response interval number corresponding to refresh parameter "1" is 1 times. Referring to table 3, table 3 illustrates a third example of a refresh mode of the plurality of data lines in an embodiment of the present disclosure.
TABLE 3 schematic representation of the refresh mode of multiple data lines in an embodiment of the present disclosure
In the above embodiment, the plurality of data lines correspond to the same one or more programmable logic devices, so that the number of programmable logic devices in the memory can be reduced, and the cost of the memory can be reduced.
In some embodiments, after determining the refresh parameter corresponding to each data line, the refresh parameter corresponding to each data line may also be stored in at least one register by programming.
Taking DRAM as an example, each mode register within DRAM typically comprises 8 bits, and each mode register stores a minimum of 4 data lines to which it can be associated, assuming that there are 4 different refresh parameters for the data lines.
Based on the descriptions in the above embodiments, in some embodiments of the present disclosure, the data retention time of the memory cell connected to the data line may be redetected every preset time period, and the refresh parameter corresponding to the data line may be updated according to the redetected data retention time.
It can be understood that, as the service time of the memory increases, the reliability of the memory also decreases, so that the data retention time of the memory cells connected to the data lines can be detected again every a preset time period, and the refresh parameters corresponding to the data lines can be updated according to the latest detected data retention time, so that the power consumption of the memory can be reduced without losing the data stored in the memory.
Based on what is described in the above embodiments, a memory refresh device is also provided in the embodiments of the present disclosure. Referring to fig. 5, fig. 5 is a schematic program module of a memory refresh apparatus provided in an embodiment of the disclosure, and the memory refresh apparatus 50 includes:
The acquisition module 501 is configured to acquire a refresh parameter corresponding to a data line, where the refresh parameter is determined according to a data retention time of a memory cell connected to the data line.
A determining module 502, configured to determine the number of refresh command response intervals corresponding to the data line according to the refresh parameter corresponding to the data line.
And a refreshing module 503, configured to perform a refreshing operation on the data line according to the number of refresh command response intervals corresponding to the data line.
According to the memory refreshing device provided by the embodiment of the disclosure, the refreshing parameters corresponding to the data lines are determined according to the data retention time of the memory unit connected with the data lines, when the memory executes the refreshing command each time, only a part of the data lines can be refreshed according to the refreshing parameters corresponding to the data lines, but not all the data lines, and some data lines can be refreshed once at intervals for a plurality of times of refreshing commands, so that the power consumption of the memory can be reduced on the premise that the data stored in the memory is not lost.
In some embodiments, the refresh module 503 is to:
When the memory responds to a refresh command, determining the refresh times corresponding to the refresh command;
Determining whether the data line belongs to a data line to be refreshed or not according to the refresh times corresponding to the refresh command and the refresh command response interval times corresponding to the data line;
And when the data line belongs to the data line to be refreshed, carrying out refreshing operation on the data line, and when the data line does not belong to the data line to be refreshed, keeping the switching state of the data line unchanged.
In some embodiments, the apparatus further comprises a detection module configured to:
detecting the data retention time of a storage unit connected with the data line;
And determining a refresh parameter corresponding to the data line according to the data retention time of the memory cell.
In some embodiments, the detection module is configured to:
writing first data in the memory cell;
reading the second data stored in the storage unit for a plurality of times according to a preset interval duration;
Comparing the first data with the second data read each time, and determining the time when the memory cell first generates a read error;
And determining the time when the memory cell first generates a read error as the data retention time of the memory cell.
In some embodiments, the detection module is configured to:
And determining the refresh parameters corresponding to the data lines according to the data retention time of the memory cells and the preset time intervals corresponding to the refresh parameters.
In some embodiments, the apparatus further comprises an adjustment module configured to:
and adjusting the state of at least one programmable logic device corresponding to the data line according to the refresh parameter corresponding to the data line.
In some embodiments, the obtaining module 501 is configured to:
Reading the state of the at least one programmable logic device;
And obtaining the refresh parameter corresponding to the data line according to the state of the at least one programmable logic device.
In some embodiments, the determining module 502 is configured to:
And determining the refresh command response interval times corresponding to the data lines according to the refresh parameters corresponding to the data lines and the corresponding relation between each preset refresh parameter and the refresh command response interval times, wherein different refresh parameters correspond to different refresh command response interval times.
In some embodiments, the apparatus further includes an update module configured to:
and re-detecting the data retention time of the storage unit connected with the data line at intervals of preset time, and updating the refresh parameter corresponding to the data line according to the re-detected data retention time.
It should be noted that, in the embodiment of the present disclosure, the specific execution of the acquiring module 501, the determining module 502, and the refreshing module 503 may refer to the relevant content in the embodiment shown in fig. 1 to 4, which is not described herein.
Further, based on the description in the foregoing embodiment, an electronic device is further provided in the embodiment of the present disclosure, where the electronic device includes at least one processor and a memory, where the memory stores computer-executable instructions, and the at least one processor executes the computer-executable instructions stored in the memory to implement each step in the memory refresh method described in the foregoing embodiment, and this embodiment is not described herein again.
For a better understanding of the embodiments of the present disclosure, referring to fig. 6, fig. 6 is a schematic hardware structure of an electronic device according to an embodiment of the present disclosure.
As shown in fig. 5, the electronic device 60 of the present embodiment includes a processor 601 and a memory 602, wherein:
A memory 602 for storing computer-executable instructions;
The processor 601 is configured to execute the computer-executable instructions stored in the memory to implement the steps of the memory refresh method described in the foregoing embodiments, and specific reference may be made to the description of the foregoing method embodiments.
In some embodiments, the memory 602 may be separate or integrated with the processor 601.
When the memory 602 is provided separately, the device further comprises a bus 603 for connecting the memory 602 and the processor 601.
Further, based on the foregoing embodiments, a computer readable storage medium is further provided in the embodiments of the present disclosure, where computer executable instructions are stored in the computer readable storage medium, and when the processor executes the computer executable instructions, the steps in the memory refresh method described in the foregoing embodiments are implemented, which is not described herein again.
In the several embodiments provided in the present disclosure, it should be understood that the disclosed apparatus and method may be implemented in other ways. For example, the above-described embodiments of the apparatus are merely illustrative, and for example, the above-described division of modules is merely a logical function division, and there may be other manners of division in actual implementation, for example, multiple modules may be combined or integrated into another system, or some features may be omitted, or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or modules, which may be in electrical, mechanical, or other forms.
The modules described above as separate components may or may not be physically separate, and components shown as modules may or may not be physical units, may be located in one place, or may be distributed over multiple network units. Some or all of the modules may be selected according to actual needs to achieve the purpose of the solution of this embodiment.
In addition, each functional module in the embodiments of the present disclosure may be integrated in one processing unit, or each module may exist alone physically, or two or more modules may be integrated in one unit. The integrated units of the modules can be realized in a form of hardware or a form of hardware and software functional units.
Finally, it should be noted that the foregoing embodiments are merely for illustrating the technical solutions of the present disclosure, and not for limiting the same, and although the present disclosure has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that the technical solutions described in the foregoing embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present disclosure.
Claims (20)
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