CN119067025A - A timing adjustment method, device, equipment and medium - Google Patents
A timing adjustment method, device, equipment and medium Download PDFInfo
- Publication number
- CN119067025A CN119067025A CN202411161615.2A CN202411161615A CN119067025A CN 119067025 A CN119067025 A CN 119067025A CN 202411161615 A CN202411161615 A CN 202411161615A CN 119067025 A CN119067025 A CN 119067025A
- Authority
- CN
- China
- Prior art keywords
- timing
- division multiplexing
- path
- programmable gate
- gate array
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/33—Design verification, e.g. functional simulation or model checking
- G06F30/3308—Design verification, e.g. functional simulation or model checking using simulation
- G06F30/3312—Timing analysis
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/31—Design entry, e.g. editors specifically adapted for circuit design
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F30/00—Computer-aided design [CAD]
- G06F30/30—Circuit design
- G06F30/32—Circuit design at the digital level
- G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist
-
- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2111/00—Details relating to CAD techniques
- G06F2111/20—Configuration CAD, e.g. designing by assembling or positioning modules selected from libraries of predesigned modules
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Evolutionary Computation (AREA)
- Geometry (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Design And Manufacture Of Integrated Circuits (AREA)
Abstract
The invention discloses a time sequence adjusting method, a time sequence adjusting device and a time sequence adjusting medium, and relates to the field of integrated circuit design. When confirming that the time sequence violations of the FPGA prototype version exist, the method does not adopt re-segmentation iteration, but obtains the time sequence resource report, the reason of the violation path and the netlist file corresponding to each FPGA prototype version of the time sequence violations to determine the time sequence violations of the FPGA prototype version, determines the newly added time division multiplexing paths based on the netlist file, performs pre-layout and interconnection relation determination on the newly added time division multiplexing paths, performs physical region constraint on the time division multiplexing modules corresponding to each newly added time division multiplexing paths, and generates the engineering file after the time sequence path adjustment to complete the time sequence convergence. The scheme solves the problem of timing violations by adding and adjusting the time division multiplexing paths of off-chip interconnection, avoids the need of re-segmentation iteration of the whole platform version caused by individual path timing violations, and greatly improves the timing convergence efficiency.
Description
Technical Field
The present invention relates to the field of integrated circuit design, and in particular, to a timing adjustment method, apparatus, device, and medium.
Background
The field programmable gate array (Field Programmable GATE ARRAY, FPGA) prototype plays a key role in Application SPECIFIC INTEGRATED Circuit (ASIC) design and verification, and provides a verification platform for simulating the behavior of the ASIC to help hardware and software developers improve the working efficiency. As the complexity of ASIC designs increases, so does the resource requirements of FPGA prototypes, which typically require multiple FPGAs to build the prototype platform.
The FPGA prototype version manufacturing is a process of adapting ASIC design to a plurality of FPGAs, and mainly comprises the steps of compiling, dividing, mapping, timing convergence, generating bit files and the like. The timing convergence is a difficulty of a multi-chip prototype platform, and each FPGA needs to meet timing requirements. If one FPGA time sequence is not satisfied, the segmentation strategy and the resource allocation are required to be modified, and the whole process is carried out again, so that the time is very consumed. In the traditional prototype version production, the segmentation is tried for many times mainly depending on the experience of engineers, however, even if the time sequence violations are small, the segmentation is needed again, the uncertainty of the production period is increased, and the follow-up verification work is easy to delay.
In view of the above problems, how to solve the problem that in the current FPGA prototype version production, the FPGA needs to be segmented again whenever a timing violation occurs, and the efficiency is low is a problem to be solved by those skilled in the art.
Disclosure of Invention
The invention aims to provide a time sequence adjusting method, a device, equipment and a medium, which are used for solving the problems that in the current FPGA prototype version production, the time sequence violations of an FPGA are required to be segmented again and the efficiency is low.
In order to solve the above technical problems, the present invention provides a timing adjustment method, including:
when the time sequence of the field programmable gate array prototype version cannot be converged, acquiring a time sequence resource report, a violation path reason and a netlist file corresponding to each field programmable gate array prototype version of which the time sequence cannot be converged, wherein the time sequence resource report at least comprises data of congestion, high fan-out, wiring density and resource utilization rate;
Mapping the time sequence resource report and the violation path reason into the corresponding netlist file so as to mark time sequence information corresponding to the field programmable gate array prototype version in the netlist file;
determining a newly added time division multiplexing path according to the netlist file, and pre-laying out the newly added time division multiplexing path;
generating each newly added time division multiplexing path based on each netlist file, and determining the interconnection relation of each newly added time division multiplexing path in each netlist file;
And performing physical area constraint on the time division multiplexing module corresponding to each newly added time division multiplexing path, and generating an engineering file after time sequence path adjustment so as to finish time sequence convergence.
In one aspect, before the acquiring the timing resource report, the violation path reason and the netlist file corresponding to each field programmable gate array prototype version where the timing cannot be converged, the method further includes:
configuring each field programmable gate array prototype version;
Judging whether the configuration of all the field programmable gate array prototype versions is completed or not;
If the configuration of all the field programmable gate array prototype versions is not completed, returning to the step of configuring each field programmable gate array prototype version;
If the configuration of all the field programmable gate array prototype versions is completed, judging whether the timing sequence of the field programmable gate array prototype versions cannot be converged;
if the time sequence of the field programmable gate array prototype version cannot be converged, generating a bit stream file and performing platform adaptation operation to finish the manufacturing of the field programmable gate array prototype version;
If the time sequence of the field programmable gate array prototype version cannot be converged, judging whether the resource occupancy rate of the field programmable gate array prototype version, which cannot be converged by all the time sequences, is not greater than a first threshold value, and the corresponding maximum setup time violation or the corresponding maximum hold time violation is not less than a second threshold value;
If the resource occupancy rate of the field programmable gate array prototype versions with the timing sequence incapable of converging is larger than a first threshold value and/or the corresponding maximum setup time violation or the corresponding maximum hold time violation is smaller than a second threshold value, reducing the system clock frequency or adjusting the resource allocation of each field programmable gate array prototype version, and re-dividing each field programmable gate array prototype version;
If the resource occupancy rate of all the field programmable gate array prototype versions which cannot be converged in the time sequence is not greater than a first threshold and the corresponding maximum setup time violation or the maximum hold time violation is not less than a second threshold, entering a step of acquiring a time sequence resource report, a violation path reason and a netlist file corresponding to each field programmable gate array prototype version which cannot be converged in the time sequence.
On the other hand, obtaining the timing resource report and the reason of the violation path corresponding to each field programmable gate array prototype version that cannot converge the timing includes:
acquiring congestion, high fan-out, wiring density and resource utilization data of each field programmable gate array prototype version to obtain the time sequence resource report;
acquiring a time sequence report of each field programmable gate array prototype version, and deriving a corresponding time sequence violation path based on each time sequence report;
And analyzing each time sequence violation path to determine the reason of the violation path.
In another aspect, the mapping the timing resource report and the violation path cause to the corresponding netlist file to label timing information corresponding to the field programmable gate array prototype version in the netlist file includes:
Mapping the congestion, high fan-out, wiring density and resource utilization rate data of each field programmable gate array prototype version into the corresponding netlist file according to a slice level;
Labeling each time sequence violation path and a corresponding time division multiplexing module thereof into a corresponding netlist file;
and copying the register information of the high fan-out on the timing violation path based on the high fan-out according to each violation path reason.
On the other hand, the determining the newly added time division multiplexing path according to the netlist file and pre-laying out the newly added time division multiplexing path comprises the following steps:
Judging whether the resource utilization rate of the time division multiplexing position adjacent to the time sequence violation path is lower than a third threshold according to each netlist file and the register information;
If not, returning the next position adjacent to the time division multiplexing position as the new time division multiplexing position adjacent to the time sequence violation path to the step of judging whether the resource utilization rate of the time division multiplexing position adjacent to the time sequence violation path is lower than a third threshold according to the netlist files and the register information;
if yes, determining the newly added time division multiplexing path according to the time division multiplexing position;
The time division multiplexing device comprises a time division multiplexing position and a number of time division multiplexing related modules, wherein the related modules at least comprise a clock module, a multiplexer, a demultiplexer, a receiving buffer, a sending buffer and a data encoding and decoding module;
and writing constraint sentences of the time division multiplexing modules corresponding to the newly added time division multiplexing paths according to the time division multiplexing positions and the netlist file.
In another aspect, the generating each of the newly added time division multiplexing paths based on each of the netlist files and determining an interconnection relationship of each of the newly added time division multiplexing paths in each of the netlist files includes:
Judging whether the timing violation of the timing violation path is caused by high fan-out;
if yes, maintaining the time sequence violation path;
If not, disconnecting the timing violation path.
On the other hand, after the physical area constraint is performed on the time division multiplexing module corresponding to each newly added time division multiplexing path and the engineering file with the adjusted time sequence path is generated, the method further comprises:
Generating a bit stream file and performing platform adaptation operation to complete the manufacture of the field programmable gate array prototype version;
generating a log containing the information of the time sequence violation processing process.
In order to solve the above technical problem, the present invention further provides a timing adjustment device, including:
The acquisition module is used for acquiring a time sequence resource report, a violation path reason and a netlist file corresponding to each field programmable gate array prototype version with the non-convergence time sequence when the non-convergence time sequence of the field programmable gate array prototype version exists, wherein the time sequence resource report at least comprises data of congestion, high fan-out, wiring density and resource utilization rate;
The mapping module is used for mapping the time sequence resource report and the violation path reason into the corresponding netlist file so as to mark time sequence information corresponding to the field programmable gate array prototype version in the netlist file;
The determining module is used for determining a newly added time division multiplexing path according to the netlist file and pre-laying out the newly added time division multiplexing path;
The generating module is used for generating each newly added time division multiplexing path based on each netlist file and determining the interconnection relation of each newly added time division multiplexing path in each netlist file;
And the constraint module is used for carrying out physical area constraint on the time division multiplexing module corresponding to each newly added time division multiplexing path and generating an engineering file after the time sequence path is adjusted so as to finish time sequence convergence.
In order to solve the above technical problem, the present invention further provides a timing adjustment apparatus, including:
A memory for storing a computer program;
And the processor is used for realizing the steps of the time sequence adjusting method when executing the computer program.
To solve the above technical problem, the present invention further provides a computer readable storage medium, on which a computer program is stored, which when executed by a processor, implements the steps of the timing adjustment method described above.
The method comprises the steps of obtaining a time sequence resource report, an illegal path reason and a netlist file corresponding to each field programmable gate array prototype version, wherein the time sequence resource report at least comprises data of congestion, high fan-out, wiring density and resource utilization rate, mapping the time sequence resource report and the illegal path reason into the corresponding netlist file to mark time sequence information corresponding to the field programmable gate array prototype version in the netlist file, determining a newly added time division multiplexing path according to the netlist file, pre-laying out the newly added time division multiplexing path, generating each newly added time division multiplexing path based on each netlist file, determining the interconnection relation of each newly added time division multiplexing path in each netlist file, and carrying out physical area constraint on the time division multiplexing module corresponding to each newly added time division multiplexing path and generating an engineering file after time sequence path adjustment so as to finish time sequence convergence.
The method has the advantages that when the situation that the time sequence of the FPGA prototype version cannot be converged is confirmed, a re-segmentation iteration mode is not adopted, the time sequence resource report, the violation path reason and the netlist file corresponding to each FPGA prototype version of which the time sequence cannot be converged are acquired, so that the time sequence violation reason of the FPGA prototype version is clear, the newly added time division multiplexing path is further determined based on the netlist file containing the time sequence violation reason, after the newly added time division multiplexing paths are subjected to pre-layout and interconnection relation determination, physical area constraint is carried out on the time division multiplexing modules corresponding to each newly added time division multiplexing path, and the engineering file with the adjusted time sequence path is generated to complete the time sequence convergence. By the scheme, the problem of solving time sequence violations such as congestion, too long time sequence path, high fan-out and the like is solved by adding and adjusting the time division multiplexing paths of the off-chip interconnection, the problem that the whole platform version needs to be segmented again and iterated due to individual path time sequence violations is avoided, the time sequence convergence efficiency is greatly improved, and the manufacturing period of the FPGA prototype version is shortened.
In addition, the invention also provides a time sequence adjusting device, equipment and medium, and the effects are the same as the above.
Drawings
For a clearer description of embodiments of the present invention, the drawings that are required to be used in the embodiments will be briefly described, it being apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to the drawings without inventive effort for those skilled in the art.
FIG. 1 is a flow chart of conventional FPGA prototype version fabrication provided by an embodiment of the present invention;
FIG. 2 is a flowchart of a timing adjustment method according to an embodiment of the present invention;
FIG. 3 is a flowchart of optimized FPGA prototype version fabrication provided by an embodiment of the present invention;
FIG. 4 is a schematic diagram of an FPGA prototype platform before and after timing adjustment according to an embodiment of the present invention;
FIG. 5 is a schematic diagram of a timing adjustment device according to an embodiment of the present invention;
fig. 6 is a schematic diagram of a timing adjustment apparatus according to an embodiment of the present invention.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by a person of ordinary skill in the art without making any inventive effort are within the scope of the present invention.
The core of the invention is to provide a time sequence adjusting method, a device, equipment and a medium, so as to solve the problem that in the current FPGA prototype version production, the FPGA needs to be segmented again every time a time sequence violation occurs, and the efficiency is low.
In order to better understand the aspects of the present invention, the present invention will be described in further detail with reference to the accompanying drawings and detailed description.
Fig. 1 is a flowchart of conventional FPGA prototype version fabrication provided in an embodiment of the present invention. As shown in fig. 1, to implement FPGA prototype version fabrication, the register transfer level code (REGISTER TRANSFER LEVEL, RTL) source files of the ASIC chip are specifically imported into an electronic design automation (Electronic Design Automation, EDA) tool for compilation to diagnose the design file and add debug analysis probes, thereby completing the circuit design compilation. And then, performing pre-segmentation processing according to the requirements of a prototype platform user, and automatically segmenting the design. Then, the design is divided according to each piece of interconnection relation obtained in the previous step. And then completing system wiring and system generation through an EDA tool, wherein the step mainly performs related work according to the time sequence requirement. And then, carrying out circuit synthesis steps such as comprehensive compiling, pre-mapping, mapping and the like on each FPGA. Placement and routing using the Vivado tool is aimed at completing timing closure of the slice FPGA, which may require trying different strategies. It is understood that the Vivado tool is an EDA tool for FPGA design. It provides a complete design flow from design input, synthesis, place and route to verification and simulation. The Vivado tool has a highly integrated design environment and a new generation of system-to-chip tools, both of which are built on a shared extensible data model and a generic debug environment. Its main functions include RTL code writing, function simulation, synthesis and implementation. The goal of the Vivado tool is to help hardware designers shorten compile time and design iterations while providing more accurate power supply estimates.
In a specific implementation, if timing convergence cannot be completed, parameters such as each piece of resource allocation, clock frequency and the like need to be readjusted, which requires experience and multiple attempts of engineers, and links such as pre-segmentation, system wiring, system generation, comprehensive compiling, pre-mapping, vivado layout and wiring and the like may need to be carried out again, which is time-consuming and cannot guarantee timing convergence. Finally, when all the time sequences of the FPGA are converged and bit files are generated, prototype version production is completed. If the timing of one of the FPGAs is not satisfied or fails to be implemented, the above procedure needs to be properly adjusted and re-performed. Therefore, the traditional method for manufacturing the prototype version of the FPGA has larger time consumption for a producer, and the version manufacturing time has uncertainty, so that delay is easily caused for the work of subsequent prototype verifiers. In order to solve the above problems, the present invention provides a timing adjustment method.
Fig. 2 is a flowchart of a timing adjustment method according to an embodiment of the present invention. As shown in fig. 2, the method includes:
And S10, when the time sequence of the field programmable gate array prototype version cannot be converged, acquiring a time sequence resource report, a violation path reason and a netlist file corresponding to each field programmable gate array prototype version of which the time sequence cannot be converged.
The time sequence resource report at least comprises data of congestion, high fan-out, wiring density and resource utilization rate.
In the process of manufacturing the FPGA prototype version, when the fact that the timing sequence of the FPGA prototype version cannot be converged is confirmed, and timing sequence violations exist, a timing sequence resource report, a violation path reason and a netlist file corresponding to each FPGA prototype version, the timing sequence of which cannot be converged, are obtained.
It should be noted that the timing resource report at least includes Congestion (Congestion), high Fanout (High Fanout), routing Density (Routing Density), and resource utilization (Resource Utilization). Congestion, high fan-out, routing density, and resource utilization are four important concepts that describe the implementation of a design within an FPGA and directly affect the timing performance and resource utilization efficiency of the design. Specifically, congestion refers to the situation that the wiring path is too long or cannot be routed due to insufficient wiring resources in the FPGA. Congestion typically occurs in areas of a design where routing resources are required, such as high speed interfaces, complex logic, etc. Congestion can cause increased signal delays, which in turn can affect the timing performance of the design. High fanout refers to the connection of the output of one signal or module to the input of a plurality of other signals or modules. High fan-out can result in reduced driving capability of the signal, increasing delay and power consumption of the signal. In FPGA designs, high fan-out typically needs to be addressed by adding buffers or using dedicated routing resources. The wiring density refers to the extent to which the wiring resources within the FPGA are used. A higher wiring density means that the use of wiring resources is more efficient, but at the same time the risk of congestion is increased. In the FPGA design, the use of wiring resources is required to be reasonably planned according to the design requirements and the characteristics of FPGA resources so as to balance the relationship between wiring density and time sequence performance. The resource utilization ratio refers to the ratio of the FPGA logic resources used by the design to the FPGA total resources. The higher resource utilization means that the design utilizes the logic resources of the FPGA more fully, but at the same time increases the difficulty and risk of design implementation. In the FPGA design, the use of logic resources is reasonably planned according to the design requirements and the characteristics of FPGA resources so as to balance the relationship between the resource utilization rate and the design implementation difficulty.
In addition, the netlist file is a description file of the FPGA design logic structure, and is generated after synthesis is performed in an FPGA design tool such as Vivado. The netlist file is composed of cells, pins, ports and networks, and contains connection relations and attribute information among the logic cells in the design. The netlist file is an important intermediate product in the design of the FPGA, and is used for subsequent layout and routing, timing analysis, program downloading, and the like. Through the netlist file, the FPGA design tool can determine the implementation mode of the design in the FPGA and generate a corresponding bit stream file for configuring the FPGA.
In this embodiment, the time sequence resource report and the acquisition process of the reason of the offending path are not limited, and depend on the specific implementation situation.
And S11, mapping the time sequence resource report and the violation path reasons into corresponding netlist files so as to mark time sequence information of corresponding field programmable gate array prototype versions in the netlist files.
Further, mapping the time sequence resource report and the violation path reasons into corresponding netlist files to mark time sequence information of corresponding FPGA prototype versions in the netlist files, so as to obtain a plurality of FPGA netlist files containing the time sequence information of the FPGA prototype versions. In this embodiment, the specific process of mapping the timing resource report and the reason of the violation path to the corresponding netlist file is not limited, and depends on the specific implementation.
S12, determining a newly added time division multiplexing path according to the netlist file, and pre-laying out the newly added time division multiplexing path.
After obtaining the netlist file mapped with the time sequence resource report and the reason of the violation path, some key information of the prototype version of the FPGA needs to be analyzed according to the related information in the netlist file, so as to determine a newly added time division multiplexing path. The time division multiplexing path is added to supplement the original time division multiplexing path in the FPGA prototype platform version, and the problem that the timing sequence of the current FPGA prototype version cannot be converged can be solved by adding the time division multiplexing path. After the newly added time division multiplexing path is determined, in order to configure the newly added time division multiplexing path, the newly added time division multiplexing path also needs to be pre-laid out.
In this embodiment, the determination manner and the pre-layout process of the added time division multiplexing path are not limited, and depend on the specific implementation situation.
S13, generating each newly added time division multiplexing path based on each netlist file, and determining the interconnection relation of each newly added time division multiplexing path in each netlist file.
S14, the time division multiplexing module corresponding to each newly added time division multiplexing path is subjected to physical area constraint, and an engineering file after time sequence path adjustment is generated, so that time sequence convergence is completed.
Further, generating the determined newly added time division multiplexing paths in all netlist files, and determining the interconnection relation of the newly added time division multiplexing paths in each netlist file. And (3) performing Physical Block (Pblock) constraint on the time division multiplexing module corresponding to each newly added time division multiplexing path. In FPGA design, pblock is a constraint method for defining physical areas that allows a designer to specify specific areas within an FPGA chip for implementing specific logic functions or meeting specific layout wiring requirements. By using the Pblock constraint, a designer can better control the layout and wiring process of the design, and the time sequence performance and the resource utilization efficiency of the design are improved. And finally, generating an engineering file after the time sequence path adjustment, namely a Vivado engineering file, so as to finish the time sequence convergence.
In the embodiment, when confirming that the time sequence of the FPGA prototype version cannot be converged, a re-segmentation iteration mode is not adopted, and the time sequence resource report, the reason of the violation path and the netlist file corresponding to each FPGA prototype version of which the time sequence cannot be converged are acquired, so that the time sequence violation reason of the FPGA prototype version is clear, further, based on the netlist file containing the time sequence violation reason, a newly added time division multiplexing path is determined, after the newly added time division multiplexing path is subjected to pre-layout and interconnection relation determination, physical region constraint is carried out on the time division multiplexing module corresponding to each newly added time division multiplexing path, and the engineering file after the time sequence path adjustment is generated, so that the time sequence convergence is completed. By the scheme, the problem of solving time sequence violations such as congestion, too long time sequence path, high fan-out and the like is solved by adding and adjusting the time division multiplexing paths of the off-chip interconnection, the problem that the whole platform version needs to be segmented again and iterated due to individual path time sequence violations is avoided, the time sequence convergence efficiency is greatly improved, and the manufacturing period of the FPGA prototype version is shortened.
Based on the above embodiments, in some embodiments, before acquiring the timing resource report, the reason of the violation path, and the netlist file corresponding to each field programmable gate array prototype version where the timing cannot converge, the method further includes:
S101, configuring prototype versions of all field programmable gate arrays;
S102, judging whether the configuration of all field programmable gate array prototype versions is completed or not, if not, returning to the step S101, and if so, entering the step S103:
S103, judging whether the time sequence of the field programmable gate array prototype version cannot be converged or not, if not, entering a step S104, and if so, entering a step S105;
s104, generating a bit stream file and performing platform adaptation operation to finish the manufacture of a field programmable gate array prototype version;
S105, judging whether the resource occupancy rate of all field programmable gate array prototype versions which cannot be converged in time sequence is not larger than a first threshold value, and the corresponding maximum setup time violation or the corresponding maximum hold time violation is not smaller than a second threshold value, if not, entering a step S106, and if so, entering a step S10;
s106, reducing the system clock frequency or adjusting the resource allocation of each field programmable gate array prototype version, and re-dividing each field programmable gate array prototype version.
Fig. 3 is a flowchart of optimized FPGA prototype version fabrication provided in an embodiment of the present invention. In order to avoid multiple re-segmentation iterations, as shown in fig. 3, the scheme preferably configures all FPGA prototype versions, and then determines whether the timing cannot converge. It can be appreciated that the configuration of the prototype version of the FPGA specifically includes operations such as comprehensive compiling, pre-mapping, and layout and wiring.
In specific implementation, whether the configuration of all the FPGA prototype versions is completed is judged in real time. If the configuration of all the FPGA prototype versions is completed, judging whether the timing sequence of the FPGA prototype versions cannot be converged or not.
If the timing sequence of the FPGA prototype version cannot be converged, generating a bit stream file and performing platform adaptation operation to finish the manufacture of the FPGA prototype version. If the timing sequence of the FPGA prototype version cannot be converged, a plurality of collaborative timing violation path integration processing flows are started. And specifically judging whether the resource occupancy rate of all the FPGA prototype versions which cannot be converged in the time sequence is not larger than a first threshold, and the corresponding maximum setup time violation or the corresponding maximum hold time violation is not smaller than a second threshold. In this embodiment, the first threshold and the second threshold are not limited, for example, the first threshold may be set to be 50%, the second threshold may be set to be-2 ns, and then it is determined whether the resource occupancy rate of all FPGA prototype versions whose timings cannot converge is not greater than 50%, and the corresponding maximum setup time violation or the maximum hold time violation is not less than-2 ns.
If the resource occupancy rate of the FPGA prototype versions with the timing sequence incapable of converging is larger than a first threshold value and/or the corresponding maximum setup time violation or the corresponding maximum hold time violation is smaller than a second threshold value, the threshold value of the multi-piece cooperative processing is not met at the moment, or the timing sequence violation is needed to be eliminated by re-segmentation iteration, namely, the system clock frequency is reduced or the resource allocation of each FPGA prototype version is adjusted, and each FPGA prototype version is segmented again. If the resource occupancy rate of all the FPGA prototype versions which cannot be converged in the time sequence is not greater than the first threshold and the corresponding maximum setup time violation or the maximum hold time violation is not less than the second threshold, the threshold which is processed cooperatively by a plurality of pieces is considered to be met, and the steps of acquiring the time sequence resource report, the violation path reason and the netlist file corresponding to each FPGA prototype version which cannot be converged in the time sequence are carried out, so that the time sequence violation is eliminated by adding a time division multiplexing path.
Based on the above embodiments, in some embodiments, obtaining a timing resource report and a reason for a violation path corresponding to each field programmable gate array prototype version where timing cannot converge includes:
s107, obtaining congestion, high fan-out, wiring density and resource utilization rate data of each field programmable gate array prototype version to obtain a time sequence resource report;
S108, acquiring time sequence reports of each field programmable gate array prototype version, and deriving corresponding time sequence violation paths based on each time sequence report;
And S109, analyzing each time sequence violation path to determine the reason of the violation path.
In the implementation, in order to obtain the time sequence resource report and the reason of the violation path, the congestion, high fan-out, wiring density and resource utilization rate data of each FPGA prototype version are specifically obtained to obtain the time sequence resource report, the time sequence report of each FPGA prototype version is specifically obtained, the time sequence report is generated by a Vivado tool, and the corresponding time sequence violation path is derived based on each time sequence report. Finally, each timing violation path is analyzed to determine the violation path cause. Therefore, time sequence resource report and acquisition of reasons of the illegal paths are realized.
Based on the above embodiments, in some embodiments, mapping the timing resource report and the violation path cause into the corresponding netlist file to tag timing information of the corresponding field programmable gate array prototype version in the netlist file includes:
S111, mapping congestion, high fan-out, wiring density and resource utilization rate data of each field programmable gate array prototype version into a corresponding netlist file according to a slice level;
S112, labeling each time sequence violation path and a corresponding time division multiplexing module into a corresponding netlist file;
S113 copies the high fan-out register information on the high fan-out based timing violation path according to each violation path cause.
In order to map netlist files, in a specific implementation, congestion, high fan-out, routing density and resource utilization data of each FPGA prototype version are mapped into corresponding netlist files in a SLICE Level (SLICE). Note that SLICE (Slice Logic Cell) is a basic logic unit in the FPGA, and is used to implement the combinational logic and the sequential logic. The SLICE level refers to the level of logic resources inside the FPGA chip, i.e., the SLICE level. The resources at this level are the smallest configurable logic block in the FPGA, typically consisting of a look-up table (LUT), flip-Flop (Flip-Flop), multiplexer (MUX) and some other logic gates. In FPGA design, chip-level design refers to the process of designing and optimizing directly on the logic resources inside the FPGA chip.
Further, extracting each time sequence violation path and a corresponding time division multiplexing module thereof, and labeling the time sequence violation paths and the corresponding time division multiplexing modules into corresponding netlist files. Finally, according to the reasons of each violation path, the register information of high fan-out on the timing violation path based on high fan-out is copied. Therefore, mapping of the sequential resource report and the violation path reasons to the netlist file is realized.
Based on the above embodiments, in some embodiments, determining a newly added time division multiplexing path according to the netlist file, and pre-laying out the newly added time division multiplexing path includes:
S121, judging whether the resource utilization rate of a time division multiplexing position adjacent to a time sequence violation path is lower than a third threshold according to each netlist file and register information, if not, entering a step S122, and if so, entering a step S123;
s122, taking the next position adjacent to the time division multiplexing position as a new time division multiplexing position adjacent to the time sequence violation path, and returning to the step S121;
S123, determining a newly added time division multiplexing path according to the time division multiplexing position;
s124, instantiating a related module of the time division multiplexing according to the time division multiplexing position and the number thereof;
The related module at least comprises a clock module, a multiplexer, a demultiplexer, a receiving buffer, a transmitting buffer and a data encoding and decoding module;
s125, writing constraint sentences of the time division multiplexing module corresponding to the newly added time division multiplexing paths according to the time division multiplexing positions and the netlist file.
In order to determine and pre-layout the newly added time division multiplexing path, in a specific implementation, according to each netlist file and register information, whether the resource utilization rate of the time division multiplexing position adjacent to the time sequence violation path is lower than a third threshold value is judged. The third threshold is not limited in this embodiment, and may be set to 20% according to the specific implementation.
If the resource utilization of the time division multiplexing location adjacent to the time-sequence violating path is not lower than the third threshold, the time division multiplexing location adjacent to the time-sequence violating path is considered not to support the newly added time division multiplexing path, and the next location adjacent to the time division multiplexing location needs to be used as the new time division multiplexing location adjacent to the time-sequence violating path, and the process returns to step 121 to be judged again. And if the resource utilization rate of the time division multiplexing position adjacent to the time sequence violation path is lower than a third threshold, the time division multiplexing position adjacent to the time sequence violation path is considered to support a newly added time division multiplexing path, and the newly added time division multiplexing path is determined according to the time division multiplexing position.
The time division multiplexing related module is further exemplified according to the time division multiplexing position and the number thereof. The correlation module at least includes a clock module (all time division multiplexing transmission rates on the FPGA prototype version are the same, so the clock generation module may not need to be instantiated again, and the clock signal may be connected to the newly instantiated module), a multiplexer, a demultiplexer, a receiving buffer, a transmitting buffer, and a data codec module. And finally, writing constraint sentences of the time division multiplexing modules corresponding to the newly added time division multiplexing paths according to the time division multiplexing positions and the netlist file so as to facilitate the generation of the newly added time division multiplexing paths. It should be noted that the transmission rate of the newly added time division multiplexing path is consistent with the transmission rate of the original time division multiplexing path. Thus, the determination and pre-layout of the newly added time division multiplexing path are realized.
Based on the above embodiments, in some embodiments, generating each newly added time division multiplexing path based on each netlist file, and determining an interconnection relationship of each newly added time division multiplexing path in each netlist file includes:
s131, judging whether the timing violation of the timing violation path is caused by high fan-out, if so, entering a step S132, otherwise, entering a step S133;
S132, maintaining a time sequence violation path;
s133, disconnecting the timing violation path.
After the newly added time division multiplexing paths are obtained, each newly added time division multiplexing path is generated based on each netlist file. In a specific implementation, it is also required to consider whether the newly added time division multiplexing path overlaps with the original time division multiplexing path.
The method comprises the steps of judging whether the timing violations of the timing violating paths of the FPGA prototype version are caused by high fan-out or not, if the timing violations of the timing violating paths of the FPGA prototype version are confirmed to be caused by high fan-out, disconnecting the original timing violating paths, and if the timing violations of the timing violating paths of the FPGA prototype version are confirmed to be not caused by high fan-out, disconnecting the original timing violating paths, so that the normal operation of the newly added time division multiplexing paths is guaranteed.
Based on the above embodiments, in some embodiments, after performing physical area constraint on the time division multiplexing module corresponding to each newly added time division multiplexing path and generating the engineering file after the time sequence path adjustment, the method further includes:
S15, generating a bit stream file and performing platform adaptation operation to finish the manufacturing of a field programmable gate array prototype version;
s16, generating a log containing the information of the time sequence violation processing procedure.
In the implementation, after the physical area constraint is carried out on the time division multiplexing module corresponding to each newly added time division multiplexing path and the engineering file after the time sequence path adjustment is generated, the time sequence convergence is completed. In order to finally generate the FPGA prototype version, a bit stream file is specifically generated and platform adaptation operation is carried out, so that the manufacture of the FPGA prototype version is completed. Meanwhile, in order to enable the user to better know the current time sequence violation processing and adjusting process, a log containing the current time sequence violation processing process information is further generated, so that the user can analyze the whole process according to log content.
In addition, after the FPGA prototype version is manufactured, performance test can be further performed on the FPGA prototype. First, by analyzing the power consumption report of the FPGA prototype, it can be evaluated whether the designed power consumption meets the requirements. The power consumption analysis may help discover potential power consumption hot spots, such as high power consumption logic modules or interfaces, and unnecessary power consumption wastage. These problems may lead to heat dissipation problems or reduced battery life in the design in practice. Other aspects of performance testing may also be performed, such as signal integrity analysis, electromagnetic compatibility testing, and the like. These tests may help to find other problems that the design may experience in practical applications, such as reduced signal transmission quality or electromagnetic interference. Through performance test, the feasibility of design can be comprehensively evaluated, and subsequent optimization work is guided. If a power consumption hotspot is found, the logic design may be optimized or a low power implementation may be employed. The results of the performance test may also be used to guide subsequent ASIC design and verification work to improve the success rate and performance of the ASIC design.
In order to enable those skilled in the art to better understand the present solution, a timing adjustment method provided by the present solution is described below with reference to specific examples.
Fig. 4 is a schematic diagram of an FPGA prototype platform before and after timing adjustment according to an embodiment of the present invention. As shown in fig. 4, after timing adjustment, a logic circuit a of a large ASIC design in the field programmable gate array prototype version a is changed into two smaller logic circuits A1 and a logic circuit A2, and a part of logic is specifically duplicated and divided into two parts, and then a time division multiplexing path A6-C4 is newly added to transmit related signals to the field programmable gate array prototype version C. The method solves the problems of high fan-out and local area congestion, the two time division multiplexing positions of A6 and C4 are needed to be newly added to the field programmable gate array prototype version A and the field programmable gate array prototype version C respectively, the corresponding time division multiplexing modules are instantiated to the area, corresponding time sequence constraint sentences are added, and the newly added time division multiplexing modules are constrained to the area through Pblock constraint.
The signals transmitted via the time division multiplexed paths A6-C4 are further examined to disconnect the old one of the time division multiplexed paths A7, A8, C1. The connection of the logic circuit B to the logic circuit D in the field programmable gate array prototype version B is added with a time division multiplexing path B6-D2, and a part of signals originally passing through the time division multiplexing path B7-D1 are transferred to the time division multiplexing path B6-D2, so that the problem of congestion is mainly solved, the paths of the logic circuits B to B7 are far or the situation that time division multiplexing signals are more and cause time sequence violations is solved, and the processing mode needs to remove the paths transmitted on the time division multiplexing path B6-D2 from the time division multiplexing path B7-D1, and the time sequence constraint at two positions B6 and B7 is newly added or updated. The time division multiplexing paths C8-D7 are adjusted to be the time division multiplexing paths C7-D7 in the field programmable gate array prototype version C, and the time division multiplexing paths C8-D7 are relieved due to the fact that time sequence violations are generated when logic wires in the field programmable gate array prototype version C are distributed to the vicinity of the C8 in a relatively far mode, so that the interconnection relation of the time division multiplexing paths C7-D7 is completed.
In the above embodiments, the detailed description is given to the timing adjustment method, and the present invention further provides a corresponding embodiment of the timing adjustment device.
Fig. 5 is a schematic diagram of a timing adjustment device according to an embodiment of the present invention. As shown in fig. 5, the timing adjustment apparatus includes:
And the acquisition module 10 is used for acquiring a time sequence resource report, a violation path reason and a netlist file corresponding to each field programmable gate array prototype version with the non-convergence time sequence when the non-convergence time sequence exists, wherein the time sequence resource report at least comprises data of congestion, high fan-out, wiring density and resource utilization rate.
The mapping module 11 is configured to map the timing resource report and the reason of the violation path into a corresponding netlist file, so as to mark timing information corresponding to the prototype version of the field programmable gate array in the netlist file.
And the determining module 12 is used for determining a newly added time division multiplexing path according to the netlist file and pre-laying out the newly added time division multiplexing path.
And the generating module 13 is used for generating each newly added time division multiplexing path based on each netlist file and determining the interconnection relation of each newly added time division multiplexing path in each netlist file.
And the constraint module 14 is configured to constrain the physical area of the time division multiplexing module corresponding to each newly added time division multiplexing path, and generate an engineering file after the adjustment of the time sequence path, so as to complete the time sequence convergence.
In some embodiments, further comprising:
the configuration submodule is used for configuring prototype versions of all field programmable gate arrays;
the system comprises a first judging sub-module, a second judging sub-module, a third judging sub-module and a fourth judging sub-module, wherein the first judging sub-module is used for judging whether the configuration of all the field programmable gate array prototype versions is completed or not;
the second judging sub-module is used for judging whether the time sequence of the field programmable gate array prototype version cannot be converged or not, triggering the first generating sub-module if the time sequence of the field programmable gate array prototype version cannot be converged, and triggering the third judging sub-module if the time sequence of the field programmable gate array prototype version cannot be converged;
the first generation sub-module is used for generating a bit stream file and performing platform adaptation operation so as to finish the manufacture of a field programmable gate array prototype version;
The third judging sub-module is used for judging whether the resource occupancy rate of the field programmable gate array prototype version which cannot be converged by all time sequences is not more than a first threshold value, and the corresponding maximum setup time violation or the corresponding maximum hold time violation is not less than a second threshold value, and triggering the splitting sub-module if the resource occupancy rate of the field programmable gate array prototype version which cannot be converged by all time sequences is more than the first threshold value and/or the corresponding maximum setup time violation or the corresponding maximum hold time violation is not less than the second threshold value, and triggering the acquiring module 10 if the resource occupancy rate of the field programmable gate array prototype version which cannot be converged by all time sequences is not more than the first threshold value, and the corresponding maximum setup time violation or the corresponding maximum hold time violation is not less than the second threshold value;
And the segmentation submodule is used for reducing the system clock frequency or adjusting the resource allocation of each field programmable gate array prototype version and re-segmenting each field programmable gate array prototype version.
In some embodiments, the acquisition module 10 includes:
the first acquisition submodule is used for acquiring congestion, high fan-out, wiring density and resource utilization rate data of each field programmable gate array prototype version so as to obtain a time sequence resource report;
The second acquisition submodule is used for acquiring the time sequence reports of each field programmable gate array prototype version and deriving a corresponding time sequence violation path based on each time sequence report;
And the analysis submodule is used for analyzing each time sequence violation path to determine the reason of the violation path.
In some embodiments, the mapping module 11 comprises:
the first mapping submodule is used for mapping the congestion, high fan-out, wiring density and resource utilization rate data of each field programmable gate array prototype version into a corresponding netlist file according to a slice level;
The first labeling sub-module is used for labeling each time sequence violation path and the corresponding time division multiplexing module thereof into the corresponding netlist file;
and the first replication sub-module is used for replicating the high-fanout register information on the high-fanout time sequence violation path according to each violation path reason.
In some embodiments, the determination module 12 includes:
the fourth judging sub-module is used for judging whether the resource utilization rate of the time division multiplexing position adjacent to the time sequence violation path is lower than a third threshold according to the information of each netlist file and each register;
A selecting sub-module, configured to return the next position adjacent to the time division multiplexing position as a new time division multiplexing position adjacent to the time sequence violation path, to a step of determining whether the resource utilization rate of the time division multiplexing position adjacent to the time sequence violation path is lower than a third threshold according to each netlist file and register information;
A first determining submodule, configured to determine a newly added time division multiplexing path according to the time division multiplexing position;
The system comprises an instantiation sub-module, a correlation module and a data coding and decoding module, wherein the instantiation sub-module is used for instantiating a correlation module of time division multiplexing according to a time division multiplexing position and the number of the time division multiplexing position;
and the writing sub-module is used for writing constraint sentences of the time division multiplexing module corresponding to the newly added time division multiplexing paths according to the time division multiplexing positions and the netlist file.
In some embodiments, the generating module 13 includes:
The fifth judging sub-module is used for judging whether the timing violations of the timing violating paths are caused by high fan-out, if so, the timing violating paths are kept, and if not, the disconnection sub-module is triggered;
and the disconnection sub-module is used for disconnecting the time sequence violation path.
In some embodiments, further comprising:
the second generation submodule is used for generating a bit stream file and carrying out platform adaptation operation so as to finish the manufacture of a field programmable gate array prototype version;
and the third generation sub-module is used for generating a log containing the information of the time sequence violation processing process.
Since the embodiments of the apparatus portion and the embodiments of the method portion correspond to each other, the embodiments of the apparatus portion are referred to the description of the embodiments of the method portion, and are not repeated herein.
Furthermore, the present invention provides a computer program product comprising a computer program/instruction which, when executed by a processor, implements the steps of the above-described timing adjustment method.
Fig. 6 is a schematic diagram of a timing adjustment apparatus according to an embodiment of the present invention. As shown in fig. 6, the timing adjustment apparatus includes:
a memory 20 for storing a computer program;
a processor 21 for implementing the steps of the timing adjustment method as mentioned in the above embodiments when executing a computer program.
The timing adjustment device provided in this embodiment may include, but is not limited to, a smart phone, a tablet computer, a notebook computer, a desktop computer, or the like.
Processor 21 may include one or more processing cores, such as a 4-core processor, an 8-core processor, etc. The Processor 21 may be implemented in at least one hardware form of a digital signal Processor (DIGITAL SIGNAL Processor, DSP), field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA), programmable logic array (Programmable Logic Array, PLA). The processor 21 may also include a main processor for processing data in the awake state, also referred to as a central processor (Central Processing Unit, CPU), and a coprocessor for processing data in the standby state, which is a low-power processor. In some embodiments, the processor 21 may integrate a graphics processor (Graphics Processing Unit, GPU) for rendering and drawing of content required to be displayed by the display screen. In some embodiments, the processor 21 may also include an artificial intelligence (ARTIFICIAL INTELLIGENCE, AI) processor for processing computing operations related to machine learning.
Memory 20 may include one or more computer-readable storage media, which may be non-transitory. Memory 20 may also include high-speed random access memory, as well as non-volatile memory, such as one or more magnetic disk storage devices, flash memory storage devices. In this embodiment, the memory 20 is at least used for storing a computer program 201, which, when loaded and executed by the processor 21, is capable of implementing the relevant steps of the timing adjustment method disclosed in any of the foregoing embodiments. In addition, the resources stored in the memory 20 may further include an operating system 202, data 203, and the like, where the storage manner may be transient storage or permanent storage. Operating system 202 may include Windows, unix, linux, among other things. The data 203 may include, but is not limited to, data related to a timing adjustment method.
In some embodiments, the timing adjustment device may further include a display 22, an input/output interface 23, a communication interface 24, a power supply 25, and a communication bus 26.
Those skilled in the art will appreciate that the structure shown in fig. 6 does not constitute a limitation of the timing adjustment device and may include more or fewer components than shown.
Finally, the invention also provides a corresponding embodiment of the computer readable storage medium. The computer-readable storage medium has stored thereon a computer program which, when executed by a processor, performs the steps as described in the method embodiments above.
It will be appreciated that the methods of the above embodiments, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored on a computer readable storage medium. Based on this understanding, the technical solution of the present invention may be embodied essentially or in part or all of the technical solution or in part in the form of a software product stored in a storage medium for performing all or part of the steps of the method according to the embodiments of the present invention. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.
The method, the device, the equipment and the medium for adjusting the time sequence provided by the invention are described in detail. In the description, each embodiment is described in a progressive manner, and each embodiment is mainly described by the differences from other embodiments, so that the same similar parts among the embodiments are mutually referred. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section. It should be noted that it will be apparent to those skilled in the art that the present invention may be modified and practiced without departing from the spirit of the present invention.
It should also be noted that in this specification, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in a process, method, article, or apparatus that comprises an element.
Claims (10)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411161615.2A CN119067025A (en) | 2024-08-22 | 2024-08-22 | A timing adjustment method, device, equipment and medium |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202411161615.2A CN119067025A (en) | 2024-08-22 | 2024-08-22 | A timing adjustment method, device, equipment and medium |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN119067025A true CN119067025A (en) | 2024-12-03 |
Family
ID=93638974
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN202411161615.2A Pending CN119067025A (en) | 2024-08-22 | 2024-08-22 | A timing adjustment method, device, equipment and medium |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN119067025A (en) |
-
2024
- 2024-08-22 CN CN202411161615.2A patent/CN119067025A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US8839171B1 (en) | Method of global design closure at top level and driving of downstream implementation flow | |
| US5572436A (en) | Method and system for creating and validating low level description of electronic design | |
| US5557531A (en) | Method and system for creating and validating low level structural description of electronic design from higher level, behavior-oriented description, including estimating power dissipation of physical implementation | |
| NL192892C (en) | Computer-aided system for integrated circuit design. | |
| US7117143B2 (en) | Clock distribution in a circuit emulator | |
| US8205174B2 (en) | Integrated circuit modeling method and framework tool | |
| US5553002A (en) | Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, using milestone matrix incorporated into user-interface | |
| US5544066A (en) | Method and system for creating and validating low level description of electronic design from higher level, behavior-oriented description, including estimation and comparison of low-level design constraints | |
| US5933356A (en) | Method and system for creating and verifying structural logic model of electronic design from behavioral description, including generation of logic and timing models | |
| CN103678745B (en) | Cross-platform multi-level integrated design system for FPGA | |
| CN101539958B (en) | Method and device for designing standard cell library and integrated circuit | |
| CN110457849B (en) | A Configurable Digital Integrated Circuit Design Method | |
| JP2004531056A (en) | Block-based design methodology using programmable components | |
| KR20010085867A (en) | Block based design methodology | |
| US7305639B2 (en) | Method and apparatus for specifying multiple voltage domains and validating physical implementation and interconnections in a processor chip | |
| CN104239595B (en) | For realizing the method and apparatus for design planning and the system level design tool of framework exploration | |
| US8082530B1 (en) | Power estimation in high-level modeling systems | |
| Darringer et al. | Early analysis tools for system-on-a-chip design | |
| US20050268268A1 (en) | Methods and systems for structured ASIC electronic design automation | |
| EP1129483A1 (en) | Dram cell system and method for producing same | |
| US8751998B2 (en) | Method and system for partial reconfiguration simulation | |
| US20230101972A1 (en) | SYSTEM AND METHOD FOR AREA AND TIMING ASSESSMENT OF A NETWORK-ON-CHIP (NoC) IMPLEMENTATION | |
| US7979262B1 (en) | Method for verifying connectivity of electrical circuit components | |
| CN119067025A (en) | A timing adjustment method, device, equipment and medium | |
| CN119514465A (en) | Method and device for processing a layout |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PB01 | Publication | ||
| PB01 | Publication | ||
| SE01 | Entry into force of request for substantive examination | ||
| SE01 | Entry into force of request for substantive examination |