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CN119026565A - Chip diagnosis coverage rate calculation method and device - Google Patents

Chip diagnosis coverage rate calculation method and device Download PDF

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CN119026565A
CN119026565A CN202410989408.XA CN202410989408A CN119026565A CN 119026565 A CN119026565 A CN 119026565A CN 202410989408 A CN202410989408 A CN 202410989408A CN 119026565 A CN119026565 A CN 119026565A
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chip
diagnostic coverage
test
simulation
coverage rate
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CN119026565B (en
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雷黎丽
张峻卿
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Beijing National New Energy Vehicle Technology Innovation Center Co Ltd
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    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/39—Circuit design at the physical level
    • G06F30/398—Design verification or optimisation, e.g. using design rule check [DRC], layout versus schematics [LVS] or finite element methods [FEM]
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/30—Monitoring
    • G06F11/34—Recording or statistical evaluation of computer activity, e.g. of down time, of input/output operation ; Recording or statistical evaluation of user activity, e.g. usability assessment
    • G06F11/3457—Performance evaluation by simulation
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F30/00—Computer-aided design [CAD]
    • G06F30/30—Circuit design
    • G06F30/32—Circuit design at the digital level
    • G06F30/327—Logic synthesis; Behaviour synthesis, e.g. mapping logic, HDL to netlist, high-level language to RTL or netlist

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  • General Engineering & Computer Science (AREA)
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Abstract

The invention relates to the technical field of chip diagnosis coverage rate, and discloses a chip diagnosis coverage rate calculation method and device, wherein the method comprises the following steps: according to the design of a security mechanism of an RTL code stage, different types of faults are injected onto a designated chip module through an EDA tool, and the chip module is tested for diagnostic coverage rate; obtaining and classifying test results of diagnosis coverage rate of the chip module according to the injected faults of different types; and calculating the duty ratio of each classified test result in the overall test result, and judging the diagnosis coverage rate of the safety mechanism in the working state based on the ISO26262 standard. Multiple test conditions are designed aiming at characteristics with unreasonable and accurate simulation evaluation and diagnosis coverage rate, a plurality of calculation formulas of the diagnosis coverage rates are set according to the test conditions, fault injection simulation is adopted as simulation data, a more reasonable calculation model is adopted to bring the simulation data, and more accurate and reasonable simulation coverage rate is calculated.

Description

Chip diagnosis coverage rate calculation method and device
Technical Field
The invention relates to the technical field of chip diagnosis coverage rate, in particular to a chip diagnosis coverage rate calculation method and device.
Background
The content of safety of automotive semiconductor functions is proposed in part 11 of ISO 26262:2018 in 2018, which highlights the importance of safety of automotive semiconductor functions. The safety mechanism diagnosis coverage rate in the safety design of the vehicle-gauge chip function can provide a method and a guide for verifying the integrity and the correctness of the safety development of the vehicle-gauge chip function, and provide a basis and a reference of a chip application layer for a chip user.
The effective rate of the safety mechanism mainly refers to the diagnosis coverage rate of the safety mechanism, and the coverage rate describes the probability that the safety mechanism can be timely discovered and the system can make effective reaction when the real physical risk is discovered, namely, the fault is injected in the chip design simulation test. The diagnostic coverage rate (DC) is a core test index designed by a functional safety mechanism, a simulation test is usually adopted for a vehicle-mounted chip diagnostic coverage rate calculation method, the simulation test can only carry out simulation evaluation on single test excitation or single safety mechanism in the simulation test, and the tested module has only one fault injection simulation test case condition under the conventional condition, can directly calculate the diagnostic coverage rate through the simulation, namely:
However, in practical application, there are a plurality of security mechanisms and a plurality of simulation environments of the tested module, so the conventional DC calculation model cannot meet the DC calculation requirement any more, and the result calculated by the conventional DC calculation model is not reasonable and accurate enough.
Disclosure of Invention
The invention provides a chip diagnosis coverage rate calculation method and device for solving the problem that the result of the diagnosis coverage rate of a vehicle-mounted chip in the prior art is unreasonable and accurate.
The technical content of the invention is as follows:
the invention provides a chip diagnosis coverage rate calculation method, which comprises the following steps:
according to the design of a security mechanism of an RTL code stage, different types of faults are injected onto a designated chip module through an EDA tool, and the chip module is tested for diagnostic coverage rate;
Obtaining and classifying test results of diagnosis coverage rate of the chip module according to the injected faults of different types;
and calculating the duty ratio of each classified test result in the overall test result, and judging the diagnosis coverage rate of the safety mechanism in the working state based on the ISO26262 standard.
Further, the testing of the diagnostic coverage of the chip module when the different types of faults are injected onto the designated chip module by the EDA tool includes:
and simulating fault injection into simulation data, and carrying the simulation data into different fault models to realize the test of diagnosis coverage rate.
Further, injecting the different types of faults includes:
Different test excitation is designed aiming at different tested chip modules and fault models, and different test excitation outputs different test results.
Further, obtaining and classifying the test result of the chip module for diagnosing coverage rate according to the injected different types of faults, including:
the test results are classified as safe and risky based on whether the results of the fault injection change the standard functional output results.
Further, obtaining and classifying the test result of the chip module for diagnosing coverage rate according to the injected different types of faults, including:
Based on whether the results of fault injection can be classified as monitorable and non-monitorable by the security mechanism capture.
Further, the fault model is built based on the same or multiple simulation environments.
Further, the fault model is based on the diagnosis coverage rate when the same simulation environment is established, and comprises:
under a plurality of safety mechanisms, the calculation of the diagnosis coverage rate is calculated in a mode of insufficient combination, and the calculation is realized through a formula (1):
DCeff＝DC1°+DC2°*(1-DC1)+DC3°*(1-DC1°-DC2°*(1-DC1))°...(3);
under a plurality of safety mechanisms, the diagnostic coverage adopts an average value, and the calculation is realized through a formula (2):
under a plurality of safety mechanisms, the diagnosis coverage rate adopts a conservation result, and the calculation is realized through a formula (3):
DCeff＝DClowest (3)；
Wherein, DC 1、DC2、DC3 refers to the diagnostic coverage rate of different safety mechanisms for the tested module, DC eff is the diagnostic coverage rate, and DC lowest is the lowest diagnostic coverage rate of the safety mechanism.
Further, the fault model is based on diagnostic coverage at the time of construction of a plurality of simulation environments, and comprises:
in the case of a plurality of different diagnostic coverage, the average of the population is calculated by equation (4):
under the condition that different diagnosis coverage rates appear under a single safety mechanism, the method is calculated by a formula (5):
The invention also provides a chip diagnosis coverage rate calculating device, which at least comprises: the chip diagnosis coverage rate calculation method comprises the steps of injecting faults into the simulator through the fault injection script module, and comparing the injected fault simulation with normal simulation through the comparator to obtain simulation data.
The beneficial effects of the invention at least comprise: the method is characterized in that various test conditions are designed aiming at characteristics with unreasonable and accurate simulation evaluation and diagnosis coverage rate, a plurality of calculation formulas of the diagnosis coverage rates are set according to the test conditions, fault injection simulation is adopted as simulation data, a more reasonable calculation model is adopted to bring the simulation data, more accurate and more reasonable simulation coverage rate is calculated, the integrity and the correctness of the safety design of the calculation and evaluation function in the chip design stage are improved, and a benefit rate basis is provided for the follow-up chip function safety quantitative analysis.
Drawings
Fig. 1 is a schematic diagram of fault injection result classification of a chip diagnosis coverage rate calculation method according to the present invention.
Fig. 2 is a fault injection architecture of a chip diagnosis coverage rate calculating device provided by the invention.
FIG. 3 is a schematic diagram illustrating an operation architecture of a chip diagnosis coverage rate calculating apparatus according to the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
The invention provides a chip diagnosis coverage rate calculation method, which comprises the following steps:
in the chip design stage, in order to verify the correctness and effectiveness of the security mechanism, fault injection simulation is needed, namely, according to the security mechanism design in the RTL code stage, different types of faults are injected onto a designated chip module through an EDA tool, and the chip module is tested for diagnosis coverage rate;
Obtaining and classifying test results of diagnosis coverage rate of the chip module according to the injected faults of different types;
and calculating the duty ratio of each classified test result in the overall test result, and judging the diagnosis coverage rate of the safety mechanism in the working state based on the ISO26262 standard.
Further, the testing of the diagnostic coverage of the chip module when the different types of faults are injected onto the designated chip module by the EDA tool includes:
and simulating fault injection into simulation data, and carrying the simulation data into different fault models to realize the test of diagnosis coverage rate.
Further, injecting the different types of faults includes:
different test excitation is designed for different tested chip modules and fault models, different test excitation outputs different test results, and the fault models (constant 0/1 clamping stagnation overturning).
As shown in fig. 1, the fault injection results are classified into 4 categories, which are classified by:
obtaining and classifying test results of the chip module for diagnosing coverage rate according to different types of injected faults, wherein the test results comprise:
the test results are classified as safe and risky based on whether the results of the fault injection change the standard functional output results.
Obtaining and classifying test results of the chip module for diagnosing coverage rate according to different types of injected faults, wherein the test results comprise:
Based on whether the results of fault injection can be classified as monitorable and non-monitorable by the security mechanism capture.
In practical application, a tested module commonly exists and has a plurality of safety mechanisms and a plurality of simulation environments, so the invention is matched with a plurality of fault injection simulation test excitation aiming at the problem, the DC calculation requirement can not be further met through a conventional DC calculation model, and in the case, the invention provides 5 DC calculation models which are applicable to the condition that the tested module has a plurality of fault injection simulation test excitation and have a plurality of fault injection simulation results.
Further, the fault model is built based on the same or multiple simulation environments.
Further, the fault model is based on the diagnosis coverage rate when the same simulation environment is established, and comprises:
under a plurality of safety mechanisms, the calculation of the diagnosis coverage rate is calculated in a mode of insufficient combination, and the calculation is realized through a formula (1):
DCeff＝DC1°+DC2°*(1-DC1)+DC3°*(1-DC1°-DC2°*(1-DC1))°...(3);
under a plurality of safety mechanisms, the diagnostic coverage adopts an average value, and the calculation is realized through a formula (2):
under a plurality of safety mechanisms, the diagnosis coverage rate adopts a conservation result, and the calculation is realized through a formula (3):
DCeff＝DClowest (3)；
Wherein, DC 1、DC2、DC3 refers to the diagnostic coverage rate of different safety mechanisms for the tested module, DC eff is the diagnostic coverage rate, and DC lowest is the lowest diagnostic coverage rate of the safety mechanism.
Further, the fault model is based on diagnostic coverage at the time of construction of a plurality of simulation environments, and comprises:
in the case of a plurality of different diagnostic coverage, the average of the population is calculated by equation (4):
under the condition that different diagnosis coverage rates appear under a single safety mechanism, the method is calculated by a formula (5):
According to fig. 2, the invention further provides a chip diagnosis coverage rate calculating device, which at least comprises: the chip diagnosis coverage rate calculation method comprises the steps of injecting faults into the simulator through the fault injection script module, and comparing the injected fault simulation with normal simulation through the comparator to obtain simulation data.
Linux system: as a basic operating system for the test environment, platforms and tools are provided that are required to run the test system. The compiler is responsible for converting the source code into executable code. The emulator then emulates a software operating environment, allowing the developer to test the code without actually running the software. Fault injection scripts are used to inject specific faults into the simulator to simulate the behavior of software in case of anomalies. The test limit injection compiler adds specific limits in the compiling process to test the performance of the software under the condition of limited resources. The actual running result and the expected result can be compared by the comparator, so that the stability and the reliability of the software are verified. This process not only helps to find potential problems, but also optimizes software performance, ensuring that it will function properly under a variety of conditions.
The structure shown in fig. 2 further includes: test vector: refers to an input data set for testing software, and the data can be data required by normal operation or special data for triggering potential defects of the software;
Simulation results: and the simulator runs the output result obtained after simulation according to the test vector.
And starting from the compiler, performing simulation through the simulator and fault injection, and finally outputting a test result by the comparator. The whole process embodies the complete period from code compiling to result verification in software testing, ensures that software can normally run under various conditions, and timely discovers and repairs potential problems.
According to the invention, as shown in fig. 3, the PC end is connected with the tested target board through the CAN communication equipment, the tested chip is arranged on the tested target board, the PC end also controls the power supply and the oscilloscope on the tested target board, and the PC end exchanges signals with the tested target board through the oscilloscope.
The invention provides a board-level vehicle-gauge-level control chip function safety test, a diagnosis coverage rate calculation method based on fault injection simulation results, designs more calculation models, considers more safety mechanisms and complex conditions of multiple test excitation compared with the traditional calculation method, provides a new scheme for evaluating the integrity and correctness of chip function safety development, and provides a more accurate and reasonable method for evaluating whether the chip function safety development meets application requirements for chip users.
The foregoing description is only illustrative of the present invention and is not intended to limit the scope of the invention, and all equivalent structures or equivalent processes or direct or indirect application in other related technical fields are included in the scope of the present invention.

Claims (9)

1.一种芯片诊断覆盖率计算方法，其特征在于：包括以下步骤：1. A chip diagnostic coverage calculation method, characterized in that it includes the following steps: 根据RTL代码阶段的安全机制设计，通过EDA工具将不同类型的故障注入到指定的芯片模块上，对芯片模块进行诊断覆盖率的测试；According to the safety mechanism design at the RTL code stage, different types of faults are injected into the specified chip modules through EDA tools to test the diagnostic coverage of the chip modules; 获取并归类所述芯片模块根据注入的不同类型故障所进行诊断覆盖率的测试结果；Acquire and classify test results of diagnostic coverage of the chip module according to different types of faults injected; 计算被归类的测试结果各自在总体测试结果中的占比，并基于ISO26262标准评判所述安全机制在工作状态下的诊断覆盖率。The proportion of each classified test result in the overall test result is calculated, and the diagnostic coverage of the safety mechanism in the working state is judged based on the ISO26262 standard. 2.根据权利要求1所述的芯片诊断覆盖率计算方法，其特征在于：所述通过EDA工具将不同类型的故障注入到指定的芯片模块上时，对芯片模块进行诊断覆盖率的测试，包括：2. The chip diagnostic coverage calculation method according to claim 1, characterized in that: when different types of faults are injected into a specified chip module through an EDA tool, the diagnostic coverage test of the chip module comprises: 对故障注入仿真为仿真数据，将所述仿真数据带入至不同的故障模型上实现诊断覆盖率的测试。The fault injection simulation is simulation data, and the simulation data is introduced into different fault models to implement the test of diagnostic coverage. 3.根据权利要求2所述的芯片诊断覆盖率计算方法，其特征在于：注入所述不同类型的故障包括：3. The chip diagnosis coverage calculation method according to claim 2, characterized in that: injecting the different types of faults comprises: 针对不同的被测芯片模块及故障模型设计不同的测试激励，不同的测试激励输出不同的测试结果。Different test stimuli are designed for different chip modules and fault models under test, and different test stimuli output different test results. 4.根据权利要求1所述的芯片诊断覆盖率计算方法，其特征在于：获取并归类所述芯片模块根据注入的不同类型故障进行诊断覆盖率的测试结果，包括：4. The chip diagnostic coverage calculation method according to claim 1, characterized in that: obtaining and classifying the test results of the diagnostic coverage of the chip module according to different types of faults injected, comprises: 基于故障注入的结果是否改变了标准的功能输出结果将测试结果分为安全及有风险。The test results are classified as safe or risky based on whether the results of the fault injection change the standard functional output results. 5.根据权利要求1所述的芯片诊断覆盖率计算方法，其特征在于：获取并归类所述芯片模块根据注入的不同类型故障进行诊断覆盖率的测试结果，包括：5. The chip diagnostic coverage calculation method according to claim 1, characterized in that: obtaining and classifying the test results of the diagnostic coverage of the chip module according to different types of faults injected, comprises: 基于故障注入的结果是否能够被所述安全机制捕捉分为可监控及不可监控。Based on whether the result of fault injection can be captured by the safety mechanism, it is divided into monitorable and unmonitorable. 6.根据权利要求3所述的芯片诊断覆盖率计算方法，其特征在于：所述故障模型基于同一或多个仿真环境建立。6 . The chip diagnosis coverage calculation method according to claim 3 , wherein the fault model is established based on the same or multiple simulation environments. 7.根据权利要求6所述的芯片诊断覆盖率计算方法，其特征在于：所述故障模型基于同一仿真环境建立时的诊断覆盖率，包括：7. The chip diagnostic coverage calculation method according to claim 6, characterized in that: the diagnostic coverage of the fault model when established based on the same simulation environment includes: 在多个安全机制下，诊断覆盖率的计算采用合并不足的方式进行计算，通过式(1)实现计算：Under multiple safety mechanisms, the calculation of diagnostic coverage is performed by combining insufficient calculations, and the calculation is implemented through formula (1): DCeff＝DC1°+DC2°*(1-DC1)+DC3°*(1-DC1°-DC2°*(1-DC1))°…(3)；DC eff ＝DC 1 °+DC 2 °*(1-DC 1 )+DC 3 °*(1-DC 1 °-DC 2 °*(1-DC 1 ))°…(3); 在多个安全机制下，诊断覆盖率采取平均值，通过式(2)实现计算：Under multiple safety mechanisms, the diagnostic coverage rate takes the average value and is calculated using formula (2): 在多个安全机制下，诊断覆盖率采用保守结果，通过式(3)实现计算：Under multiple safety mechanisms, the diagnostic coverage adopts conservative results and is calculated by formula (3): DCeff＝DClowest (3)；DC eff = DC lowest (3); 其中，DC1、DC2、DC3是指不同安全机制对于被测模块的诊断覆盖率，DCeff为诊断覆盖率，DClowest为最低的安全机制诊断覆盖率。Among them, DC 1 , DC 2 , and DC 3 refer to the diagnostic coverage of different safety mechanisms for the module under test, DC eff is the diagnostic coverage, and DC lowest is the lowest diagnostic coverage of the safety mechanism. 8.根据权利要求6所述的芯片诊断覆盖率计算方法，其特征在于：所述故障模型基于多个仿真环境建立时的诊断覆盖率，包括：8. The chip diagnostic coverage calculation method according to claim 6, characterized in that: the diagnostic coverage when the fault model is established based on multiple simulation environments includes: 多个不同的诊断覆盖率的情况下，通过式(4)计算总体的平均值：In the case of multiple different diagnostic coverages, the overall average is calculated by formula (4): 单个安全机制下出现不同的诊断覆盖率的情况下，通过式(5)计算得到：When different diagnostic coverage rates occur under a single safety mechanism, the following is calculated using formula (5): 9.一种芯片诊断覆盖率计算装置，根据权利要求1-8任一项所述的芯片诊断覆盖率计算方法，其特征在于：至少包括：编译器、仿真器、故障注入脚本模块及比较器，仿真器分别与编译器、故障注入脚本模块及比较器相连，所述芯片诊断覆盖率计算方法通过故障注入脚本模块将故障注入至仿真器，并通过比较器比较注入的故障仿真与正常仿真获取仿真数据。9. A chip diagnostic coverage calculation device, according to the chip diagnostic coverage calculation method according to any one of claims 1-8, characterized in that it at least includes: a compiler, a simulator, a fault injection script module and a comparator, the simulator is respectively connected to the compiler, the fault injection script module and the comparator, the chip diagnostic coverage calculation method injects the fault into the simulator through the fault injection script module, and compares the injected fault simulation with the normal simulation through the comparator to obtain simulation data.
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