Detailed Description
The following description of the embodiments of the present application will be made in detail and with reference to the accompanying drawings, wherein it is apparent that the embodiments described are only some, but not all embodiments of the present application. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to fall within the scope of the application. The various embodiments described below and their technical features can be combined with each other without conflict.
Furthermore, the terms "first," "second," and the like, are used for descriptive purposes only and are not to be construed as indicating or implying a relative importance or implicitly indicating the number of technical features indicated. Thus, a feature defining "a first" or "a second" may explicitly or implicitly include at least one such feature. In the description of the present application, the meaning of "plurality" means at least two, for example, two, three, etc., unless specifically defined otherwise. In the description of the present application, the meaning of "several" means at least one, such as one, two, etc., unless specifically defined otherwise.
Unless defined otherwise, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the application. The term "and/or" as used herein includes any and all combinations of one or more of the associated listed items. The terms "connected," "electrically connected," and "electrically connected" as used herein include any direct and indirect electrical or structural connection. Accordingly, if a first device couples/connects/electrically connects to a second device, that connection may be through a direct electrical/structural connection, or through an indirect electrical/structural connection via other devices or connections.
The application provides a preparation method of a piezoelectric resonator, which comprises the following steps:
A silicon substrate is provided.
A portion of the silicon substrate is removed to form a recess.
Bonding a silicon-on-insulator (SOI) substrate and one surface of the silicon substrate, which is provided with the groove, so as to form a cavity, wherein the silicon-on-insulator substrate comprises a first insulating layer, a silicon layer and a second insulating layer which are arranged in a laminated mode, the silicon-on-insulator substrate is provided with an anchor point area and a main body area, the cavity and the main body area are arranged opposite to each other, and the acoustic impedances of the first insulating layer and the second insulating layer are different from those of the silicon layer.
A drive function layer is formed on a silicon-on-insulator substrate.
And selectively removing the silicon-on-insulator substrate to form a resonance main body in the main body region, and forming an anchor for fixing the resonance main body by matching the silicon substrate in the anchor point region.
According to the application, by using a stacking mode of at least two materials with larger acoustic impedance difference in the anchor point area, the acoustic wave is blocked to be difficult to pass through, the excessive flow of the acoustic wave into the anchor point is restrained, the anchor point loss is effectively reduced, and the Q value of the resonator is greatly improved.
In addition, after the groove is formed by etching the silicon substrate, bonding is performed on the silicon substrate on the insulator and the surface of the silicon substrate provided with the groove so as to form a cavity; then, the silicon substrate on the insulator is etched to expose the cavity, so that the resonant main body can be released without being released through a sacrificial layer, the corrosion influence of the corrosive liquid on the piezoelectric resonator is avoided, and the performance of the piezoelectric resonator is further improved.
Referring to fig. 1 to 6, fig. 1 is a schematic flow chart of a method for manufacturing a piezoelectric resonator according to the present application; fig. 2 to fig. 6 are schematic structural flow diagrams of a first method for manufacturing a piezoelectric resonator according to the present application. The application provides a preparation method of a piezoelectric resonator, which comprises the following steps:
S11, a silicon substrate 100 and an SOI base 200 are provided.
In some embodiments, the material forming the silicon substrate 100 is silicon. Of course, the material of the silicon substrate 300 may be other semiconductor materials, such as SiC.
In some embodiments, referring to fig. 2, the soi substrate 200 has a multi-layered structure including a first insulating layer 210, a silicon layer 220, and a second insulating layer 230, which are sequentially stacked. Of course, not limited thereto, in other embodiments, the SOI substrate 200 may not include the first insulating layer 210.
In some embodiments, the silicon layer 220 is formed of silicon (e.g., single crystal silicon) or other semiconductor material. The first insulating layer 210 and the second insulating layer 230 may be formed of the same material or different materials; for example, the first insulating layer 210 and the second insulating layer 230 may be formed of silicon oxide, silicon nitride, silicon oxynitride, or the like.
In the present embodiment, the SOI substrate 200 has an anchor region 200B and a body region 200A. The anchor region 200B is disposed in association with the body region 200A. Wherein, the anchor 10B in the piezoelectric resonator 10 is formed in the anchor region 200B, and the resonating body 10A is formed in the body region 200A. The resonating body 10A is for vibration, and the anchor 10B is connected to the resonating body 10A and is for fixing the resonating body 10A. It will be appreciated that the number of anchor points 200B may be set to be plural, provided that the number of anchors 10B is plural and spaced apart; likewise, the number of the resonance bodies 10A is set to be plural and spaced apart, and for this purpose, the number of the body regions 200A may be set to be plural.
In this embodiment, the acoustic impedance of the second insulating layer 230 is different from the acoustic impedance of the silicon layer 220. In this case, when the piezoelectric resonator 10 is operated, the generated acoustic wave is transmitted to the contact interface of the second insulating layer 230 and the silicon layer 220, and the acoustic wave is easily reflected due to the difference in acoustic impedance therebetween, thereby blocking the acoustic wave from passing therethrough. It can be understood that the anchor 10B formed in the anchor point region 200B may have a multilayer structure such as a silicon layer 220 and a second insulating layer 230, and the acoustic impedances of the adjacent layers are different, so that the acoustic waves can be blocked to make it difficult to pass through the contact interface, and the acoustic waves are prevented from excessively flowing into the anchor 10B, so that the anchor point loss is effectively reduced, and the Q value of the resonator is greatly improved.
Preferably, the second insulating layer 230 has a larger difference in acoustic impedance from the silicon layer 220, so that sound waves can be better blocked. For this reason, the formation material of the second insulating layer 230 is not limited too much. For example, the second insulating layer 230 is made of an insulating material, and the insulating material and the silicon layer 220 are formed of different acoustic impedances or larger acoustic impedances, which can meet the current semiconductor process.
Alternatively, the acoustic impedance of the first insulating layer 210 is different from that of the silicon layer 220 or the silicon substrate 100. Thus, if the acoustic wave is transmitted to the contact interface of the first insulating layer 210 and the first silicon layer 120 or the silicon substrate 100, the acoustic wave is also easily reflected, thereby blocking the acoustic wave from passing through, and suppressing the acoustic wave from excessively flowing into the anchor 10B.
Optionally, the thickness of the first insulating layer 210 and the thickness of the second insulating layer 230 are both smaller than the thickness of the silicon layer 220.
S12, patterning the silicon substrate 100.
In this step, referring to fig. 2, one surface of the silicon substrate 100 is subjected to patterning treatment to form a groove in the silicon substrate 100.
The patterning of the silicon substrate 100 includes: the silicon substrate 100 is subjected to, for example, an etching process, and a portion of the silicon substrate 100 is removed to form the recess 110.
S13, bonding the silicon substrate 100 to the SOI substrate 200.
In this step, referring to fig. 3, bonding the silicon substrate 100 with the SOI substrate 200 specifically includes: the SOI substrate 200 is bonded to the side of the silicon substrate 100 where the recess 110 is provided, and the SOI substrate 200 is capped at the opening of the recess 110 to form the cavity 300. In this case, the SOI substrate 200 may enclose the recess 110 to form the cavity 300, thereby reducing adverse effects of the outside on the inside of the cavity 300.
Alternatively, a region of the SOI substrate 200 disposed directly opposite the recess 110 is provided as the body region 200A. Thereby enabling the cavity 300 to be easily released directly from the resonating body 10A in a subsequent process, which will be described in detail later. Of course, not limited thereto, a partial region may be selected as the body region 200A in a region of the SOI substrate 200 disposed opposite to the recess 110.
Alternatively, the side of the SOI substrate 200 close to the silicon substrate 100 (i.e., the side of the first insulating layer 210 facing the silicon substrate 100) is a flat side, i.e., the side of the silicon substrate 300 close to the SOI substrate 100 has no pattern, i.e., is not subjected to patterning treatment. In this case, since there is no pattern on the silicon substrate 300 at the time of bonding, an additional overlay alignment step is not added, and an alignment error in the process can be effectively controlled. Of course, the present application is not limited thereto, and the first insulating layer 210 located in the body region 200A may be removed first, and then the SOI substrate 200 and the silicon substrate 100 may be aligned and bonded. In this case, it is possible to reduce the adverse effect of the first insulating layer 210 on the vibration mode of the subsequently formed resonance body 10A due to the young's modulus different from that of the silicon layer 220; and the first insulating layer 210 is reserved in the anchoring piece 10B, so that sound waves can be blocked, and anchor point loss is effectively reduced.
In some embodiments, the second insulating layer 220 located in the body region 200A may be removed, in which case the adverse effect of the second insulating layer 220 on the vibrational mode of the subsequently formed resonating body 10A due to the different young's modulus than the silicon layer 220 can be reduced. It is of course also possible to leave the second insulating layer 220 in the body region 200A, and after the subsequent formation of the resonance body 10A, the second insulating layer 220 can serve as a TCF (temperature coefficient of frequency) adjusting layer for improving the TCF of the piezoelectric resonator 10, thereby reducing the influence of temperature on the resonance frequency of the piezoelectric resonator 10.
S14, the driving function layer 400 is formed on the SOI silicon substrate 200.
In this step S14, the driving function layer 400 is used to drive the resonance body 10A to vibrate after receiving the driving signal. The driving function layer 400 is disposed on a side of the SOI silicon substrate 200 remote from the silicon substrate 100. Referring to fig. 4, the driving function layer 400 may include a bottom electrode 410, a piezoelectric layer 420, and a top electrode 430, which are stacked.
In some embodiments, the driving function layer 400 is formed by depositing a first metal layer, a piezoelectric material layer, a second metal layer, and the like on the second insulating layer 230, and performing a corresponding patterning process.
Specifically, a layer of metal material is deposited on the second insulating layer 230 to form a first metal layer, and a layer of piezoelectric material is deposited on the first metal layer to form a piezoelectric material layer; then, patterning the piezoelectric material layer by dry etching to form a piezoelectric layer 420; then, patterning the first metal layer by dry etching or wet etching to form a bottom electrode 410; then, a layer of metal material is deposited on the piezoelectric layer 420 to form a second metal layer, photoresist is deposited on the second metal layer, and patterning treatment is carried out on the photoresist; then, the second metal layer is patterned using the patterned photoresist as a mask to form a top electrode 430, and the formed bottom electrode 410, piezoelectric layer 420 and top electrode 430 constitute a driving function layer.
Although not limited thereto, the driving function layer may be formed by other process steps, for example, the first metal layer may be patterned to form the bottom electrode 410, then the piezoelectric material layer may be formed on the bottom electrode 410, and patterned to form the piezoelectric layer 420; then, a second metal layer is deposited on the piezoelectric layer 420, photoresist is deposited on the second metal layer, and patterning treatment is carried out on the photoresist; then, the second metal layer is patterned using the patterned photoresist as a mask to form the top electrode 430.
Optionally, the first metal layer and the second metal layer may be made of metal materials such as molybdenum, ruthenium, gold, aluminum, magnesium, tungsten, copper, titanium, iridium, osmium, chromium, and the like, and the piezoelectric material layer may be made of aluminum nitride, zinc oxide, PZT, and the like.
In one embodiment, after step S14, the method further includes:
in one embodiment, after step S14, the method further includes: a metal material is deposited on the driving function layer 400 to form a conductive connection pad. Thus, the bottom electrode 410 and the top electrode 430 in the driving functional layer 400 can be electrically connected to the outside through the conductive connection pad.
In this embodiment, the conductive connection pad includes at least a first connection pad and a second connection pad. The first connection pad is electrically connected to the bottom electrode 410 through the connection hole 421, and the second connection pad is electrically connected to the top electrode 430. The connection hole 421 may be formed during the patterning of the piezoelectric layer 420 and the top electrode 430 in step S14; of course, the driving function layer 400 may be formed by etching the piezoelectric layer 420 and/or the top electrode 430.
Specifically, the first connection pad is partially disposed on the piezoelectric layer 420 and partially disposed in the connection hole 421 to be electrically connected to the bottom electrode 410; the second connection pad is located on the top electrode 430 and is directly electrically connected to the top electrode 430. Of course, the positions of the first connection pad and the second connection pad are not limited to the above, and the bottom electrode 410 and the top electrode 430 can be electrically connected correspondingly; and the number of conductive connection pads can be increased according to the driving manner adopted by the driving function layer 400.
The first connecting pad and the second connecting pad are made of metal materials, and the metal materials can be gold, aluminum, magnesium or copper. Optionally, an isolation layer is disposed between the piezoelectric layer 420 and the first connection pad to reduce the influence of the first connection pad on the piezoelectric layer 420.
S15, etching the SOI substrate 200.
In this step, referring to fig. 5, the soi substrate 200 is etched as a device layer to form a resonating body 10A, and the resonating body 10A may include a resonator for vibration and a connection beam connected to the resonator. Specifically, the SOI substrate 200 (and the driving function layer 400 and the like over the SOI substrate 200) located in the body region 200A is etched to form a resonance body 10A; the SOI substrate 200 located in the anchor region 200B cooperates with the underlying silicon substrate 100 to form the anchor 10B. The connection beam in the resonating body 10A may be used to connect the anchor 10B and the resonator.
It is understood that the positions to be etched in this step S15 are different depending on the shape of the resonance body 10A. For example, the resonator body 10A shown in fig. 5 is in a cantilever structure, and the resonator and the connection beam in the resonator body 10A may be regarded as a single body, which is not clearly distinguished herein, and in step S15, the SOI substrate 200 on the side of the body region 200A away from the anchor region 200B is etched and penetrated to form a through hole communicating with the cavity 400 through the driving functional layer and the second silicon layer 140, etc., so as to form the resonator body 10A. The present application is not limited thereto, and the resonance body 10A having different structures may be formed by etching different positions of the body region 200A, and is not limited thereto, for example, a resonator in the resonance body 10A may be formed as a tuning fork, one or more squares, etc., and a connection beam in the resonance body 10A may be formed as a straight beam, a folded beam, an arc beam, etc.
In the present application, the first insulating layer 210 and the second insulating layer 230 are disposed on two sides of the silicon layer 220 to form the silicon-on-insulator substrate 200, where the first insulating layer 210 is close to one surface of the silicon substrate 100, so that in the process of etching or even penetrating (e.g. forming the through hole 500) the silicon-on-insulator substrate 200, the etching means are different from those of the silicon layer 220 and the silicon substrate 100, and the first insulating layer 210 can be used as a buffer barrier layer, so that the situation of over-etching in the etching process, such as affecting the underlying silicon substrate 100, is avoided, thereby ensuring the yield of the piezoelectric resonator 10 and further ensuring the performance of the piezoelectric resonator 10.
In an embodiment, referring to fig. 6, after step S15, the method further includes: an etching gas is introduced into the cavity 300 to remove a portion of the first insulating layer 210 located on the body region 200A or the resonance body 10A or to remove all of the first insulating layer 210 located on the body region 200A or the resonance body 10A. In this case, by removing the first insulating layer 210 on the resonator body 10A, the influence of the bad vibration or the like caused by the difference between the young's modulus of the first insulating layer 210 and the silicon layer 220 can be reduced, and the resonator body 10A can have a high Q value and a stable vibration mode. Alternatively, the etching gas may be HF, or other etching gases, without limitation. Of course, the first insulating layer 210 located in the body region 200A is retained, and the second insulating layer 230 can be used to adjust the frequency temperature coefficient (i.e., TCF) of the resonant body 10A, thereby reducing the influence of temperature on the resonant frequency of the resonant body 10A and improving the performance of the piezoelectric resonator 10.
In the present application, after the groove 110 is formed by etching the silicon substrate 100, the silicon substrate 200 on the insulator is bonded with the surface of the silicon substrate 100 where the groove 110 is provided to form the cavity 300, and the cavity 300 is disposed opposite to the main body region 200A; then, after the silicon substrate 200 on the insulator is etched to form the resonant main body 10A, the cavity 200 below the resonant main body 10A can directly enable the resonant main body 10A to be released without being released through a sacrificial layer, so that the corrosion influence of corrosive liquid on other film layers is avoided, in the process of releasing the resonant main body, the generated stress change is small, the risk of damage of other film layers due to overlarge stress change is reduced, the yield of the piezoelectric resonator 10 is further improved, and the performance of the piezoelectric resonator 10 is improved; in addition, the piezoelectric resonator 10 is prepared by adopting the preparation method provided by the application, the preparation process is simple, the operation is easy, and the preparation efficiency of the piezoelectric resonator 10 is further improved.
In the piezoelectric resonator 10 prepared by adopting the preparation method provided by the application, the first insulating layer 210, the silicon layer 220 and the second insulating layer 230 are stacked in the anchor point region, and the acoustic impedances of the first insulating layer 210 and the second insulating layer 230 are set to be different from those of the silicon layer 220, so that when the resonant main body vibrates under the action of sound waves, the sound waves are easily reflected when propagating to the contact interface of the insulating layer and the silicon layer 220 (such as the contact interface of the second insulating layer 230 and the silicon layer 220, the contact interface of the silicon layer 220 and the first insulating layer 210 and the like), and therefore the sound waves are difficult to pass through the insulating layer or the silicon layer 220 and excessively flow into the anchor point, anchor point loss is effectively reduced, the Q value of the piezoelectric resonator 10 is further improved, the impedance of the piezoelectric resonator 10 is reduced, and the performance of the piezoelectric resonator 10 is further improved.
Referring to fig. 7 and 8, fig. 7 and 8 are schematic flow diagrams illustrating a second structure of the method for manufacturing the piezoelectric resonator 10 according to the present application. It should be noted that the second structure is different from the first structure in that:
with continued reference to fig. 1-4. After step S14, further comprising:
an insulating protective layer 600 is provided on the driving function layer 400; then, the insulating protection layer 600 is subjected to an etching process, and the insulating protection layer 600 is selectively removed to form a plurality of electrical connection holes exposing the top electrode 430 or the bottom electrode 410, respectively. For example, referring to fig. 7, the plurality of electrical connection holes may include connection holes 421 and vias 610 disposed at intervals, the vias 610 penetrating through the insulating protection layer 600 to expose the top electrode 430, the connection holes 421 penetrating through the insulating protection layer 600, the piezoelectric layer 420, and the like to expose the bottom electrode 410. Conductive material is deposited in the electrical connection holes such as connection hole 421 and via hole 610 to form a conductive connection pad.
In the present embodiment, in step S15, it includes:
the driving function layer 400, the silicon-on-insulator substrate 200, and the insulating protection layer 600 located in the body region 200A are subjected to an etching process, such as etching the through-holes 500 penetrating the driving function layer 400, the silicon layer 220, and the insulating protection layer 600 and communicating with the cavity 300, thereby etching the resonant body 10A. Other steps are the same as those of the first preparation method, and are not repeated here.
In the present application, before the driving function layer 400 and the silicon-on-insulator substrate 200 are etched to form the through hole 500 for releasing the resonant body, an insulating protection layer 600 is disposed on the driving function layer 400, so as to avoid damage to the driving function layer 400 in the subsequent etching process, and to effectively inhibit the problems of oxidation of the top electrode 430, thereby ensuring the performance of the piezoelectric resonator 10.
The piezoelectric resonator 10 of the present application is formed as a semiconductor structure. The semiconductor structure includes a silicon-on-insulator base 200 and a silicon substrate 100 in a bonded arrangement. The silicon-on-insulator substrate 200 includes a first insulating layer 210, a silicon layer 220, and a second insulating layer 230, which are sequentially stacked. The acoustic impedances of the second insulating layer 230 and the first insulating layer 210 are different from those of the silicon layer 220. The silicon substrate 100 is arranged with a recess 110 on the side facing the silicon-on-insulator base 200. The silicon-on-insulator substrate 200 has an anchor region 200B and a body region 200A connected. The recess 110 is disposed opposite to the body region 200A, and the projection of the body region 200A on the silicon substrate 100 coincides with the contour of the recess 110, or the projection of the body region 200A on the silicon substrate 100 falls within the coverage of the recess 110. The recess 110 cooperates with the silicon-on-insulator substrate 200 to form a cavity 300. The second insulating layer 230 has a driving function layer 400 disposed thereon. The body region 200A of the silicon-on-insulator substrate 200 is etched to form a resonating body 10A in cooperation with the drive function layer 400, and the anchor region 200B of the silicon-on-insulator substrate 200 forms an anchor 10B in cooperation with the silicon substrate 100.
The foregoing description is only exemplary of the application and is not intended to limit the scope of the application, as long as the equivalent structure or equivalent flow changes made by the description of the application and the accompanying drawings, such as the combination of technical features between the embodiments, or the direct or indirect application in other related technical fields, are included in the scope of the present application.