CN119002826B - A memory and a control method thereof - Google Patents
A memory and a control method thereof Download PDFInfo
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- CN119002826B CN119002826B CN202411464230.3A CN202411464230A CN119002826B CN 119002826 B CN119002826 B CN 119002826B CN 202411464230 A CN202411464230 A CN 202411464230A CN 119002826 B CN119002826 B CN 119002826B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0628—Interfaces specially adapted for storage systems making use of a particular technique
- G06F3/0646—Horizontal data movement in storage systems, i.e. moving data in between storage devices or systems
- G06F3/0652—Erasing, e.g. deleting, data cleaning, moving of data to a wastebasket
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
- G06F12/023—Free address space management
- G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
- G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/0608—Saving storage space on storage systems
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/061—Improving I/O performance
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0602—Interfaces specially adapted for storage systems specifically adapted to achieve a particular effect
- G06F3/062—Securing storage systems
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F3/00—Input arrangements for transferring data to be processed into a form capable of being handled by the computer; Output arrangements for transferring data from processing unit to output unit, e.g. interface arrangements
- G06F3/06—Digital input from, or digital output to, record carriers, e.g. RAID, emulated record carriers or networked record carriers
- G06F3/0601—Interfaces specially adapted for storage systems
- G06F3/0668—Interfaces specially adapted for storage systems adopting a particular infrastructure
- G06F3/0671—In-line storage system
- G06F3/0673—Single storage device
- G06F3/0679—Non-volatile semiconductor memory device, e.g. flash memory, one time programmable memory [OTP]
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Abstract
本发明提供了一种存储器及其控制方法，存储器包括：闪存芯片，部分存储块被划分为系统块；纠错模块，电性连接于闪存芯片，在编辑二级地址映射表时，若二级地址映射表报错且纠错失败，纠错模块生成并发出报错数据；重建模块，电性连接于纠错模块，并接收报错数据，在纠错模块纠错失败后，重建模块生成融合二级表并用融合二级表替换系统块中的二级地址映射表；其中融合二级表包括系统块中的二级地址映射表、缓存模块中存储的二级地址映射表和系统块中最新被编辑的用户数据的地址映射信息。本发明提供了一种存储器及其控制方法，能够提升存储器的数据存储稳定性。
The present invention provides a memory and a control method thereof, wherein the memory comprises: a flash memory chip, wherein some storage blocks are divided into system blocks; an error correction module, which is electrically connected to the flash memory chip, and when editing a secondary address mapping table, if the secondary address mapping table reports an error and the error correction fails, the error correction module generates and sends error reporting data; a reconstruction module, which is electrically connected to the error correction module and receives the error reporting data, and after the error correction of the error correction module fails, the reconstruction module generates a fused secondary table and replaces the secondary address mapping table in the system block with the fused secondary table; wherein the fused secondary table includes the secondary address mapping table in the system block, the secondary address mapping table stored in the cache module, and the address mapping information of the latest edited user data in the system block. The present invention provides a memory and a control method thereof, which can improve the data storage stability of the memory.
Description
Technical Field
The invention relates to the technical field of storage, in particular to a memory and a control method thereof.
Background
The flash memory medium has the characteristic of power failure and is not easy to lose, so that the flash memory medium is widely applied to the field of storage. Since flash memory storage data depends on level flipping, the storage data in flash memory may also be lost. The ability to check and correct Errors (ECC) is therefore related to the performance of the storage stability of the memory.
Under the condition of error of read-write data, the error checking and correcting technology can timely find out the error of the data and correct the error data. However, when the power is abnormally lost or the power supply is unstable, the error correction data exceeds the error correction capability of the error checking and correcting technology, and the storage system can report errors. And read-write data that cannot be corrected is lost.
Disclosure of Invention
The invention aims to provide a memory and a control method thereof, which can improve the data storage stability of the memory.
In order to solve the technical problems, the invention is realized by the following technical scheme:
the present invention provides a memory comprising:
The flash memory chip comprises a plurality of storage blocks, wherein part of the storage blocks are divided into system blocks, and a primary address mapping table and a secondary address mapping table are stored in the system blocks;
the cache module is electrically connected with the flash memory chip and the upper computer and allows the primary address mapping table and the secondary address mapping table to be edited in the cache module;
The error correction module is electrically connected with the flash memory chip, and generates and sends error reporting data if the secondary address mapping table fails to report errors when the secondary address mapping table is edited, and
The reconstruction module is electrically connected with the error correction module, receives the error reporting data, generates a fused secondary table after the error correction of the error correction module fails, and replaces the secondary address mapping table in the system block by the fused secondary table;
The secondary address mapping table in the system block, the secondary address mapping table stored in the cache module and the address mapping information of the user data which is edited recently in the system block are included in the fusion secondary table.
In an embodiment of the present invention, the secondary address mapping table stores address mapping information of the user data, and the primary address mapping table stores address mapping information of the secondary address mapping table, where the address mapping information is a mapping relationship between a logical address and a physical address of the user data.
In an embodiment of the present invention, the rebuilding module includes a marking unit, when the secondary address mapping table fails to correct errors, the marking unit marks the secondary address mapping table that fails to correct errors as a to-be-rebuilt table, and records a serial number of the to-be-rebuilt table and a logical address of the to-be-rebuilt table.
In an embodiment of the present invention, the rebuilding module includes an old data query unit, and the old data query unit obtains old table information of the to-be-rebuilt table from the primary address mapping table according to the logical address of the to-be-rebuilt table, where the old table information includes address mapping information when the to-be-rebuilt table is edited last time.
In an embodiment of the present invention, the reconstruction module includes a scan unit, where the scan unit is electrically connected to the system block, and allows the scan unit to read the system block, and obtain, according to address mapping information stored in the system block, a physical address range of the flash memory chip related to the address mapping information, where the physical address range includes an initial address and a termination address, and allows the scan unit to scan the physical address range, and reconstruct, according to address mapping information in the physical address range, a secondary address mapping table as address mapping information of user data that is newly edited in the system block.
In an embodiment of the present invention, the reconstruction module includes a data filling unit, where the data filling unit stores single or multiple types of blank data, and when the secondary address mapping table fails to report errors and correct errors, the data filling unit is allowed to fill the blank data into the secondary address mapping table that fails to report errors and correct errors, where the blank data is preset data.
In an embodiment of the present invention, the rebuilding module includes a programming unit, when the secondary address mapping table fails to correct errors, the programming unit is allowed to transfer the secondary address mapping table filled with the blank data to the cache module, and the programming unit is allowed to transfer the system block with errors to a bad block pool, and the programming unit generates a task construction indication signal after completing a programming task.
In an embodiment of the present invention, the reconstruction module includes a task construction unit, where the task construction unit receives the task construction instruction signal and establishes a reconstruction task in a task queue of the memory, where a priority of the reconstruction task is lower than an instruction task of the upper computer.
In an embodiment of the present invention, an erasure count table, a reading count table, and a valid data count table are further stored in the system block, where the erasure count table stores erasure counts of a plurality of the storage blocks, the reading count table stores reading counts of a plurality of the storage blocks, and the valid data count table stores valid data counts of a plurality of the storage blocks.
The invention provides a memory control method based on the memory, which is characterized by comprising the following steps:
when user data is read and written, a secondary address mapping table is generated according to the address mapping information of the user data;
reading the secondary address mapping table with the same logical address from the flash memory chip into a cache module according to the logical address of the secondary address mapping table, and editing the secondary address mapping table and the primary address mapping table in the cache module;
When editing the secondary address mapping table, if the secondary address mapping table reports errors and the error correction fails, the error correction module generates and sends error reporting data, and
The reconstruction module receives the error-reported data, generates a fused secondary table according to the secondary address mapping table in the system block, the secondary address mapping table stored in the cache module and the address mapping information of the user data which is edited latest in the system block after the error correction of the error correction module fails, and
And the fused secondary table replaces the secondary address mapping table which reports errors and fails in error correction in the system block.
As described above, the present invention provides a memory and a control method thereof, which can recover address mapping information which cannot be corrected on the basis of completing a working instruction of an upper computer when address mapping information of user data in the memory cannot be corrected due to failure, thereby not only improving data storage stability of the memory, but also not affecting working performance of the memory itself. In addition, the memory and the control method thereof can completely recover the address mapping information of the user data, thereby avoiding the system block from being processed by a direct bad block and prolonging the service life of the memory.
Of course, it is not necessary for any one product to practice the invention to achieve all of the advantages set forth above at the same time.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed for the description of the embodiments will be briefly described below, and it is obvious that the drawings in the following description are only some embodiments of the present invention, and that other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
FIG. 1 is a schematic diagram of a memory according to an embodiment of the invention.
FIG. 2 is a flow chart of a method for controlling a memory according to an embodiment of the invention.
FIG. 3 is a schematic diagram illustrating a mapping relationship between a primary address mapping table and a secondary address mapping table according to an embodiment of the present invention.
In the figure, 10, a memory, 20, a main controller, 21, an error correction module, 22, a reconstruction module, 221, a data filling unit, 222, a programming unit, 223, a marking unit, 224, a task construction unit, 225, an old data query unit, 226, a scanning unit, 227, a fusion reconstruction unit, 30, a cache module, 40, a flash memory chip, 41, a storage block, 411, a storage page, 42, a system block, 50 and an upper computer.
Detailed Description
The following description of the embodiments of the present invention will be made clearly and completely with reference to the accompanying drawings, in which it is apparent that the embodiments described are only some embodiments of the present invention, but not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1 and 2, the present invention provides a memory 10. The memory 10 includes a main controller 20, a buffer module 30 and a flash memory chip 40, wherein the main controller 20 is electrically connected with the upper computer 50 through an interface to receive instructions and data of the upper computer 50 and feed back data of the main controller 20. In the present embodiment, the main controller 20 includes an error correction module 21 and a reconstruction module 22. In the present embodiment, the flash memory chip 40 is electrically connected to the error correction module 21 to correct the error of the data read from and written to the flash memory chip 40 during the read-write process of the flash memory chip 40. It should be noted that, the error correction module 21 may complete the error checking and correction of the flash memory chip 40 through a Low-density parity Code (LDPC). And the present invention is not limited to the error correction algorithm of the error correction module 21. In the present invention, when the error-corrected data exceeds the error correction capability of the error correction module 21, the error correction module 21 marks the data currently corrected as uncorrectable errors, generates error-reporting data, and then reports the error-reporting data to the main controller 20. It should be noted that the main controller 20 may be a microprocessor-based controller, such as a reduced instruction system computer (Reduced Instruction System Computer, RISC), and in particular an ARM processor. The reconstruction module 22 is electrically connected to the error correction module 21, and receives the error-reported data of the error correction module 21. In the present invention, the control method of the memory 10 provided by the present invention may be performed when uncorrectable errors in the error-prone data originate from the address mapping information. Specifically, the control method of the memory 10 provided by the present invention includes steps S100 to S500.
In step S100, when an uncorrectable secondary address mapping table appears in the memory 10, the uncorrectable secondary address mapping table is marked as a table to be reconstructed, and the table to be reconstructed is filled with blank data.
Step 200, obtaining a system block in which the table to be rebuilt is located, moving the system block into the bad block pool, and constructing a rebuilding task in a task queue of the main controller 20, wherein the rebuilding task is executed in an idle state of the memory 10.
And step 300, in the reconstruction task, according to the serial numbers of the tables to be reconstructed, retrieving the system block, and acquiring the secondary address mapping tables which are valid before the tables to be reconstructed appear and have the same serial numbers from the system block, and taking the secondary address mapping tables as a first table to be fused.
Step 400, if there is a behavior of updating the table information between the table to be reconstructed and the first table to be fused, scanning a storage block corresponding to the address mapping information according to the address mapping information stored in the system block, and establishing a secondary address mapping table of the user data as a second table to be fused.
And S500, acquiring a secondary address mapping table in the cache module as a third table to be fused.
And S600, fusing the first table to be fused, the second table to be fused and the third table to be fused to obtain a fused secondary table, and replacing the secondary address mapping table in the system block with the fused secondary table.
Referring to fig. 1 and 2, in one embodiment of the present invention, when an uncorrectable secondary address mapping table is present in the memory 10, step S100 is performed. The host write command is a data write command sent by the host 50, and is used for writing user data into the memory 10. After receiving the host write command, the memory 10 reads the secondary address mapping table from the flash memory chip 40 into the cache module 30 according to the logical address of the user data, and edits the secondary address mapping table in the cache module 30. In this process of reading the secondary address mapping table, if the error correction module 21 finds that the secondary address mapping table is in error and the error correction fails, the current secondary address mapping table is the secondary address mapping table that cannot be corrected, and step S100 is performed.
Referring to fig. 1 to 3, in an embodiment of the present invention, it should be noted that data written into the memory 10 has a logical address and a physical address, wherein the physical address is a storage location of the written data in the memory 10. And when the data is written, an address mapping relation is established between the logical address and the physical address of the written data, so that the physical address of the written data can be found according to the address mapping relation when the written data is called. Wherein the address mapping relation of the written data may be stored in a specific location of the memory 10 in the form of a linked list. In this embodiment, a linked list storing the address mapping relationship of the user data is set as the secondary address mapping table. Likewise, the secondary address mapping table also has a physical address and a logical address, wherein the logical address of the secondary address mapping table may also be embodied as a sequence number of the secondary address mapping table. In this embodiment, a mapping relationship is established between the physical address and the logical address of the secondary address mapping table, and the mapping relationship is expressed in a linked list form, so as to obtain the primary address mapping table. When reading data or writing data, the edited data may be data which has been written, so that it can be determined whether the secondary address mapping table is to be changed according to the logical address of the user data. Specifically, when the cache module 30 or the flash memory chip 40 has the secondary address mapping table with the same logical address as the user data to be edited, the relevant secondary address mapping table is read into the cache module 30, and the read secondary address mapping table is edited while the user data is written.
Referring to fig. 1 to 3, in an embodiment of the present invention, it should be noted that the flash memory chip 40 includes a plurality of memory blocks 41, where the memory blocks 41 may be physical blocks (blocks) of a NAND flash memory, and each memory block 41 has a unique device number. The memory block 41 includes a plurality of memory pages 411, and the memory pages 411 may be physical pages (pages) of the NAND flash memory. In the present embodiment, the partial memory block 41 may be divided into the system blocks 42 at the factory-opening stage of the memory 10. The system block 42 is used to store table information for the flash memory chip 40. In the present embodiment, a primary address map table, a secondary address map table, an erasure number record table, a read number record table, and a valid data number record table are stored in the system block 42. Wherein the erasure number of the plurality of memory blocks 41 is stored in the erasure number recording table, the reading number of the plurality of memory blocks 41 is stored in the reading number recording table, and the number of effective data of the plurality of memory blocks 41 is stored in the effective data number recording table.
Referring to fig. 1 to 3, in one embodiment of the present invention, it should be noted that the secondary address mapping table stored in the system block 42 includes a secondary address mapping table directly stored in the flash memory chip 40 and a secondary address mapping table that is flushed from the cache module 30 to the system block 42. In this embodiment, the cache module 30 may be set to be always on, and the secondary address mapping tables in the system block 42 are all transferred from the cache module 30. In other embodiments of the present invention, the buffer module 30 may be turned off, and the main controller 20 is directly electrically connected to the flash memory chip 40. After the secondary address mapping table is generated, it is stored directly into the system block 42. Specifically, in this embodiment, a flush cycle or a flush threshold is set, and when the time of storing data in the cache module 30 reaches the flush cycle or when the stored data in the cache module 30 reaches the flush threshold, the secondary address mapping table in the cache module 30 is transferred to the system block 42, so as to obtain better storage stability while considering the high performance of the memory 10.
Referring to fig. 1 to 3, in an embodiment of the present invention, in step S100, a secondary address mapping table that cannot be corrected is marked as a table to be reconstructed, and the table to be reconstructed is filled with blank data. Wherein the blank data is data of all 0 s or all 1 s. And then writing the address mapping information of the current written user data into a table to be rebuilt so as to avoid the loss of the address mapping information of the current user data. The table to be reconstructed of the written data is written back into the system block 42. It should be noted that, after the second-level address mapping table is edited and written back to the system block 42, the corresponding first-level address mapping table also adjusts the physical address. The original secondary address mapping table is changed into invalid data because the physical address of the original secondary address mapping table is the old physical address, and the old secondary address mapping table can be recycled in the garbage recycling process (garbage collection, gc). The present invention fills the secondary address mapping table with address mapping information before writing to the system block 42 to avoid affecting the execution of the host write command of the memory 10.
Referring to fig. 1 to 3, in an embodiment of the present invention, in step S200, a system block 42 corresponding to a table to be reconstructed is moved into a bad block pool. Specifically, the address information of the system block 42 is written into the bad block table, so that the system block 42 where the table to be reconstructed is located is prevented from being called when information is written later, and the stability of the storage system is improved. In step S200, the rebuild task may be built in the task queue of the main controller 20 while or before and after the system block 42 is moved into the bad block pool. Wherein the rebuild task is performed only in an idle state of the memory 10. It should be noted that, the idle state of the memory 10 means that the main controller 20 has executed the instruction of the upper computer 50, and has not received the instruction of the new upper computer 50 within a preset time.
Referring to fig. 1 to 3, in step S300, when the memory 10 enters an idle state, a rebuilding task is performed, i.e. steps S300 to S600. In step S300, a sequence number of a table to be reconstructed is acquired. The sequence number of the table to be rebuilt is obtained, which may be equal to the logical address of the table to be rebuilt. It should be noted that, the table to be reconstructed is copied from the system block 42 to the buffer module 30, so that the original data of the table to be reconstructed can be found in the system block 42. The corresponding system block 42 is retrieved according to the logical address of the table to be reconstructed. Specifically, from the corresponding system block 42, the primary address mapping table is retrieved according to the logical address of the table to be reconstructed, thereby obtaining the physical address of the table to be reconstructed. And acquiring the effective secondary address mapping table which is the same as the serial number of the table to be rebuilt from the corresponding physical address, and taking the found secondary address mapping table as a first table to be fused.
Referring to fig. 1 to 3, in an embodiment of the invention, if there is an update table information between the table to be reconstructed and the first table to be merged. Specifically, according to the logical address and the serial number, the physical addresses of the first table to be fused and the table to be rebuilt found in the system block 42 are inconsistent, and the current first table to be fused cannot actually represent the original data of the table to be rebuilt, but represents the data updated a certain time before the table to be rebuilt. That is, only the secondary address mapping table which is identical to the table sequence number to be reconstructed and is invalid is found in step S300, step S400 is performed. In step S400, the system block 42 stores therein address mapping information of the user data and address mapping information of the secondary address mapping table. The storage range of the user data in the flash memory chip 40 can be acquired based on the address mapping information of the user data. The storage range of the secondary address mapping table in the system block 42 can be acquired from the address mapping information of the secondary address mapping table. In this embodiment, the secondary address mapping table of the user data corresponding to the system block 42 is reconstructed by scanning the storage block 41 corresponding to the address mapping information of the user data. Specifically, the physical addresses of all secondary address mapping tables are found from the logical address ranges in the primary address mapping tables in the system block 42. And finding the physical addresses of the user data related in the all secondary address mapping tables from the physical addresses of the all secondary address mapping tables. The secondary address mapping table is reconstructed from the logical address and the actual physical address of the user address stored in the memory block 41, corresponding to the physical address of the user data involved in the search. In this embodiment, the reconstructed secondary address map is the entire secondary address map in the system block 42. It should be noted that, in the process of obtaining the second table to be fused, the primary valid secondary address mapping table in the system block 42 may be directly inherited to skip the reconstruction process.
Referring to fig. 1 to 3, in another embodiment of the present invention, if there is an update table information between the table to be reconstructed and the first table to be merged. Specifically, according to the logical address and the serial number of the table to be rebuilt, the physical addresses of the first table to be fused found in the system block 42 and the table to be rebuilt are inconsistent, and the current first table to be fused cannot actually represent the original data of the table to be rebuilt, but represents the data updated a certain time before the table to be rebuilt. That is, only the secondary address mapping table which is identical to the table sequence number to be reconstructed and is invalid is found in step S300, step S400 is performed. In step S400, the system block 42 stores address mapping information updated between the first table to be fused and the table to be reconstructed. For example, the logical address of the user data in the first to-be-fused table is LBA1, and the physical address of the user data is PBA1. With the update of the table information in between, the logical address of the user data is still LBA1, but in reality the physical address of the user data has been changed to PBA5. The correct information of the user data is stored in the table to be reconstructed which is not filled with blank data, and at this time the information of the table to be reconstructed has been lost. However, according to the logical address LBA1 of the user data found in the first table to be fused, the user data corresponding to the logical address LBA1 can be found by retrieving the storage block 41 referred to by the system block 42, and the actual physical PB5 of the user data is obtained. And reestablishing address mapping information of the user data as a second table to be fused. It should be noted that, although the specific physical address of the user data cannot be directly known, the physical address of the user data located in the previous sequence number of the table to be rebuilt and the physical address of the user data located in the next sequence number of the table to be rebuilt may be obtained according to the sequence number of the table to be rebuilt. The user data physical address of the former serial number of the table to be rebuilt is marked as a first physical address, and the user data physical address of the latter serial number of the table to be rebuilt is marked as a second physical address. According to the range from the first physical address to the second physical address, the corresponding memory block 41 is retrieved, and user data of a desired logical address can be quickly retrieved.
Referring to fig. 1 to 3, in step S500, a secondary address mapping table in the cache module 30 is obtained as a third table to be fused in an embodiment of the present invention. It should be noted that, instead of storing only one piece of address mapping information in the table to be rebuilt extracted to the buffer module 30, there may be stored address mapping information of a plurality of pieces of user data. Therefore, in the present embodiment, in step S600, the secondary address mapping table currently written in the cache module 30, the secondary address mapping table reconstructed by retrieving the partial memory blocks 41 in the flash memory chip 40, and the original data of the table to be reconstructed in the original system block 42 are fused, so as to reconstruct the secondary address mapping table in the system block 42. It should be noted that, during the period from the establishment of the reconstruction task to the execution of the reconstruction task, the table to be reconstructed is already written with new address mapping information, so that the secondary address mapping table in the cache module 30 is fused when the fusion is performed. In addition, it should be noted that, if the secondary address mapping table is flushed during the period from the establishment of the reconstruction task to the execution of the reconstruction task, the portion of the flushed secondary address mapping table may be found from the primary address mapping table as a portion of the third to-be-fused table. In step S600, in the present embodiment, all secondary address mapping tables in the original system block 42 are replaced with the merged secondary address mapping table. In another embodiment of the present invention, the table to be rebuilt is replaced with the fused secondary address mapping table.
Referring to fig. 1 to 3, in an embodiment of the present invention, the reconstruction module 22 includes a data filling unit 221, a programming unit 222, a marking unit 223, a task building unit 224, an old data query unit 225, a scanning unit 226, and a fusion reconstruction unit 227. When the secondary address mapping table is reported to be wrong and fails to correct the error, the marking unit 223 marks the secondary address mapping table reported to be wrong and fails to correct the error as a table to be rebuilt, and records the serial number of the table to be rebuilt and the logical address of the table to be rebuilt. The data filling unit 221 stores single or multiple types of blank data, and when the secondary address mapping table fails to report errors and correct errors, the data filling unit 221 fills the blank data into the secondary address mapping table that fails to report errors and correct errors, where the blank data is preset data, such as all 1 data or all 0 data. When the secondary address mapping table fails to report errors and correct errors, the programming unit 222 transfers the to-be-reconstructed table filled with blank data to the cache module 30, and the programming unit 222 transfers the erroneous system block 42 to the bad block pool, and the programming unit 222 generates a task construction indication signal after completing the programming task. The task construction unit 224 receives the task construction indication signal and establishes a reconstruction task in the task queue of the main controller 20, wherein the reconstruction task has a priority lower than the instruction task of the upper computer 50. In the present invention, the data filling unit 221 and the marking unit 223 are used to implement step S100. The task construction unit 224 and the programming unit 222 are used to implement step S200.
Referring to fig. 1 to 3, in an embodiment of the invention, according to a logical address of a table to be rebuilt, the old data query unit 225 obtains old table information of the table to be rebuilt from the primary address mapping table, wherein the old table information includes address mapping information of the table to be rebuilt when the table to be rebuilt was last edited. Specifically, the old data query unit 225 performs step S400 to query and obtain the first table to be fused. The old data query unit 225 is used to implement step S300. The scanning unit 226 reads the system block 42 and obtains a physical address range of the flash memory chip 40 related to the address mapping information according to the address mapping information stored in the system block 42, wherein the physical address range includes an initial address and a termination address. The scanning unit 226 scans the memory page 411 between the initial address and the termination address, and reconstructs a secondary address mapping table as a second table to be fused according to the address mapping information in the physical address range. The scanning unit 226 is configured to implement step S400. The fusion reconstruction unit 227 fuses the first table to be fused, the second table to be fused, and the third table to be fused as a fusion secondary table. The secondary address mapping table in system block 42 is replaced with the fused secondary table to complete the rebuilding task. The fusion reconstruction unit 227 is used to implement steps S500 to S600. Wherein, when the rebuilding task is completed, the programming unit 222 deletes the rebuilding task from the task queue of the main controller 20. When a plurality of reconstruction tasks exist at the same time, the reconstruction tasks are executed sequentially from the morning to the evening according to the time sequence of the reconstruction tasks. When the tables to be reconstructed of a portion of the reconstruction tasks come from the same system block 42, the corresponding reconstruction tasks may be performed simultaneously. When the reconstruction task of the system block 42 is completed, the programming unit 222 removes the system block 42 from the bad block pool.
The embodiments of the invention disclosed above are intended only to help illustrate the invention. The examples are not intended to be exhaustive or to limit the invention to the precise forms disclosed. Obviously, many modifications and variations are possible in light of the above teaching. The embodiments were chosen and described in order to best explain the principles of the invention and the practical application, to thereby enable others skilled in the art to best understand and utilize the invention. The invention is limited only by the claims and the full scope and equivalents thereof.
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| CN111831476A (en) * | 2019-04-23 | 2020-10-27 | 三星电子株式会社 | Method of controlling the operation of a RAID system |
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| KR20240118573A (en) * | 2023-01-27 | 2024-08-05 | 삼성전자주식회사 | Storage device |
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