CN119008564A - Fan-out type packaging structure and preparation method thereof - Google Patents
Fan-out type packaging structure and preparation method thereof Download PDFInfo
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- CN119008564A CN119008564A CN202411230838.XA CN202411230838A CN119008564A CN 119008564 A CN119008564 A CN 119008564A CN 202411230838 A CN202411230838 A CN 202411230838A CN 119008564 A CN119008564 A CN 119008564A
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Abstract
本发明提供了一种扇出型封装结构和扇出型封装结构的制备方法，涉及片封装技术领域，该扇出型封装结构包括封装芯片、引脚导电块、塑封体、重布线层和保护层，引脚导电块设置在封装芯片周围；塑封体包覆在封装芯片的周围，并至少包覆于引脚导电块靠近封装芯片的一侧的侧壁；重布线层设置在塑封体远离非功能面的一侧表面；保护层设置在重布线层远离封装芯片的一侧表面；其中，引脚导电块部分外露于塑封体，并用于与外部导电胶或导电焊料接触。相较于现有技术，本发明无需采用电镀焊球实现输出，因此可以避免电镀焊球使用过程中存在的分层甚至掉落现象，保证了电连接的性能。同时也避免了焊球焊接凸点工艺存在的桥接以及空洞现象。
The present invention provides a fan-out type packaging structure and a method for preparing the fan-out type packaging structure, and relates to the field of chip packaging technology. The fan-out type packaging structure includes a packaging chip, a pin conductive block, a plastic package, a redistribution layer and a protective layer. The pin conductive block is arranged around the packaging chip; the plastic package is coated around the packaging chip, and at least coated on the side wall of the pin conductive block close to the packaging chip; the redistribution layer is arranged on the side surface of the plastic package away from the non-functional surface; the protective layer is arranged on the side surface of the redistribution layer away from the packaging chip; wherein the pin conductive block is partially exposed to the plastic package and is used to contact with an external conductive glue or conductive solder. Compared with the prior art, the present invention does not need to use electroplated solder balls to achieve output, so the delamination or even falling phenomenon of the electroplated solder balls during use can be avoided, and the performance of the electrical connection is guaranteed. At the same time, the bridging and void phenomena existing in the solder ball welding bump process are also avoided.
Description
Technical Field
The invention relates to the technical field of chip packaging, in particular to a fan-out type packaging structure and a preparation method of the fan-out type packaging structure.
Background
With the rapid development of the semiconductor industry, fan-out type wafer level package (FOWLP) package structures are widely used in the semiconductor industry. In the fan-out technology, a tin ball is formed on a rewiring layer in an electroplating mode to serve as an output end, current density is generally controlled in an electroplating process to control electroplating uniformity/thickness, a multi-layer metal layer structure (electroplated copper/nickel tin silver) is electroplated to form the tin ball, and once the current density is unstable, the layering phenomenon of the electroplated multi-layer metal layer exists, and the tin ball is caused to fall off in welding, so that the electrical connection performance is affected. Meanwhile, the existing solder ball bump welding process has the phenomena of welding bridging and hollowness, and the electric connection performance is also affected.
Disclosure of Invention
The invention aims at providing a fan-out type packaging structure and a preparation method of the fan-out type packaging structure, which can avoid adopting an electrotinning ball process as an output end and adopting an embedded pin conducting block as the output end, and solve the problems caused by the traditional electrotinning ball process.
Embodiments of the invention may be implemented as follows:
in a first aspect, the present invention provides a fan-out package structure, comprising:
The packaging chip is provided with a functional surface and a non-functional surface at two sides;
the pin conducting blocks are arranged around the packaging chip;
The plastic package body is coated around the packaged chip and at least coated on the side wall of one side, close to the packaged chip, of the pin conducting block;
the rewiring layer is arranged on the surface of one side, far away from the non-functional surface, of the plastic package body, is in electrical contact with the functional surface, and is in electrical contact with the pin conducting block;
The protective layer is arranged on the surface of one side of the rewiring layer, which is far away from the packaged chip;
The pin conductive block part is exposed out of the plastic package body and is used for being contacted with external conductive adhesive or conductive solder.
In an alternative embodiment, a side surface of the pin conductive block, which is far away from the rewiring layer, is exposed to the plastic package body.
In an alternative embodiment, the non-functional surface is flush with a surface of the pin conductive block away from the rewiring layer, and the non-functional surface is exposed from the plastic package body.
In an alternative embodiment, the plastic package body wraps around the pin conductive block, and a surface of the pin conductive block, which is close to the rewiring layer, is exposed to the plastic package body.
In an alternative embodiment, the plastic package body is at least filled in an area between the package chip and the pin conductive block, and a side wall of the pin conductive block, which is far away from one side of the package chip, is exposed to the plastic package body.
In an alternative embodiment, the pin conductive block is further provided with a pin groove on the side wall exposed from the plastic package body.
In an alternative embodiment, the pin recess is located at a corner of the pin conductive block and extends to a side surface of the pin conductive block remote from the rewiring layer.
In an alternative embodiment, the number of the pin conductive blocks is multiple, and the plurality of the pin conductive blocks are surrounded to form multiple circles and are stacked around the packaged chip.
In an optional embodiment, the plastic package body is wrapped on a surface of one side of the packaged chip far away from the rewiring layer and a surface of one side of the pin conductive block far away from the rewiring layer, and a side wall of one side of the pin conductive block far away from the packaged chip is exposed out of the plastic package body.
In an alternative embodiment, the width of the plastic package body is greater than the width of the rewiring layer, and the edge of the surface of the pin conducting block, which is close to the rewiring layer, is exposed out of the plastic package body and the rewiring layer.
In an alternative embodiment, a side wall of the pin conducting block, which is far away from one side of the packaged chip, is provided with a pin groove.
In an alternative embodiment, the pin recess is located at a corner of the pin conductive block and extends to a side surface of the pin conductive block adjacent to the rewiring layer.
In an alternative embodiment, the rewiring layer includes a first dielectric layer, a first wiring layer, a second dielectric layer and a second wiring layer, where the first dielectric layer is disposed on a side surface of the plastic package body away from the non-functional surface, the first wiring layer is disposed in the first dielectric layer and is simultaneously electrically contacted with the pin conductive block and the package chip, the second dielectric layer is disposed on a side surface of the first dielectric layer away from the package chip, and the second wiring layer is disposed in the second dielectric layer and is electrically contacted with the first wiring layer, and the protection layer is disposed on a side surface of the second dielectric layer away from the package chip.
In an alternative embodiment, the functional surface is provided with conductive studs, which are in electrical contact with the redistribution layer, so that the redistribution layer is electrically connected to the packaged chip via the conductive studs.
In a second aspect, an embodiment of the present invention provides a method for preparing a fan-out package structure, for preparing the fan-out package structure, where the method includes:
providing a carrier;
mounting a packaging chip on the carrier, wherein the non-functional surface of the packaging chip is attached to the carrier;
mounting a pin conducting block on the carrier, wherein the pin conducting block is arranged around the packaged chip;
forming a plastic package body on the carrier, wherein the plastic package body is coated around the packaged chip and at least coated on the side wall of one side of the pin conducting block, which is close to the packaged chip;
Forming a rewiring layer on the plastic package body, wherein the rewiring layer is in electrical contact with the functional surface of the packaged chip, and the rewiring layer is in electrical contact with the pin conducting block;
And forming a protective layer on the rerouting layer, wherein the protective layer is arranged on the surface of one side of the rerouting layer far away from the packaged chip.
Peeling the carrier to enable the pin conductive block part to be exposed out of the plastic package body and used for being contacted with external conductive adhesive or conductive solder;
Cutting along the cutting path.
In a third aspect, an embodiment of the present invention provides a method for preparing a fan-out package structure, configured to prepare the foregoing fan-out package structure, where the method includes:
providing a carrier;
forming a metal layer on the surface of the carrier;
etching the metal layer and forming a pin conductive block;
Mounting a packaging chip on the surface of the carrier, wherein the functional surface of the packaging chip is downwards mounted on the carrier, and the pin conducting block is arranged around the packaging chip;
forming a plastic package body on the carrier, wherein the plastic package body is coated around the packaged chip and at least coated on the side wall of one side of the pin conducting block, which is close to the packaged chip;
Stripping the carrier;
Forming a rewiring layer on the plastic package body, wherein the rewiring layer is in electrical contact with the functional surface of the packaged chip, and the rewiring layer is in electrical contact with the pin conducting block;
Forming a protective layer on the rewiring layer, wherein the protective layer is arranged on the surface of one side of the rewiring layer away from the packaged chip;
Forming cutting channels on the protective layer and the rewiring layer, wherein the cutting channels correspondingly extend to the pin conducting blocks;
cutting is performed along the midline of the cutting channel.
The beneficial effects of the embodiment of the invention include, for example:
According to the fan-out type packaging structure and the preparation method thereof, the pin conducting blocks are arranged around the packaging chip, the plastic package body is used for wrapping the periphery of the packaging chip and wrapping at least the side wall of one side, close to the packaging chip, of the pin conducting blocks, a rewiring layer is arranged on the surface of one side, far away from the non-functional surface of the packaging chip, of the plastic package body, the rewiring layer is in electrical contact with the functional surface, the rewiring layer is in electrical contact with the pin conducting blocks, and finally a protective layer is arranged on the surface of the rewiring layer, wherein part of the pin conducting blocks is exposed out of the plastic package body and is used for being in contact with external conductive glue or conductive solder. Compared with the prior art, the embodiment of the invention utilizes the pin conductive block to be electrically connected with the rewiring layer, and exposes the surface part of the pin conductive block to the plastic package body, and in the process of upper plate, the pin conductive block can be covered by conductive adhesive or conductive solder to realize electrical output. And because the electroplating solder balls are not required to be adopted for realizing output, but the embedded pin conducting blocks are adopted as output ends, the layering and even dropping phenomena existing in the use process of the electroplating solder balls can be avoided, and the electric connection performance is ensured. And meanwhile, bridging and cavitation phenomena existing in the solder ball bump welding process are avoided.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic diagram of a fan-out package structure according to a first embodiment of the present invention under a first viewing angle;
Fig. 2 is a schematic diagram of a fan-out package structure according to a first embodiment of the present invention under a second viewing angle;
Fig. 3 to 8 are process flow diagrams of a method for manufacturing a fan-out package structure according to a first embodiment of the present invention;
Fig. 9 is a schematic diagram of a fan-out package structure according to a second embodiment of the present invention under a first viewing angle;
fig. 10 is a schematic diagram of a fan-out package structure according to a second embodiment of the present invention at a second viewing angle;
fig. 11 is a schematic diagram of a fan-out package structure according to a third embodiment of the present invention;
fig. 12 is a schematic diagram of an upper plate structure of a fan-out package structure according to a third embodiment of the present invention;
fig. 13 is a schematic diagram of a fan-out package structure according to a fourth embodiment of the present invention under a first viewing angle;
Fig. 14 is a schematic diagram of a fan-out package structure according to a fourth embodiment of the present invention under a second viewing angle;
fig. 15 is a schematic diagram of a fan-out package structure according to a fifth embodiment of the present invention;
fig. 16 to 23 are process flow diagrams of a method for manufacturing a fan-out package structure according to a fifth embodiment of the present invention.
Icon: 100-fan-out package structure; 110-packaging the chip; 111-conductive posts; 120-pin conductive blocks; 121-pin grooves; 130-plastic packaging body; 140-rewiring layers; 141-a first dielectric layer; 143-a first wiring layer; 145-a second dielectric layer; 147-a second wiring layer; 150-a protective layer; 160-a metal layer; 170-cutting the channel; 200-carrier; 300-a circuit board; 310-tin layer.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. The components of the embodiments of the present invention generally described and illustrated in the figures herein may be arranged and designed in a wide variety of different configurations.
Thus, the following detailed description of the embodiments of the invention, as presented in the figures, is not intended to limit the scope of the invention, as claimed, but is merely representative of selected embodiments of the invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
It should be noted that: like reference numerals and letters denote like items in the following figures, and thus once an item is defined in one figure, no further definition or explanation thereof is necessary in the following figures.
In the description of the present invention, it should be noted that, if the terms "upper", "lower", "inner", "outer", and the like indicate an azimuth or a positional relationship based on the azimuth or the positional relationship shown in the drawings, or the azimuth or the positional relationship in which the inventive product is conventionally put in use, it is merely for convenience of describing the present invention and simplifying the description, and it is not indicated or implied that the apparatus or element referred to must have a specific azimuth, be configured and operated in a specific azimuth, and thus it should not be construed as limiting the present invention.
Furthermore, the terms "first," "second," and the like, if any, are used merely for distinguishing between descriptions and not for indicating or implying a relative importance.
As disclosed in the background art, in the fan-out technology in the prior art, a tin ball is formed on the rewiring layer by adopting an electroplating manner as an output end, the electroplating process generally controls the electroplating uniformity/thickness by controlling the current density, and the tin ball is formed by electroplating a multi-layer metal layer structure (electroplated copper/nickel tin silver), so that once the current density is unstable, the layering phenomenon of the electroplated multi-layer metal layer exists, and the tin ball is caused to be welded and fall, thereby affecting the electrical connection performance. Meanwhile, the existing solder ball bump welding process has the phenomena of welding bridging and hollowness, and the electric connection performance is also affected.
In addition, in the prior art, metal is usually electroplated on the dielectric layer of the re-wiring layer to form the solder balls, and in the process of electroplating the surface of the dielectric opening, the problem of residual electroplated metal ions exists, so that ion migration problems exist in the subsequent wiring layer and the solder balls, and the solder failure is also easy to cause.
In order to solve the above-mentioned problems, the embodiments of the present invention provide a novel fan-out package structure and a method for manufacturing the fan-out package structure, and it should be noted that features in the embodiments of the present invention may be combined with each other without collision.
First embodiment
Referring to fig. 1 and 2, the present embodiment provides a fan-out package structure 100, which can avoid using an electroplated solder ball process as an output terminal and using an embedded pin conductive block 120 as an output terminal, so as to solve the problems caused by the conventional electroplated solder ball process. Avoid the ion migration problem that can avoid electroplating the solder ball to bring, guaranteed the welded fastening effect.
The fan-out package structure 100 provided in this embodiment includes a package chip 110, a pin conductive block 120, a plastic package body 130, a rewiring layer 140 and a protection layer 150, where two sides of the package chip 110 have a functional surface and a non-functional surface; the pin conductive block 120 is disposed around the package chip 110; the plastic package body 130 is wrapped around the packaged chip 110 and at least wrapped on the side wall of the pin conductive block 120, which is close to one side of the packaged chip 110; the rewiring layer 140 is disposed on a surface of the plastic package body 130, which is far away from the non-functional surface, and is in electrical contact with the functional surface, and the rewiring layer 140 is in electrical contact with the pin conductive block 120; the protective layer 150 is disposed on a surface of the redistribution layer 140 away from the packaged chip 110; the pin conductive block 120 is partially exposed out of the plastic package 130 and is used for contacting with external conductive adhesive or conductive solder.
It should be noted that, in the embodiment of the present invention, the pin conductive block 120 is disposed around the package chip 110, the package chip 110 is covered with the plastic package body 130, and at least the side wall of the side of the pin conductive block 120 near the package chip 110, the redistribution layer 140 is disposed on the surface of the side of the plastic package body 130 far from the non-functional surface of the package chip 110, the redistribution layer 140 is in electrical contact with the functional surface, the redistribution layer 140 is in electrical contact with the pin conductive block 120, and finally, the protection layer 150 is disposed on the surface of the redistribution layer 140, and part of the pin conductive block 120 is exposed out of the plastic package body 130 and is used for contact with external conductive adhesive or conductive solder. In the embodiment of the invention, the pin conductive block 120 is electrically connected with the rewiring layer 140, and the surface part of the pin conductive block 120 is exposed out of the plastic package body 130, and in the process of upper plate, the package structure is arranged on the circuit board 300, and the bottom of the package structure is required to be filled with conductive glue or solder to realize upper plate, so that the pin conductive block 120 can be covered by the conductive glue or the conductive solder to realize electrical output. And because the output is realized without adopting electroplated solder balls, but the embedded pin conducting block 120 is adopted as an output end, the layering and even dropping phenomena existing in the use process of the electroplated solder balls can be avoided, and the performance of electric connection is ensured. And meanwhile, bridging and cavitation phenomena existing in the solder ball bump welding process are avoided. Further, since the metal does not need to be electroplated on the re-wiring layer 140 to form the solder balls, the formation of the solder balls by electroplating on the openings on the dielectric layer is avoided, the ion migration problem existing in the wiring layer and the solder balls is avoided, and the welding and fixing effect is ensured.
In the present embodiment, a side surface of the pin conductive block 120 away from the redistribution layer 140 is exposed to the plastic package 130. Specifically, the pin conductive block 120 may be attached to the package chip 110, and a surface of a side of the pin conductive block 120 away from the redistribution layer 140 is exposed to the plastic package body 130, so that the pin conductive block can replace solder balls in the conventional technology to realize external electrical connection, and the exposed area is large, and the electrical conductivity is better.
In the present embodiment, the non-functional surface is flush with a surface of the pin conductive block 120 away from the redistribution layer 140, and the non-functional surface is exposed to the plastic package 130. Specifically, during actual preparation, the lead conductive block 120 and the package chip 110 prepared in advance may be attached and fixed on a carrier 200 along the same plane, and then plastic packaging is performed to form a plastic package body 130, and after the carrier 200 is peeled, the non-functional surface of the package chip 110 and the surface of the lead conductive block 120 are exposed to the plastic package body 130. The non-functional surface of the packaged chip 110 is exposed, so that the heat dissipation effect of the packaged chip 110 can be improved, and the whole height is thinned, thereby being beneficial to miniaturization of devices. Moreover, it is possible to implement the pin terminal on the same side as the non-functional surface of the packaged chip 110, unlike the conventional package structure in which the solder balls are formed on the redistribution layer 140.
In the present embodiment, the plastic package body 130 wraps around the pin conductive block 120, and a side surface of the pin conductive block 120, which is close to the redistribution layer 140, is exposed to the plastic package body 130. Specifically, the surface of the side of the pin conductive block 120, which is close to the redistribution layer 140, is exposed to the plastic package 130, so that the redistribution layer 140 can be directly electrically connected with the pin conductive block 120, and reliability and stability of electrical output are ensured. The plastic package body 130 is wrapped around the pin conductive block 120, that is, the plastic package body 130 covers the peripheral side wall of the pin conductive block 120 at the same time, so that the side wall of the pin conductive block 120 can be protected by the plastic package body 130, and the function of protecting the side wall of the pin conductive block 120 is achieved.
In this embodiment, the redistribution layer 140 includes a first dielectric layer 141, a first wiring layer 143, a second dielectric layer 145 and a second wiring layer 147, where the first dielectric layer 141 is disposed on a side surface of the plastic package body 130 away from the non-functional surface, the first wiring layer 143 is disposed in the first dielectric layer 141 and is simultaneously electrically contacted with the lead conductive bumps 120 and the package chip 110, the second dielectric layer 145 is disposed on a side surface of the first dielectric layer 141 away from the package chip 110, the second wiring layer 147 is disposed in the second dielectric layer 145 and is electrically contacted with the first wiring layer 143, and the protection layer 150 is disposed on a side surface of the second dielectric layer 145 away from the package chip 110. Specifically, the first wiring layer 143 and the second wiring layer 147 may be copper layers, the first dielectric layer 141 and the second dielectric layer 145 are both made of dielectric materials, and meanwhile, the protection layer 150 may also be made of dielectric materials, which can cover the second wiring layer 147 inside, so as to play a good role in protecting against external impurities or water vapor erosion. Of course, other materials, such as silicon nitride or silicon, may be used for the protective layer 150, so that the protective effect is better and the overall structural strength can be improved.
In this embodiment, the functional surface is provided with conductive studs 111, and the conductive studs 111 are electrically contacted with the redistribution layer 140, so that the redistribution layer 140 is electrically connected with the packaged chip 110 through the conductive studs 111. Specifically, the functional surface of the packaged chip 110 is provided with a bonding pad, the bonding pad is provided with a conductive convex column 111, the conductive convex column 111 is in a copper column structure, the plastic package body 130 is wrapped around the conductive convex column 111, the first wiring layer 143 of the rewiring layer 140 is in electrical contact with the conductive convex column 111, and the conductive convex column 111 is designed to enable the electrical connection between the first wiring layer 143 and the packaged chip 110 to be more stable and reliable, and the heat dissipation effect is better. Of course, in other preferred embodiments of the present invention, the conductive bump 111 may be not provided, and the pad may be directly connected to the first wiring layer 143, or the first wiring layer 143 may be directly connected to the pad on the functional surface by a slot plating method, which is not particularly limited herein.
It is noted that, compared to the conventional lead frame structure, the fan-out package structure 100 provided in the present embodiment has no base island and connection rib structure, and can realize high-density QFN package by using wafer level package, thereby replacing the lead frame and the conventional wire bonding structure, and avoiding the defect that the pins of the conventional lead frame are easily deformed by external force.
The embodiment of the invention also provides a preparation method of the fan-out type packaging structure 100, which is used for preparing the fan-out type packaging structure 100, and the preparation method comprises the following steps:
S1: a carrier 200 is provided.
Referring to fig. 3, specifically, firstly, a carrier 200 is taken, and a film layer, which may be a UV adhesive layer, is coated on the surface of the carrier 200, so that the subsequent bonding effect is ensured and the stripping is also facilitated. The carrier 200 may be made of glass, silicon oxide, metal, or the like.
S2: the package chip 110 and the lead conductive block 120 are disposed on the carrier 200.
Referring to fig. 4, in particular, the non-functional surface of the packaged chip 110 is attached to the carrier 200, and the lead conductive blocks 120 are disposed around the packaged chip 110. In the actual mounting, the package chip 110 is first mounted on the surface of the carrier 200, the non-functional surface of the package chip 110 is mounted on the carrier 200 with the functional surface facing up, and the conductive bump 111 may be fabricated in advance or the conductive bump 111 may not be fabricated on the functional surface, and in this embodiment, the conductive bump 111 is taken as an example. After the packaging of the packaged chip 110 is completed, the pin conductive block 120 may be mounted on the surface of the carrier 200, where the pin conductive block 120 is a metal block that is prepared in advance, and the metal block is used as a pin of the packaging structure. Preferably, the metal bump may be a copper bump here, and the height of the pin conductive bump 120 may be the same as the height of the conductive bump 111 on the package chip 110.
S3: the molding compound 130 is formed on the carrier 200.
Referring to fig. 5, in particular, the plastic package 130 is wrapped around the packaged chip 110 and at least wrapped around a side wall of the pin conductive block 120 near one side of the packaged chip. Preferably, in actual manufacturing, the plastic packaging process may be used for plastic packaging, and the plastic package body 130 may be completely wrapped around the packaged chip 110 and the pin conductive block 120. Grinding may be performed after the plastic packaging to expose the pin conductive bumps 120 and the conductive posts 111 of the packaged chip 110. Of course, in other preferred embodiments of the present invention, the electrical connection may be achieved by a subsequent grooving plating process without grinding.
S4: a redistribution layer 140 is formed on the molding compound 130.
Referring to fig. 6, in particular, wherein the redistribution layer 140 is in electrical contact with the functional surface of the packaged chip 110, and the redistribution layer 140 is in electrical contact with the pin conductive bumps 120. In actual preparation, the first dielectric layer 141 may be formed on the surface of the plastic package body 130 by spin-coating, then patterned openings may be formed by exposing and developing, and the first wiring layer 143 may be formed by electroplating a copper layer, then the second dielectric layer 145 may be formed again, then patterned openings may be formed by exposing and developing, and the second wiring layer 147 may be formed by electroplating a copper layer, thereby completing the wiring. The first dielectric layer 141 and the second dielectric layer 145 are made of dielectric materials, for example, silicon nitride, silicon oxynitride, polyimide, benzocyclobutene, and the like. And the first wiring layer 143 and the second wiring layer 147 may be electroplated copper micro-wiring layers.
S5: a protective layer 150 is formed on the re-wiring layer 140.
Referring to fig. 7, in particular, the protective layer 150 is disposed on a side surface of the redistribution layer 140 remote from the packaged chip 110. The protection layer 150 is also a dielectric material, and the protection layer 150 is formed by spin-coating, physical vapor deposition, and chemical vapor deposition, so as to protect the second wiring layer 147 and the first wiring layer 143.
S6: the carrier 200 is peeled off.
Referring to fig. 8, in particular, UV irradiation of the adhesive film layer on the back of the carrier 200 may be performed to separate the carrier 200 to remove the adhesive layer and the carrier 200. After the carrier 200 is peeled off, the bottom leads and the back surface of the chip can be exposed, so that the lead conductive blocks 120 are partially exposed to the plastic package 130 and used for contacting with external conductive adhesive or conductive solder.
S7: cutting along the cutting path.
With continued reference to fig. 1, in particular, a dicing process may be performed, in which the product is diced into individual finished processes by mechanical dicing or laser dicing.
In summary, in the fan-out package structure 100 and the method for manufacturing the same provided in the present embodiment, the lead conductive block 120 is disposed around the package chip 110, the package chip 110 is covered with the plastic package body 130, and at least the side wall of the lead conductive block 120 near to the package chip 110, the redistribution layer 140 is disposed on the surface of the plastic package body 130 far from the non-functional surface of the package chip 110, the redistribution layer 140 is electrically contacted with the functional surface, and the redistribution layer 140 is electrically contacted with the lead conductive block 120, and finally the protection layer 150 is disposed on the surface of the redistribution layer 140, wherein a portion of the lead conductive block 120 is exposed out of the plastic package body 130 and is used for contacting with external conductive adhesive or conductive solder. Compared with the prior art, the embodiment of the invention utilizes the pin conductive block 120 to be electrically connected with the rewiring layer 140, and exposes the surface part of the pin conductive block 120 to the plastic package body 130, and in the process of board feeding, the pin conductive block 120 can be covered by conductive glue or conductive solder to realize electrical output. And because the output is realized without adopting electroplated solder balls, but the embedded pin conducting block 120 is adopted as an output end, the layering and even dropping phenomena existing in the use process of the electroplated solder balls can be avoided, and the performance of electric connection is ensured. And meanwhile, bridging and cavitation phenomena existing in the solder ball bump welding process are avoided.
Second embodiment
The basic structure and principle of the fan-out package structure 100 are the same as those of the first embodiment, and for brevity, reference is made to the corresponding parts of the first embodiment.
Referring to fig. 9 and 10, in the present embodiment, the plastic package body 130 is at least filled in the area between the package chip 110 and the pin conductive block 120, and the side wall of the pin conductive block 120 away from the package chip 110 is exposed to the plastic package body 130. Specifically, the side wall of the side of the pin conductive block 120 far away from the package chip 110 is flush with the side wall of the plastic package body 130, so that exposure is realized, and the exposed area is increased, so that the contact area with conductive adhesive or conductive solder during board mounting is further increased, and the electrical connection performance is further improved.
In actual manufacturing, the dicing may be performed along the edge of the side of the pin conductive block 120 away from the package chip 110, so that the side wall of the pin conductive block 120 on the single product is flush with the side wall of the plastic package body 130.
Third embodiment
The basic structure and principle of the fan-out package structure 100 according to the present embodiment and the technical effects thereof are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment.
Referring to fig. 11, in the present embodiment, the plastic package body 130 is at least filled in the area between the package chip 110 and the pin conductive block 120, and the side wall of the side of the pin conductive block 120 away from the package chip 110 is exposed to the plastic package body 130, and the side wall of the pin conductive block 120 exposed to the plastic package body 130 is further provided with a pin groove 121.
Further, the lead groove 121 is located at a corner of the lead conductive block 120 and extends to a side surface of the lead conductive block 120 away from the rewiring layer 140. Specifically, the pin grooves 121 are delayed until the side walls of the plastic package body 130 are exposed, and the pin grooves 121 can be formed by etching or cutting during the preparation, so that the contact area of the conductive adhesive or the conductive solder during the board mounting can be further improved, and the electrical connection performance and the welding reliability are further improved.
Referring to fig. 12, in actual board, the surface of one side of the pin conductive block 120 facing away from the redistribution layer 140 is directly attached to the bonding pad of the circuit board 300 correspondingly, and then a solder layer 310 is disposed around to realize soldering, so that the soldering area of the solder is increased due to the existence of the pin groove 121, and the soldering reliability is improved.
Fourth embodiment
Referring to fig. 13 and 14, the embodiment of the present invention provides a fan-out package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents in the first embodiment where the description of the embodiment is not mentioned.
In the present embodiment, the number of the lead conductive blocks 120 is plural, and the plurality of lead conductive blocks 120 are enclosed to form plural circles and are enclosed around the package chip 110 in a stacked manner. Specifically, in this embodiment, the pin conductive blocks 120 are taken as two circles for illustration, the pin conductive blocks 120 of the inner circle are distributed around the package chip 110 along a rectangle or a circle, and the pin conductive blocks 120 of the outer circle are distributed around the pin conductive blocks 120 of the inner circle along a rectangle or a circle.
Through setting up the multiturn pin, can further promote the area of contact when welding, promote electric connection performance. And in actual preparation, the pin conducting blocks 120 of a plurality of circles can be attached to the carrier 200 according to preset positions, and in cutting, cutting can be performed along the edges of the pin conducting blocks 120 of the outer ring, so that the side walls of the edges of the pin conducting blocks 120 of the outer ring are flush with the side walls of the plastic package body 130, the exposed area of the pin conducting blocks 120 is further improved, and the electrical connection performance is ensured.
Fifth embodiment
Referring to fig. 15, the present embodiment provides a fan-out package structure 100, whose basic structure and principle and technical effects are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment where the description of the embodiment is not mentioned.
In the present embodiment, the plastic package body 130 is wrapped on a side surface of the package chip 110 away from the redistribution layer 140 and a side surface of the pin conductive block 120 away from the redistribution layer 140, and a side wall of the pin conductive block 120 away from the package chip 110 is exposed to the plastic package body 130. Specifically, the plastic package body 130 completely encapsulates the package chip 110 and encapsulates the back surface of the pin conductive block 120, so as to achieve better protection. Meanwhile, a part of the pin conductive block 120, which is close to the redistribution layer 140, is exposed out of the plastic package 130 and a part of the pin conductive block is exposed out of the redistribution layer 140, so that the effect of connecting and contacting with external conductive glue or conductive solder can be achieved.
Further, the width of the plastic package body 130 is greater than the width of the redistribution layer 140, and the edge of the surface of the pin conductive block 120, which is close to the redistribution layer 140, is exposed to the plastic package body 130 and the redistribution layer 140. Specifically, the redistribution layer 140 is located in the middle area of the plastic package body 130, and its width is smaller than that of the plastic package body 130, so that the pin conductive block 120 located at the edge of the plastic package body 130 can be partially exposed, and the electrical connection effect between the pin conductive block and the conductive adhesive or the conductive solder is ensured.
In the present embodiment, a side wall of the lead conductive block 120, which is far from the side of the package chip 110, is provided with a lead groove 121. Specifically, the lead grooves 121 are located at corners of the lead conductive block 120 and extend to a side surface of the lead conductive block 120 adjacent to the rewiring layer 140. Specifically, the inner side walls of the pin grooves 121 are flush with the side walls of the redistribution layer 140, so that the groove depth can be increased, and the reliability of the side wall welding dust collection can be further improved. Meanwhile, the redistribution layer 140 can serve as a buffer layer here, preventing the plastic package body 130 from being warped, and particularly preventing the soldering ends of the pin grooves 121 from being warped.
In addition, in the embodiment, the height of the pin conductive block 120 relative to the redistribution layer 140 is smaller than the height of the packaged chip 110 relative to the redistribution layer 140, so that the material consumption of the pin conductive block 120 can be reduced, the material is saved, and the process difficulty is reduced.
The embodiment of the present invention further provides a method for preparing the fan-out package structure 100, which is used for preparing the fan-out package structure 100, and the basic steps and principles and the technical effects thereof are the same as those of the first embodiment, and for brevity, reference may be made to the corresponding contents in the first embodiment.
The preparation method provided by the embodiment comprises the following steps:
S1: a carrier 200 is provided.
Specifically, firstly, a carrier 200 is taken, and a glue film layer, which can be a UV glue layer, is coated on the surface of the carrier 200, so that the subsequent bonding effect is ensured and the stripping is convenient. The carrier 200 may be made of glass, silicon oxide, metal, or the like.
S2: a metal layer 160 is formed on the surface of the carrier 200.
Referring to fig. 16 in combination, in particular, a metal layer 160 may be formed on the surface of the carrier 200 by physical vapor deposition or chemical vapor deposition, and the metal layer 160 may be a copper layer.
S3: the metal layer 160 is etched and the pin conductive block 120 is formed.
Referring to fig. 17 in combination, specifically, the chip attach region may be recessed using dry etching or chemical etching, a portion of the metal layer 160 is removed, and the remaining metal layer 160 forms the pin conductive bump 120.
S4: the package chip 110 is mounted on the surface of the carrier 200.
Referring to fig. 18 in combination, the functional surface of the packaged chip 110 is mounted on the carrier 200 with the lead conductive block 120 disposed around the packaged chip 110. The non-functional surface of the packaged chip 110 is wrapped inside the plastic package 130.
S5: the molding compound 130 is formed on the carrier 200.
Referring to fig. 19 in combination, in particular, the plastic package 130 is wrapped around the packaged chip 110, and at least wrapped around a side wall of the pin conductive block 120 near one side of the packaged chip. Preferably, the plastic package 130 is wrapped around the packaged chip 110 and the pin conductive block 120.
S6: the carrier 200 is peeled off.
Referring to fig. 20 in combination, specifically, after the carrier 200 is peeled off, the functional surface of the packaged chip 110 is exposed, and the surface of the pin conductive block 120 is exposed.
S7: a redistribution layer 140 is formed on the molding compound 130.
Referring to fig. 21 in combination, in particular, the formation of the re-wiring layer 140 may be prepared in the manner in the foregoing embodiment, wherein the re-wiring layer 140 is in electrical contact with the functional surface of the package chip 110, and the re-wiring layer 140 is in electrical contact with the pin conductive block 120, through which signal output may be achieved.
S8: a protective layer 150 is formed on the re-wiring layer 140.
Referring to fig. 22 in combination, in particular, the protective layer 150 is disposed on a surface of the redistribution layer 140 on a side away from the packaged chip 110. The protective layer 150 may be prepared in the manner and materials described with reference to the previous embodiments.
S9: dicing channels 170 are formed on the protective layer 150 and the rewiring layer 140, the dicing channels 170 extending to the pin conductive bumps 120, respectively.
Referring to fig. 23, in particular, the cutting channel 170 may be formed by one cut, at which time the cutting channel 170 may be cut just to the surface of the lead pad 120, or may partially cut the lead pad 120, thereby forming the lead groove 121, and the cutting channel 170 may be exposed to the surface of the lead pad 120.
S10: the cut is made along the midline of the cutting channel 170.
With continued reference to fig. 15, in particular, cutting is performed along the center line of the scribe line such that the edge of the molded lead conductive block 120 forms a lead groove 121.
According to the fan-out type packaging structure 100 and the manufacturing method thereof provided by the embodiment of the invention, the lead conducting blocks 120 are exposed by the cutting channels 170, the lead grooves 121 are formed at the edges, and the inner side walls of the lead grooves 121 are flush with the side walls of the rewiring layer 140, so that the groove depth is increased, and the reliability of welding tin layers on the side walls is further improved. Meanwhile, the rewiring layer 140 can serve as a buffer layer to prevent the plastic package body 130 from warping, and particularly, the welding end where the pin groove 121 can be placed can warp. The metal layer 160 is formed by deposition and the pin conductive block 120 is formed after etching, so that the thickness of the pin conductive block 120 can be reduced, and the height of the pin conductive block 120 is lower than that of the packaged chip 110, thereby reducing the consumption and reducing the difficulty of the preparation process.
The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any changes or substitutions easily contemplated by those skilled in the art within the scope of the present invention should be included in the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.
Claims (16)
1. A fan-out package structure, comprising:
The packaging chip is provided with a functional surface and a non-functional surface at two sides;
the pin conducting blocks are arranged around the packaging chip;
The plastic package body is coated around the packaged chip and at least coated on the side wall of one side, close to the packaged chip, of the pin conducting block;
the rewiring layer is arranged on the surface of one side, far away from the non-functional surface, of the plastic package body, is in electrical contact with the functional surface, and is in electrical contact with the pin conducting block;
The protective layer is arranged on the surface of one side of the rewiring layer, which is far away from the packaged chip;
The pin conductive block part is exposed out of the plastic package body and is used for being contacted with external conductive adhesive or conductive solder.
2. The fan-out package structure of claim 1, wherein a side surface of the pin conductive block away from the rewiring layer is exposed to the plastic package body.
3. The fan-out package structure of claim 2, wherein the non-functional surface is flush with a surface of the pin conductive block away from the redistribution layer, and the non-functional surface is exposed from the plastic package body.
4. The fan-out package structure of claim 3, wherein the plastic package body is wrapped around the pin conductive block, and a side surface of the pin conductive block, which is close to the rewiring layer, is exposed to the plastic package body.
5. The fan-out package structure of claim 2, wherein the plastic package body is filled at least in a region between the package chip and the lead conductive block, and a side wall of the lead conductive block away from the package chip is exposed to the plastic package body.
6. The fan-out package structure of claim 5, wherein the pin conductive block is further provided with a pin groove on a side wall of the plastic package body.
7. The fan-out package structure of claim 6, wherein the lead recess is located at a corner of the lead pad and extends to a side surface of the lead pad remote from the redistribution layer.
8. The fan-out package structure of claim 2, wherein the plurality of lead conductive bumps are formed in a plurality of circles and are stacked around the package chip.
9. The fan-out package structure of claim 1, wherein the plastic package body is coated on a surface of the package chip on a side far away from the rewiring layer and a surface of the pin conductive block on a side far away from the rewiring layer, and a side wall of the pin conductive block on a side far away from the package chip is exposed to the plastic package body.
10. The fan-out package structure of claim 9, wherein the plastic package body has a width greater than a width of the redistribution layer, and the pin conductive bump is exposed to the plastic package body and the redistribution layer near an edge of a side surface of the redistribution layer.
11. The fan-out package structure of claim 10, wherein a side wall of the pin conducting block away from a side of the package chip is provided with a pin groove.
12. The fan-out package structure of claim 11, wherein the lead recess is located at a corner of the lead pad and extends to a side surface of the lead pad adjacent to the redistribution layer.
13. The fan-out package structure of any of claims 1-12, wherein the redistribution layer comprises a first dielectric layer, a first wiring layer, a second dielectric layer, and a second wiring layer, the first dielectric layer is disposed on a side surface of the plastic package body away from the nonfunctional surface, the first wiring layer is disposed in the first dielectric layer and is simultaneously in electrical contact with the pin conductive block and the package chip, the second dielectric layer is disposed on a side surface of the first dielectric layer away from the package chip, the second wiring layer is disposed in the second dielectric layer and is in electrical contact with the first wiring layer, and the protective layer is disposed on a side surface of the second dielectric layer away from the package chip.
14. The fan-out package structure according to any one of claims 1-12, wherein the functional surface is provided with conductive studs, which are in electrical contact with the redistribution layer, so that the redistribution layer is electrically connected with the package chip through the conductive studs.
15. A method for preparing the fan-out package structure according to any one of claims 1 to 14, wherein the preparing method comprises:
providing a carrier;
mounting a packaging chip on the carrier, wherein the non-functional surface of the packaging chip is attached to the carrier;
mounting a pin conducting block on the carrier, wherein the pin conducting block is arranged around the packaged chip;
forming a plastic package body on the carrier, wherein the plastic package body is coated around the packaged chip and at least coated on the side wall of one side of the pin conducting block, which is close to the packaged chip;
Forming a rewiring layer on the plastic package body, wherein the rewiring layer is in electrical contact with the functional surface of the packaged chip, and the rewiring layer is in electrical contact with the pin conducting block;
Forming a protective layer on the rewiring layer, wherein the protective layer is arranged on the surface of one side of the rewiring layer away from the packaged chip;
peeling the carrier to enable the pin conductive block part to be exposed out of the plastic package body and used for being contacted with external conductive adhesive or conductive solder;
Cutting along the cutting path.
16. A method for preparing the fan-out package structure according to any one of claims 1 to 14, wherein the preparing method comprises:
providing a carrier;
forming a metal layer on the surface of the carrier;
etching the metal layer and forming a pin conductive block;
Mounting a packaging chip on the surface of the carrier, wherein the functional surface of the packaging chip is downwards mounted on the carrier, and the pin conducting block is arranged around the packaging chip;
forming a plastic package body on the carrier, wherein the plastic package body is coated around the packaged chip and at least coated on the side wall of one side of the pin conducting block, which is close to the packaged chip;
Stripping the carrier;
Forming a rewiring layer on the plastic package body, wherein the rewiring layer is in electrical contact with the functional surface of the packaged chip, and the rewiring layer is in electrical contact with the pin conducting block;
Forming a protective layer on the rewiring layer, wherein the protective layer is arranged on the surface of one side of the rewiring layer away from the packaged chip;
Forming cutting channels on the protective layer and the rewiring layer, wherein the cutting channels correspondingly extend to the pin conducting blocks;
cutting is performed along the midline of the cutting channel.
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| CN202411230838.XA CN119008564A (en) | 2024-09-04 | 2024-09-04 | Fan-out type packaging structure and preparation method thereof |
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| CN202411230838.XA CN119008564A (en) | 2024-09-04 | 2024-09-04 | Fan-out type packaging structure and preparation method thereof |
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| JPH11121641A (en) * | 1997-10-08 | 1999-04-30 | Nec Corp | Semiconductor device and manufacturing method thereof |
| JP2010073893A (en) * | 2008-09-18 | 2010-04-02 | Shinko Electric Ind Co Ltd | Semiconductor device and production process thereof |
| US20110278707A1 (en) * | 2010-05-17 | 2011-11-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die |
| CN110890340A (en) * | 2018-09-11 | 2020-03-17 | 株式会社东芝 | Semiconductor device and method for manufacturing the same |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| JPH11121641A (en) * | 1997-10-08 | 1999-04-30 | Nec Corp | Semiconductor device and manufacturing method thereof |
| JP2010073893A (en) * | 2008-09-18 | 2010-04-02 | Shinko Electric Ind Co Ltd | Semiconductor device and production process thereof |
| US20110278707A1 (en) * | 2010-05-17 | 2011-11-17 | Stats Chippac, Ltd. | Semiconductor Device and Method of Forming Prefabricated Multi-Die Leadframe for Electrical Interconnect of Stacked Semiconductor Die |
| CN110890340A (en) * | 2018-09-11 | 2020-03-17 | 株式会社东芝 | Semiconductor device and method for manufacturing the same |
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