CN1189939C - Semiconductor device and its making method - Google Patents
Semiconductor device and its making method Download PDFInfo
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- CN1189939C CN1189939C CNB021074569A CN02107456A CN1189939C CN 1189939 C CN1189939 C CN 1189939C CN B021074569 A CNB021074569 A CN B021074569A CN 02107456 A CN02107456 A CN 02107456A CN 1189939 C CN1189939 C CN 1189939C
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Abstract
Description
技术领域technical field
本发明涉及在硅等组成的半导体衬底的一表面上形成多个凸点电极和在凸点电极间形成密封膜的半导体器件,更详细地说,涉及使各凸点电极的上表面比密封膜的表面低,具有缓和作用于凸点电极上形成的接合元件上的应力的构造的半导体器件及其制造方法。The present invention relates to a semiconductor device in which a plurality of bump electrodes are formed on one surface of a semiconductor substrate composed of silicon or the like and a sealing film is formed between the bump electrodes. A semiconductor device having a structure in which the surface of the film is low and the stress acting on bonding elements formed on bump electrodes is relieved, and a method for manufacturing the same.
背景技术Background technique
包括上述应力缓和构造的半导体器件被称为CSP(chip sizepackage;芯片尺寸封装),作为一例,如图8所示。在该半导体器件中,形成如下构造:在硅等构成的半导体衬底1的表面上形成连接焊盘2,在该表面的除了连接焊盘2的中央部以外的部分上形成绝缘膜3,从通过绝缘膜3上形成的开口部4露出的连接焊盘2的表面到绝缘膜3表面的规定的地方形成再布线5,在再布线5的前端的焊盘部表面上形成凸点电极6,在除了凸点电极6以外的整个表面上,以其表面比凸点电极6的表面高来形成密封膜7,在密封膜7上形成的开口部8内和其上侧形成与凸点电极6电连接的焊料球9。A semiconductor device including the above stress relaxation structure is called a CSP (chip size package), and is shown in FIG. 8 as an example. In this semiconductor device, a structure is formed in which
这种情况下,使凸点电极6的表面比密封膜7的表面低,在密封膜7上形成的开口部8内和其上侧形成与凸点电极6电连接的焊料球9的原因在于,在将该半导体器件封装在电路衬底(未图示)上后,在进行温度周期试验等时,不容易因半导体衬底1和电路衬底之间的热膨胀系数差产生的应力,而在凸点电极6和焊料球9的界面上产生裂纹。In this case, the surface of the
下面,依次参照图9~图12来说明该半导体器件的制造方法的一例。首先,如图9所示,在晶片状态的半导体衬底1的表面上形成连接焊盘2,在除了其表面的连接焊盘2的中央部以外的部分上形成绝缘膜3,从通过绝缘膜3上形成的开口部4露出的连接焊盘2的表面到绝缘膜3表面的规定地方形成再布线5,在再布线5的前端的焊盘部表面上,作为一例,形成高度120μm左右的凸点电极6。Next, an example of the method for manufacturing the semiconductor device will be described with reference to FIGS. 9 to 12 in order. First, as shown in FIG. 9, the
接着,如图10所示,在包含凸点电极6和再布线5的绝缘膜3的整个表面上,通过递模法、分配法、浸渍法、印刷法等来形成厚度比凸点电极6的高度稍厚的环氧系树脂组成的密封膜7。因此,在该状态下,凸点电极6的表面被密封膜7覆盖。Next, as shown in FIG. 10 , on the entire surface of the
接着,如图11所示,通过对密封膜7的表面侧和凸点电极6的表面侧进行研磨,使凸点电极6的表面露出,并且使该露出的凸点电极6的表面与密封膜7的表面为同一平面。由于这种情况的研磨不仅使凸点电极6的表面露出,同时还具有加工密封膜7的表面的作用,所以对凸点电极6的表面侧研磨约30μm左右。因此,该状态下的凸点电极6的高度约为90μm左右。Next, as shown in FIG. 11, by grinding the surface side of the
接着,如图12所示,通过半腐蚀处理,将凸点电极6的表面侧约腐蚀30μm左右,在密封膜7上形成开口部8。因此,该状态下的凸点电极6的高度约为60μm左右。接着,如图8所示,在密封膜7中形成的开口部8内和其上侧形成与凸点电极6电连接的焊料球9。接着,经过切割工序后,获得各个芯片组成的半导体器件。Next, as shown in FIG. 12 , the surface side of the
但是,在上述现有的半导体器件中,凸点电极6的初始高度为比较高的约120μm左右,而经过兼有表面加工的研磨处理和半腐蚀处理后,凸点电极6的高度降低到初始的一半、约60μm左右,使得对凸点电极6本身产生的应力的缓和降低。这里,有进一步提高凸点电极6的初始高度的方法,但通过电镀形成凸点电极6时的抗蚀剂膜变厚,使对半导体衬底进行涂敷和曝光时的厚度方向的透光性难以均匀,在用光刻法的形成上有限制。即使假设克服了抗蚀剂膜的形成和曝光的问题,在通过电镀来形成高的凸点电极后,再进行60μm左右腐蚀的方法,显然生产效率低。而且,通过半腐蚀处理在凸点电极6的高度上产生偏差,进而在焊料球9的高度上产生偏差,所以产生与电路衬底的连接不良。However, in the above-mentioned conventional semiconductor device, the initial height of the
发明内容Contents of the invention
本发明的目的在于,在具有包括应力缓和构造的凸点电极的半导体器件中,可高效率地提高凸点电极的高度,并且使其均匀。An object of the present invention is to efficiently increase and make the height of the bump electrode uniform in a semiconductor device having a bump electrode including a stress relaxation structure.
根据本发明,提供一种半导体器件,该半导体器件将密封膜形成得比凸点电极的高度厚,在该密封膜上形成使所述各凸点电极的上表面露出的开口部。According to the present invention, there is provided a semiconductor device in which a sealing film is formed thicker than the height of the bump electrodes, and openings exposing the upper surfaces of the respective bump electrodes are formed in the sealing film.
根据该构造,由于凸点电极处于其上表面比密封膜的上表面低的位置,所以对作用于凸点电极上形成的粘结剂界面上的应力具有缓和功能。由于密封膜的开口部可以不用实施使凸点电极的高度偏差增大的腐蚀处理来形成,所以可以使凸点电极的高度均匀,并且进行高效率的生产。According to this configuration, since the upper surface of the bump electrode is located at a position lower than the upper surface of the sealing film, it has a function of relieving stress acting on the interface of the adhesive formed on the bump electrode. Since the openings of the sealing film can be formed without performing an etching process that increases the variation in the height of the bump electrodes, the height of the bump electrodes can be made uniform and efficient production can be performed.
附图说明Description of drawings
图1是表示本发明实施例1的半导体器件的放大剖面图;1 is an enlarged sectional view showing a semiconductor device according to
图2是说明有关图1所示的半导体器件的制造方法的最初制造工序的放大剖面图;2 is an enlarged cross-sectional view illustrating an initial manufacturing process of the manufacturing method of the semiconductor device shown in FIG. 1;
图3是说明接续图2的工序的放大剖面图;Fig. 3 is an enlarged cross-sectional view illustrating a process continued from Fig. 2;
图4是说明接续图3的工序的放大剖面图;Fig. 4 is an enlarged cross-sectional view illustrating a process continued from Fig. 3;
图5是说明接续图4的工序的放大剖面图;Fig. 5 is an enlarged cross-sectional view illustrating a process continued from Fig. 4;
图6是表示第1实施例的变形例的半导体器件的放大剖面图;6 is an enlarged cross-sectional view showing a semiconductor device according to a modified example of the first embodiment;
图7是本发明第2实施例的半导体器件的放大剖面图;7 is an enlarged cross-sectional view of a semiconductor device according to a second embodiment of the present invention;
图8是现有的半导体器件的放大剖面图;FIG. 8 is an enlarged cross-sectional view of a conventional semiconductor device;
图9是说明有关图6所示的半导体器件的制造方法的最初制造工序的放大剖面图;FIG. 9 is an enlarged cross-sectional view illustrating an initial manufacturing process of the manufacturing method of the semiconductor device shown in FIG. 6;
图10是说明接续图7的制造工序的剖面图;Fig. 10 is a cross-sectional view illustrating the manufacturing process following Fig. 7;
图11是说明接续图8的制造工序的剖面图;以及FIG. 11 is a cross-sectional view illustrating the manufacturing process following FIG. 8; and
图12是说明接续图9的制造工序的剖面图。FIG. 12 is a cross-sectional view illustrating a manufacturing process following FIG. 9 .
具体实施方式Detailed ways
第1实施例first embodiment
图1是表示本发明的半导体器件的一实施例的放大剖面图,以下,说明该半导体器件的构造。FIG. 1 is an enlarged cross-sectional view showing an embodiment of a semiconductor device of the present invention, and the structure of the semiconductor device will be described below.
在硅等组成的半导体衬底11的上表面上形成连接焊盘12,在除了半导体衬底上表面的连接焊盘12的中央部以外的部分上形成绝缘膜13。在绝缘膜13上,形成露出连接焊盘12的开口部14,从各连接焊盘12的上表面通过开口部14在绝缘膜13上使再布线15延伸。再布线15例如由铜等形成。在各再布线15的前端的焊盘部表面上,例如形成铜构成的柱状的凸点电极16。在从柱状的凸点电极16露出的半导体衬底11的整个表面上形成第1密封膜17。第1密封膜17的上表面以与凸点电极16的上表面基本上为同一平面来形成。在第1密封膜17上,形成带有使各凸点电极16的上表面露出的开口部19的第2密封膜18。在第2密封膜18中形成的开口部19内和其上侧,形成与凸点电极16电连接的焊料球20(低熔点金属层)。
这种情况下,使凸点电极16的上表面与第1密封膜17的上表面为同一平面,在第1密封膜17上形成的第2密封膜18上形成的开口部19内和在其上侧,形成与凸点电极16电连接的焊料球20的原因在于,在将该半导体器件封装在电路衬底(未图示)上后,在进行温度周期试验等时,不容易因半导体衬底11和电路衬底之间的热膨胀系数差产生的应力,而在凸点电极16和焊料球20的界面上产生裂纹。In this case, the upper surface of the
下面,依次参照图2~图5来说明该半导体器件的制造方法的一例。首先,如图2所示,在晶片状态的半导体衬底11的上表面上形成铝系金属等组成的连接焊盘12,在除了其上表面的连接焊盘12的中央部以外的部分上形成绝缘膜13,从通过绝缘膜13上形成的开口部14露出的连接焊盘12的上表面,直到绝缘膜13上表面的规定地方形成再布线15,在再布线15的前端的焊盘部上表面上,作为一例,制备形成高度120μm左右的柱状的凸点电极16。凸点电极16的形成利用光刻技术来进行,例如,在绝缘膜13上的整个表面上,通过溅射法等来成膜用于再布线的金属膜,在该金属膜上,形成光致抗蚀剂膜,在该光致抗蚀剂膜上形成用于形成凸点的开口部,通过将绝缘膜13上形成的金属膜作为一个电极来进行电镀,从而形成凸点电极16。凸点电极形成后,将光致抗蚀剂剥离,通过光刻技术对金属膜进行构图来形成再布线15后,成为图2所示的状态。Next, an example of the method for manufacturing the semiconductor device will be described with reference to FIGS. 2 to 5 in sequence. First, as shown in FIG. 2, a
接着,如图3所示,在包含凸点电极16和再布线15的绝缘膜13的整个上表面上,通过递模法、分配法、浸渍法、印刷法等来形成厚度比凸点电极16的高度稍厚的环氧系树脂组成的第1密封膜17。因此,在该状态下,凸点电极16的上表面被第1密封膜17覆盖。Next, as shown in FIG. 3, on the entire upper surface of the insulating
接着,如图4所示,通过对第1密封膜17的上表面侧和凸点电极16的表面侧进行研磨,使凸点电极16的表面露出,并且使该露出的凸点电极16的上表面与密封膜7的上表面为同一平面。由于此时的研磨通过后述的第2密封膜18的形成而不必进行第1密封膜17的表面(上表面)精加工,所以只要使凸点电极16的表面露出,并且使该露出的凸点电极16的上表面与密封膜7的上表面为同一平面就可以。因此,对凸点电极16的上表面侧进行比以往(约30μm左右)少的例如5~20μm左右的研磨。因此,该状态下的凸点电极16的高度约为100~115μm左右。Next, as shown in FIG. 4, by polishing the upper surface side of the
接着,如图5所示,在除了凸点电极16以外的第1密封膜17的表面上,通过丝网印刷法、光刻法等来形成厚度10~15μm、最好20~30μm左右的环氧系树脂组成的第2密封膜18。在该状态下,在第2密封膜18的与凸点电极16的上表面对应的部分上形成开口部19。接着,如图1所示,在形成了第2密封膜18的开口部19内和其上侧,形成与凸点电极16电连接的焊料球20。焊料球20除了直接装载在各凸点电极16上的方法以外,也可以使用在各凸点电极16上涂敷焊膏的回流法。通过回流熔融的焊膏因表面张力形成球状。接着,经过切割工序,可获得各个芯片组成的半导体器件。Next, as shown in FIG. 5, on the surface of the
在这样得到的半导体器件中,由于在通过研磨来使得上表面与凸点电极16的上表面为同一平面的第1密封膜17上,以使在与凸点电极16的上表面对应的位置上带有开口部19来形成第2密封膜18,所以在可以使凸点电极16的上表面比第2密封膜18的上表面低之后,凸点电极16的高度与第1密封膜17的厚度相同,因此,可以提高凸点电极16的高度并且使其均匀。In the semiconductor device obtained in this way, on the
即,在上述实施例中,相对于凸点电极16的约120μm左右的初始高度来说,由于最终的高度约为100~115μm,所以比初始高度稍低,与现有的最终高度约60μm相比,可以很大地提高。其结果,可以提高缓和凸点电极16本身产生的应力。由于可以使凸点电极16的高度均匀,所以焊料球20的高度也均匀,不会对与电路衬底的电连接产生障碍。That is, in the above-mentioned embodiment, with respect to the initial height of about 120 μm of the
通过对第1密封膜17的上表面侧进行研磨,使凸点电极16的上表面与第1密封膜17的上表面为同一平面,在第1密封膜17上以使与凸点电极16的上表面对应的位置上带有开口部19来形成第2密封膜18,所以代替以往的半腐蚀处理,通过丝网印刷法、光刻法等来形成第2密封膜18也可以,因此,能够使制造工序容易。By grinding the upper surface side of the
图6是表示图1所示的半导体器件的变形例的放大剖面图。在该变形例中,将第2密封膜18上形成的开口部19的尺寸(平面尺寸)比凸点电极16的尺寸(平面尺寸)形成得大一圈,由此,即使有对准线偏差,焊料球20的整体也能够可靠地接触凸点电极。为了降低开口部19内形成的焊料球20的内部应力,可以将开口部19的侧面形成向上方扩大的倾斜状。在图6的情况下,第2密封膜18上形成的开口部19的尺寸比凸点电极16大,并且其侧面为向上方扩大的倾斜状,但开口部19的侧面与图1的情况同样,也可以大致垂直。此外,与图1同样,也可以使开口部19的尺寸与凸点电极16的尺寸大致相同,使其侧面为向上方扩大的倾斜状。也可以在第1密封膜17和凸点电极16上将第2密封膜18以完整形状成膜后,照射激光来形成开口部19。6 is an enlarged cross-sectional view showing a modified example of the semiconductor device shown in FIG. 1 . In this modified example, the size (planar size) of the
(第2实施例)(second embodiment)
图7是表示本发明第2实施例的半导体器件的放大剖面图。该实施例中的与第1实施例的不同点在于,密封膜21为一层。凸点电极16的上表面处于比该一层的密封膜21的上表面低的位置。下面说明该第2实施例的半导体器件的制造方法。凸点电极16如下形成:在具有连接焊盘12、绝缘膜13、再布线15的半导体衬底11的上表面上形成光致抗蚀剂膜,通过光刻法在形成光致抗蚀剂膜的凸点电极16的位置形成开口部(未图示光致抗蚀剂),接着,通过电镀法等来形成凸点电极16,然后,在除去光致抗蚀剂膜后,对凸点电极16的上表面进行研磨来使各凸点电极16的高度均匀,接着,通过递模法、分配法、浸渍法、印刷法等来形成膜厚度比凸点电极16厚的密封膜21(因此,这种情况下的密封膜的厚度为将图1和图6中的第1密封膜17的厚度和第2密封膜18的厚度相加所得的厚度),随后,根据需要,在对该密封膜的上表面进行研磨并进行平坦化处理后,对密封膜照射激光,形成露出凸点电极16的开口部19。此后的工序与第1实施例相同。如图6所示,在第2实施例的情况下,也可以使开口部19的大小(平面尺寸)比凸点电极16的尺寸大,以向上方扩大的倾斜状来形成侧面。Fig. 7 is an enlarged cross-sectional view showing a semiconductor device according to a second embodiment of the present invention. The difference between this embodiment and the first embodiment is that the sealing
在上述各实施例中,也可以通过电镀法、溅射法、印刷法等来形成厚度大致相同的低熔点金属层,代替凸点电极16的焊料球20。这样的焊料球或低熔点金属层也可以形成在装载半导体器件的电路衬底的连接端子上,而不形成在半导体器件上。在上述实施例中,在第1密封膜17上,在形成与凸点电极16的上表面对应的部分上形成了开口部19的第2密封膜18后,立即在开口部19内和其上侧形成焊料球20,但在凸点电极19的表面被氧化的情况下,也可以在进行湿式腐蚀或干式腐蚀来实施凸点电极19的上表面的氧化膜除去处理,并在进行用于防止产生氧化膜的镀镍等的金属层形成处理后,形成焊料球20。金属层形成处理例如是实施镀镍处理。在进行了氧化膜除去处理的情况下,凸点电极16的高度即使多少有些降低,但其量很小,仍可获得与第1密封膜实质上为同一平面的相同效果。第2密封膜18的开口部19的大小(平面尺寸)也可以比凸点电极16的上表面形状小一圈。在上述实施例中,也可以不形成焊料球20,而通过各向异性导电粘结剂与电路衬底的连接端子进行电连接来取代。In each of the above-mentioned embodiments, a low-melting-point metal layer having approximately the same thickness may be formed by electroplating, sputtering, printing, etc., instead of the
如以上说明,根据本发明,由于凸点电极的上表面处于比密封膜的上表面低的位置,所以对作用于凸点电极上形成的粘结剂界面上的应力具有缓和功能。此外,由于密封膜的开口部可以不用实施使凸点电极的高度偏差增大的腐蚀处理来形成,所以可以使凸点电极的高度均匀,并且高效率地生产。As described above, according to the present invention, since the upper surface of the bump electrode is located lower than the upper surface of the sealing film, it has a function of alleviating stress acting on the interface of the adhesive formed on the bump electrode. In addition, since the opening of the sealing film can be formed without performing an etching process that increases the variation in the height of the bump electrodes, the height of the bump electrodes can be made uniform and can be produced efficiently.
Claims (9)
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| JP077772/2001 | 2001-03-19 | ||
| JP2001077772A JP3767398B2 (en) | 2001-03-19 | 2001-03-19 | Semiconductor device and manufacturing method thereof |
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| CN1189939C true CN1189939C (en) | 2005-02-16 |
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| US (1) | US20020132461A1 (en) |
| JP (1) | JP3767398B2 (en) |
| KR (1) | KR100455404B1 (en) |
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254874A (en) * | 2007-01-31 | 2011-11-23 | 三洋电机株式会社 | Semiconductor module, mthod for manufacturing semiconductor module, and portable device |
| TWI623988B (en) * | 2013-09-03 | 2018-05-11 | Senju Metal Industry Co., Ltd. | Bump electrode, bump electrode substrate and manufacturing method thereof |
Families Citing this family (35)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3829325B2 (en) * | 2002-02-07 | 2006-10-04 | 日本電気株式会社 | Semiconductor element, manufacturing method thereof, and manufacturing method of semiconductor device |
| JP4126389B2 (en) * | 2002-09-20 | 2008-07-30 | カシオ計算機株式会社 | Manufacturing method of semiconductor package |
| KR100778597B1 (en) | 2003-06-03 | 2007-11-22 | 가시오게산키 가부시키가이샤 | Stackable Semiconductor Device and Method of Manufacturing the Same |
| JP4360873B2 (en) * | 2003-09-18 | 2009-11-11 | ミナミ株式会社 | Manufacturing method of wafer level CSP |
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| TWI278048B (en) | 2003-11-10 | 2007-04-01 | Casio Computer Co Ltd | Semiconductor device and its manufacturing method |
| JP3925809B2 (en) | 2004-03-31 | 2007-06-06 | カシオ計算機株式会社 | Semiconductor device and manufacturing method thereof |
| JP2006086378A (en) * | 2004-09-16 | 2006-03-30 | Denso Corp | Semiconductor device and manufacturing method thereof |
| US7390688B2 (en) | 2005-02-21 | 2008-06-24 | Casio Computer Co.,Ltd. | Semiconductor device and manufacturing method thereof |
| JP4458029B2 (en) * | 2005-11-30 | 2010-04-28 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
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| US7855452B2 (en) | 2007-01-31 | 2010-12-21 | Sanyo Electric Co., Ltd. | Semiconductor module, method of manufacturing semiconductor module, and mobile device |
| JP4506767B2 (en) * | 2007-02-28 | 2010-07-21 | カシオ計算機株式会社 | Manufacturing method of semiconductor device |
| JP2008294323A (en) * | 2007-05-28 | 2008-12-04 | Nec Electronics Corp | Semiconductor device and method for manufacturing semiconductor device |
| US7820543B2 (en) * | 2007-05-29 | 2010-10-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Enhanced copper posts for wafer level chip scale packaging |
| JP4708399B2 (en) * | 2007-06-21 | 2011-06-22 | 新光電気工業株式会社 | Electronic device manufacturing method and electronic device |
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| US7982311B2 (en) * | 2008-12-19 | 2011-07-19 | Intel Corporation | Solder limiting layer for integrated circuit die copper bumps |
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| US8264089B2 (en) | 2010-03-17 | 2012-09-11 | Maxim Integrated Products, Inc. | Enhanced WLP for superior temp cycling, drop test and high current applications |
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| CN120376535A (en) * | 2017-10-26 | 2025-07-25 | 新电元工业株式会社 | Semiconductor device with a semiconductor device having a plurality of semiconductor chips |
| WO2020110619A1 (en) * | 2018-11-27 | 2020-06-04 | リンテック株式会社 | Semiconductor device manufacturing method |
| CN109473405A (en) * | 2018-12-07 | 2019-03-15 | 华进半导体封装先导技术研发中心有限公司 | A fan-out wafer-level packaging structure with silicon etched through holes and method thereof |
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Family Cites Families (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5883435A (en) * | 1996-07-25 | 1999-03-16 | International Business Machines Corporation | Personalization structure for semiconductor devices |
| US6054376A (en) * | 1997-12-31 | 2000-04-25 | Intel Corporation | Method of sealing a semiconductor substrate |
| US6261944B1 (en) * | 1998-11-24 | 2001-07-17 | Vantis Corporation | Method for forming a semiconductor device having high reliability passivation overlying a multi-level interconnect |
| JP3756689B2 (en) * | 1999-02-08 | 2006-03-15 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
| US6495916B1 (en) * | 1999-04-06 | 2002-12-17 | Oki Electric Industry Co., Ltd. | Resin-encapsulated semiconductor device |
| JP3446825B2 (en) * | 1999-04-06 | 2003-09-16 | 沖電気工業株式会社 | Semiconductor device and manufacturing method thereof |
-
2001
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Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102254874A (en) * | 2007-01-31 | 2011-11-23 | 三洋电机株式会社 | Semiconductor module, mthod for manufacturing semiconductor module, and portable device |
| TWI623988B (en) * | 2013-09-03 | 2018-05-11 | Senju Metal Industry Co., Ltd. | Bump electrode, bump electrode substrate and manufacturing method thereof |
Also Published As
| Publication number | Publication date |
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| JP3767398B2 (en) | 2006-04-19 |
| KR100455404B1 (en) | 2004-11-06 |
| US20020132461A1 (en) | 2002-09-19 |
| KR20020074400A (en) | 2002-09-30 |
| TW554453B (en) | 2003-09-21 |
| CN1375869A (en) | 2002-10-23 |
| JP2002280485A (en) | 2002-09-27 |
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