CN118964817B

CN118964817B - Spirman simple correlation coefficient solving method and field programmable gate array operation circuit

Info

Publication number: CN118964817B
Application number: CN202410995688.5A
Authority: CN
Inventors: 徐维超; 陶雨; 黄永健
Original assignee: Guangdong University of Technology
Current assignee: Guangdong University of Technology
Priority date: 2024-07-24
Filing date: 2024-07-24
Publication date: 2025-10-17
Anticipated expiration: 2044-07-24
Also published as: CN118964817A

Abstract

The application relates to a method for solving a simple and quick correlation coefficient of Szechwan, which comprises the steps of adopting a field programmable gate array arithmetic circuit to realize the quick solving of the simple and quick correlation coefficient of Szechwan, simplifying the simple and quick correlation coefficient of Szechwan to obtain a quick version thereof, thereby simplifying the field programmable gate array arithmetic hardware circuit designed based on the simple and quick correlation coefficient of Szechwan, accelerating the arithmetic speed, solving the simple and quick correlation coefficient of Szechwan by a parallel calculation mode based on the field programmable gate array, further shortening the calculation time and achieving the aim of solving the simple and quick correlation coefficient of Szechwan in real time.

Description

Spirman simple correlation coefficient solving method and field programmable gate array operation circuit

Technical Field

The invention relates to the field of data processing, in particular to a Szelman simple correlation coefficient solving method and a field programmable gate array arithmetic circuit.

Background

The statistical signal processing, which extends from the field of signal processing, is an important research field at present, and in the statistical signal processing, analysis of the correlation between two sets of data is also becoming a research hotspot of students. Correlation analysis (Correlation Analysis) was a subject of research developed over a century with the creation of statistical disciplines, and has been widely used in various scientific and technical fields. The correlation coefficient is a specific measure of the strength of a linear relationship between two random variables in a quantitative correlation analysis, provided that one of the two random variables is positively correlated when it increases (decreases) as the other increases (decreases), whereas when one of the two random variables is decreases (increases) as the other increases (decreases), the two random variables are negatively correlated, the strength of the relationship varying in degree based on the value of the correlation coefficient. In many related fields such as signal processing and statistics, correlation coefficients have become a common method for quantifying the strength of statistical relationships between random variables. The Pearson product moment correlation coefficient (Pearson's Product Moment Correlation Coefficient, PPMCC) proposed by the creator Karl Pearson of the mathematical statistics, the Spearman rank order correlation coefficient (Spearman's rho, SR) proposed by the statistician Spearman, and the kendelian rank order correlation coefficient (Kendall's tau, KT) proposed by the psychologist Kendall are the three most used correlation coefficients currently under theoretical research and practical application. The statistics person Fisher proves that PPMCC is the optimal progressive unbiased estimation of the matrix correlation coefficient when the sample obeys binary normal distribution, the statistical property is very complete, the operation time complexity is low, the operation efficiency is high, the real-time requirement can be met, and PPMCC has the advantages, so that the method has dominant role in both theoretical research and practical application. However, in practical applications, the collected data is not necessarily free from noise interference, especially impulse noise, such as low-frequency atmospheric noise, electromagnetic interference generated by lightning storms in nature, artificial noise, and interference noise generated by electronic devices, and PPMCC is very sensitive to noise in samples. When there is impulse noise in the sample, the performance of PPMCC will drop sharply or even fail completely, and SR and KT are less sensitive to non-normal distribution in the sample and have a certain robustness to impulse noise because only the ordering information of the sample, i.e. the rank information, is used.

The Spearman' sfootrule, SF correlation coefficient has relatively few studies and applications relative to the three classical correlation coefficients described above. The spearman simple correlation coefficient is a natural attribute for measuring the manhattan distance between two sets of rank variables, and depends on the rank information of the samples, so that the spearman simple correlation coefficient has certain robustness to impulse noise like the SR and KT. The relevant literature has demonstrated that the performance of the spearman short-cut correlation coefficient under certain conditions is superior to SR and KT, while the calculation of SF is based on the absolute specification 100002, 2023.03 value of the difference of the sample ordering information, which also makes the calculation of spearman short-cut correlation coefficients more simple and efficient than SR and KT.

Due to the advantages of simplicity, robustness, natural properties of SF and the like, SF has been newly discovered and applied to multiple research fields of genetics, information retrieval and the like, and therefore the implementation of SF quick solution has a certain practical significance. In the prior art, a CPU is often adopted to calculate and solve the simple and direct correlation coefficient of the Szechwan, but the CPU is mainly adopted in a serial calculation mode, so that the calculation and the solution of the simple and direct correlation coefficient of the Szechwan are limited by the limitation of serial operation, and the calculation and the solution of the simple and direct correlation coefficient of the Szechwan by the CPU are time-consuming.

In summary, the method is suitable for calculating and solving the simple and direct correlation coefficient of the spearman by the CPU in the prior art, and the CPU is limited by the limitation of serial operation due to the serial calculation mode, so that the problem that the calculation and the solution of the simple and direct correlation coefficient of the spearman by the CPU are time-consuming is solved, and the inventor makes corresponding exploration in consideration of solving the problem.

Disclosure of Invention

The application aims to solve the problems and provide a spearman simple correlation coefficient solving method and a field programmable gate array arithmetic circuit.

In order to meet the purposes of the application, the application adopts the following technical scheme:

The Szelman simple correlation coefficient solving method provided by adapting to one of the purposes of the application comprises the following steps:

Step S10, inputting a signal X _i into a row and column storage block in a field programmable gate array operation circuit to obtain X ₁...X_i...X_n and X ₁...X_j...X_n, and completing first-level caching;

Step S20, inputting X ₁...X_i...X_n and X ₁...X_j...X_n obtained in the step S10 into a comparator array, finishing n ² comparison operations to obtain a _ij＝sign(x_i-x_j), and inputting the comparison operations into a pipeline to finish secondary cache;

Step S30, inputting a signal Y _i into a row and column storage block to obtain Y ₁…Y_i…Y_n and Y ₁…Y_j…Y_n, and completing first-level caching;

Step S40, inputting Y ₁…Y_i…Y_n and Y ₁…Y_j…Y_n obtained in the step S30 into a comparator array, finishing n ² times of comparison operation to obtain b _ij＝sign(y_i-y_j), and inputting the comparison result into a pipeline to finish secondary cache;

Step S50, inputting Y ₁…Y_i…Y_n obtained in the step S10 and Y ₁…Y_j…Y_n obtained in the step S3 into a comparator, completing n times of comparison operation to obtain c _i＝sign(x_i-y_i), and inputting the comparison result into a pipeline to complete secondary cache;

Step S60, step S20, step S40 and step S50

A _ij＝sign(X_i-X_j)、b_ij＝sign(Y_i-Y_j) and c _i＝sign(X_i-Y_i) are simultaneously input into the array multiply accumulator, under the control of the control unit, time-sharing is completedAnd

Step S70, step S60

Inputting the subtracter to finish

Step S80, step S70Inputting into divider to complete

Step S90, step S80

Inputting a subtracter to determine the Szelman simple correlation coefficient as follows:

And step 100, inputting the Speermann simple correlation coefficient obtained in the step 90 into a register to obtain an output result, wherein i, j=1.

Optionally, the step S60 includes:

Step S601, inputting a _ij＝sign(X_i-X_j)、b_ij＝sign(Y_i-Y_j) and c _i＝sign(X_i-Y_i) into corresponding multiplier arrays simultaneously, and under the control of a control unit, completing n ² times of parallel input multiplication operations in a time sharing manner to obtain sign (X _i-X_j)sign(X_i-Y_i) and sign (Y _i-Y_j)sign(X_i-Y_i);

step S602, input sign (X _i-X_j)sign(X_i-Y_i) and sign (Y _i-Y_j)sign(X_i-Y_i) obtained in step S601 into corresponding adders simultaneously, and complete n ² parallel input addition operations in a time-sharing manner to obtain And

The application provides a field programmable gate array arithmetic circuit suitable for another purpose, which is applied to the spearman simple correlation coefficient solving method, and comprises the following steps:

A comparator array for calculating a _ij and b _ij from signals X _i and Y _i;

a comparator for calculating c _i from signals X _i and Y _i;

Array multiply accumulator for computing

Subtracter for calculating T1-T2 and

A divider for calculating

Row and column memory blocks for serial register signals X _i and Y _i, which support block addressing;

A pipeline for temporarily storing intermediate operation results;

A control unit for timing controlling the array multiply accumulator;

a register for registering a final operation result;

The operation steps performed by signals X _i and Y _i after they are input into the FPGA operation circuit are:

step S1, inputting a signal X _i into a row and column storage block to obtain X ₁…X_i…X_n and X ₁…X_j…X_n, and completing first-level caching;

s2, inputting X ₁…X_i…X_n and X ₁…X_j…X_n obtained in the step S1 into a comparator array, finishing n ² comparison operations to obtain a _ij＝sign(x_i-x_j), and inputting the comparison operations into a pipeline to finish secondary cache;

Step S3, inputting a signal Y _i into a row storage block and a column storage block to obtain Y ₁…Y_j…Y_n and Y ₁…Y_j…Y_n, and completing first-level caching;

S4, inputting Y ₁…Y_i…Y_n and Y ₁…Y_i…Y_n obtained in the step S3 into a comparator array, finishing n ² times of comparison operation to obtain b _ij＝sign(y_i-y_j), and inputting the comparison result into a pipeline to finish secondary cache;

Step S5, inputting the X ₁…X_i…X_n obtained in the step S1 and the Y ₁…Y_j…Y_n obtained in the step S3 into a comparator, completing n times of comparison operation to obtain c _i＝sign(x_i-y_i), and inputting the comparison result into a pipeline to complete secondary cache;

Step S6, step S2, step S4 and step S5

Step S7, step S6

Inputting the subtracter to finish

Step S8, step S7

Inputting into divider to complete

Step S9, step S8

and step S10, inputting the Speermann simple correlation coefficient obtained in the step S9 into a register to obtain an output result, wherein i, j=1.

Optionally, the array multiply accumulator comprises:

A multiplier array for calculating a _ijc_i、b_ijc_i, wherein i, j=1..n;

adder for calculating

The operation performed by signals X _i and Y _i after input to the array multiply accumulator is as follows:

step S61, a _ij＝sign(X_i-X_j)、b_ij＝sign(Y_i-Y_j) and c _i＝sign(X_i-Y_i) are simultaneously input into corresponding multiplier arrays, and under the control of a control unit, n ² times of parallel input multiplication operations are completed in a time sharing mode, so that sign (X _i-X_j)sign(X_i-Y_i) and sign (Y _i-Y_j)sign(X_i-Y_i) are obtained;

Step S62, step S61, sign (X _i-X_j)sign(X_i-Y_i) and sign (Y _i-Y_j)sign(X_i-Y_i) are input into corresponding adders simultaneously, and n ² parallel input addition operations are completed in a time-sharing manner to obtain Wherein, i is a group of the total number, j=1..n.

Optionally, the field programmable gate array arithmetic circuit adopts a pipeline processing mode.

The application provides electronic equipment adapting to the other purpose, and the Szelman simple correlation coefficient solving method is applied.

A computer device adapted to another object of the present application comprises a memory and a processor, the memory storing a computer program implemented according to the method of any one of the above, the processor implementing a spearman's simple correlation coefficient solving method of any one of the above when executing the computer program.

A computer-readable storage medium adapted to another object of the present application stores a computer program implemented according to the method of any one of the above-mentioned claims in the form of computer-readable instructions, which when invoked by a computer, performs the steps comprised by the corresponding method.

Compared with the prior art, the application aims at the problems that the CPU calculates and solves the simple and direct correlation coefficient of the Szelman in the prior art, and the CPU is limited by the limitation of serial operation because the CPU mainly adopts a serial calculation mode, so that the CPU has time-consuming calculation and solving of the simple and direct correlation coefficient of the Szelman, and the application has the following beneficial effects:

firstly, the spearman simple and direct correlation coefficient solving method fully utilizes the high-performance parallel processing capability of a Field Programmable Gate Array (FPGA) arithmetic circuit, can further shorten the calculation time of the spearman simple and direct correlation coefficient, and realizes real-time and rapid signal correlation processing based on the spearman simple and direct correlation coefficient (SF);

Secondly, the pearson moment correlation coefficient basically fails in a pulse noise environment, while the spearman simple correlation coefficient (SF) is stable to pulse noise, and is simple and efficient in calculation compared with the correlation number between the spearman rank order correlation coefficient and the Kendall rank order correlation coefficient;

Thirdly, because the SF is time-consuming to solve by a CPU, the application adopts a Field Programmable Gate Array (FPGA) operation circuit to realize the quick solution of the Szechwan simple and fast correlation coefficient, and the Szechwan simple and fast correlation coefficient is simplified to obtain a quick version of the Szechwan simple and fast correlation coefficient, thereby simplifying the field programmable gate array operation hardware circuit designed based on the Szechwan simple and fast correlation coefficient, accelerating the operation speed, and solving the Szechwan simple and fast correlation coefficient by a parallel calculation mode based on the field programmable gate array, further shortening the calculation time and achieving the purpose of solving the Szechwan simple and fast correlation coefficient in real time.

Drawings

The foregoing and/or additional aspects and advantages of the application will become apparent and readily appreciated from the following description of the embodiments, taken in conjunction with the accompanying drawings, in which:

fig. 1 is an exemplary architecture of a spearman short-cut correlation coefficient solving method in an embodiment of the present application.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative only and are not to be construed as limiting the application.

As used herein, the singular forms "a", "an", "the" and "the" are intended to include the plural forms as well, unless expressly stated otherwise, as understood by those skilled in the art. It will be further understood that the terms "comprises" and/or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and/or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and/or groups thereof. It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements may also be present. Further, "connected" or "coupled" as used herein may include wirelessly connected or wirelessly coupled. The term "and/or" as used herein includes all or any element and all combination of one or more of the associated listed items.

The various embodiments of the present application to be disclosed herein, unless the plain text indicates a mutually exclusive relationship with each other, the technical features related to the various embodiments may be cross-combined to flexibly construct a new embodiment as long as such combination does not depart from the inventive spirit of the present application and can satisfy the needs in the art or solve the deficiencies in the prior art. This variant will be known to the person skilled in the art.

Referring to fig. 1, in one embodiment of the spearman simple correlation coefficient solving method of the present application, a field programmable gate array arithmetic circuit is applied, including:

Step S10, inputting a signal X _i into a row and column storage block in a field programmable gate array operation circuit to obtain X ₁…X_i…X_n and X ₁…X_j…X_n, and completing first-level caching;

Step S20, inputting X ₁…X_i…X_n and X ₁…X_j…X_n obtained in the step S10 into a comparator array, finishing n ² comparison operations to obtain a _ij＝sign(x_i-x_j), and inputting the comparison operations into a pipeline to finish secondary cache;

Step S50, inputting the X ₁…X_i…X_n obtained in the step S10 and the Y ₁…Y_j…Y_n obtained in the step S3 into a comparator, completing n times of comparison operation to obtain c _i＝sign(x_i-y_i), and inputting the comparison result into a pipeline to complete secondary cache;

Step S60, step S20, step S40 and step S50

Step S70, step S60

Inputting the subtracter to finish

Step S80, step S70

Inputting into divider to complete

Step S90, step S80

Further, the step S60 includes:

In some embodiments, in practical applications, many signal processing tasks require detection of signals under noise interference. The signal detection problem under single channel impulse noise is typically modeled as follows:

X[i]=θY[i]+Z[i],

Wherein Y [ i ] is a known transmission signal not interfered by noise, θ is an attenuation coefficient representing a signal with (θ+.0) or without (θ=0), Z [ i ] is impulse noise, and X [ i ] is a reception signal interfered by noise;

Order the Representing a received signal of length n in the system model X [ i ] =thetay [ i ] +z [ i ],Representing a known transmitted signal that is not disturbed by noise,Representing noise;

sequences are sequenced Sequentially arranging the sequences from small to large according to the amplitude to obtain a group of new sequence statistical data sequences X ₁＜L＜X_n, wherein X _j is assumed to be positioned in the sequencesThe k-th position of (b) is defined as the rank order of the number k being X _j, denoted as P _j. The rank order of Y _j is similarly defined as Q _j.

The Spearman's footrule, SF correlation coefficient is defined as follows:

Definition of the definition P _i is the ordering of the signals X _i, i.eQ _i is the ordering of the signals Y _i, i.eThe sign function sgn (·) can be expressed as sgn (·) =2h (·) -1, where H (t) is defined asThus U can be expressed as:

Based on the relationship between rank and empirical cumulative distribution function, AndThe method can obtain the following steps:

therefore, according to the law of large numbers, AndConverging on F _X (t) =Φ (t) and F _Y (t) =Φ (t), respectively, when n goes to infinity:

Substituting formula (4) into formula (2) can yield an approximate expression of U:

The spearman short-cut correlation coefficient (SF) can be approximated as:

substituting formula (4) into formula (2) by The relation of sgn (·) =2h (·) -1 reduces U to obtain formula (7):

Wherein, i is a group of the total number, j=1..n.

Substituting formula (7) into formula (6) can obtain a rapid version of the spearman short-cut correlation coefficient (SF):

In some embodiments, in order to effectively illustrate the accuracy of the approximate version spearman short-cut correlation coefficient provided by the invention, the approximate version spearman short-cut correlation coefficient and the original version spearman short-cut correlation coefficient provided by the invention are compared through a Monte Carlo experiment, and the specific experimental design is as follows:

The attenuation coefficient θ=0.5, y _i is a known definite input signal, obeys a standard normal model N (0, 1), and the impulse noise Z _i is generated by a mixed gaussian model Z to (1-epsilon) N (0, sigma ₁)+εN(0,σ₂), wherein epsilon=0.05 represents the probability that the impulse component occurs in the whole impulse noise environment, and sigma ₂＝100＞＞σ₁ =1 represents the standard deviation of the impulse component.

The number of Monte Carlo experiments is 1000, the purpose of the experiments is to verify the unbiasedness of the simple and direct correlation coefficient of the approximate version of the Szelman provided by the invention to the simple and direct correlation coefficient of the original version of the Szelman, and the related experimental data are shown in Table 1:

TABLE 1 data relating to experiments

Signal length n	E(r_ASF)-E(r_SF)
		100	0.0155
150	0.0124
		200	0.0107
250	0.0095
		300	0.0089
350	0.0084
		400	0.0082
450	0.0078
		500	0.0076
550	0.0075
		600	0.0073
650	0.0072
		700	0.0071
750	0.0070
		800	0.0069

The experimental result shows that the deviation of the two coefficients is gradually reduced along with the increase of the signal length, which shows that the simple correlation coefficient of the approximate version of the Szechwan is gradually unbiased relative to the simple correlation coefficient of the original version of the Szechwan, and when the signal length is large enough, the simple correlation coefficient (SF) of the original version of the Szechwan can be well estimated.

In some embodiments, in order to effectively explain the reliability of the rapid solution method for the spearman short-cut correlation coefficient provided by the invention, the rapid version of the spearman short-cut correlation coefficient and the approximate version of the spearman short-cut correlation coefficient provided by the invention are compared through a Monte Carlo experiment, and the specific experimental design is as follows:

Y _i is a known deterministic input signal, obeys a standard normal model N (0, 1), and the impulse noise Z _i is generated from a mixed gaussian model Z to (1-epsilon) N (0, sigma ₁)+εN(0,σ₂), where epsilon=0.05 represents the probability that the impulse component occurs throughout the impulse noise environment, and sigma ₂＝100＞＞σ₁ =1 represents the standard deviation of the impulse component.

The Monte Carlo experiment times are set to 1000 times, and the experiment purpose is to verify the unbiasedness of the simplified approximate version of the Szelman simple correlation coefficient by the fast version of the Szelman simple correlation coefficient under different attenuation coefficients. Comparative experimental data are shown in table 2:

Table 2 comparative experimental data

Attenuation coefficient theta	SF	ASF	SF of the invention
				0	0.0005±5.89e^-4	0.0015±5.94e^-4	0.0015±5.94e^-4
0.1	0.0559±5.95e^-4	0.0570±6.00e^-4	0.0570±6.00e^-4
				0.2	0.1104±6.04e^-4	0.1116±6.10e^-4	0.1116±6.10e^-4
0.3	0.1649±6.07e^-4	0.1665±6.17e^-4	0.1665±6.17e^-4
				0.4	0.2186±5.86e^-4	0.2209±6.05e^-4	0.2209±6.05e^-4
0.5	0.2701±4.79e^-4	0.2738±5.01e^-4	0.2738±5.01e^-4
				0.6	0.3162±4.98e^-4	0.3220±5.35e^-4	0.3220±5.35e^-4
0.7	0.3604±4.57e^-4	0.3694±5.10e^-4	0.3694±5.10e^-4
				0.8	0.4002±3.55e^-4	0.4135±4.15e^-4	0.4135±4.15e^-4
0.9	0.4377±3.17e^-4	0.4567±3.95e^-4	0.4567±3.95e^-4

The data in table 2 shows the "mean ± standard deviation" of multiple monte carlo experiments. Experimental results show that when the environmental noise is single-channel impulse noise, the method has the same excellent robustness to the impulse noise interference as the original version of the Szelman simple correlation coefficient, and meanwhile, the method for rapidly solving the Szelman simple correlation coefficient has excellent unbiasedness compared with the approximate version of the Szelman simple correlation coefficient, and can well estimate the original version of SF.

Compared with the prior art, the application aims at the problems that the CPU calculates and solves the simple and direct correlation coefficient of the Szelmann in the prior art, and the CPU mainly adopts a serial calculation mode and is limited by the limitation of serial operation, so that the CPU has time-consuming calculation and solving of the simple and direct correlation coefficient of the Szelmann, and the application has the following advantages that:

On the basis of any of the above embodiments, a field programmable gate array (fpga) operation circuit for rapidly solving a spearman simple correlation coefficient (SF) according to another aspect of the present application, the operation of which adopts a pipeline processing manner, is applied to the spearman simple correlation coefficient solving method described in any of the above embodiments, and includes:

A comparator array for calculating a _ij and b _ij from signals X _i and Y _i;

a comparator for calculating c _i from signals X _i and Y _i;

Array multiply accumulator for computing

Subtracter for calculating T1-T2 and

A divider for calculating

A pipeline for temporarily storing intermediate operation results;

A control unit for timing controlling the array multiply accumulator;

a register for registering a final operation result;

Step S3, inputting a signal Y _i into a row storage block and a column storage block to obtain Y ₁…Y_i…Y_n and Y ₁…Y_j…Y_n, and completing first-level caching;

S4, inputting Y ₁…Y_i…Y_n and Y ₁…Y_j…Y_n obtained in the step S3 into a comparator array, finishing n ² times of comparison operation to obtain b _ij＝sign(y_i-y_j), and inputting the comparison result into a pipeline to finish secondary cache;

Step S6, step S2, step S4 and step S5

Step S7, step S6

Inputting the subtracter to finish

Step S8, step S7

Inputting into divider to complete

Step S9, step S8

Optionally, the array multiply accumulator comprises:

A multiplier array for calculating a _ijc_i、b_ijc_i, wherein i, j=1..n;

adder for calculating

In some embodiments, the FPGA (Field-Programmable gate array) is an FPGA (Field Programmable gate array) and the FPGA is a semi-custom integrated circuit, which has abundant logic resources and high-performance mathematical operation modules, such as multipliers and adders, so that the FPGA can implement fast parallel operation. The programmability of the internal logic determines the flexibility of the designed circuit structure, so that the FPGA can be used for designing and realizing a real-time and high-dynamic centralized complex mathematical operation circuit.

The application also provides electronic equipment, and the method for solving the Szelman simple correlation coefficient is applied.

The application also provides a computer device, which comprises a memory and a processor, wherein the memory stores a computer program realized by the method according to any one of the above, and the processor realizes the method for solving the Szelman simple correlation coefficient according to any one of the above when executing the computer program.

The application also proposes a computer-readable storage medium storing in the form of computer-readable instructions a computer program implemented according to the method of any one of the above, which when invoked by a computer, performs the steps comprised by the corresponding method.

The foregoing is only a partial embodiment of the present application, and it should be noted that it will be apparent to those skilled in the art that modifications and adaptations can be made without departing from the principles of the present application, and such modifications and adaptations are intended to be comprehended within the scope of the present application.

In summary, compared with the prior art, the application aims at the problems that the CPU calculates and solves the simple and direct correlation coefficient of the Szelman in the prior art, and the CPU is limited by the limitation of serial operation due to the serial calculation mode, so that the CPU has time-consuming calculation and solving of the simple and direct correlation coefficient of the Szelman, and the application has the following advantages that:

Claims

1. A Szelman simple correlation coefficient solving method is characterized by comprising the following steps:

Step S50, inputting the X ₁…X_i…X_n obtained in the step S10 and the Y ₁…Y_j…Y_n obtained in the step S30 into a comparator, completing n times of comparison operation to obtain c _i＝sign(x_i-y_i), and inputting the comparison result into a pipeline to complete secondary cache;

Step S60, step S20, step S40 and step S50

Step S70, step S60Inputting the subtracter to finish

Step S80, step S70Inputting into divider to complete

Step S90, step S80

2. The spearman short-cut correlation coefficient solving method according to claim 1, wherein the step S60 includes:

3. A field programmable gate array arithmetic circuit applied to the spearman simple correlation coefficient solving method according to any one of claims 1 to 2, characterized by comprising:

A comparator array for calculating a _ij and b _ij from signals X _i and Y _i;

a comparator for calculating c _i from signals X _i and Y _i;

Array multiply accumulator for computing

Subtracter for calculating T1-T2 and

A divider for calculating

A pipeline for temporarily storing intermediate operation results;

A control unit for timing controlling the array multiply accumulator;

a register for registering a final operation result;

step S6, inputting a _ij＝sign(X_i-X_j)、b_ij＝sign(Y_i-Y_j) and c _i＝sign(X_i-Y_i) obtained in step S2, step S4 and step S5 into the array multiplication accumulator at the same time, under the control of the control unit, completing time sharing And

Step S7, step S6

Inputting the subtracter to finish

Step S8, step S7

Inputting into divider to complete

Step S9, step S8

4. A field programmable gate array arithmetic circuit as defined in claim 3, wherein said array multiply accumulator comprises:

A multiplier array for calculating a _ijc_i、b_ijc_i, wherein i, j=1..n;

adder for calculating

Step S62, step S61, sign (X _i-X_j)sign(X_i-Y_i) and sign (Y _i-Y_j)sign(X_i-Y_i) are input into corresponding adders simultaneously, and n ² parallel input addition operations are completed in a time-sharing manner to obtain AndWherein, i is a group of the total number, j=1..n.

5. A field programmable gate array arithmetic circuit as claimed in claim 3, wherein the field programmable gate array arithmetic circuit is pipelined.

6. An electronic device characterized by applying the spearman short-cut correlation coefficient solving method according to any one of claims 1 to 2.

7. A computer device comprising a memory storing a computer program implemented in accordance with the method of any one of claims 1 to 2 and a processor implementing a spearman's simple correlation coefficient solving method of any one of claims when the computer program is executed.

8. A computer-readable storage medium, characterized in that it stores in the form of computer-readable instructions a computer program implemented according to the method of any one of claims 1 to 2, which, when invoked by a computer, performs the steps comprised by the corresponding method.