CN118944810A

CN118944810A - Timing-level lightweight FC downlink processing engine

Info

Publication number: CN118944810A
Application number: CN202410989585.8A
Authority: CN
Inventors: 余锋; 邢钱舰; 张千隆
Original assignee: Zhejiang University ZJU
Current assignee: Zhejiang University ZJU
Priority date: 2024-07-23
Filing date: 2024-07-23
Publication date: 2024-11-12

Abstract

The invention discloses a timing-stage light-weight FC downlink processing engine, which comprises: the data encapsulation module encapsulates the control information or data in the AXIS format into an FC frame according to an FC protocol; a sending control module, which sends FC primitive or FC frame; the word validity judging and primitive detecting module is used for judging the validity of the transmission word and detecting various frame delimiters and primitive signals; the receiving control module deduces an FC frame according to the frame delimiter for the decoded data and carries out error detection on the received FC frame; the data analysis module analyzes the received FC frame, extracts head information and restores the FC frame into AXIS format data; the data encoding and decoding module adopts different encoding modes to encode and decode the transmitted and received data according to the encoding requirements under different line rates. The timing-stage light-weight FC downlink processing engine of the invention is a simplex transmission mode, supports non-standard linear rate, supports two coding modes, has multiple error detection mechanisms and ensures correct receiving and transmission of data.

Description

Timing-level lightweight FC downlink processing engine

Technical Field

The invention belongs to the field of network technology and FPGA, and particularly relates to a timing-stage light-weight FC downlink processing engine.

Background

The Fibre Channel (FC) protocol is a high-speed high-performance transport protocol defined between computers and I/O devices, and is an open network technology with high bandwidth, strong real-time, and high reliability. Similar to the generic OSI model, fibre channel also employs a hierarchical structure, which can be divided into FC-0, FC-1, FC-2, FC-3, FC-4 layers. At the same time, fibre channel provides a mapping of the various upper layer protocols that are grouped into ULPs layers.

Currently, fibre channel technology has been widely used in the commercial field and provides support for unified network construction for the next generation of avionics systems. The mainstream fibre channel rate at present is 2G, 4G, 8G and 16G, and the sixth generation fibre channel protocol provides the fibre channel protocol specification based on the 32G and 128G rate standards of 256B/257B codes, and simultaneously introduces mechanisms such as forward error correction coding, link training and the like to ensure the reliability of data under high-speed data transmission. However, when the method is applied to some special situations, such as data/instruction transmission, the data transmission mode is required to be simplex transmission mode, and the fiber channel rate is non-standard line rate, and the corresponding processing engine needs to be customized for such special application situations.

Disclosure of Invention

The invention provides a timing-stage light-weight FC downlink processing engine which solves the technical problems, and specifically adopts the following technical scheme:

a timing-stage lightweight FC downlink processing engine, comprising: the device comprises a data encapsulation module, a transmission control module, a word effective judgment and primitive detection module, a receiving control module, a data analysis module and a data encoding and decoding module;

The data packaging module is used for receiving AXIS format control or pulse data transmitted by an upper layer, packaging the AXIS format control or pulse data into an FC frame according to an FC protocol, performing CRC-12 check on FC_ASM header information in the FC_ASM frame, filling a check result into the low 12 bits of a Reserved field in the FC_ASM header, and packaging the AXIS format data according to an FC protocol standard;

the sending control module is used for sending FC primitives or FC frames;

The word validity judging and primitive detecting module is used for judging the validity of the transmission word and detecting various frame delimiters and primitive signals, and outputting primitive detecting results to the receiving control module;

The receiving control module is used for deducing an FC frame from the decoded data according to the frame delimiter, carrying out error detection on the received FC frame, and then outputting the FC frame to a subsequent module for processing;

The data analysis module is used for performing CRC-12 check on FC_ASM header information in the output data of the receiving control module, discarding the frame if a check error occurs, otherwise analyzing the related data content, and re-packaging the related data content into an axis data format;

the data encoding and decoding module adopts different encoding modes to encode and decode the receiving and transmitting data according to the encoding requirements under different linear rates.

Further, the data encapsulation module includes: the device comprises a data extraction module, a header CRC generation module and a data encapsulation sub-module;

The data extraction module is used for analyzing and extracting the axis interface data to obtain data, and writing the data into a cache;

The header CRC generation module is used for generating header information of the FC_ASM, carrying out CRC-12 checksum calculation on the header information of the FC_ASM, and filling the checksum into a Reserved field of the ASM header;

and the data encapsulation submodule encapsulates the data into FC frames according to the FC protocol standard.

Further, the sending control module sends primitive signals according to the primitive signal effective marks according to the indication of the sending control state machine, and transmits FC frames or idle filling words under the other conditions;

The sending control module has the following transmission priority, primitive signal > FC frame > idle filling word;

The sending control module also has a cyclic redundancy check code generating function, calculates cyclic redundancy check codes from a frame start delimiter to a last 4-byte data load during FC frame transmission, and inserts the cyclic redundancy check codes before an end of frame delimiter;

The transmission control module also matches the corresponding transmission word type code for the subsequent 64B/66B encoding according to the type of the current transmission word.

Further, the transmission control module has a frame scrambling function, and when the subsequent encoding is 8B/10B encoding, the transmission control module scrambles a data payload portion from a start of frame delimiter to an end of frame delimiter.

Further, the word validity judging and primitive detecting module judges the validity of the transmission word and the primitive signal according to the transmission word validity judging criterion and the primitive signal detecting criterion, then respectively identifies the code words according to the four bytes of the transmission number to infer whether the current transmission word is a data transmission word, a frame delimiter or a primitive signal, and outputs a corresponding indication signal to the receiving control module for use.

Further, the receiving control module judges the FC frame according to the frame delimiter, and sequentially detects the frame end delimiter loss, the ultralong/ultrashort frame detection and the cyclic redundancy check code error detection, and marks different types of errors through the mark signal.

Further, the frame end delimiter loss detection analyzes the abnormal situation of 'frame data is followed by FC control word/filling word', if such abnormal situation occurs, the frame end delimiter is inserted immediately, and the 1 st bit of the sign signal is used for identifying the abnormal situation;

The ultra-long/ultra-short frame detection analyzes abnormal conditions that the frame length is more than 2148 bytes or less than 36 bytes, cuts off the current frame immediately after the ultra-long frame, inserts a frame abnormal end delimiter, and marks the ultra-long frame condition by using the 3 rd bit of the marking signal; for the ultra-short frame, marking the condition of the ultra-short frame by using the 2 nd bit of the marking signal;

And the error detection of the cyclic redundancy check code analyzes the abnormal condition that the cyclic redundancy check code check result is matched with the check code field in the transmission word, and the 0 th bit of the marking signal is used for marking.

Further, the receiving control module has a frame descrambling function, and when the encoding mode is 8B/10B encoding, the receiving control module descrambles a data load part between a start frame delimiter and an end frame delimiter of the received FC frame.

Further, the data parsing module is configured to parse the received FC protocol data, encapsulate the FC protocol data into axi format data, and perform CRC-12 check on the header information of the fc_asm, and discard the FC frame that fails the check;

the data parsing module calculates the current data length, truncates the current data when the data length is greater than or equal to 2048B, and writes the data information into the data information FIFO.

Further, the data encoding and decoding module includes: a transport word segmentation module, a transport word reassembly module, a 64b/66b encoding module, a 64b/66b decoding module, a scramble module, and a descramble module;

The transmission word segmentation module is used for carrying out bit sequence adjustment on data sent to the high-speed serial transceiver when the coding scheme uses 8b/10b coding, transmitting K code information and calculating a frame RD value from a frame start delimiter to a CRC end;

The transmission word reorganizing module is used for carrying out bit sequence adjustment on data received from the high-speed serial transceiver, and if the data K code after the bit sequence adjustment does not appear in the 1 st byte, the data is translated according to the Comma position indication signal so that the K code is fixed in the 1 st byte, and FC transmission words are formed and input into the receiving clock isolation FIFO;

The 64b/66b coding module is used for combining two FC transmission words, carrying out 64b/66b coding according to transmission word type codes, scrambling coded data and outputting the scrambled data to the high-speed serial transceiver;

The 64b/66b decoding module is used for synchronizing the data received by the high-speed serial transceiver according to the synchronization head, then descrambling the data, and completing 64b/66b decoding of the descrambled data according to the information of the synchronization head, the type field, the control code and the like;

the scramble module scrambles the data after 64B/66B coding, and the randomness of the data is increased;

And the descramble module descrambles the parallel data received by the GTH to recover the original data.

The timing-stage light-weight FC downlink processing engine provided by the invention is a simplex transmission mode, supports a non-standard linear rate, supports two coding modes, has multiple error detection mechanisms and ensures correct receiving and transmission of data.

Drawings

In order to more clearly illustrate the embodiments of the application or the technical solutions of the prior art, the drawings which are used in the description of the embodiments or the prior art will be briefly described, it being obvious that the drawings in the description below are only some embodiments of the application, and that other drawings can be obtained according to these drawings without inventive faculty for a person skilled in the art.

FIG. 1 is a schematic diagram of a timing-stage lightweight FC downlink processing engine of the present invention;

FIG. 2 is a schematic diagram of a data encapsulation module structure of a timing-level lightweight FC downlink processing engine according to the present invention;

FIG. 3 is a schematic diagram of a transmission control module of a timing-level lightweight FC downlink processing engine according to the present invention;

FIG. 4 is a transmission frame data read state machine transition diagram of a timing level lightweight FC downlink processing engine of the present invention;

FIG. 5 is a schematic diagram of a frame scrambling module of a timing level lightweight FC downlink processing engine according to the present invention;

FIG. 6 is a schematic diagram of a word valid decision and primitive detection function of a timing-level lightweight FC downlink processing engine according to the present invention;

FIG. 7 is a schematic diagram of a timing-level lightweight FC downlink processing engine according to the present invention;

FIG. 8 is a schematic diagram of a data parsing module of a timing-level lightweight FC downlink processing engine according to the present invention;

fig. 9 is a schematic diagram of a codec module structure of a timing-stage lightweight FC downlink processing engine according to the present invention.

Detailed Description

Embodiments of the present application are described in detail below, examples of which are illustrated in the accompanying drawings, wherein like or similar reference numerals refer to like or similar elements or elements having like or similar functions throughout. The embodiments described below by referring to the drawings are illustrative and intended to explain the present application and should not be construed as limiting the application.

The "FC transport word" described in the present application refers to a basic unit of data transmission of the time-scale lightweight FC downlink engine, which is 4 bytes in length.

The FC-ASM frame described in the application is an FC frame used in an avionic environment and comprises an ASM extension header;

the "FC primitive" described in the present application refers to a series of FC transport words having a special meaning specified in the FC protocol, consisting of 1K code and 3D codes.

The "FC frame" described in the present application refers to a set of a start of frame delimiter (SOF, 4 bytes), an FC Header (FC Header,24 bytes), a data Payload (Payload, 0-2048 bytes), a cyclic redundancy check code (CRC, 4 bytes), and an end of frame delimiter (EOF, 4 bytes), which are basic units of FC protocol data link layer transmission.

The "CRC-12" described in the present application is a 12-bit cyclic redundancy check code with error detection and correction capabilities, filling the lower 12 bits of the Reserved field in the ASM header.

The "IDLE filler word" described in the present application refers to an IDLE primitive.

Fig. 1 is a schematic diagram showing the overall structure of a timing-stage lightweight FC downlink processing engine according to the present application. The timing-stage light-weight FC downlink processing engine is based on the FC protocol standard, and aims at the requirements of simplex no-flow control, non-standard linear rate and timing control integration, so that part of functions of FC-1 and FC-2 layers are simplified. Specifically, the timing-stage lightweight FC downlink processing engine includes: the device comprises a data encapsulation module, a transmission control module, a word effective judgment and primitive detection module, a receiving control module, a data analysis module and a data encoding and decoding module (comprising a data encoding module and a data decoding module). The data encapsulation module receives the AXIS format control or pulse data transmitted by the upper layer, encapsulates the AXIS format control or pulse data into an FC frame according to an FC protocol, performs CRC-12 check on an ASM_HEADER field in the FC frame, fills the low 12 bits of a RESERVED field in the ASM_HEADER with a check result, and then sends the result to the sending control module. The transmission control module transmits primitive signals or FC frames according to the indication of the transmission control state machine. If the subsequent code is 8B/10B code, scrambling the data before data transmission; if the subsequent code is a 64B/66B code, no scrambling is required. And then the data is encoded and then output to the high-speed serial transceiver to complete data transmission. And the receiving end of the other node decodes the parallel data received by the high-speed serial transceiver to obtain the FC transmission word. The word validity judging and primitive detecting module is mainly responsible for judging the validity of the transmitted word and detecting various frame delimiters and primitive signals, and outputting primitive detecting results to the receiving control module. Specifically, the word valid judgment and primitive detection module deduces an FC frame and a primitive signal according to the frame delimiter, and then enters the receiving control module to perform error detection. If the coding mode is 8B/10B coding, descrambling is needed at present and then data is input into a receiving control module; if the coding mode is 64B/66B coding, the data is directly input into the receiving control module. And extracting the content of the FC frame through a data analysis module, and packaging the FC frame into data in an AXIS format. And meanwhile, the CRC-12 check of the ASM_HEADER is finished, and if the check fails, the current frame is directly discarded. Specifically, the data analysis module is responsible for performing CRC-12 check on FC_ASM header information in the output data of the receiving control module, if a check error occurs, discarding the frame, otherwise, analyzing the related data content, and repackaging into an axis data format. The data encoding and decoding module adopts different encoding modes to encode and decode the transmitted and received data according to the encoding requirements under different line rates.

As shown in fig. 2, as a preferred embodiment, the data package module includes: the device comprises a data extraction module, a header CRC generation module and a data encapsulation sub-module. The data extraction module extracts data information from the AXIS format data transmitted by the upper layer application, and caches control information and data of the current data. The HEADER CRC generation module generates HEADER information for the FC_ASM and calculates CRC-12 padding to the RESERVED field for FC_ASM_HEADER. The data encapsulation sub-module reads the data information from the data cache and integrates the header information of the FC frame to form an FC frame which is sent to the sending control module.

The data extraction module extracts the AXIS format data, the data extraction state machine extracts the data according to tvalid, tready, tlast of AXIS, calculates the length of the current frame, judges whether the current frame is the first frame and the last frame of the sequence, and judges the current sequence number through tuser signals. And integrating all data information together and caching the data respectively.

The data packaging submodule packages data according to the FC protocol, the data reading state machine judges whether the current data information FIFO is empty, and if not, the data information is read, and the length of the current frame, the first frame mark of the sequence, the last frame of the sequence and the sequence number are obtained. Filling the corresponding fields of the FC frame header with the information, combining the data and the header information, sending the combined data and the header information to a sending control module for processing, and adding frame delimiters at the beginning and the end of the frame.

As shown in fig. 3, as a preferred embodiment, the transmission control module mainly implements the transmission of primitive signals and FC frames, and generates CRC-32, and scrambles the transmission frames under 8B/10B encoding. The sending frame data reading state machine and the sending control state machine in the sending control module work cooperatively, and the sending frame data reading module comprises the following steps according to the frame mark when the sending clock isolation FIFO is not full: the frame is valid, the start of frame delimiter, the end of frame delimiter reads the FC frame from the data encapsulation module. The transmission control state machine is responsible for controlling transmission of the transport words, and transmits an idle filling word transmission instruction in an idle state, and transmits a frame transmission instruction or a CRC filling instruction in the rest state. The CRC generator calculates a CRC-32 value starting from the start of frame delimiter to before the end of frame delimiter, filling in the 4 bytes before the end of frame delimiter. If the 8B/10B coding scheme is adopted, the data between the frame start delimiter and the frame end delimiter needs to be scrambled before the data is transmitted, so that the randomness of the data is increased, and the direct current balance of the data transmission is ensured.

And the sending control module sends primitive signals according to the primitive signal valid mark according to the indication of the sending control state machine, and transmits FC frames or idle filling words under the rest conditions. The transmit control module has the following transmission priority, primitive signal > FC frame > idle filler word. The transmission control module further has a cyclic redundancy check code generating function of calculating a cyclic redundancy check code from a start of frame delimiter to a last 4-byte data payload at the time of FC frame transmission and inserting the cyclic redundancy check code before an end of frame delimiter. The transmission control module also matches the corresponding transport word type code for the subsequent 64B/66B encoding based on the type of the current transport word.

As shown in fig. 4, the transmission frame data read state machine is composed of four states s_wait_sof, s_sof_reg, s_sof_reg2, s_wait_eof. And loading data when the transmission clock isolation FIFO buffer memory is enough, judging whether the current data is valid, if so, continuing to read the data, judging whether the data is SOF, and if so, entering an S_SOF_REG state. Judging whether the current effective data is SOF or not in the S_SOF_REG state, if so, indicating that the EOF loss needs to be inserted with an abnormal end-of-frame delimiter EOFa; and judging whether the current valid data is EOF, if so, returning to the S_WAIT_SOF state again to read the next frame. And sending a data transmission instruction by the waiting state machine in the S_SOF_REG2 state, and entering the S_WAIT_EOF state to start data transmission after the data transmission instruction is valid. And waiting for the arrival of a valid EOF in the S_WAIT_EOF state to finish reading a complete FC frame, and returning to the S_WAIT_SOF state to prepare for reading of the next frame after a frame is completely read.

The transmission control module further has a frame scrambling function, and when the subsequent encoding is 8B/10B encoding, the transmission control module scrambles a data payload portion from the start of frame delimiter to the end of frame delimiter. Specifically, as shown in fig. 5, a scrambling scheme for 64bit data is provided. The frame scrambling module in the transmission control module performs scrambling operation on the extended frame header, the load and the CRC part, wherein the scrambling principle is that shift exclusive-or operation is performed on data, and the formula is as follows: g (x) =x ⁵⁸+x³⁹ +1. The frame scrambling module consists of a feedback shift register (LSFR), a shifter (LFSRN) and two exclusive-or trees, and is used for inputting 64-bit parallel original data and outputting 64-bit parallel scrambling data. The frame scrambling function is implemented in two parts, the input 64-bit transmission word is divided into a high-order 32-bit transmission word and a low-order 32-bit transmission word, and then the input 64-bit transmission word and the corresponding feedback shift register are respectively subjected to exclusive-or operation, and taking low-order 32-bit data as an example, output data can be represented by the following logical relation:

dout[31]＝din[31]⊕lfsr[58]⊕lfsr[39]

dout[30]＝din[30]⊕lfsr[57]⊕lfsr[38]

……

dout[0]＝din[0]⊕lfsr[27]⊕lfsr[8]

The word validity judging and primitive detecting module judges the validity of the transmission word and the primitive signal according to the transmission word validity judging criterion and the primitive signal detecting criterion, then respectively identifies the code words according to the four bytes of the transmission number to deduce whether the current transmission word is a data transmission word, a frame delimiter or a primitive signal, and outputs corresponding indication signals to the receiving control module for use. As shown in fig. 6, as a preferred embodiment, the word validity judging and primitive detecting module first judges the validity of the transmission word, and the judging steps are as follows: (1) Judging the 4 bytes 8B/10B coding effectiveness of the current transmission word through the non_in_table and run_disparity_error signals, and further judging whether the transmission word is effective or not; (2) Judging whether the K code appears in bytes 2-4 or not through charisk signals, and if so, invalidating the transmission word; (3) whether K30.7 occurs through byte 1. The signal single word valid early is set to 1 when the transfer word is valid and the value of single word valid early is assigned to the single word valid o output in the next clock cycle. Then detecting frame delimiter and primitive signal, judging steps are as follows: (1) judging whether the byte 1 of the current transmission word is a K code or not; (2) determining whether the current transport word is valid; (3) Judging whether the current transmission word is an ordered set of a valid frame delimiter and primitive signals, and judging the type of the frame delimiter or the primitive signals to which the transmission word belongs. When it is recognized that byte 1 is a K code, the transfer word is recognized as a non-data transfer word, and the signal single word not data o is set to 1. When the transfer word is valid and is any one of SOFc1, SOFi2, SOFn2, SOFi3, SOFn3, single word sofc123_o is set to 1. When the transmission word is valid and is any one of EOFa, EOFni, EOFdti, single_word_invalid_ eof _o is set to 1, and the transmission word is determined to be the end-of-frame delimiter of the invalid frame.

And the receiving control module judges the FC frame according to the frame delimiter, sequentially detects the loss of the frame end delimiter, the ultra-long/ultra-short frame, and the error of the cyclic redundancy check code, and marks the errors of different types through the mark signal.

Specifically, the end-of-frame delimiter loss detection analyzes the abnormal condition of the frame data followed by the FC control word/filler word (except the end-of-frame delimiter), if such abnormal condition occurs, the end-of-frame delimiter is inserted immediately, and the 1 st bit of the flag signal is used for identifying the abnormal condition. Detecting and analyzing abnormal conditions of a frame length of more than 2148 bytes or less than 36 bytes by using an ultra-long/ultra-short frame, immediately cutting off a current frame after the ultra-long frame is ultra-long, inserting a frame abnormal end delimiter, and using a 3 rd bit of a marking signal to mark the condition of the ultra-long frame; for the ultrashort frame, the 2 nd bit of the sign signal is used to identify the ultrashort frame condition. And the abnormal condition that the cyclic redundancy check code error detection analyzes that the cyclic redundancy check code check result is matched with the check code field in the transmission word is identified by using the 0 th bit of the marking signal.

Specifically, as shown in fig. 7, as a preferred embodiment, the receiving control module is responsible for splitting the FC received transmission word into FC frames according to the word valid judgment and the frame delimiter flag output by the primitive detection module. The receiving control module has a frame descrambling function, and if the coding mode is 8B/10B coding, the receiving control module firstly descrambles the received data when the data enter the receiving control module, and the original data is recovered. Meanwhile, the receiving control module detects the conditions of invalid frames, ultra-long frames, ultra-short frames, CRC check errors and the like and marks the conditions through error indication marks. The receiving control module is cooperatively operated by a data path, a receiving control state machine 1 and a receiving control state machine 2, the data path segments FC receiving transmission words according to the indication of the receiving control state machine, the receiving control state machine 1 is responsible for judging and processing the frame start, and the receiving control state machine 2 is started through a start_assistant_fsm signal. The receiving control state machine is mainly responsible for judging and processing the end of the frame. For the case of very long frames or EOF loss, the receiving control module will truncate the current frame and add EOFni, the receiving control status module uses clientrxstatus _o signal to identify various error types, and clientrxstatus _o different bits represent different types of errors when clientrxstatusvalid _o is active: clientrxstatus _o0 is set to represent that CRC check errors occur in the current received frame; clientrxstatus _o1 sets the current received frame as an invalid frame; clientrxstatus _o2 sets the current received frame as an ultrashort frame; clientrxstatus _o4 set represents that the EOF of the currently received frame is lost or that the EOF is invalid.

The data analysis module is used for analyzing the received FC protocol data, encapsulating the FC protocol data into axi format data, performing CRC-12 check on the FC_ASM header information, and discarding FC frames with failed check. The data parsing module calculates the current data length, truncates the current data when the data length is greater than or equal to 2048B, and writes the data information into the data information FIFO.

As shown in fig. 8, as a preferred embodiment, the data parsing module is responsible for parsing the received FC frame, extracting data and frame information, and finally converting to an AXIS data stream. First, the header CRC check module performs CRC-12 check on ASM header fields in the received frame, and feeds back the check result to the data separation module. The data separation module judges the start of a received FC frame through an rx_begin_en signal, then starts counting the head, sequentially extracts a sequence end mark (last_sequence_mk), a sequence number (sequence_mk), a sequence first frame mark (first_frame_mk) and a sequence last frame mark (last_frame_mk) in the head of the received FC frame, and combines frame length information to form received frame information to be written into a frame information cache FIFO; writing data into the data cache FIFO is done by pulling rx_finish_en high for one complete frame process.

The control state machine in the FC packet group module judges whether effective frame information exists in the frame information cache FIFO, if not, one frame information is read, and according to different serial numbers in the frame information, different control codes are filled at the beginning of an AXIS data stream, and current sequence information is marked. The data in the data cache FIFO is then read continuously for transmission until after a complete FC sequence has been processed, a new control code is transmitted, identifying the start of the next sequence.

As shown in fig. 9, as a preferred embodiment, the data codec module includes: a transport word segmentation module, a transport word reassembly module, a 64b/66b encoding module, a 64b/66b decoding module, a scramble module, and a descramble module.

The transmission word segmentation module performs bit order adjustment of data transmitted to the high-speed serial transceiver, delivers K-code information, and calculates a frame RD value from a start of frame delimiter to a CRC end when the encoding scheme uses 8b/10b encoding. And the transmission word reorganizing module adjusts the bit sequence of the data received from the high-speed serial transceiver, and if the data K code after the bit sequence is adjusted does not appear in the 1 st byte, the data is translated according to the Comma position indication signal so that the K code is fixed in the 1 st byte, and the FC transmission word is formed and input into the receiving clock isolation FIFO. Each byte adopts 8B/10B coding mode to need 2bit additional data cost, 64B/66B coding only needs 2bit additional cost, and the effective bandwidth of the data is greatly improved.

And the transmission word reorganizing module is used for carrying out bit sequence adjustment on data received from the high-speed serial transceiver, and if the data K code after the bit sequence adjustment does not appear in the 1 st byte, the data is translated according to the Comma position indication signal so that the K code is fixed in the 1 st byte, and the FC transmission word is formed and is input into the receiving clock isolation FIFO.

The 64b/66b encoding module combines the two FC transport words, and performs 64b/66b encoding according to the transport word type code, and scrambles the encoded data, and then outputs to the high-speed serial transceiver. Specifically, the 64B/66B encoding module determines the type of the current transport word according to the transport word type code attached to each FC transport word by the transmission control module, and completes data encoding according to the FC protocol specification. The transmission word types mainly include the following: 1. a data transmission word; 2. IDLE fill word IDLE;3. a start of frame delimiter SOF;4. end of frame delimiter EOF. If the current two 32-bit transmission words are data, the coded synchronization header is 2'b10, otherwise, 2' b01, which indicates that the control information is contained. The 64B/66B encoding module forms an 8bit transmission type code based on the current two FC transmission word types to fill the highest byte of the encoded data, as shown in table 1 below.

TABLE 1 64B/66B coded transmission type codes for timing-level lightweight FC downlinks

Transmission type code	FC transmission word combination
		1Eh	{IDLE,IDLE}
33h	{SOF,IDLE}
		B4h	{IDLE,EOF}
78h	{data,SOF}
		FFh	{EOF,data}

The 64B/66B coding module does not code the data transmission word; if the transmission word is IDLE, 4 7bit control codes are obtained after coding; if the transmission word is SOF or EOF, the transmission word is encoded into a 4bit ordered code and 38 bit modifier codes, as shown in table 2 below.

TABLE 2 64B/66B code transport word coding for timing-stage lightweight FC downlink

FC transmission word	Control code/order code	Control code/modifier code	Control code/modifier code	Control code/modifier code
					IDLE	00h	00h	00h	00h
SOFi3	Fh	B5h	56h	56h
					SOFn3	Fh	B5h	36h	36h
EOFt	Fh	95h	75h	75h
					EOFn	Fh	95h	D5h	D5h
EOFni	Fh	8Ah	D5h	D5h

The 64b/66b decoding module firstly completes synchronization of the data received by the high-speed serial transceiver according to the synchronization head, then descrambles the data, and completes 64b/66b decoding of the descrambled data according to the information of the synchronization head, the type field, the control code and the like. Specifically, the 64b/66b decoding module firstly completes synchronization of the data received by the high-speed serial transceiver according to the synchronization header, if the receiving end detects an invalid synchronization header, the invalid synchronization header count value is added by 1, rx_ gearboxslip is pulled up when the invalid synchronization header count value is greater than a threshold value, the high-speed serial transceiver shifts the serial data, and the receiving synchronization is considered to be completed after the valid synchronization header count value continuously detected by the synchronization module exceeds the threshold value. Then, the data is descrambled, and 64b/66b decoding is completed on the descrambled data according to the information such as the synchronous head, the type field, the control code and the like.

The scramble module scrambles the data after the 64B/66B coding, the 64B/66B coding does not encode the data transmission word, so that the randomness of the data is increased by scrambling, the data is ensured to have enough jumps, the receiving end is ensured to recover the clock information from the data, and the scrambling principle is similar to that of frame scrambling.

The descramble module descrambles the parallel data received by the GTH to recover the original data, and then delivers the original data to the 64B/66B decoding module to finish the decoding work.

The foregoing has shown and described the basic principles, principal features and advantages of the invention. It will be appreciated by persons skilled in the art that the above embodiments are not intended to limit the invention in any way, and that all technical solutions obtained by means of equivalent substitutions or equivalent transformations fall within the scope of the invention.

Claims

1. A timing-level lightweight FC downlink processing engine, characterized by comprising: a data encapsulation module, a transmission control module, a word validity judgment and primitive detection module, a reception control module, a data analysis module and a data encoding and decoding module;

The data encapsulation module is used to receive the AXIS format control or pulse data transmitted from the upper layer, encapsulate it into an FC frame according to the FC protocol, perform CRC-12 check on the FC_ASM header information therein, and fill the check result into the lower 12 bits of the Reserved field in the FC_ASM header, and then encapsulate the axis format data according to the FC protocol standard;

The sending control module is used to send FC primitives or FC frames;

The word validity judgment and primitive detection module is used for judging the validity of the transmission word and detecting various frame delimiters and primitive signals, and outputting the primitive detection result to the receiving control module;

The receiving control module is used to infer the FC frame from the decoded data according to the frame delimiter, and perform error detection on the received FC frame, and then output it to the subsequent module for processing;

The data parsing module is used to perform CRC-12 check on the FC_ASM header information in the output data of the receiving control module. If a check error occurs, the frame is discarded; otherwise, the relevant data content is parsed and repackaged into the axis data format;

The data encoding and decoding module adopts different encoding methods to encode and decode the received and sent data according to the encoding requirements at different line rates.

2. The timing-level lightweight FC downlink processing engine according to claim 1, characterized in that:

The data encapsulation module comprises: a data extraction module, a header CRC generation module and a data encapsulation submodule;

The data extraction module is used to parse the axis interface data to extract data and write it into the cache;

The header CRC generation module is used to generate header information of FC_ASM, perform CRC-12 checksum calculation on the FC_ASM header information, and fill the checksum into the Reserved field of the ASM header;

The data encapsulation submodule encapsulates the data into FC frames according to the FC protocol standard.

3. The timing-level lightweight FC downlink processing engine according to claim 1, characterized in that:

The sending control module sends the primitive signal according to the instruction of the sending control state machine and the primitive signal valid flag, and transmits the FC frame or the idle filling word in other cases;

The sending control module has the following transmission priority: primitive signal>FC frame>idle filling word;

The transmission control module also has a cyclic redundancy check code generation function. When the FC frame is transmitted, the cyclic redundancy check code from the frame start delimiter to the last 4 bytes of data payload is calculated, and the cyclic redundancy check code is inserted before the frame end delimiter;

The sending control module also matches a corresponding transmission word type code according to the type of the current transmission word for subsequent 64B/66B encoding.

4. The timing-level lightweight FC downlink processing engine according to claim 3, characterized in that:

The sending control module also has a frame scrambling function. When the subsequent encoding is 8B/10B encoding, the sending control module scrambles the data payload portion from the frame start delimiter to the frame end delimiter.

5. The timing-level lightweight FC downlink processing engine according to claim 1, characterized in that:

The word validity judgment and primitive detection module judges the validity of the transmission word and the primitive signal according to the transmission word validity judgment criteria and the primitive signal detection criteria, and then infers whether the current transmission word is a data transmission word, a frame delimiter or a primitive signal based on the recognition of the code words of the four bytes of the transmission word, and outputs the corresponding indication signal to the receiving control module for use.

6. The timing-level lightweight FC downlink processing engine according to claim 1, characterized in that:

The receiving control module determines the FC frame according to the frame delimiter, performs frame end delimiter loss detection, overlong/undershort frame detection, cyclic redundancy check code error detection in sequence, and identifies different types of errors through flag signals.

7. The timing-level lightweight FC downlink processing engine according to claim 6, characterized in that:

The frame end delimiter loss detection analyzes the abnormal situation of "the frame data is followed by the FC control word/filling word", and if such abnormal situation occurs, the frame abnormal end delimiter is immediately inserted, and the first bit of the flag signal is used to identify such abnormal situation;

The overlong/undershort frame detection analyzes abnormal situations such as "frame length is greater than 2148 bytes or less than 36 bytes". For an overlong frame, the current frame is truncated immediately after the overlong frame, and then a frame abnormal end delimiter is inserted, and the overlong frame situation is identified by the third bit of the flag signal; for an overshort frame, the overshort frame situation is identified by the second bit of the flag signal;

The cyclic redundancy check error detection and analysis of abnormal situations such as "the cyclic redundancy check check result matches the check code field in the transmission word" is identified using the 0th bit of the flag signal.

8. The timing-level lightweight FC downlink processing engine according to claim 6, characterized in that:

The receiving control module has a frame descrambling function. When the encoding mode is 8B/10B encoding, the receiving control module descrambles the data payload part between the frame start delimiter and the frame end delimiter of the received FC frame.

9. The timing-level lightweight FC downlink processing engine according to claim 1, characterized in that:

The data parsing module is used to parse the received FC protocol data and encapsulate it into axi format data, and perform CRC-12 check on the FC_ASM header information and discard the FC frame that fails the check;

The data analysis module calculates the current data length, truncates the current data when the data length is greater than or equal to 2048B, and writes the data information into the data information FIFO.

10. The timing-level lightweight FC downlink processing engine according to claim 1, characterized in that:

The data encoding and decoding module comprises: a transmission word segmentation module, a transmission word reorganization module, a 64b/66b encoding module, a 64b/66b decoding module, a scramble module and a descramble module;

The transmission word segmentation module is used to adjust the bit sequence of data sent to the high-speed serial transceiver when the encoding scheme uses 8b/10b encoding, transmit K code information, and calculate the frame RD value from the frame start delimiter to the end of CRC;

The transmission word reorganization module is used to adjust the bit sequence of the data received from the high-speed serial transceiver. If the K code of the data after the bit sequence adjustment does not appear in the first byte, the data is shifted according to the Comma position indication signal so that the K code is fixed in the first byte, and the FC transmission word is formed and input into the receiving clock isolation FIFO;

The 64b/66b encoding module is used to combine two FC transmission words, perform 64b/66b encoding according to the transmission word type code, scramble the encoded data, and then output it to the high-speed serial transceiver;

The 64b/66b decoding module is used to synchronize the data received by the high-speed serial transceiver according to the synchronization header, and then descramble the data, and complete 64b/66b decoding of the descrambled data according to the synchronization header, type field, control code and other information;

The scramble module scrambles the data after 64B/66B encoding to increase the randomness of the data;

The descramble module descrambles the parallel data received by the GTH to restore the original data.