CN118937810B - Capacitor testing circuit and method by charge-discharge method - Google Patents
Capacitor testing circuit and method by charge-discharge method Download PDFInfo
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- 239000003990 capacitor Substances 0.000 title claims abstract description 199
- 238000012360 testing method Methods 0.000 title claims abstract description 125
- 238000000034 method Methods 0.000 title claims abstract description 50
- 238000005070 sampling Methods 0.000 claims abstract description 32
- 238000010998 test method Methods 0.000 claims description 4
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R27/00—Arrangements for measuring resistance, reactance, impedance, or electric characteristics derived therefrom
- G01R27/02—Measuring real or complex resistance, reactance, impedance, or other two-pole characteristics derived therefrom, e.g. time constant
- G01R27/26—Measuring inductance or capacitance; Measuring quality factor, e.g. by using the resonance method; Measuring loss factor; Measuring dielectric constants ; Measuring impedance or related variables
- G01R27/2605—Measuring capacitance
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- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R1/00—Details of instruments or arrangements of the types included in groups G01R5/00 - G01R13/00 and G01R31/00
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- G01R1/206—Switches for connection of measuring instruments or electric motors to measuring loads
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Abstract
The invention discloses a charge-discharge method test capacitor circuit and a method, wherein the test capacitor circuit comprises a first branch, a second branch, an inherent resistor, a third branch, a fourth branch and a sampling processing device, the first branch comprises a first switch and a first standard resistor which are connected in series, the second branch comprises a second switch and a second standard resistor which are connected in series, one end of the first branch and one end of the second branch are both connected with a power supply voltage, the other end of the second branch is connected with the first end of the inherent resistor, the resistance values of the first standard resistor and the resistance value of the second standard resistor are different, the third branch comprises a third switch and a test capacitor which are connected in series, the fourth branch comprises a stray capacitor, one end of the third branch and one end of the fourth branch are both connected with the second end of the inherent resistor and are also connected with the sampling processing device, and the other end of the third branch is grounded. According to the invention, by acquiring the charging time of the charging capacitor under the connection of different branches, a more accurate capacitance value of the tested capacitor can be obtained, and the capacitor test with wide range and high precision is realized.
Description
Technical Field
The invention relates to the technical field of circuit electronics, in particular to a capacitor testing circuit and a capacitor testing method by a charge-discharge method.
Background
The existing charge-discharge method test capacitor circuit utilizes a test capacitor C, a standard resistor R and a power supply to construct an RC charge-discharge loop, charges the capacitor through the power supply or causes the capacitor to discharge naturally, measures parameters such as voltage or time and the like, and calculates the value of the capacitor according to the charge-discharge characteristics of the capacitor.
However, the value of the capacitor obtained by the prior art cannot reach the required precision under certain factors, and the factors influencing the test precision mainly connect the inherent resistance of the circuit in series with the standard resistor and the stray capacitance existing in the circuit. Based on this, it is necessary to design a circuit to eliminate the influence of these inherent parameters of the circuit, and to realize a wide-range and high-precision capacitance test.
Disclosure of Invention
In view of the above problems, the invention aims to provide a capacitor testing circuit and method by a charge-discharge method, which can eliminate the influence of inherent impedance and stray capacitance of the charge-discharge circuit, realize the detection of PCBA circuit boards and various single capacitors and realize the capacitance testing of pf-uF stages in a wide range and high precision.
The invention provides a charge-discharge method test capacitor circuit which comprises a first branch, a second branch, an inherent resistor, a third branch, a fourth branch and a sampling processing device, wherein the first branch comprises a first switch and a first standard resistor which are connected in series, the second branch comprises a second switch and a second standard resistor which are connected in series, one end of the first branch and one end of the second branch are both connected with a power supply voltage, the other end of the first branch and the other end of the second branch are both connected with the first end of the inherent resistor, the resistance values of the first standard resistor and the second standard resistor are different, the third branch comprises a third switch and a test capacitor which are connected in series, the fourth branch comprises a stray capacitor, one end of the third branch and one end of the fourth branch are both connected with the second end of the inherent resistor and are also connected with the sampling processing device, and the other end of the third branch and the other end of the fourth branch are both grounded.
Optionally, the sampling processing device comprises a 555 timer and a processing module, wherein the 555 timer comprises a power supply end, a high trigger end and an output end, the power supply end of the 555 timer receives the power supply voltage, the high trigger end of the 555 timer is connected with the second end of the inherent resistor, and the processing module comprises a receiving end, and the receiving end of the processing module is connected with the output end of the 555 timer.
Optionally, the 555 timer further includes a low trigger end, and the low trigger end of the 555 timer is configured to receive an external pulse trigger signal.
Optionally, the processing module further includes a trigger end, and the trigger end of the processing module is connected with the low trigger end of the 555 timer.
Optionally, the low trigger end of the 555 timer receives the power supply voltage through a pull-up resistor.
The invention further provides a method for testing the capacitor circuit based on the charge-discharge method, which comprises the steps of controlling the third switch to be opened, the first switch to be closed and the second switch to be opened, obtaining first charge time from the first voltage to the second voltage of the stray capacitor, controlling the third switch to be opened, the first switch to be opened and the second switch to be closed, obtaining second charge time from the first voltage to the second voltage of the stray capacitor, controlling the third switch to be closed, the first switch to be closed and the second switch to be opened, obtaining third charge time from the first voltage to the second voltage of the test capacitor, controlling the third switch to be closed, the first switch to be opened and the second switch to be closed, obtaining fourth charge time from the first voltage to the second voltage of the test capacitor, and determining the standard resistance value, the second resistance value and the test capacitance of the test capacitor according to the first charge time, the second charge time, the third charge time, the fourth charge time, the first resistance value and the standard resistance value.
Optionally, determining the capacitance value of the test capacitor according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage and the second voltage includes determining the capacitance value of the test capacitor according to a formula C=(Tw1'-Tw2')/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2))))-(Tw1-Tw2)/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2)))),, wherein C represents the capacitance value of the test capacitor, R1 represents the resistance value of the first standard resistor, R2 represents the resistance value of the second standard resistor, tw1 represents the first charging time, tw2 represents the second charging time, tw1 'represents the third charging time, tw2' represents the fourth charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage.
Optionally, the determining the capacitance value of the test capacitor according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage and the second voltage comprises determining the capacitance value of the test capacitor according to the first charging time, the second charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage and the second voltage, and determining the capacitance value of the test capacitor according to the third charging time, the fourth charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage, the second voltage and the capacitance value of the stray capacitor.
Optionally, the determining the capacitance value of the stray capacitance according to the formula cs= (Tw 1-Tw 2)/((R1-R2)/((Vcc-Uc (t 1))/(Vcc-Uc (t 2)))) according to the first charging time, the second charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage, and the second voltage, wherein Cs represents the capacitance value of the stray capacitance, R1 represents the resistance value of the first standard resistor, tw2 represents the second charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage.
Optionally, determining the capacitance value of the test capacitor according to the formula c= (Tw 1'-Tw 2')/(R1-R2)/((Vcc-Uc (t 1))/(Vcc-Uc (t 2))))) -Cs, wherein C represents the capacitance value of the test capacitor, cs represents the capacitance value of the stray capacitor, R1 represents the resistance value of the first standard resistor, R2 represents the resistance value of the second standard resistor, tw1 'represents the third charging time, tw2' represents the fourth charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage.
According to the capacitor circuit and the capacitor testing method by the charge-discharge method, the charge time of the charge capacitor connected by different branches is obtained through the control of the first switch, the second switch and the third switch, the first charge time, the second charge time, the third charge time and the fourth charge time are obtained, and according to the first charge time, the second charge time, the third charge time, the fourth charge time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage and the second voltage, the more accurate capacitor value of the tested capacitor is obtained, the influence of the inherent impedance and the stray capacitor of the charge-discharge circuit can be eliminated, the PCBA circuit board and various monomer capacitors can be detected, and the capacitor testing of the pf-uF level wide range and high precision is realized.
Drawings
In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings that are needed in the embodiments will be briefly described below, it being understood that the following drawings only illustrate some embodiments of the present invention and therefore should not be considered as limiting the scope, and other related drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.
Fig. 1 shows a schematic circuit connection diagram of a charge-discharge method test capacitor circuit according to a first embodiment of the present invention.
Fig. 2 shows an equivalent circuit diagram of the charge-discharge method test capacitive circuit of fig. 1 when the capacitance is charged.
Fig. 3 is a schematic diagram showing the circuit connection of a charge-discharge method test capacitor circuit according to a second embodiment of the present invention.
Fig. 4 shows a timing diagram of the voltage on the port of the 555 timer in the charge-discharge method test capacitor circuit of fig. 3.
Fig. 5 is a schematic flow chart of a method for testing capacitance by charge-discharge method according to a third embodiment of the invention.
Detailed Description
The foregoing and other features, aspects, and advantages of the present invention will become more apparent from the following detailed description of the preferred embodiments, which proceeds with reference to the accompanying drawings. While the invention may be susceptible to further details of technical means and effects for achieving the desired purpose, there is shown in the drawings a form a further part hereof, and in which is shown by way of illustration and not by way of limitation, certain well-known elements of the invention. Like elements are denoted by like reference numerals throughout the various figures. For purposes of clarity, the various elements in the drawings are not necessarily drawn to scale.
It is to be understood that the terms "first," "second," "third," "fourth," and the like are merely used to distinguish between similar elements or circuits and do not indicate or imply relative importance or a particular order. The terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a list of elements does not include only those elements but may include other elements not expressly listed.
It should be noted that, without conflict, the embodiments of the present application and features of the embodiments may be combined with each other. The application will be described in detail below with reference to the drawings in connection with embodiments.
First embodiment
Fig. 1 shows a schematic circuit connection diagram of a charge-discharge method test capacitor circuit according to a first embodiment of the present invention. As shown in fig. 1, the present embodiment provides a charge-discharge method test capacitor circuit, which includes a first branch, a second branch, an intrinsic resistor 15, a third branch, a fourth branch, and a sampling processing device 20. The first branch comprises a first switch 11 and a first standard resistor 12 which are connected in series, the second branch comprises a second switch 13 and a second standard resistor 14 which are connected in series, one end of the first branch and one end of the second branch are both used for receiving a power supply voltage Vcc, and the other end of the first branch and the other end of the second branch are both connected with the first end of an inherent resistor 15, wherein the resistance values of the first standard resistor 12 and the second standard resistor 14 are different. The third branch comprises a third switch 17 and a test capacitor 16 which are connected in series, the fourth branch comprises a stray capacitor 18, one end of the third branch and one end of the fourth branch are connected with the second end of the inherent resistor 15 and also connected with a sampling processing device 20, and the other end of the third branch and the other end of the fourth branch are grounded.
In one embodiment, as shown in fig. 1, in the first branch, a first terminal of the first switch 11 receives the power supply voltage Vcc, a first terminal of the first reference resistor 12 is connected to a second terminal of the first switch 11, and a second terminal of the first reference resistor 12 is connected to a first terminal of the inherent resistor 15.
In an embodiment, as shown in fig. 1, in the second branch, the first terminal of the second switch 13 receives the power supply voltage Vcc, the first terminal of the second reference resistor 14 is connected to the second terminal of the second switch 13, and the second terminal of the second reference resistor 14 is connected to the first terminal of the inherent resistor 15.
In an embodiment, as shown in fig. 1, in the third branch, a first terminal of the test capacitor 16 is connected to a second terminal of the intrinsic resistor 15 and further connected to the sample processing device 20, a first terminal of the third switch 17 is connected to a second terminal of the test capacitor 16, and a second terminal of the third switch 17 is grounded.
Specifically, the capacitor circuit tested by the charge-discharge method in this embodiment may be a capacitor charge-discharge circuit, and different branch connections are formed by controlling the on-off of the first switch 11, the second switch 13 and the third switch 17. When the charging capacitor is charged, the sampling processing device 20 is connected to the third branch and the fourth branch, and can sample the voltage of the charging capacitor, obtain the charging time of the charging capacitor connected by different branches, and calculate the capacitance value of the test capacitor 16. When the third switch 17 is turned off, the charging capacitor charged by the access circuit is a stray capacitor 18, and when the third switch 17 is turned on, the charging capacitor charged by the access circuit is a test capacitor 16 and the stray capacitor 18 connected in parallel. The sampling device 20 obtains a first charging time of the stray capacitance 18 from the first voltage to the second voltage if the third switch 17 is opened, the first switch 11 is closed, and the second switch 13 is opened, the sampling device 20 obtains a second charging time of the stray capacitance 18 from the first voltage to the second voltage if the third switch 17 is opened, the first switch 11 is closed, and the second switch 13 is opened, the sampling device 20 obtains a third charging time of the test capacitance 16 from the first voltage to the second voltage if the third switch 17 is closed, the first switch 11 is opened, and the second switch 13 is closed, and the sampling device 20 obtains a fourth charging time of the test capacitance 16 from the first voltage to the second voltage if the third switch 17 is closed, the first switch 11 is opened, and the second switch 13 is closed. When the charge capacitor discharges, the sampling processing device 20 can be connected to the third branch and the fourth branch to discharge the test capacitor 16 and the stray capacitor 18, so that the voltages of the test capacitor 16 and the stray capacitor 18 drop to the first voltage or below, and the first charge time, the second charge time, the third charge time and the fourth charge time can be acquired in multiple times during multiple charge.
Fig. 2 shows an equivalent circuit diagram of the charge-discharge method test capacitive circuit of fig. 1 when the capacitance is charged. The total resistor is connected with the charging capacitor in series, the excitation source charges the charging capacitor through the total resistor, the resistance value of the total resistor is R, the capacitance value of the charging capacitor is C, the excitation source is Us (t), and real-time voltages at two ends of the capacitor are Uc (t). When the charging capacitor is charged, the charging time from the first voltage to the second voltage can be obtained through differential calculation, and according to the kirchhoff voltage law, the loop voltage equation of the equivalent circuit is as follows:
R*i(t)+Uc(t)=Us(t)...................................(1)
That is to say,
............................(2)
The following differential equation is rewritten:
..........................(3)
To obtain a solution of the complex,
..............................(4)
Wherein, For a constant to be determined, the capacitance voltage when t=0 is Uc (0), and the constant is obtained:
..................................(5)
(5) The carrying-in (4) comprises the following steps:
.............................(6)
Obtaining:
..........................................(7)
In the following, fig. 1 and 2 are combined, the voltage of the excitation source Us (t) corresponds to the power supply voltage Vcc, the charging voltage of the charging capacitor after the limit large charging time is the power supply voltage Vcc, the capacitance voltage when t=t1 is set to be the first voltage Uc (t 1), and the capacitance voltage when t=t2 is set to be the second voltage Uc (t 2), and the charging time Tw is:
。
If the third switch 17 is controlled to be opened, the first switch 11 is closed, and the second switch 13 is controlled to be opened, the total resistance is the first standard resistance 12 and the inherent resistance 15 connected in series, the charging capacitance is the stray capacitance 18, the first charging time from the first voltage to the second voltage of the stray capacitance 18 is obtained, the first charging time is Tw1, the resistance value of the first standard resistance 12 is R1, the resistance value of the inherent resistance 15 is R0, and the capacitance value of the stray capacitance 18 is Cs, then:
............................(8)
If the third switch 17 is controlled to be opened, the first switch 11 is opened, and the second switch 13 is controlled to be closed, the total resistance is the second standard resistor 14 and the inherent resistor 15 connected in series, the charging capacitor is the stray capacitor 18, the second charging time from the first voltage to the second voltage of the stray capacitor 18 is obtained, the first charging time is Tw2, the resistance value of the second standard resistor 14 is R2, the resistance value of the inherent resistor 15 is R0, and the capacitance value of the stray capacitor 18 is Cs, then:
............................(9)
and (8) - (9) are provided with
................... (10)
Cs= (Tw 1-Tw 2)/((R1-R2) ×ln ((Vcc-Uc (t 1))/(Vcc-Uc (t 2)))))......... (11)
If the third switch 17 is controlled to be closed, the first switch 11 is closed, and the second switch 13 is controlled to be opened, the total resistance is the first standard resistor 12 and the inherent resistor 15 connected in series, the charging capacitor is the test capacitor 16 and the stray capacitor 18 connected in parallel, the third charging time from the first voltage to the second voltage of the test capacitor 16 is obtained, the third charging time is Tw1', the resistance value of the first standard resistor 12 is R1, the resistance value of the inherent resistor 15 is R0, the capacitance value of the test capacitor 16 is C, and the capacitance value of the stray capacitor 18 is Cs, then:
......................(12)
if the third switch 17 is controlled to be closed, the first switch 11 is opened, and the second switch 13 is controlled to be closed, the total resistance is the second standard resistor 14 and the inherent resistor 15 connected in series, the charging capacitor is the test capacitor 16 and the stray capacitor 18 connected in parallel, the fourth charging time from the first voltage to the second voltage of the test capacitor 16 is obtained, the fourth charging time is Tw2', the resistance value of the second standard resistor 14 is R2, the resistance value of the inherent resistor 15 is R0, the capacitance value of the test capacitor 16 is C, and the capacitance value of the stray capacitor 18 is Cs, then:
.....................(13)
will have (12) - (13)
;
Then c= (Tw 1'-Tw 2')/(R1-R2) × ln ((Vcc-Uc (t 1))/(Vcc-Uc (t 2))) -Cs...times. (14)
Substituting (11) into (14) have
C=(Tw1'-Tw2')/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2))))-(Tw1-Tw2)/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2))))………………………………(15)
It can be seen that the sampling processing device 20 can determine the capacitance value of the test capacitor 16 according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vcc, the first voltage and the second voltage, and eliminate the influence of the inherent resistor 15 and the stray capacitor 18. Therefore, the method for testing the capacitor 16 of the capacitor circuit by the charge-discharge method of this embodiment may include:
The method comprises the steps of controlling the third switch 17 to be opened, the first switch 11 to be closed and the second switch 13 to be opened to obtain a first charging time of the stray capacitance 18 from the first voltage to the second voltage, controlling the third switch 17 to be opened, the first switch 11 to be opened and the second switch 13 to be closed to obtain a second charging time of the stray capacitance 18 from the first voltage to the second voltage, controlling the third switch 17 to be closed, the first switch 11 to be closed and the second switch 13 to be opened to obtain a third charging time of the test capacitance 16 from the first voltage to the second voltage, controlling the third switch 17 to be closed, the first switch 11 to be opened and the second switch 13 to be closed to obtain a fourth charging time of the test capacitance 16 from the first voltage to the second voltage, and determining the capacitance value of the test capacitance 16 by the sampling processing device 20 according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vc, the first voltage and the second voltage. When the first charging time, the second charging time, the third charging time and the fourth charging time are acquired, the charging capacitor should be first discharged, and the test capacitor 16 and the stray capacitor 18 can be discharged through the connection between the sampling processing device 20 and the third branch and the fourth branch, so that the voltages of the test capacitor 16 and the stray capacitor 18 are reduced to the first voltage or lower.
In an embodiment, the sampling processing device 20 determines the capacitance value of the test capacitor 16 according to the formula C=(Tw1'-Tw2')/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2))))-(Tw1-Tw2)/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2)))),, where C represents the capacitance value of the test capacitor 16, R1 represents the resistance value of the first standard resistor 12, R2 represents the resistance value of the second standard resistor 14, tw1 represents the first charging time, tw2 represents the second charging time, tw1 'represents the third charging time, tw2' represents the fourth charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage. Wherein the derivation of the formulas can be seen in (1) - (15) above.
In one embodiment, the sampling processing device 20 determines the capacitance value of the stray capacitance 18 according to the first charging time, the second charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vcc, the first voltage and the second voltage, and determines the capacitance value of the test capacitance 16 according to the third charging time, the fourth charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vcc, the first voltage, the second voltage and the capacitance value of the stray capacitance 18.
In one embodiment, the sampling processing device 20 determines the capacitance value of the stray capacitance 18 according to the formula cs= (Tw 1-Tw 2)/((R1-R2) ×ln ((Vcc-Uc (t 1))/(Vcc-Uc (t 2))), where Cs represents the capacitance value of the stray capacitance 18, R1 represents the resistance value of the first standard resistor 12, R2 represents the resistance value of the second standard resistor 14, tw1 represents the first charging time, tw2 represents the second charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage. Wherein the derivation of the formulas can be seen in (1) - (11) above.
In one embodiment, the sampling processing device 20 determines the capacitance value of the test capacitor 16 according to the formula c= (Tw 1'-Tw 2')/(R1-R2) ×ln ((Vcc-Uc (t 1))/(Vcc-Uc (t 2))) -Cs, where C represents the capacitance value of the test capacitor 16, cs represents the capacitance value of the stray capacitor 18, R1 represents the resistance value of the first standard resistor 12, R2 represents the resistance value of the second standard resistor 14, tw1 represents the first charging time, tw2 represents the second charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage. Wherein the derivation of the formulas can be seen in (1) - (14) above.
Therefore, in this embodiment, the charging time of the charging capacitor connected by different branches is obtained by controlling the first switch 11, the second switch 13 and the third switch 17, so as to obtain the first charging time, the second charging time, the third charging time and the fourth charging time, and according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance of the first standard resistor 12, the resistance of the second standard resistor 14, the power supply voltage Vcc, the first voltage and the second voltage, a more accurate capacitance value of the test capacitor 16 is obtained, the influence of the inherent impedance of the charging and discharging circuit and the stray capacitor 18 can be eliminated, the PCBA circuit board and various monomer capacitors can be detected, and the capacitor test of pf-uF level wide range and high precision can be realized.
In one embodiment, the test capacitor 16 circuit further includes a voltage dividing resistor disposed between the power supply voltage Vcc and the first and second branches, such that the first and second branches need to receive the power supply voltage Vcc through the voltage dividing resistor. In the calculation of the capacitance value of the test capacitor 16, the voltage dividing resistor like the inherent resistor 15 can be eliminated without affecting the calculation result of the capacitance value of the test capacitor 16.
In an embodiment, the test capacitor 16 circuit further comprises an auxiliary capacitor connected in parallel with the stray capacitor 18 in the fourth branch, which can be used to better form the circuit loop. In the calculation of the capacitance value of the test capacitor 16, the auxiliary capacitor like the stray capacitor 18 can be eliminated without affecting the calculation result of the capacitance value of the test capacitor 16.
In one embodiment, the sampling processing device 20 is configured to receive the power supply voltage Vcc at a power supply terminal.
In an embodiment, the sampling device 20 is provided with a ground connection.
Second embodiment
Fig. 3 is a schematic diagram showing the circuit connection of a charge-discharge method test capacitor circuit according to a second embodiment of the present invention. The principle and the technical effects of the charge-discharge method test capacitor circuit are the same as those of the first embodiment, and for brevity, reference is made to the corresponding contents of the first embodiment.
In one embodiment, the sampling processing device 20 comprises a 555 timer 21 and a processing module 22, wherein the 555 timer 21 comprises a power supply terminal VDD, a high trigger terminal THR and an output terminal OUT, the power supply terminal VDD of the 555 timer 21 receives the power supply voltage Vcc, the high trigger terminal THR of the 555 timer 21 is connected with the second terminal of the inherent resistor 15, the processing module 22 comprises a receiving terminal ICP, and the receiving terminal ICP of the processing module 22 is connected with the output terminal OUT of the 555 timer 21.
Specifically, the 555 timer 21 may be connected to a monostable trigger circuit or an oscillating circuit in this embodiment, and may be configured to output a high level to the processing module 22 from the output terminal OUT of the 555 timer 21 when the charging voltage of the charging capacitor is between the first voltage and the second voltage, where the processing module 22 determines the charging time according to the duration of the high level, and may determine the capacitance value of the test capacitor 16 according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor 12, and the resistance value of the second standard resistor 14.
If the 555 timer 21 is connected to a monostable trigger circuit, the 555 timer 21 sets the first voltage for one charge and one discharge of the charging capacitor to 0V, the second voltage is set to 2/3 Vcc which is the voltage value of 2/3 of the power supply voltage Vcc, when the 555 timer 21 is triggered, the charging capacitor starts to charge and boost up from the first voltage, namely 0V, the voltage of the high trigger terminal THR of the 555 timer 21 starts to be high level, and is sent to the receiving terminal ICP of the processing module 22, the processing module 22 starts to count time, when the charging capacitor rises to the second voltage, namely 2/3 Vcc, the voltage of the high trigger terminal THR of the 555 timer 21 reaches 2/3 Vcc, the internal discharge tube of the 555 timer 21 is turned on, the charging capacitor starts to discharge through the internal discharge tube of the 555 timer 21, the output terminal OUT of the 555 timer 21 starts to be low level, and is sent to the receiving terminal ICP of the processing module 22, and the processing module 22 stops to acquire the time of the charging capacitor 22.
If the 555 timer 21 is connected to the oscillating circuit, the 555 timer 21 sets the voltage value of 1/3 of the power supply voltage Vcc, i.e. 1/3 Vcc, the first voltage during charging to be 1/3 of the power supply voltage Vcc, and the second voltage to be 2/3 Vcc, the 555 timer 21 starts charging and boosting from the first voltage, i.e. 1/3 Vcc, the 555 timer 21 is turned off when the low trigger terminal TRI receives the charging capacitor to the first voltage, i.e. 1/3 Vcc, the internal discharge tube of the 555 timer 21 is turned off, the charging capacitor starts charging and boosting from the first voltage, i.e. 1/3 Vcc, the voltage of the high trigger terminal THR of the 555 timer 21 is correspondingly boosted from 1/3 Vcc, the output terminal OUT of the 555 timer 21 starts to be high, and is sent to the receiving terminal ICP of the processing module 22, and the processing module 22 starts timing, when the charging capacitor is boosted to the second voltage, i.e. 2/3 Vcc, the voltage of the high trigger terminal THR of the 555 timer 21 reaches 2/3 Vcc, the internal discharge tube of the 555 timer 21 starts charging and the internal discharge tube of the 555 timer 21 is turned on, the high trigger terminal THR of the 555 timer 21 starts to be discharged to the processing module 22, and the processing module starts to obtain the processing time of the discharging from the internal discharge tube of the 555 timer 21 is started.
The configuration of the test circuit and the test method will be described below by taking the example that the 555 timer 21 is connected to a monostable trigger circuit.
In an embodiment, as shown in fig. 3, the 555 timer 21 further includes a low trigger TRI, and the low trigger TRI of the 555 timer 21 is configured to receive an external pulse trigger signal.
In an embodiment, as shown in fig. 3, the 555 timer 21 further includes a ground GND, a reset RST, a control terminal CON and a discharge terminal DIS, the ground GND of the 555 timer 21 is grounded, the reset RST of the 555 timer 21 receives the power voltage Vcc, the control terminal CON of the 555 timer 21 is grounded through a immunity capacitor 211, for example, 0.1 μf, and the discharge terminal DIS of the 555 timer 21 is connected to the high trigger terminal THR of the 555 timer 21.
In an embodiment, as shown in fig. 3, the processing module 22 further includes a trigger terminal TRI, the trigger terminal TRI of the processing module 22 is connected to the low trigger terminal TRI of the 555 timer 21, and the processing module 22 sends an external pulse trigger signal to the low trigger terminal TRI of the 555 timer 21 through the trigger terminal TRI. However, the present application is not limited thereto, and the low trigger terminal TRI of the 555 timer 21 may be set to be grounded through the fourth switch, and the low trigger terminal TRI of the 555 timer 21 may receive the external pulse trigger signal at a low level by controlling the closing of the fourth switch.
In one embodiment, the low trigger TRI of the 555 timer 21 receives the power supply voltage Vcc through a pull-up resistor. Can be used to ensure that the low trigger TRI of the 555 timer 21 remains always high when no external pulse trigger signal is received.
Specifically, fig. 4 shows a timing diagram of the voltage on the port of 555 timer 21 in the charge-discharge method test capacitor circuit of fig. 3, which is described below in connection with fig. 3 and 4. The first voltage during charging may be set to 0V, the second voltage may be set to a voltage value of 2/3 of the power supply voltage Vcc, i.e., 2/3 Vcc, and then the 555 timer 21 is triggered by the external pulse trigger signal received by the low trigger terminal TRI, such as Vi in fig. 4, the internal discharge tube of the 555 timer 21 starts to be turned off, the charging capacitor starts to charge and boost up from the first voltage, i.e., 0V, the voltage of the high trigger terminal THR of the 555 timer 21 is correspondingly boosted up from 0V, such as Vc in fig. 4, the output terminal OUT of the 555 timer 21 starts to become high level, such as Vo in fig. 4, and is sent to the receiving terminal of the processing module 22, and the processing module 22 starts to count time, and when the charging capacitor rises to the second voltage, i.e., 2/3 Vcc, the voltage of the high trigger terminal THR of the 555 timer 21 reaches 2/3 Vcc, the internal discharge tube of the 555 timer 21 is turned on, the charging capacitor starts to discharge from the internal discharge tube of the 555 timer 21, the voltage of the high trigger terminal THR of the 555 timer 21 correspondingly changes from 0V to high trigger terminal OUT of the output terminal OUT of the 555 timer 21 becomes high level, such as Vo in fig. 4, vo in fig. 4 is sent to the receiving terminal of the processing module 22 starts to be counted, and the processing module 22 starts to acquire the voltage of the high trigger terminal THR 2/3, i.e.2/3 35 in the second voltage of the high trigger terminal THR of the processing module is turned down to reach 2/3 Vcc, as shown in fig. 4. The method for testing the capacitor 16 of the capacitor circuit by the charge-discharge method of this embodiment may include:
The method comprises the steps of controlling the third switch 17 to be opened, the first switch 11 to be closed and the second switch 13 to be opened to obtain a first charging time of the stray capacitance 18 from the first voltage to the second voltage, controlling the third switch 17 to be opened, the first switch 11 to be opened and the second switch 13 to be closed to obtain a second charging time of the stray capacitance 18 from the first voltage to the second voltage, controlling the third switch 17 to be closed, the first switch 11 to be closed and the second switch 13 to be opened to obtain a third charging time of the test capacitance 16 from the first voltage to the second voltage, controlling the third switch 17 to be closed, the first switch 11 to be opened and the second switch 13 to be closed to obtain a fourth charging time of the test capacitance 16 from the first voltage to the second voltage, and determining the capacitance value of the test capacitance 16 by the sampling processing device 20 according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vc, the first voltage and the second voltage. When the first charging time, the second charging time, the third charging time and the fourth charging time are acquired, the charging capacitor should be first discharged, and the test capacitor 16 and the stray capacitor 18 can be discharged through the connection between the sampling processing device 20 and the third branch and the fourth branch, so that the voltages of the test capacitor 16 and the stray capacitor 18 are reduced to the first voltage or lower.
In one embodiment, the sampling processing device 20 determines the capacitance value of the test capacitor 16 according to the formula c= (Tw 1'-Tw 2')/(R1-R2) ×ln 3) - (Tw 1-Tw 2)/((R1-R2) ×ln 3), where C represents the capacitance value of the test capacitor 16, R1 represents the resistance value of the first standard resistor 12, R2 represents the resistance value of the second standard resistor 14, tw1 represents the first charging time, tw2 represents the second charging time, tw1 'represents the third charging time, and Tw2' represents the fourth charging time. The derivation of the formula can be seen in (1) - (15) above, and the voltage value Uc (t 1) =0v of the first voltage and the voltage value Uc (t 2) =2/3 Vcc of the second voltage are substituted into (15).
In one embodiment, the sampling processing device 20 determines the capacitance value of the stray capacitance 18 according to the first charging time, the second charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vcc, the first voltage and the second voltage, and determines the capacitance value of the test capacitance 16 according to the third charging time, the fourth charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vcc, the first voltage, the second voltage and the capacitance value of the stray capacitance 18.
In one embodiment, the sampling processing device 20 determines the capacitance value of the stray capacitance 18 according to the formula cs= (Tw 1-Tw 2)/((R1-R2) ×ln3), where Cs represents the capacitance value of the stray capacitance 18, R1 represents the resistance value of the first standard resistor 12, R2 represents the resistance value of the second standard resistor 14, tw1 represents the first charging time, and Tw2 represents the second charging time. The derivation of the formula can be seen in (1) - (11) above, and the voltage value Uc (t 1) =0v of the first voltage and the voltage value Uc (t 2) =2/3 Vcc of the second voltage are substituted into (11).
In one embodiment, the sampling processing device 20 determines the capacitance value of the test capacitor 16 according to the formula c= (Tw 1'-Tw 2')/(R1-R2) ×ln3) -Cs, where C represents the capacitance value of the test capacitor 16, cs represents the capacitance value of the stray capacitor 18, R1 represents the resistance value of the first standard resistor 12, R2 represents the resistance value of the second standard resistor 14, tw1 'represents the third charging time, tw2' represents the fourth charging time. The derivation of the formula can be seen in (1) - (14) above, and the voltage value Uc (t 1) =0v of the first voltage and the voltage value Uc (t 2) =2/3 Vcc of the second voltage are substituted into (14).
Third embodiment
Fig. 5 is a schematic flow chart of a method for testing capacitance by charge-discharge method according to a third embodiment of the invention. The principle and the technical effects of the method for testing capacitance by charge and discharge method are the same as those of the above embodiments, and for brevity, reference may be made to the corresponding contents of the above embodiments. As shown in fig. 5, the method for testing capacitance by charge-discharge method of the present embodiment includes the following steps:
S1, controlling the third switch 17 to be opened, the first switch 11 to be closed and the second switch 13 to be opened, and obtaining a first charging time of the stray capacitor 18 from the first voltage to the second voltage;
S2, controlling the third switch 17 to be opened, the first switch 11 to be opened and the second switch 13 to be closed, and obtaining a second charging time of the stray capacitor 18 from the first voltage to the second voltage;
S3, controlling the third switch 17 to be closed, the first switch 11 to be closed and the second switch 13 to be opened, and obtaining a third charging time of the test capacitor 16 from the first voltage to the second voltage;
s4, controlling the third switch 17 to be closed, the first switch 11 to be opened and the second switch 13 to be closed, and obtaining fourth charging time of the test capacitor 16 from the first voltage to the second voltage;
s5, determining the capacitance value of the test capacitor 16 according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vcc, the first voltage and the second voltage.
In one embodiment, determining the capacitance value of the test capacitor 16 based on the first charge time, the second charge time, the third charge time, the fourth charge time, the resistance of the first standard resistor 12, the resistance of the second standard resistor 14, the power supply voltage Vcc, the first voltage, and the second voltage includes determining the capacitance value of the test capacitor 16 based on a formula C=(Tw1'-Tw2')/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2))))-(Tw1-Tw2)/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2)))),, where C represents the capacitance value of the test capacitor 16, R1 represents the resistance of the first standard resistor 12, R2 represents the resistance of the second standard resistor 14, tw1 represents the first charge time, tw2 represents the second charge time, tw1 'represents the third charge time, tw2' represents the fourth charge time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage.
In one embodiment, determining the capacitance value of the test capacitor 16 according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vcc, the first voltage, and the second voltage includes:
Determining a capacitance value of the stray capacitor 18 according to the first charging time, the second charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vcc, the first voltage and the second voltage;
The capacitance value of the test capacitor 16 is determined according to the third charging time, the fourth charging time, the resistance value of the first reference resistor 12, the resistance value of the second reference resistor 14, the power supply voltage Vcc, the first voltage, the second voltage, and the capacitance value of the stray capacitor 18.
In one embodiment, determining the capacitance of the stray capacitor 18 based on the first charging time, the second charging time, the resistance of the first reference resistor 12, the resistance of the second reference resistor 14, the power supply voltage Vcc, the first voltage, and the second voltage includes:
The capacitance value of the stray capacitance 18 is determined according to the formula cs= (Tw 1-Tw 2)/((R1-R2) ×ln ((Vcc-Uc (t 1))/(Vcc-Uc (t 2)))), where Cs represents the capacitance value of the stray capacitance 18, R1 represents the resistance value of the first standard resistor 12, R2 represents the resistance value of the second standard resistor 14, tw1 represents the first charging time, tw2 represents the second charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage.
In one embodiment, determining the capacitance value of the test capacitor 16 according to the formula c= (Tw 1'-Tw 2')/(R1-R2)/((Vcc-Uc (t 1))/(Vcc-Uc (t 2))))) -Cs, wherein C represents the capacitance value of the test capacitor 16, cs represents the capacitance value of the stray capacitor 18, R1 represents the resistance value of the first standard resistor 12, R2 represents the resistance value of the second standard resistor 14, tw1 'represents the third charging time, tw2' represents the fourth charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage, is determined according to the third charging time, the fourth charging time, the resistance value of the first standard resistor 12, the resistance value of the second standard resistor 14, the power supply voltage Vcc, the second voltage of the stray capacitor 18, and the stray capacitor 18.
Therefore, the charge-discharge method test capacitor circuit and the capacitor method provided by the application acquire the charge time of the charge capacitor under the connection of different branches through the control of the first switch 11, the second switch 13 and the third switch 17, acquire the first charge time, the second charge time, the third charge time and the fourth charge time, and acquire more accurate capacitor values of the test capacitor 16 according to the resistance of the first standard resistor 12, the resistance of the second standard resistor 14, the power supply voltage Vcc, the first voltage and the second voltage, so as to eliminate the inherent impedance of the charge-discharge circuit and the influence of the stray capacitor 18, detect PCBA circuit boards and various monomer capacitors, and realize the capacitor test of pf-uF stages in a wide range and high precision.
The above description is only illustrative of the preferred embodiments of the present application and of the principles of the technology employed. It will be appreciated by persons skilled in the art that the scope of the application referred to in the present application is not limited to the specific combinations of the technical features described above, but also covers other technical features formed by any combination of the technical features described above or their equivalents without departing from the inventive concept. Such as the above-mentioned features and the technical features disclosed in the present application (but not limited to) having similar functions are replaced with each other.
Claims (10)
1. A charge-discharge method test capacitor circuit is characterized by comprising a first branch, a second branch, an inherent resistor, a third branch, a fourth branch and a sampling processing device;
The first branch comprises a first switch and a first standard resistor which are connected in series, the second branch comprises a second switch and a second standard resistor which are connected in series, one end of the first branch and one end of the second branch both receive power supply voltage, and the other end of the first branch and the other end of the second branch are both connected with the first end of the inherent resistor, wherein the resistance values of the first standard resistor and the second standard resistor are different;
The third branch comprises a third switch and a test capacitor which are connected in series, the fourth branch comprises a stray capacitor, one end of the third branch and one end of the fourth branch are connected with the second end of the inherent resistor and are also connected with the sampling processing device, and the other end of the third branch and the other end of the fourth branch are grounded.
2. The charge-discharge method test capacitor circuit according to claim 1, wherein the sampling processing device comprises a 555 timer and a processing module, the 555 timer comprises a power supply end, a high trigger end and an output end, the power supply end of the 555 timer receives the power supply voltage, the high trigger end of the 555 timer is connected with the second end of the inherent resistor, the processing module comprises a receiving end, and the receiving end of the processing module is connected with the output end of the 555 timer.
3. The charge-discharge method test capacitor circuit of claim 2, wherein the 555 timer further comprises a low trigger terminal, the low trigger terminal of the 555 timer being configured to receive an external pulse trigger signal.
4. A charge and discharge method test capacitor circuit according to claim 3, wherein the processing module further comprises a trigger terminal, the trigger terminal of the processing module being connected to the low trigger terminal of the 555 timer.
5. The charge-discharge method test capacitor circuit of claim 4, wherein a low trigger terminal of said 555 timer receives said supply voltage via a pull-up resistor.
6. A method for testing capacitance by a charge-discharge method, which is applied to the circuit for testing capacitance by a charge-discharge method according to any one of claims 1 to 5, and comprises the steps of:
controlling the third switch to be opened, the first switch to be closed and the second switch to be opened, and obtaining a first charging time of the stray capacitance from a first voltage to a second voltage;
controlling the third switch to be opened, the first switch to be opened and the second switch to be closed, and obtaining second charging time of the stray capacitance from the first voltage to the second voltage;
controlling the third switch to be closed, the first switch to be closed and the second switch to be opened, and obtaining third charging time of the test capacitor from the first voltage to the second voltage;
Controlling the third switch to be closed, the first switch to be opened and the second switch to be closed, and obtaining fourth charging time of the test capacitor from the first voltage to the second voltage;
And determining the capacitance value of the test capacitor according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage and the second voltage.
7. The method according to claim 6, wherein determining the capacitance value of the test capacitor according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage, and the second voltage includes determining the capacitance value of the test capacitor according to a formula C=(Tw1'-Tw2')/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2))))-(Tw1-Tw2)/((R1-R2)*ln((Vcc-Uc(t1))/(Vcc-Uc(t2)))),, wherein C represents the capacitance value of the test capacitor, R1 represents the resistance value of the first standard resistor, R2 represents the resistance value of the second standard resistor, tw1 represents the first charging time, tw2 represents the second charging time, tw1 'represents the third charging time, tw2' represents the fourth charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage.
8. The method of testing a capacitor according to claim 6, wherein determining the capacitance value of the test capacitor according to the first charging time, the second charging time, the third charging time, the fourth charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage, and the second voltage comprises:
Determining the capacitance value of the stray capacitor according to the first charging time, the second charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage and the second voltage;
And determining the capacitance value of the test capacitor according to the third charging time, the fourth charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage, the second voltage and the capacitance value of the stray capacitor.
9. The method of testing capacitance according to claim 8, wherein determining the capacitance value of the stray capacitance according to the first charging time, the second charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage, and the second voltage comprises:
Determining a capacitance value of the stray capacitance according to a formula cs= (Tw 1-Tw 2)/((R1-R2) ×ln ((Vcc-Uc (t 1))/(Vcc-Uc (t 2)))), wherein Cs represents the capacitance value of the stray capacitance, R1 represents the resistance value of the first standard resistor, R2 represents the resistance value of the second standard resistor, tw1 represents the first charging time, tw2 represents the second charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage.
10. The method of testing capacitance according to claim 8, wherein determining the capacitance value of the test capacitance according to the third charging time, the fourth charging time, the resistance value of the first standard resistor, the resistance value of the second standard resistor, the power supply voltage, the first voltage, the second voltage, and the capacitance value of the stray capacitance comprises:
Determining a capacitance value of the test capacitor according to a formula c= (Tw 1'-Tw 2')/(R1-R2)/(Vcc-Uc (t 1))/(Vcc-Uc (t 2))))) -Cs, wherein C represents a capacitance value of the test capacitor, cs represents a capacitance value of the stray capacitor, R1 represents a resistance value of the first standard resistor, R2 represents a resistance value of the second standard resistor, tw1 'represents the third charging time, tw2' represents the fourth charging time, vcc represents the power supply voltage, uc (t 1) represents the first voltage, and Uc (t 2) represents the second voltage.
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| CN108614161A (en) * | 2018-07-27 | 2018-10-02 | 青岛澳科仪器有限责任公司 | A kind of capacitance measurement system |
| CN113295930A (en) * | 2021-05-31 | 2021-08-24 | 西安电子科技大学 | Micro-watt level micro-capacitance measuring method and circuit |
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| CN108614161A (en) * | 2018-07-27 | 2018-10-02 | 青岛澳科仪器有限责任公司 | A kind of capacitance measurement system |
| CN113295930A (en) * | 2021-05-31 | 2021-08-24 | 西安电子科技大学 | Micro-watt level micro-capacitance measuring method and circuit |
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