CN118918818B

CN118918818B - Shift register, driving method thereof and display device

Info

Publication number: CN118918818B
Application number: CN202411194864.1A
Authority: CN
Inventors: 李�根; 刘梦晴; 周庄奇; 杜正兴; 杨姮; 熊小强; 王淮民; 黄应龙; 张锴
Original assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Current assignee: BOE Technology Group Co Ltd; Chengdu BOE Optoelectronics Technology Co Ltd
Priority date: 2024-08-28
Filing date: 2024-08-28
Publication date: 2026-01-27
Anticipated expiration: 2044-08-28
Also published as: CN118918818A

Abstract

This invention provides a shift register and its driving method, as well as a display device, relating to the field of display technology, for improving the stability of the gate drive signal output by the shift register unit. In the shift register, a first output sub-circuit, under the control of a first output node, controls the electrical connection between the gate drive signal output terminal and the first clock signal input terminal to be turned on or off. A first output node control sub-circuit, under the control of a first level signal input at a first level signal input terminal, controls the electrical connection between the first node and the first output node to be turned on or off, and also, under the control of a second node, controls the electrical connection between the first output node and the first level signal input terminal to be turned on or off. A first cascade control sub-circuit, under the control of the potential of the second node, controls the electrical connection between the second clock signal input terminal and the cascade signal output terminal to be turned on or off.

Description

Shift register, driving method thereof and display device

Technical Field

The present invention relates to the field of display technologies, and in particular, to a shift register, a driving method thereof, and a display device.

Background

Along with the continuous development of display technology, the application fields of display products are becoming wider, and the display quality requirements of people on the display products are becoming higher. In order to better realize a narrow-frame display product, a GOA (Gate On Array) technology is adopted in the display product, namely a Gate driving circuit is directly manufactured On an Array substrate, and sub-pixel rows of a display area are driven by all levels of shift register units included in the Gate driving circuit, so that the display function of the display product is realized. However, the stability of the gate driving signal output by the conventional shift register unit is poor, and how to improve the stability of the gate driving signal output by the shift register unit is a technical problem to be solved.

Disclosure of Invention

The invention aims to provide a shift register, a driving method thereof and a display device, which are used for improving the stability of a grid driving signal output by a shift register unit.

In order to achieve the above object, the present invention provides the following technical solutions:

a first aspect of the present invention provides a shift register comprising:

The first output sub-circuit is respectively coupled with the grid driving signal output end, the first clock signal input end and the first output node and is used for controlling to be connected or disconnected with the electric connection between the grid driving signal output end and the first clock signal input end under the control of the potential of the first output node;

the first output node control sub-circuit is respectively coupled with a first node, a second node, the first output node and a first level signal input end, and is used for controlling to conduct or break the electric connection between the first node and the first output node under the control of a first level signal input by the first level signal input end and controlling to conduct or break the electric connection between the first output node and the first level signal input end under the control of the potential of the second node;

The first cascade control sub-circuit is respectively coupled with the cascade signal output end, the second clock signal input end and the second node and is used for controlling to be connected or disconnected with the electric connection between the second clock signal input end and the cascade signal output end under the control of the potential of the second node;

And the first isolation control sub-circuit is used for controlling to conduct or break the electric connection between the first node and the second node.

Optionally, the method further comprises:

The second output sub-circuit is respectively coupled with the grid driving signal output end, the second level signal input end and the second output node and is used for controlling to be connected or disconnected with the electric connection between the grid driving signal output end and the second level signal input end under the control of the potential of the second output node;

the fourth node control sub-circuit is respectively coupled with the first node, the fourth node, the fifth node and the third level signal input end, is also coupled with the fourth clock signal input end or the second clock signal input end, and is used for controlling to be connected or disconnected with the electric connection between the fourth node and the third level signal input end under the control of the electric potential of the first node;

the fourth node control sub-circuit is further used for controlling to conduct or break the electrical connection between the fourth node and the fourth clock signal input end under the control of the potential of the fifth node, or controlling to conduct or break the electrical connection between the fourth node and the second clock signal input end under the control of the potential of the fifth node;

And the second output node control sub-circuit is respectively coupled with the second output node and the fifth node and is used for controlling the connection or disconnection of the electrical connection between the second output node and the fifth node under the control of the potential of the fifth node.

Optionally, the method further comprises:

the second isolation control sub-circuit is respectively coupled with the first level signal input end, the second output node and the sixth node and is used for controlling to conduct or break the electric connection between the second output node and the sixth node under the control of the first level signal input by the first level signal input end;

The third isolation control sub-circuit is respectively coupled with the first level signal input end, the fifth node and the seventh node and is used for controlling to conduct or break the electric connection between the fifth node and the seventh node under the control of the first level signal input by the first level signal input end;

And the second input sub-circuit is respectively coupled with the third clock signal input end, the sixth node, the seventh node and the input node, and is used for controlling to conduct or break the electrical connection between the sixth node and the input node under the control of the third clock signal input by the third clock signal input end and controlling to conduct or break the electrical connection between the seventh node and the input node under the control of the third clock signal input by the third clock signal input end.

Optionally, the input node is directly coupled to the first level signal input terminal, and the shift register further comprises:

A sixth node control sub-circuit, coupled to the first node, the third clock signal input terminal, and the sixth node, respectively, for controlling to turn on or off an electrical connection between the third clock signal input terminal and the sixth node under the control of the potential of the first node;

and the seventh node control sub-circuit is respectively coupled with the first node, the third clock signal input end and the seventh node and is used for controlling to conduct or break the electric connection between the third clock signal input end and the seventh node under the control of the potential of the first node.

Optionally, the method further comprises:

the first input node control sub-circuit is respectively coupled with the initial signal input end, the third level signal input end and the input node and is used for controlling to be connected or disconnected with the electrical connection between the third level signal input end and the input node under the control of an initial signal input by the initial signal input end;

the second input node control sub-circuit is respectively coupled with the eighth node, the first level signal input end and the input node and is used for controlling to conduct or break the electric connection between the first level signal input end and the input node under the control of the potential of the eighth node;

And the eighth node control sub-circuit is respectively coupled with the third clock signal input end, the initial signal input end, the eighth node and the third level signal input end, and is used for controlling the potential of the eighth node according to the third clock signal input by the third clock signal input end and controlling the connection or disconnection of the electrical connection between the third level signal input end and the eighth node under the control of the initial signal input by the initial signal input end.

A sixth node control sub-circuit, coupled to the first node, the third level signal input terminal, and the sixth node, respectively, for controlling to turn on or off an electrical connection between the third level signal input terminal and the sixth node under the control of the potential of the first node;

A seventh node control sub-circuit, coupled to the first node, the third level signal input terminal, and the seventh node, respectively, for controlling to turn on or off an electrical connection between the third level signal input terminal and the seventh node under the control of the potential of the first node;

A coupling sub-circuit, the second input sub-circuit being coupled to a ninth node, the ninth node being coupled to the third clock signal input through the coupling sub-circuit;

And the ninth node control sub-circuit is respectively coupled with the ninth node, the initial signal input end and the third level signal input end and is used for controlling to conduct or break the electric connection between the third level signal input end and the ninth node under the control of the initial signal input by the initial signal input end.

Optionally, also include

And the first input sub-circuit is respectively coupled with the initial signal input end, the third clock signal input end and the first node and is used for controlling to conduct or break the electric connection between the initial signal input end and the first node under the control of the third clock signal input by the third clock signal input end.

Optionally, the method further comprises:

And the first node control sub-circuit is respectively coupled with the first node, the sixth node, the third level signal input end and the second clock signal input end and is used for controlling to be connected or disconnected with the electric connection between the first node and the third level signal input end under the common control of the potential of the sixth node and the second clock signal input by the second clock signal input end.

Optionally, the method further comprises:

The second cascade control sub-circuit is respectively coupled with a sixth node, a cascade signal output end and a third level signal input end, and is used for controlling the connection or disconnection of the electric connection between the cascade signal output end and the third level signal input end under the control of the electric potential of the sixth node, and is also used for controlling the electric potential of the sixth node according to a third level signal input by the third level signal input end.

Optionally, the first output sub-circuit includes an eleventh transistor, a gate of the eleventh transistor is coupled to the first output node, a first pole of the eleventh transistor is coupled to the first clock signal input terminal, and a second pole of the eleventh transistor is coupled to the gate drive signal output terminal;

The first output node control subcircuit includes a sixteenth transistor having a gate coupled to the first level signal input, a first pole coupled to the first node, and a nineteenth transistor having a second pole coupled to the first output node; a gate of the nineteenth transistor is coupled to the second node, a first pole of the nineteenth transistor is coupled to the first level signal input, and a second pole of the nineteenth transistor is coupled to the first output and node;

The first cascade control sub-circuit comprises an eighth transistor and a second capacitor, wherein the grid electrode of the eighth transistor is coupled with the second node, the first pole of the eighth transistor is coupled with the second clock signal input end, and the second pole of the eighth transistor is coupled with the cascade signal output end;

The first isolation control sub-circuit includes a sixth transistor having a gate coupled to the first level signal input, a first pole coupled to the first node, and a second pole coupled to the second node.

Optionally, the second output sub-circuit includes a tenth transistor, a gate of the tenth transistor is coupled to the second output node, a first pole of the tenth transistor is coupled to the second level signal input terminal, and a second pole of the tenth transistor is coupled to the gate driving signal output terminal;

The fourth node control sub-circuit comprises a twelfth transistor, a thirteenth transistor and a third capacitor, wherein the grid electrode of the twelfth transistor is coupled with the fifth node, the first electrode of the twelfth transistor is coupled with the fourth clock signal input end or the second clock signal input end, the second electrode of the twelfth transistor is coupled with the fourth node, the grid electrode of the thirteenth transistor is coupled with the first node, the first electrode of the thirteenth transistor is coupled with the third level signal input end, the second electrode of the thirteenth transistor is coupled with the fourth node, the first end of the third capacitor is coupled with the fourth node, and the second end of the third capacitor is coupled with the fifth node;

the second output node control sub-circuit includes a fourteenth transistor having a gate coupled to the fifth node, a first pole coupled to the fifth node, and a second pole coupled to the second output node.

Optionally, the second isolation control subcircuit includes a ninth transistor having a gate coupled to the first level signal input, a first pole coupled to the sixth node, a second pole coupled to the second output node;

The third isolation control sub-circuit comprises a fifteenth transistor, a gate of the fifteenth transistor is coupled with the first level signal input end, a first pole of the fifteenth transistor is coupled with the seventh node, and a second pole of the fifteenth transistor is coupled with the fifth node;

The second input sub-circuit comprises a second transistor and a seventeenth transistor, wherein the grid electrode of the second transistor is coupled with the third clock signal input end, the first pole of the second transistor is coupled with the first level signal input end, the second pole of the second transistor is coupled with the sixth node, the grid electrode of the seventeenth transistor is coupled with the third clock signal input end, the first pole of the seventeenth transistor is coupled with the first level signal input end, and the second pole of the seventeenth transistor is coupled with the seventh node.

Optionally, the sixth node control sub-circuit includes a third transistor, a gate of the third transistor is coupled to the first node, a first pole of the third transistor is coupled to the third clock signal input terminal, and a second pole of the third transistor is coupled to the sixth node;

the seventh node control sub-circuit includes an eighteenth transistor having a gate coupled to the first node, a first pole coupled to the third clock signal input, and a second pole coupled to the seventh node.

Optionally, the first input node control subcircuit includes a twentieth transistor having a gate coupled to the start signal input, a first pole coupled to the third level signal input, and a second pole coupled to the input node;

The second input node control sub-circuit comprises a twenty-first transistor, a gate of the twenty-first transistor is coupled with the eighth node, a first pole of the twenty-first transistor is coupled with the first level signal input terminal, and a second pole of the twenty-first transistor is coupled with the input node;

The eighth node control sub-circuit comprises a twenty-second transistor and a fourth capacitor, wherein the grid electrode of the twenty-second transistor is coupled with the initial signal input end, the first electrode of the twenty-second transistor is coupled with the third level signal input end, the second electrode of the twenty-second transistor is coupled with the eighth node, the first end of the fourth capacitor is coupled with the third clock signal input end, and the second end of the fourth capacitor is coupled with the eighth node.

Optionally, the sixth node control sub-circuit includes a third transistor, a gate of the third transistor is coupled to the first node, a first pole of the third transistor is coupled to the third level signal input terminal, and a second pole of the third transistor is coupled to the sixth node;

The seventh node control sub-circuit comprises an eighteenth transistor, a gate of the eighteenth transistor is coupled with the first node, a first pole of the eighteenth transistor is coupled with the third level signal input terminal, and a second pole of the eighteenth transistor is coupled with the seventh node;

The coupling sub-circuit comprises a fifth capacitor, a first end of the fifth capacitor is coupled with the third clock signal input end, and a second end of the fifth capacitor is coupled with the ninth node;

The ninth node control sub-circuit includes a thirteenth transistor, a gate of the twenty-third transistor is coupled to the start signal input terminal, a first pole of the twenty-third transistor is coupled to the third level signal input terminal, and a second pole of the twenty-third transistor is coupled to the ninth node.

Optionally, the first input sub-circuit includes a first transistor, a gate of the first transistor is coupled to the third clock signal input terminal, a first pole of the first transistor is coupled to the start signal input terminal, and a second pole of the first transistor is coupled to the first node.

Optionally, the first node control sub-circuit includes a fourth transistor and a fifth transistor, wherein a gate of the fourth transistor is coupled to the sixth node, a first pole of the fourth transistor is coupled to the third level signal input terminal, a second pole of the fourth transistor is coupled to the first pole of the fifth transistor, a gate of the fifth transistor is coupled to the second clock signal input terminal, and a second pole of the fifth transistor is coupled to the first node.

Optionally, the second cascade control sub-circuit includes a seventh transistor and a first capacitor, where a gate of the seventh transistor is coupled to the sixth node, a first pole of the seventh transistor is coupled to the third level signal input terminal, a second pole of the seventh transistor is coupled to the cascade signal output terminal, a first end of the first capacitor is coupled to the third level signal input terminal, and a second end of the first capacitor is coupled to the sixth node.

Based on the technical scheme of the shift register, a second aspect of the present invention provides a driving method of a shift register, which is applied to the shift register, and the driving method includes:

the first output sub-circuit controls to conduct or break the electric connection between the grid driving signal output end and the first clock signal input end under the control of the potential of the first output node;

the first output node control sub-circuit controls to conduct or break the electric connection between the first node and the first output node under the control of a first level signal input by the first level signal input end, and controls to conduct or break the electric connection between the first output node and the first level signal input end under the control of the potential of the second node;

the first cascade control sub-circuit controls to be connected or disconnected with the electric connection between the second clock signal input end and the cascade signal output end under the control of the potential of the second node, and controls the potential of the second node according to the cascade signal output by the cascade signal output end;

the first isolation control sub-circuit controls and conducts electrical connection between the first node and the second node under the control of the first level signal.

Optionally, the driving method further includes:

The second output sub-circuit controls to conduct or break the electric connection between the grid driving signal output end and the second level signal input end under the control of the potential of the second output node;

The fourth node control sub-circuit controls to conduct or break the electric connection between the fourth node and the third level signal input end under the control of the potential of the first node;

The fourth node control sub-circuit is also used for controlling to conduct or break the electrical connection between the fourth node and the fourth clock signal input end under the control of the potential of the fifth node, or controlling to conduct or break the electrical connection between the fourth node and the second clock signal input end under the control of the potential of the fifth node;

the second output node control sub-circuit controls to turn on or off an electrical connection between the second output node and the fifth node under control of the potential of the fifth node.

Based on the technical scheme of the shift register, a third aspect of the invention provides a display device, which comprises the shift register.

In the technical scheme provided by the invention, under the condition that the cascade signal output end and the second clock signal input end are controlled to be conducted by the potential of the second node, the second clock signal input by the second clock signal input end is transmitted to the cascade signal output end, and then the potential of the second node is influenced. Because the electric potential of the second node can control to be conducted or disconnected the electric connection between the first output node and the first level signal input end, when the electric potential of the second node becomes lower under the condition of being influenced, the electric connection between the first output node and the first level signal input end can be better controlled to be conducted, the electric potential of the first output node is controlled to be an effective electric potential, the effective electric potential can be conducted to be electrically connected between the grid driving signal output end and the first clock signal input end, signals of the grid driving signal output end and signals input by the first clock signal input end are kept consistent, and the signal stability output by the grid driving signal output end is ensured.

When the potential of the second node becomes higher under the condition of being influenced, the potential of the first node is influenced under the control of the first isolation control sub-circuit, and the first output node control sub-circuit can control to disconnect the electric connection between the first node and the first output node under the control of the first level signal input by the first level signal input end, so that the potential of the first output node can avoid being influenced by the potential of the first node, the first output node can keep the original state, and the control state of the first output node to the first output sub-circuit is kept, so that the signal stability output by the gate driving signal output end is better maintained.

Drawings

The accompanying drawings, which are included to provide a further understanding of the invention and are incorporated in and constitute a part of this specification, illustrate embodiments of the invention and together with the description serve to explain the invention and do not constitute a limitation on the invention. In the drawings:

FIG. 1 is a schematic diagram of a shift register according to an embodiment of the present invention;

FIG. 2 is a schematic diagram of a shift register according to an embodiment of the present invention;

FIG. 3 is a schematic diagram of a third configuration of a shift register according to an embodiment of the present invention;

FIG. 4 is a schematic diagram of a fourth configuration of a shift register according to an embodiment of the present invention;

FIG. 5 is a specific circuit configuration corresponding to FIG. 4;

FIG. 6 is a timing diagram corresponding to FIG. 5;

FIG. 7 is a schematic diagram of a shift register cascade according to an embodiment of the present invention;

FIG. 8 is a schematic diagram of a shift register according to an embodiment of the present invention;

fig. 9 is a specific circuit configuration diagram corresponding to fig. 8;

FIG. 10 is a timing diagram of the driving of FIG. 9;

FIG. 11 is a schematic diagram of a sixth structure of a shift register according to an embodiment of the present invention;

Fig. 12 is a specific circuit configuration diagram corresponding to fig. 11.

Detailed Description

In order to further explain the shift register, the driving method thereof and the display device provided by the embodiment of the invention, the following detailed description is given with reference to the accompanying drawings.

Referring to fig. 1 to 12, an embodiment of the present invention provides a shift register, including:

A first output sub-circuit 10 coupled to the gate driving signal output terminal OUT, the first clock signal input terminal GCK, and the first output node Q3, respectively, for controlling to turn on or off an electrical connection between the gate driving signal output terminal OUT and the first clock signal input terminal GCK under the control of the potential of the first output node Q3;

The first output node control sub-circuit 11 is coupled with the first node Q1, the second node Q2, the first output node Q3 and the first level signal input end VGL1 respectively, and is used for controlling to conduct or break the electrical connection between the first node Q1 and the first output node Q3 under the control of the first level signal input by the first level signal input end VGL1, and is also used for controlling to conduct or break the electrical connection between the first output node Q3 and the first level signal input end VGL1 under the control of the potential of the second node Q2;

a first cascade control sub-circuit 12, coupled to the cascade signal output terminal CR, the second clock signal input terminal CKB, and the second node Q2, respectively, for controlling to connect or disconnect the electrical connection between the second clock signal input terminal CKB and the cascade signal output terminal CR under the control of the potential of the second node Q2;

The first isolation control subcircuit 13 is used to control the connection between the first node Q1 and the second node Q2 to be turned on or off.

The first cascade control sub-circuit 12 is further configured to control the potential of the second node Q2 according to a cascade signal output from the cascade signal output terminal CR.

The first isolation control sub-circuit 13 is coupled to the first level signal input terminal VGL1, the first node Q1, and the second node Q2, respectively, and is configured to control to switch on or off an electrical connection between the first node Q1 and the second node Q2 under the control of the first level signal.

Illustratively, the first output sub-circuit 10 includes an eleventh transistor T11, a gate of the eleventh transistor T11 is coupled to the first output node Q3, a first pole of the eleventh transistor T11 is coupled to the first clock signal input terminal GCK, and a second pole of the eleventh transistor T11 is coupled to the gate driving signal output terminal OUT. The eleventh transistor T11 is configured to control on or off an electrical connection between the gate driving signal output terminal OUT and the first clock signal input terminal GCK under control of the potential of the first output node Q3.

Illustratively, the first output node control sub-circuit 11 includes a sixteenth transistor T16 and a nineteenth transistor T19, wherein the sixteenth transistor T16 has a gate coupled to the first level signal input terminal VGL1, a first pole coupled to the first node Q1, a second pole coupled to the first output node Q3, the nineteenth transistor T16 has a gate coupled to the second node Q2, a first pole coupled to the first level signal input terminal VGL1, and a second pole coupled to the first output node Q3. The sixteenth transistor T16 is configured to control on or off an electrical connection between the first node Q1 and the first output node Q3 under control of a first level signal input by the first level signal input terminal VGL1, and the nineteenth transistor T19 is configured to control on or off an electrical connection between the first output node Q3 and the first level signal input terminal VGL1 under control of a potential of the second node Q2.

The first cascade control sub-circuit 12 includes an eighth transistor T8 and a second capacitor C2, where a gate of the eighth transistor T8 is coupled to the second node Q2, a first pole of the eighth transistor T8 is coupled to the second clock signal input terminal CKB, a second pole of the eighth transistor T8 is coupled to the cascade signal output terminal CR, a first end of the second capacitor C2 is coupled to the cascade signal output terminal CR, a second end of the second capacitor C2 is coupled to the second node Q2, the eighth transistor T8 is configured to control the electrical connection between the second clock signal input terminal CKB and the cascade signal output terminal CR to be turned on or off under the control of the potential of the second node Q2, and the second capacitor C2 is configured to control the potential of the second node Q2 according to the cascade signal output by the cascade signal output terminal CR.

Illustratively, the first isolation control sub-circuit 13 includes a sixth transistor T6, the gate of the sixth transistor T6 is coupled to the first level signal input terminal VGL1, the first pole of the sixth transistor T6 is coupled to the first node Q1, and the second pole of the sixth transistor T6 is coupled to the second node Q2. The sixth transistor T6 controls to turn on or off the electrical connection between the first node Q1 and the second node Q2 under the control of the first level signal.

In the shift register provided by the embodiment of the invention, the transistors included in each sub-circuit can be P-type transistors, but the shift register is not limited to the P-type transistors.

According to the specific structure of the shift register, in the shift register provided by the embodiment of the invention, when the cascade signal output terminal CR and the second clock signal input terminal CKB are turned on by the potential control of the second node Q2, the second clock signal input by the second clock signal input terminal CKB is transmitted to the cascade signal output terminal CR, so that the potential of the second node Q2 is affected.

Because the electric potential of the second node Q2 can control to turn on or off the electric connection between the first output node Q3 and the first level signal input terminal VGL1, when the electric potential of the second node Q2 becomes lower under the condition of being affected, the electric connection between the first output node Q3 and the first level signal input terminal VGL1 can be better controlled to be turned on, the electric potential of the first output node Q3 is controlled to be an effective electric potential, and the effective electric potential can be turned on to electrically connect between the gate driving signal output terminal OUT and the first clock signal input terminal GCK, so that the signal of the gate driving signal output terminal OUT is kept consistent with the signal input by the first clock signal input terminal GCK, and the signal stability output by the gate driving signal output terminal OUT is ensured.

When the potential of the second node Q2 becomes higher under the influence of the potential, the potential of the first node Q1 is influenced under the control of the first isolation control sub-circuit 13, and at this time, the first output node control sub-circuit 11 can control to disconnect the electrical connection between the first node Q1 and the first output node Q3 under the control of the first level signal input by the first level signal input terminal VGL1, so that the potential of the first output node Q3 can avoid being influenced by the potential of the first node Q1, and the first output node Q3 can keep the original state, and the control state of the first output node Q3 on the first output sub-circuit 10 is kept, thereby better maintaining the stability of the signal output by the gate driving signal output terminal OUT.

As shown in fig. 2 to 12, in some embodiments, the shift register further includes:

A second output sub-circuit 14 coupled to the gate driving signal output terminal OUT, the second level signal input terminal VGL2, and the second output node QB2, respectively, for controlling to turn on or off an electrical connection between the gate driving signal output terminal OUT and the second level signal input terminal VGL2 under the control of the potential of the second output node QB 2;

A fourth node control sub-circuit 15 coupled to the first node Q1, the fourth node GD, the fifth node QB3 and the third level signal input terminal VGH, respectively, the fourth node control sub-circuit 15 further coupled to the fourth clock signal input terminal CKA2 or the second clock signal input terminal CKB for controlling to turn on or off the electrical connection between the fourth node GD and the third level signal input terminal VGH under the control of the potential of the first node Q1;

The fourth node control sub-circuit 15 is further configured to control to switch on or off an electrical connection between the fourth node GD and the fourth clock signal input terminal CKA2 under control of the potential of the fifth node QB3, or to switch on or off an electrical connection between the fourth node GD and the second clock signal input terminal CKB under control of the potential of the fifth node QB 3;

A second output node control sub-circuit 16, coupled to the second output node QB2 and the fifth node QB3, respectively, for controlling the connection and disconnection of the electrical connection between the second output node QB2 and the fifth node QB3 under the control of the potential of the fifth node QB 3.

The second output sub-circuit 14 includes a tenth transistor T10, a gate of the tenth transistor T10 is coupled to the second output node QB2, a first pole of the tenth transistor T10 is coupled to the second level signal input terminal VGL2, a second pole of the tenth transistor T10 is coupled to the gate driving signal output terminal OUT, and the tenth transistor T10 is configured to control on or off an electrical connection between the gate driving signal output terminal OUT and the second level signal input terminal VGL2 under control of a potential of the second output node QB 2.

The fourth node control sub-circuit 15 includes a twelfth transistor T12, a thirteenth transistor T13, and a third capacitor C3, wherein the gate of the twelfth transistor T12 is coupled to the fifth node QB3, the first pole of the twelfth transistor T12 is coupled to the fourth clock signal input CKA2 or the second clock signal input CKB, the second pole of the twelfth transistor T12 is coupled to the fourth node GD, the gate of the thirteenth transistor T13 is coupled to the first node Q1, the first pole of the thirteenth transistor T13 is coupled to the third level signal input VGH, the second pole of the thirteenth transistor T13 is coupled to the fourth node GD, the first end of the third capacitor C3 is coupled to the fourth node GD, and the second end of the third capacitor C3 is coupled to the fifth node QB 3.

The thirteenth transistor T13 is configured to control to turn on or off an electrical connection between the fourth node GD and the third level signal input terminal VGH under the control of the potential of the first node Q1, the third capacitor C3 is configured to control the potential of the fifth node QB3 according to the potential of the fourth node GD, the twelfth transistor T12 is configured to control to turn on or off an electrical connection between the fourth node GD and the fourth clock signal input terminal CKA2 under the control of the potential of the fifth node QB3, or the twelfth transistor T12 is configured to control to turn on or off an electrical connection between the fourth node GD and the second clock signal input terminal CKB under the control of the potential of the fifth node QB 3.

Illustratively, the second output node control subcircuit 16 includes a fourteenth transistor T14, the gate of the fourteenth transistor T14 being coupled to the fifth node QB3, the first pole of the fourteenth transistor T14 being coupled to the fifth node QB3, the second pole of the fourteenth transistor T14 being coupled to the second output node QB 2. The fourteenth transistor T14 is for controlling to turn on or off the electrical connection between the second output node QB2 and the fifth node QB3 under the control of the potential of the fifth node QB 3.

Optionally, when the fourth node control sub-circuit 15 is coupled to the second clock signal input terminal CKB, the time when the potential of the second output node QB2 is pulled down to be lower is delayed by 1H relative to the case of the fourth clock signal input terminal CKA 2.

In the shift register provided in the above embodiment, when the electrical connection between the fourth node GD and the third level signal input terminal VGH is controlled to be disconnected under the control of the potential of the first node Q1, and the electrical connection between the fourth node GD and the second clock signal input terminal CKB or the fourth clock signal input terminal CKA2 is controlled to be conducted under the control of the potential of the fifth node QB3, the potential of the fourth node GD is further controlled to control the potential of the fifth node QB 3.

When the potential of the fifth node QB3 becomes lower due to the influence, the second output node control sub-circuit 16 can better control and turn on the electrical connection between the second output node QB2 and the fifth node QB3, control the potential of the second output node QB2 at an effective potential, and turn on the electrical connection between the gate driving signal output terminal OUT and the second level signal input terminal VGL2, so that the signal of the gate driving signal output terminal OUT is consistent with the signal input by the second level signal input terminal VGL2, and ensure the signal stability output by the gate driving signal output terminal OUT.

As shown in fig. 3 to 12, in some embodiments, the shift register further includes:

A second isolation control sub-circuit 17 coupled to the first level signal input terminal VGL1, the second output node QB2, and the sixth node QB1, respectively, for controlling to turn on or off the electrical connection between the second output node QB2 and the sixth node QB1 under the control of the first level signal input from the first level signal input terminal VGL 1;

A third isolation control sub-circuit 18 coupled to the first level signal input terminal VGL1, the fifth node QB3, and the seventh node QB4, respectively, for controlling to turn on or off the electrical connection between the fifth node QB3 and the seventh node QB4 under the control of the first level signal input by the first level signal input terminal VGL 1;

A second input sub-circuit 19 coupled to the third clock signal input terminal CKA, the sixth node QB1, the seventh node QB4 and the input node QB5, respectively, for controlling the connection between the sixth node QB1 and the input node QB5 under the control of the third clock signal input by the third clock signal input terminal CKA, and for controlling the connection between the seventh node QB4 and the input node QB5 under the control of the third clock signal input by the third clock signal input terminal CKA.

The second isolation control sub-circuit 17 includes a ninth transistor T9, a gate of the ninth transistor T9 is coupled to the first level signal input terminal VGL1, a first pole of the ninth transistor T9 is coupled to the sixth node QB1, a second pole of the ninth transistor T9 is coupled to the second output node QB2, and the ninth transistor T9 is configured to control on or off an electrical connection between the second output node QB2 and the sixth node QB1 under control of the first level signal input from the first level signal input terminal VGL 1.

The third isolation control sub-circuit 18 includes a fifteenth transistor T15, a gate of the fifteenth transistor T15 is coupled to the first level signal input terminal VGL1, a first pole of the fifteenth transistor T15 is coupled to the seventh node QB4, a second pole of the fifteenth transistor T15 is coupled to the fifth node QB3, and the fifteenth transistor T15 is configured to control on or off an electrical connection between the fifth node QB3 and the seventh node QB4 under control of a first level signal input from the first level signal input terminal VGL 1.

Illustratively, the second input sub-circuit 19 includes a second transistor T2 and a seventeenth transistor T17, wherein the gate of the second transistor T2 is coupled to the third clock signal input terminal CKA, the first pole of the second transistor T2 is coupled to the first level signal input terminal VGL1, the second pole of the second transistor T2 is coupled to the sixth node QB1, the gate of the seventeenth transistor T17 is coupled to the third clock signal input terminal CKA, the first pole of the seventeenth transistor T17 is coupled to the first level signal input terminal VGL1, and the second pole of the seventeenth transistor T17 is coupled to the seventh node QB 4. The second transistor T2 is configured to control to switch on or off an electrical connection between the sixth node QB1 and the input node QB5 under control of a third clock signal input to the third clock signal input terminal CKA, and the seventeenth transistor T17 is configured to control to switch on or off an electrical connection between the seventh node QB4 and the input node QB5 under control of a third clock signal input to the third clock signal input terminal CKA.

In the shift register provided in the above embodiment, by arranging the second input sub-circuit 19, the second isolation control sub-circuit 17, and the third isolation control sub-circuit 18 such that the second input sub-circuit 19 and the second isolation control sub-circuit 17 are formed as a first transmission path, the second input sub-circuit 19 and the third isolation control sub-circuit 18 are formed as a second transmission path, the potential of the input node QB5 can be transmitted to the second output node QB2 through two transmission paths, thereby controlling the second output sub-circuit 14 to realize a stable output function.

Moreover, by the above arrangement, when the fifth node QB3 is controlled by the fourth node GD, the potential of the fifth node QB3 does not directly affect the sixth node QB1, so that stability of the transmission signal on the first transmission path is ensured, and therefore, when the second output node QB2 is controlled by the transmission signal on the first transmission path, the second output node QB2 has better stability, and further, the second output sub-circuit 14 is controlled to realize a stable output function.

As shown in fig. 4 and 5, in some embodiments, the input node QB5 is directly coupled to the first level signal input terminal VGL1, and the shift register further comprises:

A sixth node control sub-circuit 21 coupled to the first node Q1, the third clock signal input terminal CKA and the sixth node QB1, respectively, for controlling to turn on or off the electrical connection between the third clock signal input terminal CKA and the sixth node QB1 under the control of the potential of the first node Q1;

the seventh node control sub-circuit 22 is coupled to the first node Q1, the third clock signal input terminal CKA and the seventh node QB4, respectively, and is configured to control to turn on or off the electrical connection between the third clock signal input terminal CKA and the seventh node QB4 under the control of the potential of the first node Q1.

Illustratively, the sixth node control sub-circuit 21 includes a third transistor T3, the gate of the third transistor T3 is coupled to the first node Q1, the first pole of the third transistor T3 is coupled to the third clock signal input CKA, the second pole of the third transistor T3 is coupled to the sixth node QB1, and the third transistor T3 is configured to control the electrical connection between the third clock signal input CKA and the sixth node QB1 to be turned on or off under the control of the potential of the first node Q1.

Illustratively, the seventh node control sub-circuit 22 includes an eighteenth transistor T18, the gate of the eighteenth transistor T18 is coupled to the first node Q1, the first pole of the eighteenth transistor T18 is coupled to the third clock signal input terminal CKA, the second pole of the eighteenth transistor T18 is coupled to the seventh node QB4, and the eighteenth transistor T18 is configured to control on or off of the electrical connection between the third clock signal input terminal CKA and the seventh node QB4 under the control of the potential of the first node Q1.

The shift register further includes a sixth node control sub-circuit 21 and a seventh node control sub-circuit 22, so that the potential of the sixth node QB1 can be controlled by the sixth node control sub-circuit 21 and the potential of the seventh node QB4 can be controlled by the seventh node control sub-circuit 22 under the control of the potential of the first node Q1, thereby realizing independent control of the potentials of the sixth node QB1 and the seventh node QB 4.

As shown in fig. 8 and 9, in some embodiments, the shift register further includes:

A first input node control sub-circuit 25 coupled to the start signal input terminal STV, the third level signal input terminal VGH, and the input node QB5, respectively, for controlling to turn on or off the electrical connection between the third level signal input terminal VGH and the input node QB5 under the control of the start signal input from the start signal input terminal STV;

A second input node control sub-circuit 26 coupled to the eighth node QB6, the first level signal input terminal VGL1, and the input node QB5, respectively, for controlling to turn on or off the electrical connection between the first level signal input terminal VGL1 and the input node QB5 under the control of the potential of the eighth node QB 6;

The eighth node control sub-circuit 27 is coupled to the third clock signal input terminal CKA, the start signal input terminal STV, the eighth node QB6, and the third level signal input terminal VGH, and is configured to control the potential of the eighth node QB6 according to the third clock signal input by the third clock signal input terminal CKA, and to control the electrical connection between the third level signal input terminal VGH and the eighth node QB6 to be turned on or off under the control of the start signal input by the start signal input terminal STV.

Illustratively, the first input node control sub-circuit 25 includes a twentieth transistor T20, a gate of the twentieth transistor T20 is coupled to the start signal input terminal STV, a first pole of the twentieth transistor T20 is coupled to the third level signal input terminal VGH, a second pole of the twentieth transistor T20 is coupled to the input node QB5, and the twentieth transistor T20 is configured to control on or off an electrical connection between the third level signal input terminal VGH and the input node QB5 under control of a start signal input from the start signal input terminal STV.

Illustratively, the second input node control sub-circuit 26 includes a twenty-first transistor T21, a gate of the twenty-first transistor T21 is coupled to the eighth node QB6, a first pole of the twenty-first transistor T21 is coupled to the first level signal input terminal VGL1, a second pole of the twenty-first transistor T21 is coupled to the input node QB5, and the twenty-first transistor T21 is configured to control on or off of an electrical connection between the first level signal input terminal VGL1 and the input node QB5 under control of a potential of the eighth node QB 6.

The eighth node control sub-circuit 27 includes a twenty-second transistor T22 and a fourth capacitor C4, the gate of the twenty-second transistor T22 is coupled to the start signal input terminal STV, the first pole of the twenty-second transistor T22 is coupled to the third level signal input terminal VGH, the second pole of the twenty-second transistor T22 is coupled to the eighth node QB6, the first end of the fourth capacitor C4 is coupled to the third clock signal input terminal CKA, and the second end of the fourth capacitor C4 is coupled to the eighth node QB 6. The fourth capacitor C4 is used for controlling the potential of the eighth node QB6 according to the third clock signal input through the third clock signal input terminal CKA, and the second twenty-transistor T22 is used for controlling the connection or disconnection of the electrical connection between the third level signal input terminal VGH and the eighth node QB6 under the control of the start signal input through the start signal input terminal STV.

The shift register further comprises a first input node control sub-circuit 25, a second input node control sub-circuit 26 and an eighth node control sub-circuit 27, wherein the potential of the input node QB5 can be controlled through the first input node control sub-circuit 25, and the potential of the input node QB5 can be controlled through the eighth node control sub-circuit 27 and the second input node control sub-circuit 26, so that better control over the potential of the input node QB5 is realized.

As shown in fig. 11 and 12, in some embodiments, the input node QB5 is directly coupled with the first level signal input terminal VGL1, and the shift register further comprises:

A sixth node control sub-circuit 21 coupled to the first node Q1, the third level signal input terminal VGH and the sixth node QB1, respectively, for controlling to turn on or off an electrical connection between the third level signal input terminal VGH and the sixth node QB1 under the control of the potential of the first node Q1;

A seventh node control sub-circuit 22 coupled to the first node Q1, the third level signal input terminal VGH, and the seventh node QB4, respectively, for controlling to turn on or off an electrical connection between the third level signal input terminal VGH and the seventh node QB4 under the control of the potential of the first node Q1;

A coupling sub-circuit 28, the second input sub-circuit 19 is coupled to a ninth node QB7, and the ninth node QB7 is coupled to the third clock signal input CKA through the coupling sub-circuit 28;

The ninth node control sub-circuit 29 is coupled to the ninth node QB7, the start signal input terminal STV, and the third level signal input terminal VGH, and is configured to control on or off of the electrical connection between the third level signal input terminal VGH and the ninth node QB7 under the control of the start signal input from the start signal input terminal STV.

Illustratively, the sixth node control sub-circuit 21 includes a third transistor T3, the gate of the third transistor T3 is coupled to the first node Q1, the first pole of the third transistor T3 is coupled to the third level signal input terminal VGH, the second pole of the third transistor T3 is coupled to the sixth node QB1, and the third transistor T3 is configured to control on or off of the electrical connection between the third level signal input terminal VGH and the sixth node QB1 under the control of the potential of the first node Q1.

The seventh node control sub-circuit 22 includes an eighteenth transistor T18, a gate of the eighteenth transistor T18 is coupled to the first node Q1, a first pole of the eighteenth transistor T18 is coupled to the third level signal input terminal VGH, a second pole of the eighteenth transistor T18 is coupled to the seventh node QB4, and the eighteenth transistor T18 is configured to control on or off an electrical connection between the third level signal input terminal VGH and the seventh node QB4 under control of a potential of the first node Q1.

The coupling sub-circuit 28 includes a fifth capacitor C5, a first end of the fifth capacitor C5 is coupled to the third clock signal input CKA, and a second end of the fifth capacitor C5 is coupled to the ninth node QB 7.

The ninth node control sub-circuit 29 includes a thirteenth transistor T23, a gate of the twenty-third transistor T23 is coupled to the start signal input terminal STV, a first pole of the twenty-third transistor T23 is coupled to the third level signal input terminal VGH, and a second pole of the twenty-third transistor T23 is coupled to the ninth node QB 7. The twenty-third transistor T23 is configured to control on or off of an electrical connection between the third level signal input terminal VGH and the ninth node QB7 under control of a start signal input from the start signal input terminal STV.

The shift register further includes a coupling sub-circuit 28 and a ninth node control sub-circuit 29, and the potential of the input node QB5 can be controlled by the coupling sub-circuit 28 and the ninth node control sub-circuit 29, so that better control of the potential of the input node QB5 is achieved.

As shown in fig. 4-12, in some embodiments, the shift register further comprises

The first input sub-circuit 20 is coupled to the start signal input terminal STV, the third clock signal input terminal CKA, and the first node Q1, respectively, and is configured to control to switch on or off the electrical connection between the start signal input terminal STV and the first node Q1 under the control of the third clock signal input by the third clock signal input terminal CKA.

Illustratively, the first input sub-circuit 20 includes a first transistor T1, the gate of the first transistor T1 is coupled to the third clock signal input CKA, the first pole of the first transistor T1 is coupled to the start signal input STV, and the second pole of the first transistor T1 is coupled to the first node Q1. The first transistor T1 is configured to control on or off an electrical connection between the start signal input terminal STV and the first node Q1 under control of a third clock signal input by the third clock signal input terminal CKA.

As shown in fig. 4 and 5, in some embodiments, the shift register further includes:

The first node control sub-circuit 23 is coupled to the first node Q1, the sixth node QB1, the third level signal input terminal VGH, and the second clock signal input terminal CKB, and is configured to control to turn on or off the electrical connection between the first node Q1 and the third level signal input terminal VGH under the common control of the potential of the sixth node QB1 and the second clock signal input by the second clock signal input terminal CKB.

The first node control sub-circuit 23 includes a fourth transistor T4 and a fifth transistor T5, wherein the gate of the fourth transistor T4 is coupled to the sixth node QB1, the first pole of the fourth transistor T4 is coupled to the third level signal input terminal VGH, the second pole of the fourth transistor T4 is coupled to the first pole of the fifth transistor T5, the gate of the fifth transistor T5 is coupled to the second clock signal input terminal CKB, and the second pole of the fifth transistor T5 is coupled to the first node Q1. The fourth transistor T4 is configured to control on or off an electrical connection between the third level signal input terminal VGH and the first pole of the fifth transistor T5 under control of the potential of the sixth node QB 1. The fifth transistor T5 is configured to control on or off an electrical connection between the first pole of the fifth transistor T5 and the first node Q1 under the control of the second clock signal input by the second clock signal input terminal CKB.

As shown in fig. 4 to 12, in some embodiments, the shift register further includes:

The second cascade control sub-circuit 24 is coupled to the sixth node QB1, the cascade signal output terminal CR, and the third level signal input terminal VGH, and is configured to control to switch on or off an electrical connection between the cascade signal output terminal CR and the third level signal input terminal VGH under the control of the potential of the sixth node QB1, and is further configured to control the potential of the sixth node QB1 according to the third level signal input by the third level signal input terminal VGH.

The second cascaded control sub-circuit 24 includes a seventh transistor T7 and a first capacitor C1, wherein the gate of the seventh transistor T7 is coupled to the sixth node QB1, the first pole of the seventh transistor T7 is coupled to the third level signal input terminal VGH, the second pole of the seventh transistor T7 is coupled to the cascaded signal output terminal CR, the first end of the first capacitor C1 is coupled to the third level signal input terminal VGH, and the second end of the first capacitor C1 is coupled to the sixth node QB 1. The seventh transistor T7 is configured to control on or off an electrical connection between the cascade signal output terminal CR and the third level signal input terminal VGH under control of the potential of the sixth node QB 1. The first capacitor C1 is configured to control the potential of the sixth node QB1 according to the third level signal input from the third level signal input terminal VGH.

In more detail, when the shift register adopts the structure shown in fig. 4 and 5, the driving timing sequence of the shift register is shown in fig. 6, and the specific operation process is as follows:

In the period P1, when the start signal input from the start signal input terminal STV is at a high voltage, the third clock signal input from the third clock signal input terminal CKA is at a low voltage from the high voltage, the first node Q1, the second node Q2, the first output node Q3 are kept at a high voltage, the fourth node GD is at a high voltage, the fifth node QB3 is kept at a low voltage, the sixth node QB1 is kept at a low voltage, the second output node QB2 is kept at a lower voltage, the cascade signal output from the cascade signal output terminal CR is kept at a high voltage, and the gate driving signal output from the gate driving signal output terminal OUT is kept at a low voltage.

In the period P2, when the third clock signal input from the third clock signal input terminal CKA is at a high voltage, the fourth clock signal input from the fourth clock signal input terminal CKA2 is at a low voltage from the high voltage, the first node Q1, the second node Q2, the first output node Q3 are kept at a high voltage, the fourth node GD is pulled down by the fourth clock signal input from the fourth clock signal input terminal CKA2, the fifth node QB3 is pulled down to a lower voltage from the low voltage, the second output node QB2 is kept at a very low voltage, the cascade signal output from the cascade signal output terminal CR is kept at a high voltage, and the gate driving signal output from the gate driving signal output terminal OUT is kept at a low voltage.

In the period P3, when the start signal input from the start signal input terminal STV is changed from high voltage to low voltage, the third clock signal input from the third clock signal input terminal CKA is changed from high voltage to low voltage, the first node Q1 and the second node Q2 are changed from high voltage to low voltage, the eighth transistor T8 is kept on, the first output node Q3 is changed from high voltage to low voltage, the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 maintain the low voltage of the previous state, and since the second clock signal input from the second clock signal input terminal CKB is high voltage at this time, the cascade signal output from the cascade signal output terminal CR is high voltage, the first clock signal input from the first clock signal input terminal GCK is low voltage, and the gate driving signal output from the gate driving signal output terminal OUT maintains low voltage.

In the period P4, when the start signal input by the start signal input terminal STV goes low, and then the third clock signal input by the third clock signal input terminal CKA goes high from low, the first node Q1, the second node Q2, and the first output node Q3 maintain low due to the voltage stabilizing effect of the first capacitor C1 and the second capacitor C2, at this time, the third transistor T3 and the eighteenth transistor T18 maintain an on state, the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 go high from low, and the cascade signal output by the cascade signal output terminal CR is high, the first clock signal input by the first clock signal input terminal GCK is low, and the gate driving signal output by the gate driving signal output terminal OUT maintains low.

In the period P5, when the third clock signal input from the third clock signal input terminal CKA is at a high voltage and the second clock signal input from the second clock signal input terminal CKB is at a low voltage from the high voltage, since the eighth transistor T8 is kept on, the cascade signal output from the cascade signal output terminal CR is coupled to the second node Q2 through the second capacitor C2 by the voltage variation of the low voltage from the high voltage, the second node Q2 is pulled down to a lower low voltage, the first node Q1 is pulled down slightly to approach the first level signal input from the first level signal input terminal VGL1 due to the voltage limiting effect of the sixth transistor T6, the nineteenth transistor T19 is turned on, the first output node Q3 is pulled down to about the voltage value of the first level signal, the first clock signal input from the first clock signal input terminal GCK is at a low voltage, and the gate driving signal output from the gate driving signal output terminal OUT is kept at a low voltage. At this time, the sixth node QB1, the second output node QB2, the fifth node QB3, and the seventh node QB4 maintain a high voltage.

In the period P6, when the third clock signal input from the third clock signal input terminal CKA is at a high voltage and the first clock signal input from the first clock signal input terminal GCK is at a high voltage (when the first clock signal input from the first clock signal input terminal GCK is at a low voltage and the second clock signal input from the second clock signal input terminal CKB is at a high voltage), the first clock signal input from the first clock signal input terminal GCK is at a high voltage. Since the nineteenth transistor T19 is kept in the on state, the first output node Q3 maintains the potential around the voltage value of the current first level signal, and the gate drive signal output from the gate drive signal output terminal OUT is changed from the low voltage to the high voltage, and the other node voltages are not changed.

In the period P7, when the third clock signal input by the third clock signal input terminal CKA is at a high voltage, and the second clock signal input by the second clock signal input terminal CKB is changed from a low voltage to a high voltage, the cascade signal output by the cascade signal output terminal CR is changed from a low voltage to a high voltage due to the coupling effect of the second capacitor C2, and the second node Q2 and the first node Q1 are affected by the process of changing the cascade signal output by the cascade signal output terminal CR, so that the voltage is restored to the potential at the end of the third clock signal input by the third clock signal input terminal CKA from the low voltage to the high voltage, and at this time, the voltage of the first output node Q3 is basically unchanged due to the isolation effect of the sixteenth transistor T16, and the cascade signal output by the cascade signal output terminal CR is changed from the low voltage to the high voltage, and the voltages of other nodes are unchanged. In this case, the sixteenth transistor T16 is turned off due to the gate voltage and the source voltage.

In the period P8, when the third clock signal input by the third clock signal input terminal CKA is a high voltage, since the eleventh transistor T11 is a buffer transistor, the parasitic capacitance thereof is relatively large, the voltage of the first output node Q3 is pulled down to be very low, so that the eleventh transistor T11 is ensured to output a complete falling edge, and the voltages of other nodes are not changed.

In the period P9, when the start signal input from the start signal input terminal STV is at a high voltage, the third clock signal input from the third clock signal input terminal CKA is at a low voltage, the first node Q1, the second node Q2, the first output node Q3 are at a high voltage, the fourth node GD maintains the high voltage, the sixth node QB1, the second output node QB2, the fifth node QB3, the seventh node QB4 are at a low voltage, the cascade signal output from the cascade signal output terminal CR maintains the high voltage, and the gate driving signal output from the gate driving signal output terminal OUT maintains the low voltage.

In the period P10, when the third clock signal input from the third clock signal input terminal CKA is at a high voltage, the fourth clock signal input from the fourth clock signal input terminal CKA2 is at a low voltage from the high voltage, the first node Q1, the second node Q2, and the first output node Q3 are kept at a high voltage, the fourth node GD is pulled down by the fourth clock signal input from the fourth clock signal input terminal CKA2, the fifth node QB3 is pulled down to a lower voltage from the low voltage, the second output node QB2 is pulled down to a lower voltage from the low voltage, the cascade signal output from the cascade signal output terminal CR is kept at a high voltage, and the gate driving signal output from the gate driving signal output terminal OUT is kept at a low voltage.

In the period P11, when the third clock signal input by the third clock signal input terminal CKA is at a high voltage and the second clock signal input by the second clock signal input terminal CKB is at a low voltage from the high voltage, the fourth transistor T4 and the fifth transistor T5 are turned on, and the first node Q1, the second node Q2 and the first output node Q3 are input with the third level signal input by the third level signal input terminal VGH, which is less likely to be interfered by other clock signals.

It should be noted that the start signal input from the start signal input terminal STV only needs to maintain the low voltage signal during the period when the third clock signal input from the third clock signal input terminal CKA is low. The pulse width may be set to be greater than 4H or less than 1H according to the actual pixel driving requirements.

When the shift register adopts the structure shown in fig. 8 and fig. 9, the driving timing sequence of the shift register is shown in fig. 10, and the specific working process is as follows:

In the period n1, when the start signal input from the start signal input terminal STV is high, the third clock signal input from the third clock signal input terminal CKA is low from high, the eighth node QB6 is pulled down, the input node QB5 is pulled down, the first node Q1, the second node Q2, the first output node Q3 are kept high, the fourth node GD is high, the fifth node QB3 is kept low, the input node QB5, the fifth node QB3 are low, the sixth node QB1, the second output node QB2 are affected by the voltages of the input node QB5 and the fifth node QB3, and are pulled high but still low, the cascade signal output from the cascade signal output terminal CR is kept high, and the gate driving signal output from the gate driving signal output terminal OUT is kept low.

In the n2 period, when the third clock signal input from the third clock signal input terminal CKA is at a high voltage, the fourth clock signal input from the fourth clock signal input terminal CKA2 is at a low voltage from the high voltage, the eighth node QB6, the first node Q1, the second node Q2 are kept at a high voltage, the fourth node GD is pulled down by the fourth clock signal input from the fourth clock signal input terminal CKA2, the fifth node QB3 is pulled down to a lower voltage from the low voltage, the sixth node QB1 is pulled down again, the cascade signal output from the cascade signal output terminal CR is kept at a high voltage, and the gate driving signal output from the gate driving signal output terminal OUT is kept at a low voltage.

In the n3 period, when the start signal input from the start signal input terminal STV is changed from high voltage to low voltage, the eighth node QB6 and the input node QB5 maintain high voltage, when the third clock signal input from the third clock signal input terminal CKA is changed from high voltage to low voltage, the first node Q1 and the second node Q2 are changed from high voltage to low voltage, the eighth transistor T8 is kept on, the first output node Q3 is changed from high voltage to low voltage, the input node QB5 maintains high voltage, the sixth node QB1, the fifth node QB3 and the seventh node QB4 maintain high voltage, and the cascade signal output from the cascade signal output terminal CR maintains low voltage because the second clock signal input from the second clock signal input terminal CKB is high voltage, the first clock signal input from the first clock signal input terminal GCK is low voltage, and the gate driving signal output from the gate driving signal output terminal OUT maintains low voltage.

In the period n4, when the start signal input from the start signal input terminal STV goes low, the third clock signal input from the third clock signal input terminal CKA goes high from low, the first node Q1, the second node Q2, the first output node Q3 maintain low due to the voltage stabilizing effect of the first capacitor C1 and the second capacitor C2, the sixth node QB1, the fifth node QB3, the seventh node QB4, and the second output node QB2 maintain high, and the cascade signal output from the cascade signal output terminal CR is high due to the high voltage of the second clock signal input from the second clock signal input terminal CKB, the first clock signal input from the first clock signal input terminal GCK is low, and the gate driving signal output from the gate driving signal output terminal OUT maintains low.

In the period n5, when the third clock signal input from the third clock signal input terminal CKA is at a high voltage and the second clock signal input from the second clock signal input terminal CKB is at a low voltage from the high voltage, since the eighth transistor T8 is kept on, the cascade signal output from the cascade signal output terminal CR is capacitively coupled to the second node Q2 through the second capacitor C2 by the voltage variation of the low voltage from the high voltage, the second node Q2 is pulled down to a lower low voltage, the first node Q1 is pulled down slightly to a voltage close to the first level signal input from the first level signal input terminal VGL1 due to the voltage limiting effect of the sixth transistor T6, the nineteenth transistor T19 is turned on, the first output node Q3 is pulled down to about the voltage value of the first level signal input from the first level signal input terminal VGL1, the first clock signal input from the first clock signal input terminal GCK is at a low voltage, and the gate driving signal output from the gate driving signal output terminal OUT is kept at a low voltage. At this time, the input node QB5, the sixth node QB1, the fifth node QB3, the seventh node QB4, and the second output node QB2 maintain high voltages.

In the n6 period, when the third clock signal input from the third clock signal input terminal CKA is at a high voltage and the first clock signal input from the first clock signal input terminal GCK is at a high voltage (when the first clock signal input from the first clock signal input terminal GCK is at a low voltage and the second clock signal input from the second clock signal input terminal CKB is at a high voltage). The nineteenth transistor T19 maintains the potential of the first level signal voltage value input at the current first level signal input terminal VGL1 at the first output node Q3, and the gate driving signal output at the gate driving signal output terminal OUT is changed from a low voltage to a high voltage, and the other node voltages are not changed.

In the period n7, when the third clock signal input by the third clock signal input terminal CKA is high, the second clock signal input by the second clock signal input terminal CKB is changed from low to high, the cascade signal output by the cascade signal output terminal CR is changed from low to high due to the coupling effect of the capacitance of the second capacitance C2, so that the voltage is restored to the potential at the end of the change of the third clock signal input by the third clock signal input terminal CKA, at this time, the voltage of the first output node Q3 is basically unchanged due to the isolation effect of the sixteenth transistor T16, the cascade signal output by the cascade signal output terminal CR is changed from low to high, and the voltages of other nodes are unchanged.

In the period n8, when the third clock signal input by the third clock signal input end CKA is at a high voltage and the first clock signal input by the first clock signal input end GCK is at a low voltage from the high voltage, the parasitic capacitance of the eleventh transistor T11 is relatively large because the buffer transistor is a buffer transistor, the voltage of the first output node Q3 is pulled down to be very low, so that the eleventh transistor T11 is ensured to output a complete falling edge, and the voltages of other nodes are not changed.

In the n9 period, when the start signal input from the start signal input terminal STV is at a high voltage, the third clock signal input from the third clock signal input terminal CKA is at a low voltage, the eighth node QB6 is at a low voltage, the input node QB5 is at a low voltage, the first node Q1, the second node Q2, the first output node Q3 are at a high voltage, the fourth node GD maintains the high voltage, the sixth node QB1, the fifth node QB3, the seventh node QB4, the second output node QB2 are at a low voltage, the cascade signal output from the cascade signal output terminal CR maintains the high voltage, and the gate driving signal output from the gate driving signal output terminal OUT maintains the low voltage.

In the n10 period, when the third clock signal input from the third clock signal input terminal CKA is at a high voltage, the fourth clock signal input from the fourth clock signal input terminal CKA2 is at a low voltage from the high voltage, the eighth node QB6, the first node Q1, the second node Q2, the first output node Q3 maintain the high voltage, the fourth node GD is pulled down by the fourth clock signal input from the fourth clock signal input terminal CKA2, the fifth node QB3 is pulled down to a lower voltage from the low voltage, the first output node Q3 is pulled down to a lower voltage from the low voltage, the cascade signal output from the cascade signal output terminal CR maintains the high voltage, and the gate driving signal output from the gate driving signal output terminal OUT maintains the low voltage.

As shown in FIG. 7, a schematic diagram of the cascade connection of six shift registers (GOA-1, GOA-2, GOA-3, GOA-4, GOA-5, GOA-6) is illustrated. The first clock signal line GCK1, the second clock signal line GCK2, the third clock signal line GCK3, the fourth clock signal line GCK4, the start signal line STV ', the fifth clock signal line CKA ', the sixth clock signal line CKA2', the seventh clock signal line CKB ', the eighth clock signal line CKB2' are illustrated.

The clock signals transmitted by the first clock signal line GCK1, the second clock signal line GCK2, the third clock signal line GCK3 and the fourth clock signal line GCK4 are a group of clock signals with the same pulse width and different phases, and the voltage variation range is from the level value of the second level signal input by the second level signal input end to the level value of the fifth level signal transmitted by the fifth level signal input end.

The fifth clock signal line CKA ', the sixth clock signal line CKA2', the seventh clock signal line CKB ', the eighth clock signal line CKB2' transmits clock signals of the same pulse width and different phases, and the voltage variation range is from the level value of the first level signal input by the first level signal input end to the level value of the fourth level signal transmitted by the fourth level signal input end.

The relation is satisfied that the level value of the first level signal is smaller than or equal to the level value of the second level signal, and the level value of the fourth level signal is larger than or equal to the level value of the fifth level signal, and the magnitude relation is the magnitude relation in the case that the level value is signed.

In the shift register of the above embodiments, the third level signals input from the third level signal input terminals VGH may be different, for example, a part of the third level signals input from the third level signal input terminals VGH may be the same as the fourth level signal, and another part of the third level signals input from the third level signal input terminals VGH may be the same as the fifth level signal, but the shift register is not limited thereto.

The cascade signal output CR of the x-th shift register is coupled to the start signal input STV of the x+2th shift register, where x is an integer greater than 2. The start signal input STV of the 1 st shift register and the 2 nd shift register is directly coupled to the start signal line STV'.

In the case of cascade connection of a plurality of shift registers, the third clock signal input terminal CKA of the 4n+1 shift register is coupled to the fifth clock signal line CKA ', the fourth clock signal input terminal CKA2 of the 4n+1 shift register is coupled to the sixth clock signal line CKA2', the second clock signal input terminal CKB of the 4n+1 shift register is coupled to the seventh clock signal line CKB ', and the first clock signal input terminal GCK of the 4n+1 shift register is coupled to the first clock signal line GCK 1. N is an integer greater than or equal to 0.

The third clock signal input end CKA of the 4N+2 shift registers is coupled to the sixth clock signal line CKA2', the fourth clock signal input end CKA2 of the 4N+2 shift registers is coupled to the seventh clock signal line CKB ', the second clock signal input end CKB of the 4N+2 shift registers is coupled to the eighth clock signal line CKB2', and the first clock signal input end GCK of the 4N+2 shift registers is coupled to the second clock signal line GCK 2.

The third clock signal input end CKA of the 4N+3 shift registers is coupled to the seventh clock signal line CKB ', the fourth clock signal input end CKA2 of the 4N+3 shift registers is coupled to the eighth clock signal line CKB2', the second clock signal input end CKB of the 4N+3 shift registers is coupled to the fifth clock signal line CKA ', and the first clock signal input end GCK of the 4N+3 shift registers is coupled to the third clock signal line GCK 3.

The third clock signal input end CKA of the 4n+4 shift registers is coupled to the eighth clock signal line CKB2', the fourth clock signal input end CKA2 of the 4n+4 shift registers is coupled to the fifth clock signal line CKA ', the second clock signal input end CKB of the 4n+4 shift registers is coupled to the sixth clock signal line CKA2', and the first clock signal input end GCK of the 4n+4 shift registers is coupled to the fourth clock signal line GCK 4.

Also illustrated in fig. 6 and 10 are timings of cascade signals output from the cascade signal output terminal CR < N > of the nth shift register unit and the cascade signal output terminal CR < n+1> of the n+1th shift register unit, and timings of gate driving signals output from the gate driving signal output terminal OUT < N > of the nth shift register unit and the gate driving signal output terminal OUT < n+1> of the n+1th shift register unit.

The shift register provided in the above embodiment may be applied to an OLED display product of LTPO or LTPS, for example, the shift register provided in the above embodiment may be applied to LTPO, in which the tube for controlling the gate write data signal of the driving transistor in the pixel circuit is an oxide transistor, the gate driving signal of the high voltage pulse with the pulse width within 1H or about 1.5H is required to be used as the control signal of the oxide transistor, and the shift register for outputting the signal may be called NGate GOA.

The shift register provided in the above embodiment can output the gate driving signal having the shifted high voltage pulse by using the P-type transistor, and can maintain the stability of the low potential in the waveform of the signal.

The embodiment of the invention also provides a driving method of the shift register, which is applied to the shift register provided by the embodiment, and comprises the following steps:

The first output sub-circuit 10 controls to turn on or off the electrical connection between the gate driving signal output terminal OUT and the first clock signal input terminal GCK under the control of the potential of the first output node Q3;

The first output node control sub-circuit 11 controls to switch on or off the electrical connection between the first node Q1 and the first output node Q3 under the control of the first level signal input by the first level signal input terminal VGL1, and controls to switch on or off the electrical connection between the first output node Q3 and the first level signal input terminal VGL1 under the control of the potential of the second node Q2;

The first cascade control sub-circuit 12 controls to turn on or off the electrical connection between the second clock signal input terminal CKB and the cascade signal output terminal CR under the control of the potential of the second node Q2, and also controls the potential of the second node Q2 according to the cascade signal output by the cascade signal output terminal CR;

The first isolation control sub-circuit 13 controls and turns on the electrical connection between the first node Q1 and the second node Q2 under the control of the first level signal.

When the driving method provided by the embodiment of the invention is adopted to drive the shift register, under the condition that the potential control of the second node Q2 is conducted to the cascade signal output end CR and the second clock signal input end CKB, the second clock signal input by the second clock signal input end CKB is transmitted to the cascade signal output end CR, and then the potential of the second node Q2 is affected. Because the electric potential of the second node Q2 can control to turn on or off the electric connection between the first output node Q3 and the first level signal input terminal VGL1, when the electric potential of the second node Q2 becomes lower under the condition of being affected, the electric connection between the first output node Q3 and the first level signal input terminal VGL1 can be better controlled to be turned on, the electric potential of the first output node Q3 is controlled to be an effective electric potential, and the effective electric potential can be turned on to electrically connect between the gate driving signal output terminal OUT and the first clock signal input terminal GCK, so that the signal of the gate driving signal output terminal OUT is kept consistent with the signal input by the first clock signal input terminal GCK, and the signal stability output by the gate driving signal output terminal OUT is ensured.

In some embodiments, the driving method further comprises:

the second output sub-circuit 14 controls to turn on or off the electrical connection between the gate driving signal output terminal OUT and the second level signal input terminal VGL2 under the control of the potential of the second output node QB 2;

the fourth node control sub-circuit 15 controls to turn on or off the electrical connection between the fourth node GD and the third level signal input terminal VGH under the control of the potential of the first node Q1;

The fourth node control sub-circuit 15 controls to turn on or off the electrical connection between the fourth node GD and the fourth clock signal input terminal CKA2 under the control of the potential of the fifth node QB3, or controls to turn on or off the electrical connection between the fourth node GD and the second clock signal input terminal CKB under the control of the potential of the fifth node QB 3;

The second output node control sub-circuit 16 controls to turn on or off the electrical connection between the second output node QB2 and the fifth node QB3 under the control of the potential of the fifth node QB 3.

When the driving method provided by the embodiment is adopted to drive the shift register, under the control of the potential of the first node Q1, the electrical connection between the fourth node GD and the third level signal input end VGH is controlled to be disconnected, and under the control of the potential of the fifth node QB3, the electrical connection between the fourth node GD and the second clock signal input end CKB or the fourth clock signal input end CKA2 is controlled to be conducted, wherein the fourth clock signal input by the fourth clock signal input end CKA2 is transmitted to the fourth node GD, and the potential of the fourth node GD further controls the potential of the fifth node QB 3. When the potential of the fifth node QB3 becomes lower due to the influence, the second output node control sub-circuit 16 can better control and turn on the electrical connection between the second output node QB2 and the fifth node QB3, control the potential of the second output node QB2 at an effective potential, and turn on the electrical connection between the gate driving signal output terminal OUT and the second level signal input terminal VGL2, so that the signal of the gate driving signal output terminal OUT is consistent with the signal input by the second level signal input terminal VGL2, and ensure the signal stability output by the gate driving signal output terminal OUT.

The embodiment of the invention also provides a display device which comprises the shift register provided by the embodiment.

Illustratively, the display device includes a gate driving circuit including a plurality of cascaded shift registers.

It should be noted that the display device may be any product or component with display function, such as a television, a display, a digital photo frame, a mobile phone, a tablet personal computer, etc., where the display device further includes a flexible circuit board, a printed circuit board, a back board, etc.

In the shift register provided in the foregoing embodiment, when the potential control of the second node Q2 turns on the cascade signal output terminal CR and the second clock signal input terminal CKB, the second clock signal input by the second clock signal input terminal CKB is transmitted to the cascade signal output terminal CR, so as to affect the potential of the second node Q2. Because the electric potential of the second node Q2 can control to turn on or off the electric connection between the first output node Q3 and the first level signal input terminal VGL1, when the electric potential of the second node Q2 becomes lower under the condition of being affected, the electric connection between the first output node Q3 and the first level signal input terminal VGL1 can be better controlled to be turned on, the electric potential of the first output node Q3 is controlled to be an effective electric potential, and the effective electric potential can be turned on to electrically connect between the gate driving signal output terminal OUT and the first clock signal input terminal GCK, so that the signal of the gate driving signal output terminal OUT is kept consistent with the signal input by the first clock signal input terminal GCK, and the signal stability output by the gate driving signal output terminal OUT is ensured. When the potential of the second node Q2 becomes higher under the influence of the potential, the potential of the first node Q1 is influenced under the control of the first isolation control sub-circuit 13, and at this time, the first output node control sub-circuit 11 can control to disconnect the electrical connection between the first node Q1 and the first output node Q3 under the control of the first level signal input by the first level signal input terminal VGL1, so that the potential of the first output node Q3 can avoid being influenced by the potential of the first node Q1, and the first output node Q3 can keep the original state, and the control state of the first output node Q3 on the first output sub-circuit 10 is kept, thereby better maintaining the stability of the signal output by the gate driving signal output terminal OUT.

Therefore, the display device provided by the embodiment of the invention has the beneficial effects when the shift register provided by the embodiment is included, and can realize better display effect.

The transistors used in all embodiments of the present invention may be thin film transistors or field effect transistors or other devices having the same characteristics. In the embodiment of the invention, in order to distinguish the two poles of the transistor except the grid electrode, one pole is called a first pole, and the other pole is called a second pole.

In actual operation, when the transistor is a thin film transistor or a field effect transistor, the first pole may be a drain electrode, the second pole may be a source electrode, or the first pole may be a source electrode, and the second pole may be a drain electrode.

It should be noted that "same layer" in the embodiments of the present invention may refer to a film layer on the same structural layer. Or, for example, the film layers in the same layer may be a layer structure formed by forming a film layer for forming a specific pattern by the same film forming process and then patterning the film layer by one patterning process using the same mask plate. Depending on the particular pattern, a patterning process may include multiple exposure, development, or etching processes, and the particular pattern in the formed layer structure may be continuous or discontinuous. These specific patterns may also be at different heights or have different thicknesses.

In the method embodiments of the present invention, the serial numbers of the steps are not used to define the sequence of the steps, and it is within the scope of the present invention for those skilled in the art to change the sequence of the steps without performing any creative effort.

In this specification, all embodiments are described in a progressive manner, and identical and similar parts of the embodiments are all referred to each other, and each embodiment is mainly described in a different way from other embodiments. In particular, for the method embodiments, since they are substantially similar to the product embodiments, the description is relatively simple, and reference is made to the section of the product embodiments for relevant points.

Unless defined otherwise, technical or scientific terms used in this disclosure should be given the ordinary meaning as understood by one of ordinary skill in the art to which this invention belongs. The terms "first," "second," and the like, as used in this disclosure, do not denote any order, quantity, or importance, but rather are used to distinguish one element from another. The word "comprising" or "comprises", and the like, means that elements or items preceding the word are included in the element or item listed after the word and equivalents thereof, but does not exclude other elements or items. The terms "connected," "coupled," or "connected," and the like, are not restricted to physical or mechanical connections, but may include electrical connections, whether direct or indirect. "upper", "lower", "left", "right", etc. are used merely to indicate relative positional relationships, which may also be changed when the absolute position of the object to be described is changed.

It will be understood that when an element such as a layer, film, region or substrate is referred to as being "on" or "under" another element, it can be "directly on" or "under" the other element or intervening elements may be present.

In the description of the above embodiments, particular features, structures, materials, or characteristics may be combined in any suitable manner in any one or more embodiments or examples. The foregoing is merely illustrative of the present invention, and the present invention is not limited thereto, and any person skilled in the art will readily recognize that variations or substitutions are within the scope of the present invention. Therefore, the protection scope of the present invention shall be subject to the protection scope of the claims.

Claims

1. A shift register, characterized in that it comprises:

The first output sub-circuit is coupled to the gate drive signal output terminal, the first clock signal input terminal and the first output node respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the first clock signal input terminal under the control of the potential of the first output node.

The first output node control sub-circuit is coupled to the first node, the second node, the first output node, and the first level signal input terminal, respectively. It is used to control the electrical connection between the first node and the first output node to be turned on or off under the control of the first level signal input terminal; and is also used to control the electrical connection between the first output node and the first level signal input terminal to be turned on or off under the control of the potential of the second node.

The first cascaded control sub-circuit is coupled to the cascaded signal output terminal, the second clock signal input terminal, and the second node, respectively, and is used to control the electrical connection between the second clock signal input terminal and the cascaded signal output terminal to be turned on or off under the control of the potential of the second node.

The first isolation control sub-circuit is used to control the connection between the first node and the second node to be turned on or off.

2. The shift register according to claim 1, characterized in that it further comprises:

The second output sub-circuit is coupled to the gate drive signal output terminal, the second level signal input terminal, and the second output node, respectively, and is used to control the conduction or disconnection of the electrical connection between the gate drive signal output terminal and the second level signal input terminal under the control of the potential of the second output node.

The fourth node control sub-circuit is coupled to the first node, the fourth node, the fifth node, and the third level signal input terminal, respectively. The fourth node control sub-circuit is also coupled to the fourth clock signal input terminal or the second clock signal input terminal. It is used to control the electrical connection between the fourth node and the third level signal input terminal under the control of the potential of the first node; and to control the potential of the fifth node according to the potential of the fourth node.

The fourth node control sub-circuit is also used to: control the electrical connection between the fourth node and the fourth clock signal input terminal to be turned on or off under the control of the potential of the fifth node; or, control the electrical connection between the fourth node and the second clock signal input terminal to be turned on or off under the control of the potential of the fifth node.

The second output node control sub-circuit is coupled to the second output node and the fifth node respectively, and is used to control the electrical connection between the second output node and the fifth node to be turned on or off under the control of the potential of the fifth node.

3. The shift register according to claim 2, characterized in that it further comprises:

The second isolation control sub-circuit is coupled to the first level signal input terminal, the second output node and the sixth node respectively, and is used to control the conduction or disconnection of the electrical connection between the second output node and the sixth node under the control of the first level signal input terminal.

The third isolation control sub-circuit is coupled to the first level signal input terminal, the fifth node and the seventh node respectively, and is used to control the conduction or disconnection of the electrical connection between the fifth node and the seventh node under the control of the first level signal input terminal.

The second input sub-circuit is coupled to the third clock signal input terminal, the sixth node, the seventh node, and the input node, respectively; it is used to control the electrical connection between the sixth node and the input node to be turned on or off under the control of the third clock signal input to the third clock signal input terminal, and to control the electrical connection between the seventh node and the input node to be turned on or off under the control of the third clock signal input to the third clock signal input terminal.

4. The shift register according to claim 3, wherein the input node is directly coupled to the first level signal input terminal; the shift register further includes:

The sixth node control sub-circuit is coupled to the first node, the third clock signal input terminal and the sixth node respectively, and is used to control the conduction or disconnection of the electrical connection between the third clock signal input terminal and the sixth node under the control of the potential of the first node;

The seventh node control sub-circuit is coupled to the first node, the third clock signal input terminal and the seventh node respectively, and is used to control the electrical connection between the third clock signal input terminal and the seventh node to be turned on or off under the control of the potential of the first node.

5. The shift register according to claim 3, characterized in that it further comprises:

The first input node control sub-circuit is coupled to the start signal input terminal, the third level signal input terminal and the input node respectively, and is used to control the electrical connection between the third level signal input terminal and the input node to be turned on or off under the control of the start signal input at the start signal input terminal;

The second input node control sub-circuit is coupled to the eighth node, the first level signal input terminal and the input node respectively, and is used to control the conduction or disconnection of the electrical connection between the first level signal input terminal and the input node under the control of the potential of the eighth node;

The eighth node control sub-circuit is coupled to the third clock signal input terminal, the start signal input terminal, the eighth node, and the third level signal input terminal, respectively. It is used to control the potential of the eighth node according to the third clock signal input terminal, and also to control the electrical connection between the third level signal input terminal and the eighth node to be turned on or off under the control of the start signal input terminal.

6. The shift register according to claim 3, wherein the input node is directly coupled to the first level signal input terminal; the shift register further includes:

The sixth node control sub-circuit is coupled to the first node, the third level signal input terminal and the sixth node respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the sixth node under the control of the potential of the first node;

The seventh node control sub-circuit is coupled to the first node, the third level signal input terminal and the seventh node respectively, and is used to control the conduction or disconnection of the electrical connection between the third level signal input terminal and the seventh node under the control of the potential of the first node;

A coupling sub-circuit, wherein the second input sub-circuit is coupled to the ninth node, and the ninth node is coupled to the third clock signal input terminal through the coupling sub-circuit;

The ninth node control sub-circuit is coupled to the ninth node, the start signal input terminal, and the third level signal input terminal, respectively, and is used to control the electrical connection between the third level signal input terminal and the ninth node to be turned on or off under the control of the start signal input at the start signal input terminal.

7. The shift register according to any one of claims 4 to 6, characterized in that it further includes a first input sub-circuit, which is coupled to the start signal input terminal, the third clock signal input terminal and the first node respectively, and is used to control the electrical connection between the start signal input terminal and the first node to be turned on or off under the control of the third clock signal input at the third clock signal input terminal.

8. The shift register according to any one of claims 4 to 6, characterized in that it further comprises:

The first node control sub-circuit is coupled to the first node, the sixth node, the third level signal input terminal, and the second clock signal input terminal, respectively. It is used to control the electrical connection between the first node and the third level signal input terminal to be turned on or off under the joint control of the potential of the sixth node and the second clock signal input terminal.

9. The shift register according to any one of claims 4 to 6, characterized in that it further comprises:

The second cascaded control sub-circuit is coupled to the sixth node, the cascaded signal output terminal, and the third-level signal input terminal, respectively. It is used to control the electrical connection between the cascaded signal output terminal and the third-level signal input terminal under the control of the potential of the sixth node; it is also used to control the potential of the sixth node according to the third-level signal input from the third-level signal input terminal.

10. The shift register according to claim 1, characterized in that,

The first output sub-circuit includes an eleventh transistor, the gate of which is coupled to the first output node, the first terminal of which is coupled to the first clock signal input terminal, and the second terminal of which is coupled to the gate drive signal output terminal.

The first output node control sub-circuit includes a sixteenth transistor and a nineteenth transistor. The gate of the sixteenth transistor is coupled to the first level signal input terminal, the first terminal of the sixteenth transistor is coupled to the first node, and the second terminal of the sixteenth transistor is coupled to the first output node. The gate of the nineteenth transistor is coupled to the second node, the first terminal of the nineteenth transistor is coupled to the first level signal input terminal, and the second terminal of the nineteenth transistor is coupled to the first output node.

The first cascaded control sub-circuit includes an eighth transistor and a second capacitor. The gate of the eighth transistor is coupled to the second node, the first terminal of the eighth transistor is coupled to the second clock signal input terminal, and the second terminal of the eighth transistor is coupled to the cascaded signal output terminal. The first terminal of the second capacitor is coupled to the cascaded signal output terminal, and the second terminal of the second capacitor is coupled to the second node.

The first isolation control sub-circuit includes a sixth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the first node, and the second terminal of which is coupled to the second node.

11. The shift register according to claim 2, characterized in that,

The second output sub-circuit includes a tenth transistor, the gate of which is coupled to the second output node, the first terminal of which is coupled to the second level signal input terminal, and the second terminal of which is coupled to the gate drive signal output terminal.

The fourth node control sub-circuit includes a twelfth transistor, a thirteenth transistor, and a third capacitor coupled together; the gate of the twelfth transistor is coupled to the fifth node, the first terminal of the twelfth transistor is coupled to the fourth clock signal input terminal or the second clock signal input terminal, and the second terminal of the twelfth transistor is coupled to the fourth node; the gate of the thirteenth transistor is coupled to the first node, the first terminal of the thirteenth transistor is coupled to the third level signal input terminal, and the second terminal of the thirteenth transistor is coupled to the fourth node; the first terminal of the third capacitor is coupled to the fourth node, and the second terminal of the third capacitor is coupled to the fifth node;

The second output node control sub-circuit includes a fourteenth transistor, the gate of which is coupled to the fifth node, the first terminal of which is coupled to the fifth node, and the second terminal of which is coupled to the second output node.

12. The shift register according to claim 3, characterized in that,

The second isolation control sub-circuit includes a ninth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the sixth node, and the second terminal of which is coupled to the second output node;

The third isolation control sub-circuit includes a fifteenth transistor, the gate of which is coupled to the first level signal input terminal, the first terminal of which is coupled to the seventh node, and the second terminal of which is coupled to the fifth node;

The second input sub-circuit includes a second transistor and a seventeenth transistor. The gate of the second transistor is coupled to the third clock signal input terminal, the first terminal of the second transistor is coupled to the first level signal input terminal, and the second terminal of the second transistor is coupled to the sixth node. The gate of the seventeenth transistor is coupled to the third clock signal input terminal, the first terminal of the seventeenth transistor is coupled to the first level signal input terminal, and the second terminal of the seventeenth transistor is coupled to the seventh node.

13. The shift register according to claim 4, characterized in that,

The sixth node control sub-circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third clock signal input terminal, and the second terminal of which is coupled to the sixth node.

The seventh node control sub-circuit includes an eighteenth transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third clock signal input terminal, and the second terminal of which is coupled to the seventh node.

14. The shift register according to claim 5, characterized in that,

The first input node control sub-circuit includes a twentieth transistor, the gate of which is coupled to the start signal input terminal, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the input node.

The second input node control sub-circuit includes a twenty-first transistor, the gate of which is coupled to the eighth node, the first terminal of which is coupled to the first level signal input terminal, and the second terminal of which is coupled to the input node.

The eighth node control sub-circuit includes a twenty-second transistor and a fourth capacitor. The gate of the twenty-second transistor is coupled to the start signal input terminal, the first terminal of the twenty-second transistor is coupled to the third level signal input terminal, and the second terminal of the twenty-second transistor is coupled to the eighth node. The first terminal of the fourth capacitor is coupled to the third clock signal input terminal, and the second terminal of the fourth capacitor is coupled to the eighth node.

15. The shift register according to claim 6, characterized in that,

The sixth node control sub-circuit includes a third transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the sixth node.

The seventh node control sub-circuit includes an eighteenth transistor, the gate of which is coupled to the first node, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the seventh node.

The coupling sub-circuit includes a fifth capacitor, the first end of which is coupled to the third clock signal input terminal, and the second end of which is coupled to the ninth node.

The ninth node control sub-circuit includes a twenty-third transistor, the gate of which is coupled to the start signal input terminal, the first terminal of which is coupled to the third level signal input terminal, and the second terminal of which is coupled to the ninth node.

16. The shift register according to claim 7, characterized in that,

The first input sub-circuit includes a first transistor, the gate of which is coupled to the third clock signal input terminal, the first terminal of which is coupled to the start signal input terminal, and the second terminal of which is coupled to the first node.

17. The shift register according to claim 8, characterized in that,

The first node control sub-circuit includes a fourth transistor and a fifth transistor. The gate of the fourth transistor is coupled to the sixth node, the first terminal of the fourth transistor is coupled to the third level signal input terminal, and the second terminal of the fourth transistor is coupled to the first terminal of the fifth transistor. The gate of the fifth transistor is coupled to the second clock signal input terminal, and the second terminal of the fifth transistor is coupled to the first node.

18. The shift register according to claim 9, characterized in that,

The second cascaded control sub-circuit includes a seventh transistor and a first capacitor. The gate of the seventh transistor is coupled to the sixth node, the first terminal of the seventh transistor is coupled to the third-level signal input terminal, and the second terminal of the seventh transistor is coupled to the cascaded signal output terminal. The first terminal of the first capacitor is coupled to the third-level signal input terminal, and the second terminal of the first capacitor is coupled to the sixth node.

19. A method for driving a shift register, characterized in that it is applied to a shift register as described in any one of claims 1 to 18, the method comprising:

Under the control of the potential of the first output node, the first output sub-circuit controls the electrical connection between the gate drive signal output terminal and the first clock signal input terminal to be turned on or off.

The first output node control sub-circuit, under the control of the first level signal input to the first level signal input terminal, controls the electrical connection between the first node and the first output node to be turned on or off; it also controls the electrical connection between the first output node and the first level signal input terminal to be turned on or off under the control of the potential of the second node.

The first cascade control sub-circuit, under the control of the potential of the second node, controls the electrical connection between the second clock signal input terminal and the cascade signal output terminal to be turned on or off, and also controls the potential of the second node according to the cascade signal output by the cascade signal output terminal;

Under the control of the first level signal, the first isolation control sub-circuit controls the conduction of the electrical connection between the first node and the second node.

20. The driving method for a shift register according to claim 19, characterized in that the driving method further comprises:

The second output sub-circuit, under the control of the potential of the second output node, controls the electrical connection between the gate drive signal output terminal and the second level signal input terminal to be turned on or off.

The fourth node control sub-circuit, under the control of the potential of the first node, controls the electrical connection between the fourth node and the third level signal input terminal to be turned on or off; it also controls the potential of the fifth node according to the potential of the fourth node.

The fourth node control sub-circuit, under the control of the potential of the fifth node, controls the connection between the fourth node and the fourth clock signal input terminal to be turned on or off; or, under the control of the potential of the fifth node, controls the connection between the fourth node and the second clock signal input terminal to be turned on or off.

The second output node control sub-circuit, under the control of the potential of the fifth node, controls the electrical connection between the second output node and the fifth node to be turned on or off.

21. A display device, characterized in that it includes a shift register as described in any one of claims 1 to 18.