CN118900563A - Antifuse unit, antifuse array and memory - Google Patents

Abstract

The embodiments of the present disclosure provide an anti-fuse unit, an anti-fuse array and a memory, wherein the anti-fuse unit comprises: a substrate; the substrate comprises an active area and a first doped area located in the active area; a first gate structure and a second gate structure, which are located on the surface of the active area on both sides of the first doped area along a first direction; wherein the active area comprises a first pair of adjacent surfaces extending along a third direction, and a first angle is formed between the first pair of adjacent surfaces; the vertex of the first angle has a first intersection with the top surface of the active area, and the first intersection is located within the projection area of the first gate structure on the active area; the first angle is less than 180 degrees; the first direction is perpendicular to the extension direction of the first doped area and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located.

Description

Antifuse unit, antifuse array and memory

Technical Field

The present disclosure relates to the field of semiconductor technology, and relates to but is not limited to an anti-fuse unit, an anti-fuse array, and a memory.

Background Art

Anti-fuse devices are one-time programmable devices (OTP). Once the anti-fuse device is programmed, the stored data is permanent. Due to this feature, anti-fuse devices are widely used in memories such as dynamic random access memory (DRAM) to provide a one-time programming address table when redundant memory cells are repaired. For example, when a memory cell corresponding to a word line is defective, the DRAM control circuit turns off the reading and writing of this memory cell, and turns on the reading and writing of a memory cell in the redundant area through the anti-fuse device. At this time, the memory cell corresponding to the redundant area completely replaces the defective memory cell, and the DRAM defect is repaired.

Currently, when an anti-fuse device is blown, the resistance value of the anti-fuse device fluctuates greatly after it is blown due to the large channel area under the fuse gate and the unstable breakdown position, which has a great impact on subsequent reading operations.

Summary of the invention

In view of this, embodiments of the present disclosure provide an anti-fuse unit, an anti-fuse array, and a memory.

In a first aspect, an embodiment of the present disclosure provides an anti-fuse unit, comprising:

A substrate; the substrate comprises an active region and a first doped region located in the active region;

A first gate structure and a second gate structure are located on the surface of the active region at both sides of the first doped region along a first direction;

The active region includes a first pair of adjacent surfaces extending along a third direction, and a first angle is formed between the first pair of adjacent surfaces; a vertex of the first angle has a first intersection with a top surface of the active region, and the first intersection is located within a projection area of the first gate structure on the active region; and the first angle is less than 180 degrees;

The first direction is perpendicular to the extension direction of the first doping region and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located.

In some embodiments, the active region further includes a second pair of adjacent faces extending along the third direction, the second pair of adjacent faces forming a second angle;

The vertex of the second angle has a second intersection with the top surface of the active region; the second intersection is located within a projection area of the first gate structure on the active region.

In some embodiments, the second angle is less than 180 degrees;

The projections of the first intersection point and the second intersection point in a plane perpendicular to the second direction coincide with each other;

The second direction is an extension direction of the first doping region.

In some embodiments, the first angle and the second angle are both 135 degrees.

In some embodiments, the substrate further comprises a shallow trench isolation structure between the active regions;

The first gate structure is also located on a surface of a portion of the shallow trench isolation structure.

In some embodiments, the substrate further includes a second doped region formed in the active region, and a conductive contact structure connected to the second doped region;

The second gate structure is located between the first doping region and the second doping region.

In some embodiments, the anti-fuse unit further includes: a conductive line electrically connected to the conductive contact structure;

The first gate structure includes a first gate insulating layer and a first gate conductive layer located on a surface of the first gate insulating layer; the second gate structure includes a second gate insulating layer and a second gate conductive layer located on a surface of the second gate insulating layer.

In a second aspect, an embodiment of the present disclosure provides an antifuse array, comprising:

A plurality of anti-fuse units as described in the above embodiments; wherein the plurality of anti-fuse units are arranged in an array along the first direction and the second direction, and each two adjacent anti-fuse units along the first direction share the second doping region;

The first gate structures of the anti-fuse units arranged along the second direction are electrically connected, and the second gate structures of the anti-fuse units arranged along the second direction are electrically connected.

In some embodiments, the first gate conductive layers of the anti-fuse units arranged along the second direction are electrically connected, and the second gate conductive layers of the anti-fuse units arranged along the second direction are electrically connected.

In a third aspect, an embodiment of the present disclosure provides a memory, comprising the anti-fuse array in the above embodiment.

The embodiments of the present disclosure provide an anti-fuse unit, an anti-fuse array and a memory, wherein the anti-fuse unit comprises: a substrate; the substrate comprises an active area and a first doped area located in the active area; a first gate structure and a second gate structure, which are located on the surface of the active area on both sides of the first doped area along a first direction; wherein the active area comprises a first pair of adjacent surfaces extending along a third direction, and a first angle is formed between the first pair of adjacent surfaces; the vertex of the first angle has a first intersection with the top surface of the active area, and the first intersection is located within the projection area of the first gate structure on the active area; the first angle is less than 180 degrees; the first direction is perpendicular to the extension direction of the first doped area and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located. Since the first intersection where the vertex of the first angle coincides with the top surface of the active area is located within the projection area of the first gate structure on the active area, and the first intersection can serve as a tip discharge point, the breakdown point of the anti-fuse unit can be located at the first intersection (or near the first intersection), so that the breakdown position of the anti-fuse unit is controllable, and the resistance fluctuation is small after the anti-fuse unit is blown, which will not affect subsequent reading operations.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of the structure of an antifuse array;

FIG2 is a schematic diagram of the structure of a programming device in the antifuse array of FIG1 when it is blown;

FIG3 is a first structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG4 is a second structural schematic diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG5 is a third structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG6 is a fourth structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG7 is a fifth structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG8 is a sixth structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG9 is a seventh structural diagram of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG10 is a schematic diagram of a program structure when a programming device in an anti-fuse unit provided by an embodiment of the present disclosure is blown;

FIG11 is a structural schematic diagram 8 of an anti-fuse unit provided in an embodiment of the present disclosure;

FIG12 is a schematic diagram of the structure of an antifuse array provided in an embodiment of the present disclosure;

FIG13 is a schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

FIG. 14 is a schematic diagram of the structure of a memory provided in an embodiment of the present disclosure.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present disclosure to clearly and completely describe the technical solutions in the embodiments of the present disclosure. It is understood that the specific embodiments described herein are only used to explain the relevant application, rather than to limit the application. It should also be noted that, for the convenience of description, only the parts related to the relevant application are shown in the drawings.

Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein are only for the purpose of describing the embodiments of the present disclosure and are not intended to limit the present disclosure.

In the following description, reference is made to “some embodiments”, which describe a subset of all possible embodiments, but it will be understood that “some embodiments” may be the same subset or different subsets of all possible embodiments and may be combined with each other without conflict.

It should be pointed out that the terms "first\second\third" involved in the embodiments of the present disclosure are only used to distinguish similar objects and do not represent a specific ordering of the objects. It can be understood that "first\second\third" can be interchanged in a specific order or sequence where permitted, so that the embodiments of the present disclosure described here can be implemented in an order other than that illustrated or described here.

The anti-fuse structure is used in DRAM chips to provide a one-time programming address table when the redundant memory cell is repaired. The anti-fuse structure that is currently more compatible with integrated circuit technology is the fuse oxide anti-fuse. The fuse oxide anti-fuse uses a substrate, a fuse oxide layer (i.e., a gate insulating layer) and a gate electrode to form a sandwich structure. The anti-fuse structure breaks through the gate insulating layer under high voltage to form a conductive path, and the two states of the gate insulating layer, the blown and un-blown, can represent the logical value "1" and the logical value "0" respectively.

Please refer to FIG. 1 , which shows a schematic diagram of the structure of an anti-fuse array. As shown in FIG. 1 , the anti-fuse array 10 includes two anti-fuse units 11 arranged along the X-axis direction, and each anti-fuse unit 11 includes a selection device and a programming device. Among them, the selection device is controlled by the word line WL, and the programming device is controlled by the programming wire (Anti-fuse, AF). The two anti-fuse units 11 adjacent to each other along the X-axis direction share the same active area 101 and are led out through the same bit line contact plug 102, that is, the two anti-fuse units 11 adjacent to each other in the X-axis direction are connected to the same bit line BL.

It should be noted that FIG. 1 only shows two anti-fuse units 11 . In fact, an anti-fuse array 10 may include a plurality of anti-fuse units 11 arranged in an array along the X-axis direction and the Y-axis direction.

In some embodiments, please continue to refer to Figure 1. When the anti-fuse unit 11 is blown (or called a programming operation), a high voltage (about 5.5 to 6 volts) needs to be applied to the corresponding programming conductor AF, and the corresponding bit line BL is set to 0 volts, and the corresponding selection device is turned on, so that the thin gate oxide of the programming device is broken down under the high voltage, thereby significantly reducing the resistance of the programming device and realizing the programming operation.

Please refer to FIG2, which shows a schematic diagram of the structure when the programming device in the antifuse array in FIG1 is blown. As shown in FIG2, when the thin gate oxide of the programming device is blown, due to the large channel area under the gate of the programming device (i.e., the programming wire AF), the breakdown position may be located at A1, A2, A3, and A4 in FIG2, and the breakdown position is unstable, resulting in a large fluctuation in the resistance value after the thin gate oxide is blown, which has a great impact on the subsequent reading operation.

Based on this, the embodiments of the present disclosure provide an anti-fuse unit, an anti-fuse array and a memory, wherein the anti-fuse unit includes: a substrate; the substrate includes an active area and a first doped area located in the active area; a first gate structure and a second gate structure, which are located on the surface of the active area on both sides of the first doped area along a first direction; wherein the active area includes a first pair of adjacent surfaces extending along a third direction, and a first angle is formed between the first pair of adjacent surfaces; the vertex of the first angle has a first intersection with the top surface of the active area, and the first intersection is located within the projection area of the first gate structure on the active area; the first angle is less than 180 degrees; the first direction is perpendicular to the extension direction of the first doped area and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located. Since the first intersection where the vertex of the first angle coincides with the top surface of the active area is located within the projection area of the first gate structure on the active area, and the first intersection can serve as a tip discharge point, the breakdown point of the anti-fuse unit can be located at the first intersection (or near the first intersection), so that the breakdown position of the anti-fuse unit is controllable, and the resistance fluctuation is small after the anti-fuse unit is blown, which will not affect subsequent reading operations.

The embodiments of the present disclosure will be described in detail below with reference to the accompanying drawings.

In one embodiment of the present disclosure, referring to FIG. 3 to FIG. 5, a schematic diagram of the structure of an anti-fuse unit provided in an embodiment of the present disclosure is shown; wherein FIG. 3 is a three-dimensional view, FIG. 4 is a top view of FIG. 3, and FIG. 5 is a cross-sectional view. As shown in FIG. 3 to FIG. 5, the anti-fuse unit 20 may include:

The substrate includes an active region 201 and a first doped region 205 located in the active region 201 (as shown in FIG. 5 );

The first gate structure 202 and the second gate structure 203 are located on the surface of the active area 201 on both sides of the first doped area 205 along the first direction; wherein the active area 201 includes a first pair of adjacent surfaces (surface B1 and surface B2) extending along a third direction, and a first angle is formed between the first pair of adjacent surfaces (surface B1 and surface B2); the vertex of the first angle has a first intersection B with the top surface 201a of the active area 201 (as shown in FIG. 4 ), and the first intersection B is located within the projection area of the first gate structure 202 on the active area 201; the first angle is less than 180 degrees.

In the embodiment of the present disclosure, a direction intersecting (e.g., perpendicular) to the plane where the substrate is located may be defined as a third direction, and two first directions and second directions intersecting (e.g., perpendicular) to each other may be defined in the plane where the substrate is located, for example, the extension direction of the first doping region 205 is defined as the second direction. In the embodiment of the present disclosure, the first direction may be the X-axis direction, the second direction may be the Y-axis direction, and the third direction may be the Z-axis direction. The first direction may be perpendicular to the second direction and the third direction, or may not be perpendicular to each other.

Please continue to refer to FIG. 5. It can be understood that the substrate may include a semiconductor substrate, a deep N-well (DNW) 208 located in the semiconductor substrate, and an active area 201 located in the deep N-well 208. The semiconductor substrate may be a silicon substrate, and the semiconductor substrate may also include other semiconductor elements, such as germanium (Ge), or semiconductor compounds, such as silicon carbide (SiC), gallium arsenide (GaAs), gallium phosphide (GaP), indium phosphide (InP), indium arsenide (InAs) or indium antimonide (InSb), or other semiconductor alloys, such as silicon germanium (SiGe), gallium arsenic phosphide (GaAsP), aluminum indium arsenide (AlInAs), aluminum gallium arsenide (AlGaAs), gallium indium arsenide (GaInAs), gallium indium phosphide (GaInP), and/or gallium indium arsenide phosphide (GaInAsP) or a combination thereof. In the embodiment of the present disclosure, the semiconductor substrate may be a P-type doped substrate, and the deep N-well 208 is used to isolate the device formed in the active area 201 from other devices to reduce signal interference between the devices.

It should be noted that the anti-fuse unit 20 in the embodiment of the present disclosure includes a selection device and a programming device; wherein the first gate structure 202 may be a gate of the selection device (i.e., a word line WL), and the second gate structure 203 may be a gate of the programming device. The first doped region 205 may be a region formed by ion implantation of a portion of the active region 201, and the first doped region 205 may be, for example, a drain of the selection device in the anti-fuse unit 20.

5 , the substrate further includes a second doped region 206 formed in the active region 201 and a conductive contact structure 204 connected to the second doped region 206. The anti-fuse unit 20 further includes a conductive line 209 electrically connected to the conductive contact structure 204.

It can be understood that the second doped region 206 can be a region formed by ion implantation of a portion of the active region 201, and the second doped region 206 can be, for example, a source of a selection device in the anti-fuse unit 20. The conductive contact structure 204 can be a bit line contact structure, and the conductive contact structure 204 is located on the surface of the second doped region 206, and is used to electrically connect the conductive line 209 (i.e., the bit line BL) and the second doped region 206.

In some embodiments, please continue to refer to FIG. 5 , the second gate structure 203 is located on the surface of the active region between the first doping region 205 and the second doping region 206 .

In some embodiments, please continue to refer to FIG. 5 , the first gate structure 202 includes a first gate insulating layer 2021 and a first gate conductive layer 2022 located on the surface of the first gate insulating layer 2021; the second gate structure 203 includes a second gate insulating layer 2031 and a second gate conductive layer 2032 located on the surface of the second gate insulating layer 2031. The material of the first gate insulating layer 2021 and the second gate insulating layer 2031 may be silicon oxide or other suitable materials, and the material of the first gate conductive layer 2022 and the second gate conductive layer may be any material with good conductivity, such as any one of titanium, titanium nitride, tungsten nitride (WN), tungsten (W), cobalt (Co), platinum (Pt), palladium (Pd), ruthenium (Ru), and copper (Cu).

It should be noted that the first gate insulating layer 2021 in the first gate structure 202 can be regarded as a thin gate oxide layer of the programming device, the first gate conductive layer 2022 can be regarded as a programming wire of the programming device, and the second gate conductive layer 2032 of the second gate structure 203 can be regarded as a word line WL of the anti-fuse unit 20 .

During programming, the first gate insulating layer 2021 needs to be broken down, while ensuring the normal operation of the selection device, that is, ensuring that the selection device is not broken down. Next, the programming and reading principle of the anti-fuse unit 20 is explained in combination with the above specific structure:

During programming, a voltage is applied to the selection device through the second gate conductive layer 2032 (i.e., word line WL) to turn on the selection device, and a high voltage (which must be smaller than the breakdown voltage of the selection device) is applied to the programming device through the first gate conductive layer 2022, and the voltage of the conductive line 209 (i.e., bit line BL) is set to 0, so that the first gate insulating layer 2021 is broken down, thereby realizing the programming operation.

During reading, since the first gate insulating layer 2021 is broken down, there is current in the path between the programming device and the conductive line 209 , and the reading operation can be realized by reading the circuit in the path through the conductive line 209 .

In some embodiments, the active region 201 includes a first pair of adjacent faces (i.e., face B1 and face B2) extending along a third direction. Since face B1 and face B2 are adjacent (i.e., intersecting), a first angle can be formed between face B1 and face B2. It can be understood that there are countless first angles between face B1 and face B2 along the third direction, and the lines connecting the vertices of all the first angles constitute the edges where face B1 and face B2 intersect. The first angle is less than 180 degrees, and can be, for example, 100 degrees, 120 degrees, 135 degrees, 140 degrees, or 170 degrees.

In some embodiments, the first angle may be an obtuse angle.

In other embodiments, the first angle may also be an acute angle.

It should also be noted that the top surface 201a of the active region refers to the surface of the active region 201 that contacts the first gate structure 202 and the second gate structure 203, and the top surface 201a of the active region contacts both the surface B1 and the surface B2. The vertex of the first angle is located on the edge where the surface B1 and the surface B2 intersect, and the intersection of this intersecting edge and the top surface 201a of the active region constitutes a first intersection point B, that is, the first intersection point B is the point of overlap between the vertex of the first angle and the top surface 201a of the active region.

It should also be noted that the first intersection B is located within the projection area of the first gate structure 202 on the active area 201, which means that the first intersection B can be located at any position within the projection area of the first gate structure 202 on the active area 201, for example, it can be located at the inner center of the projection area, the edge of the projection area, the upper left part of the projection area, the lower left part of the projection area, the upper right part of the projection area, the lower right part of the upper right part of the projection area, etc. In the embodiment of the present disclosure, the specific position of the first intersection B in the projection area is not limited.

In the disclosed embodiment, since the first angle is less than 180 degrees, the first intersection B can have a large curvature and can serve as a tip discharge point; and since the first intersection B is located within the projection area of the first gate structure 202 on the active area 201, when the first gate insulation layer 2021 of the programming device corresponding to the first gate structure 202 is broken down, the breakdown point of the first gate insulation layer 2021 can be controlled near the first intersection B. In this way, the breakdown position of the anti-fuse unit can be controlled, so that the resistance fluctuation after the anti-fuse unit is blown is small, and will not affect subsequent reading operations.

It should also be noted that, since the third direction may be perpendicular to the plane where the substrate is located, or may not be perpendicular to the plane where the substrate is located, the projection of all the vertices of the first angles on the top surface of the active area may be a single point or multiple continuous points. In the embodiment of the present disclosure, it is only necessary to ensure that the first intersection point where the vertex of the first angle coincides with the top surface of the active area is located within the projection area of the first gate structure 202 on the active area 201.

In some embodiments, based on the anti-fuse unit 20 shown in Figures 3 to 5, please refer to Figures 6 to 9, which show another schematic diagram of the structure of the anti-fuse unit 20, wherein Figure 6 is a three-dimensional view, and Figures 7 to 9 are all top views. As shown in Figures 6 to 9, the active area 201 includes a first pair of adjacent surfaces extending along the Z-axis direction (i.e., surface B1 and surface B2) and a second pair of adjacent surfaces extending along the Z-axis direction (i.e., surface C1 and surface C2). Among them, a first angle is formed between the first pair of adjacent surfaces (surface B1 and surface B2); the vertex of the first angle has a first intersection B with the top surface 201a of the active area (as shown in Figures 7 to 9), and the first intersection B is located in the projection area of the first gate structure 202 on the active area 201; the first angle is less than 180 degrees; a second angle is formed between the second pair of adjacent surfaces (surface C1 and surface C2); the vertex of the second angle has a second intersection C with the top surface 201a of the active area (as shown in Figures 7 to 9); the second intersection C is located in the projection area of the first gate structure 202 on the active area 201.

It should be noted that, since face B1 and face B2 are adjacent (i.e., intersecting), a first angle can be formed between face B1 and face B2. It can be understood that there are countless first angles along the third direction between face B1 and face B2, and the lines connecting the vertices of all the first angles constitute the edge where face B1 and face B2 intersect. Since face C1 and face C2 are adjacent (i.e., intersecting), a second angle can be formed between face C1 and face C2. It can be understood that there are countless second angles along the third direction between face C1 and face C2, and the lines connecting the vertices of all the second angles constitute the edge where face C1 and face C2 intersect.

It should also be noted that the top surface 201a of the active region is in contact with the surface B1, the surface B2, the surface C1 and the surface C2. The vertex of the first angle is located on the edge where the surface B1 and the surface B2 intersect, and the intersection of the edge and the top surface 201a of the active region constitutes a first intersection point B, that is, the first intersection point B is the point of overlap between the vertex of the first angle and the top surface 201a of the active region. The vertex of the second angle is located on the edge where the surface C1 and the surface C2 intersect, and the intersection of the edge and the top surface 201a of the active region constitutes a second intersection point C, that is, the second intersection point C is the point of overlap between the vertex of the second angle and the top surface 201a of the active region.

It should also be noted that the second intersection C is located within the projection area of the first gate structure 202 on the active area 201, which means that the second intersection C can be located at any position within the projection area of the first gate structure 202 on the active area 201, for example, it can be located at the inner center of the projection area, the edge of the projection area, the upper left part of the projection area, the lower left part of the projection area, the upper right part of the projection area, the lower right part of the projection area, etc. In the embodiment of the present disclosure, the specific position of the second intersection C in the projection area is not limited.

It is worth noting that the first intersection point B and the second intersection point C do not coincide.

In some embodiments, the second angle is less than 180 degrees, such as 95 degrees, 105 degrees, 115 degrees, 125 degrees, 145 degrees or 165 degrees; or, the second angle is greater than 180 degrees and less than 360 degrees.

In some embodiments, when the second angle is greater than 180 degrees and less than 360 degrees, the second intersection C cannot be used as a tip discharge point, and therefore, the first gate structure 202 has only one tip discharge point in the projection area on the active area 201, namely, the first intersection B. At this time, when the first gate insulating layer 2021 of the programming device corresponding to the first gate structure 202 is broken down, the breakdown point of the first gate insulating layer 2021 can be controlled to be near the first intersection B, so that the breakdown position of the anti-fuse unit can be controlled, and the resistance value fluctuation after the anti-fuse unit is blown is small, which will not affect the subsequent reading operation.

In some embodiments, when the second angle is less than 180 degrees, the second intersection C may have a large curvature and may be used as a tip discharge point. Therefore, the first gate structure 202 has two tip discharge points in the projection area on the active area 201, namely, the first intersection B and the second intersection C. Please refer to FIG10, which shows a schematic diagram of the structure when the programming device in the anti-fuse unit provided in an embodiment of the present disclosure is blown. As shown in Figure 10, when the first gate insulation layer 2021 of the programming device corresponding to the first gate structure 202 is blown, since the top surface of the active area under the first gate structure 202 includes the first intersection B and the second intersection C, the first intersection B is the vertex of the first angle, and the second intersection C is the vertex of the second angle. In this way, when the first gate insulation layer 2021 of the programming device corresponding to the first gate structure 202 is broken down, the breakdown points A5 and A6 of the first gate insulation layer 2021 can be controlled to be near the first intersection B and the second intersection C, respectively. In this way, the breakdown position of the anti-fuse unit can be controlled, and the resistance fluctuation is small after the anti-fuse unit is blown, which will not affect the subsequent reading operation.

In some embodiments, when the second angle is less than 180 degrees, the projections of the first intersection B and the second intersection C in a plane perpendicular to the second direction (i.e., the Y-axis direction) coincide with each other. In this way, the position of the breakdown point of the first gate insulating layer 2021 can be further controlled so that the resistance values of the anti-fuse units after breakdown are consistent.

In some embodiments, please continue to refer to FIG6, two surfaces in the first pair of adjacent surfaces (i.e., surface B1 and surface B2) and the second surface in the second pair of adjacent surfaces (i.e., surface C1 and surface C2) can be spaced apart. For example, when surface B2 and surface C2 are spaced apart, the top view of the anti-fuse unit 20 is shown in FIG7. In this way, the area of the active region under the first gate structure can be made larger, and the control capability of the first gate structure can be enhanced.

In some embodiments, please continue to refer to FIG6, two surfaces in the first pair of adjacent surfaces (i.e., surface B1 and surface B2) and two surfaces in the second pair of adjacent surfaces (i.e., surface C1 and surface C2) can be arranged adjacent to each other (i.e., intersecting each other), for example, when surface B2 and surface C2 are arranged intersectingly, the top view of the anti-fuse unit 20 is shown in FIG8 and FIG9. In this way, the area of the active region under the first gate structure can be made smaller, and the area of the anti-fuse unit can be reduced while ensuring that the breakdown position is controllable, thereby achieving miniaturization of the semiconductor device finally formed.

In some embodiments, when the first angle and the second angle are both less than 180 degrees, the first angle and the second angle may be equal (please refer to FIG8 ). For example, the first angle and the second angle are both 135 degrees. In this way, the position of the breakdown point of the first gate insulating layer can be further controlled so that the resistance value of the anti-fuse unit after breakdown is consistent.

In other embodiments, the first angle and the second angle may both be 100 degrees, 110 degrees, 120 degrees, 130 degrees, 150 degrees, 160 degrees, 170 degrees, etc.

In some embodiments, when the first angle and the second angle are both less than 180 degrees, the first angle and the second angle may not be equal (please refer to FIG. 9 ). For example, the first angle is 120 degrees and the second angle is 160 degrees. In this way, the position of the breakdown point of the first gate insulating layer can also be controlled to be near the first intersection B and the second intersection C, so that the resistance value of the anti-fuse unit after breakdown is close to the same.

In the disclosed embodiment, a 45-degree beveled active area boundary is used below the fuse gate (i.e., the first gate structure) that requires high voltage breakdown to match the crystal orientation, thereby achieving the effect of roughening the boundary morphology of the active area 201, making it easier to concentrate the breakdown position on the rough boundary of the active area, thereby controlling the breakdown position and further controlling the resistance value of the programmed device after the fuse is blown.

In some embodiments, the first angle and the second angle may both be 90 degrees.

Based on the anti-fuse unit 20 disclosed above, please refer to FIG11, which shows a schematic diagram of the structure of two anti-fuse units 20. As shown in FIG11, the substrate includes an active region 201 and a shallow trench isolation structure 207 located between the active regions 201; the first gate structure 202 is located on the surface of both the active region 201 and the shallow trench isolation structure 207.

In the structure shown in Figure 11, the first gate structure 202 has two turning points in the projection area on the active area 201, namely the first intersection B and the second intersection C. In this way, when the first gate insulation layer 2021 of the programming device corresponding to the first gate structure 202 is broken down, the breakdown point of the first gate insulation layer 2021 can be controlled near the first intersection B and the second intersection C. In this way, the breakdown position of the anti-fuse unit can be controlled, and the resistance fluctuation is small after the anti-fuse unit is blown, which will not affect the subsequent reading operation.

In another embodiment of the present disclosure, see FIG12, which shows a schematic diagram of the structure of an anti-fuse array provided by the embodiment of the present disclosure. As shown in FIG12, the anti-fuse array 30 includes a plurality of anti-fuse units 20 provided by the above-mentioned embodiments; wherein the plurality of anti-fuse units 20 are arranged in an array along the first direction and the second direction, and each two adjacent anti-fuse units 20 along the first direction share a second doping region (not shown); the first gate structures 202 of the anti-fuse units arranged along the second direction are electrically connected, and the second gate structures 203 of the anti-fuse units 20 arranged along the second direction are electrically connected.

It should be noted that the anti-fuse unit 20 further includes a conductive contact structure 204 , which is located on the surface of the second doped region. Here, the position of the second doped region in the active region 201 can be understood with reference to the position of the conductive contact structure 204 .

The top of the conductive contact structure 204 is used to connect the conductive line (ie, the bit line BL). Therefore, every two adjacent anti-fuse units 20 along the first direction share the second doped region. It can be understood that every two adjacent anti-fuse units 20 along the first direction share the bit line BL.

In some embodiments, the anti-fuse in the embodiments of the present disclosure can be understood with reference to the above-mentioned Figures 3 to 5. Specifically: the anti-fuse unit 20 also includes a first doped region (not shown) located in the active region 201, and the first doped region is located in the active region between the first gate structure 202 and the second gate structure 203. The first doped region, the second gate structure, and the second doped region constitute a selection device, and the first gate structure constitutes a programming device.

The first gate structure 202 includes a first gate insulating layer 2021 and a first gate conductive layer 2022 located on the surface of the first gate insulating layer 2021 ; the second gate structure 203 includes a second gate insulating layer 2031 and a second gate conductive layer 2032 located on the surface of the second gate insulating layer 2031 .

In some embodiments, the first gate conductive layers 2022 of the anti-fuse units 20 arranged along the second direction are electrically connected, and the second gate conductive layers 2032 of the anti-fuse units 20 arranged along the second direction are electrically connected.

In some embodiments, the active area 201 of the anti-fuse unit 20 includes a first pair of adjacent surfaces (i.e., surface B1 and surface B2) extending along a third direction, and a first angle is formed between the first pair of adjacent surfaces; the vertex of the first angle has a first intersection B with the top surface 201a of the active area 201 (as shown in Figure 4), and the first intersection B is located within the projection area of the first gate structure 202 on the active area 201; the first angle is less than 180 degrees.

The anti-fuse array provided by the embodiment of the present disclosure includes an anti-fuse unit. Since there is a first intersection B on the top surface of the active area 201 in the anti-fuse unit, and the first intersection B is located in the projection area of the first gate structure 202 on the active area 201, when the first gate insulation layer 2021 of the first gate structure 202 is broken down, the breakdown point of the first gate insulation layer 2021 can be controlled to be near the first intersection B. In this way, the breakdown position of the anti-fuse unit can be controlled, and the resistance fluctuation after the anti-fuse unit is blown is small, which will not affect the subsequent reading operation.

In another embodiment of the present disclosure, referring to Fig. 13, a schematic diagram of the composition structure of a semiconductor structure provided by an embodiment of the present disclosure is shown. As shown in Fig. 13, the semiconductor structure 40 at least includes the anti-fuse array 30 as described in the above embodiment.

In the disclosed embodiment, for the semiconductor structure 40, the anti-fuse array 30 therein may include a plurality of anti-fuse units 20 arranged in an array along a first direction and a second direction, and the anti-fuse unit 20 includes: a substrate; the substrate includes an active region and a first doped region located in the active region; a first gate structure and a second gate structure, located on the surface of the active region on both sides of the first doped region along the first direction; wherein the active region includes a first pair of adjacent faces extending along a third direction, and a first angle is formed between the first pair of adjacent faces; the vertex of the first angle has a first intersection with the top surface of the active region, and the first intersection is located in the projection area of the first gate structure on the active region; the first angle is less than 180 degrees; the first direction is perpendicular to the extension direction of the first doped region and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located. Since the first angle is less than 180 degrees, the first intersection B can have a large curvature and can be used as a tip discharge point. When the first intersection is located within the projection area of the first gate structure on the active area, when the first gate insulation layer of the first gate structure is broken down, the breakdown point of the first gate insulation layer can be controlled near the first intersection. In this way, the breakdown position of the anti-fuse unit can be controlled, and the resistance fluctuation is small after the anti-fuse unit is blown, which will not affect subsequent reading operations.

In another embodiment of the present disclosure, referring to Fig. 14, a schematic diagram of the composition structure of a memory provided by the embodiment of the present disclosure is shown. As shown in Fig. 14, the memory 50 at least includes the semiconductor structure 40 as described in the above embodiment.

In some embodiments, the memory 50 may include a DRAM chip, a static random access memory (SRAM) chip, a phase change memory (PCM) chip, a NAND Flash chip, or a Nor Flash chip.

In the disclosed embodiment, for the memory 50, the semiconductor structure 40 therein may be an antifuse array 30, and the antifuse array 30 may include a plurality of antifuse units arranged in an array, and the antifuse unit 20 includes: a substrate; the substrate includes an active region and a first doped region located in the active region; a first gate structure and a second gate structure, located on the surface of the active region on both sides of the first doped region along the first direction; wherein the active region includes a first pair of adjacent faces extending along a third direction, and a first angle is formed between the first pair of adjacent faces; the vertex of the first angle has a first intersection with the top surface of the active region, and the first intersection is located in the projection area of the first gate structure on the active region; the first angle is less than 180 degrees; the first direction is perpendicular to the extension direction of the first doped region and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located. Since the first angle is less than 180 degrees, the first intersection B can have a large curvature and can be used as a tip discharge point. When the first intersection is located within the projection area of the first gate structure on the active area, when the first gate insulation layer of the first gate structure is broken down, the breakdown point of the first gate insulation layer can be controlled near the first intersection. In this way, the breakdown position of the anti-fuse unit can be controlled, and the resistance fluctuation is small after the anti-fuse unit is blown, which will not affect subsequent reading operations.

The above description is only a preferred embodiment of the present disclosure and is not intended to limit the protection scope of the present disclosure.

It should be noted that in the present disclosure, the terms "include", "comprises" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also includes other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "includes a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

The serial numbers of the above-mentioned embodiments of the present disclosure are only for description and do not represent the advantages or disadvantages of the embodiments.

The methods disclosed in several method embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

The features disclosed in several product embodiments provided in the present disclosure can be arbitrarily combined without conflict to obtain new product embodiments.

The features disclosed in several method or device embodiments provided in the present disclosure may be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

The above are only some embodiments of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art who is familiar with the technical field can easily think of changes or substitutions within the technical scope disclosed in the present disclosure, which should be included in the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be based on the protection scope of the claims.

Claims (10)

1. An anti-fuse unit, comprising: A substrate; the substrate comprises an active region and a first doped region located in the active region; A first gate structure and a second gate structure are located on the surface of the active region at both sides of the first doped region along a first direction; The active region includes a first pair of adjacent surfaces extending along a third direction, and a first angle is formed between the first pair of adjacent surfaces; a vertex of the first angle has a first intersection with a top surface of the active region, and the first intersection is located within a projection area of the first gate structure on the active region; and the first angle is less than 180 degrees; The first direction is perpendicular to the extension direction of the first doping region and is located in the plane where the substrate is located; the third direction intersects with the plane where the substrate is located. 2. The anti-fuse unit according to claim 1, characterized in that the active region further comprises a second pair of adjacent surfaces extending along the third direction, and the second pair of adjacent surfaces forms a second angle; The vertex of the second angle has a second intersection with the top surface of the active region; the second intersection is located within a projection area of the first gate structure on the active region. 3. The anti-fuse unit according to claim 2, wherein the second angle is less than 180 degrees; The projections of the first intersection point and the second intersection point in a plane perpendicular to the second direction coincide with each other; The second direction is an extension direction of the first doping region. 4 . The anti-fuse unit according to claim 3 , wherein the first angle and the second angle are both 135 degrees. 5. The anti-fuse unit according to claim 2, wherein the substrate further comprises a shallow trench isolation structure located between the active regions; The first gate structure is also located on a surface of a portion of the shallow trench isolation structure. 6. The anti-fuse unit according to claim 4, characterized in that the substrate further comprises a second doped region formed in the active region, and a conductive contact structure connected to the second doped region; The second gate structure is located between the first doping region and the second doping region. 7. The anti-fuse unit according to claim 6, characterized in that the anti-fuse unit further comprises: a conductive line electrically connected to the conductive contact structure; The first gate structure includes a first gate insulating layer and a first gate conductive layer located on a surface of the first gate insulating layer; the second gate structure includes a second gate insulating layer and a second gate conductive layer located on a surface of the second gate insulating layer. 8. An anti-fuse array, comprising a plurality of anti-fuse units according to claim 6 or 7; wherein the plurality of anti-fuse units are arranged in an array along the first direction and the second direction, and each two adjacent anti-fuse units along the first direction share the second doping region; The first gate structures of the anti-fuse units arranged along the second direction are electrically connected, and the second gate structures of the anti-fuse units arranged along the second direction are electrically connected. 9 . The anti-fuse array according to claim 8 , wherein first gate conductive layers of the anti-fuse units arranged along the second direction are electrically connected, and second gate conductive layers of the anti-fuse units arranged along the second direction are electrically connected. 10. A memory, comprising the antifuse array according to claim 8 or 9.