CN1188905C - Manufacturing method of metal oxide semiconductor transistor - Google Patents

Abstract

The present invention relates to a method for manufacturing a metal oxide semiconductor transistor, and the steps are as follows: first, a source and drain ion implantation is performed on a substrate on which a gate and a partition wall of the sidewall thereof have been formed, so as to form a source and drain region in the substrate on the side of the partition wall. Then, a self-aligned metal silicide layer is formed on the surface of the gate and the source and drain regions. Subsequently, a portion of the partition wall is removed to form an acute-angle partition wall with a triangular cross-section, and then an inclined pocket ion implantation is performed on the substrate to form a pocket doping region in the substrate on the side of the gate, and the energy and angle of the inclined pocket ion implantation are controlled to control the position and dopant distribution of the pocket doping region, and then an inclined angle ion implantation is performed on the substrate to form a source and drain extension region in the substrate under the side of the gate and the acute-angle partition wall. Finally, a thermal cycle process is used to adjust the junction depth and doping profile of the source and drain extension regions.

Description

Manufacturing method of metal oxide semiconductor transistor

technical field

The present invention relates to a method for manufacturing a semiconductor element, and in particular to a method for manufacturing a Metal Oxide Semiconductor Transistor (MOS Transistor for short).

Background technique

VLSI (Very Large Scale Integration, referred to as VSLI) technology is developing towards larger chips and smaller line widths. This trend can increase the functionality and reduce the cost of using integrated circuits of the same size. For metal-oxide-semiconductor devices, the channel length is shortened when the device is smaller, so its operation speed will be accelerated.

However, when the components are miniaturized, the source and drain depletion layer (Depletion Layer) often overlaps with the channel due to channel shortening; and the shorter the channel length, it overlaps with the source and drain depletion layer The higher the ratio, the actual length of the channel will be shortened, which is called "short channel effect" (Short Channel Effect, SCE). The most common way to solve the above problems is to form lightly doped drains (Lightly Doped Drain, LDD), but when the line width is less than 0.25μm, because the depth of the lightly doped drain must continue to decrease, so its resistance is also increasing. The larger it is, the slower the speed of the component will be. In order to avoid the above shortcomings, a method of using a higher dose of source and drain extension (Source/Drain Extension) to replace the shallow doped region has recently been proposed, and the silicon chip after the source and drain extension region is implanted, in Before the subsequent process, another thermal process is required to repair the damaged lattice structure and activate the dopant. However, when the thermal process is performed, the source and drain extension regions will produce lateral diffusion (Lateral Diffusion) and junction depth (Junction Depth) become deeper, which makes the short channel effect more serious.

In addition, when the line width is less than 0.25 μm, the design of the source and drain extension regions cannot avoid the high leakage current (Leakage Current) caused by channel shrinkage. In order to avoid the above shortcomings, the predecessors proposed a method of forming a pocket-shaped doped region (PocketRegion) at both ends of the channel near the source and drain extension regions. Shallow doping ion implantation to form source and drain extension regions; and then perform an oblique pocket implantation (Pocket Implantation) on the substrate to form a pocket doped region.

Although the metal oxide semiconductor transistor formed by the above method can effectively isolate the leakage current of the channel when the line width is less than 0.25 μm, when the line width is less than 0.13 μm, the position of the pocket-shaped doped region formed by a typical method It will also get closer and closer, and it is easy to produce the so-called reverse short channel effect (Reverse Short Channel Effect, referred to as RSCE), that is, when the channel distance is small to a fixed value, the threshold voltage (Threshold Voltage, referred to as Vt) will be Sudden rise, causing component failure. In addition, because the position of the pocket-shaped doped region obtained by the known method is relatively deep, the effect of preventing the short channel effect is poor.

Contents of the invention

Therefore, the present invention proposes a method for manufacturing metal oxide semiconductor transistors to control the junction depth and doping profile of the source and drain extension regions, and to make the pocket-shaped doped region close to the substrate surface and properly tilt the pocket-shaped ion Under implantation conditions, the short channel effect is suppressed and the reverse short channel effect is reduced, thereby completing the process technology of deep submicron components.

The present invention proposes a method for manufacturing a metal oxide semiconductor transistor, the steps of which are as follows: first, a substrate is provided, on which a gate has been formed, and a partition wall has been formed on the side of the gate, and then a substrate on the side of the partition wall is formed. Source and drain regions are formed in the bottom. After the above steps, a step of forming a self-aligned silicide layer (Self-Aligned Silicide) on the exposed surfaces of the gate, source and drain regions may also be included. Then use an etching step to remove part of the partition wall to form a sharp angle (Shrp Corner) partition wall with a roughly triangular cross-section, and then perform an oblique pocket ion implantation on the substrate to form a pocket in the substrate on the side of the gate. Doped region, and by controlling the energy and angle of the tilted pocket ion implantation, to control the position and dopant distribution of the pocket-shaped doped region, so that the pocket-shaped doped region is close to the substrate surface, and then tilt the substrate Corner ion implantation to form source and drain extensions in the substrate under the gate sides and acute-angle spacers. Finally, the junction depth and doping profile of the source and drain extension regions are adjusted using a thermal cycling process.

In addition, in the method for manufacturing metal oxide semiconductor transistors proposed by the present invention, after forming the acute-angle partition wall with a roughly triangular cross-section, the sequence of the step of implanting slanted pocket ions and the step of forming the source and drain extension regions can also be The order is reversed; that is, after forming the acute-angle spacer, the substrate is subjected to oblique-angle ion implantation to form source and drain extension regions in the substrate under the gate side and the acute-angle spacer, and then, the An oblique pocket-shaped ion implantation is performed on the substrate to form a pocket-shaped doped region in the substrate at the side of the gate. The rest of the steps are unchanged.

The present invention utilizes the acute-angle partition wall to reduce the distance of ion implantation into the substrate, makes the pocket-shaped doped region close to the substrate surface, and makes the pocket-shaped doped region inside the source region and the pocket-shaped doped region inside the drain region close to each other. The spacing is increased (to avoid overlapping of two pocket-shaped doped regions), thereby suppressing the short-channel effect and reducing the reverse short-channel effect. Moreover, the depth of ion implantation is also reduced by using the acute-angled spacers, and the implantation conditions of the inclined-angle ion implantation are controlled to form shallower source and drain extension regions in the substrate below the gate side and the spacers. Therefore, the side diffusion phenomenon of the source and drain extension regions can be alleviated, and the junction depth will not become too deep due to the thermal process, so the purpose of suppressing the short channel effect can be achieved. In addition, combined with the subsequent thermal cycle process, the junction depth and doping profile of the source and drain extension regions can be precisely adjusted to suppress the short channel effect.

Description of drawings

1A to 1E are cross-sectional views of a manufacturing process of a metal oxide semiconductor transistor according to an embodiment of the present invention.

Explanation of reference signs:

100: Substrate 102: Gate

104, 104a: Partition wall 106: Source and drain injection

108: source and drain regions 110: metal silicide layer

112: Inclined pocket ion implantation 114: Pocket doped region

116: Oblique angle ion implantation 118: Source and drain extensions

Detailed ways

1A to 1E are cross-sectional views of a manufacturing process of a metal oxide semiconductor transistor according to an embodiment of the present invention.

Please refer to Fig. 1A, at first a substrate 100 is provided, a gate 102 has been formed on the substrate 100, and a spacer 104 has been formed on the side wall of the gate 102, the material of the spacer 104 is silicon nitride, for example, The forming method is, for example, first forming a silicon nitride layer on the substrate 100 , and then performing an anisotropic etching on the silicon nitride layer to form the partition walls 104 . Then a source/drain (S/D) implantation 106 is performed on the substrate 100 to form a source and drain region 108 in the substrate 100 on the side of the partition wall 104 .

Next, referring to FIG. 1B , a self-aligned metal silicide layer (Self-Aligned Silicide) 110 is formed on the exposed surfaces of the gate 102 and the source and drain regions 108, for example, by first forming a layer on the substrate 100. Layer a metal layer and cover the gate 102, the material of the metal layer is titanium, and then perform a heat treatment step to make the metal layer and the gate 102 of silicon material react with the source and drain regions 108 to form a metal silicide, and then remove the remaining react the metal layer to form the salicide layer 110 .

Then, referring to FIG. 1C , a part of the partition wall 104 is removed by using a special anisotropic etching method, so that the cross section of the partition wall 104a is roughly triangular and the top is a sharp corner (Sharp Corner).

Subsequently, referring to FIG. 1D, an inclined pocket ion implantation (PocketImplantation) 112 is performed on the substrate 100 to form a pocket-shaped doped region 114 in the substrate 100 on the side of the gate 102, and the inclined pocket is controlled. The energy and angle of the ion implantation step 112 are used to control the position and dopant distribution of the pocket-shaped doped region 114 so that the pocket-shaped doped region 114 is close to the surface of the substrate 100 . Wherein, the dopant of the pocket-shaped doped region 114 is gallium or indium, for example.

Finally, referring to FIG. 1E , an oblique angle ion implantation 116 is performed on the substrate 100 to form source and drain extension regions 118 in the substrate 100 on the side of the gate 102 and under the spacer 104a, wherein the source and drain The dopant of the drain extension 118 is, for example, phosphorous or arsenic. A thermal cycle process (Thermal Cycle) is then performed to adjust the junction depth and doping profile of the source and drain extension regions 118 .

In addition, the cross-sectional view of the manufacturing process shown in FIG. 1D and FIG. 1E of the above-mentioned embodiment of the present invention can be reversed so that an oblique angle ion implantation 116 is performed on the substrate 100 in FIG. The source and drain extension regions 118 are formed in the substrate 100 under the partition wall 104a, and then an oblique pocket ion implantation 112 is performed on the substrate 100 as shown in FIG. shape doped region 114 .

In summary, the present invention is characterized in that:

1. The present invention utilizes roughly triangular partition walls to reduce the distance for ion implantation to go deep into the substrate, so that the pocket-shaped doped region is close to the surface, and the pocket-shaped doped region inside the source region is connected to the pocket-shaped doped region inside the drain region. The distance between the impurity regions is increased (to avoid overlapping of two pocket doped regions), thereby suppressing the short channel effect and reducing the reverse short channel effect.

2. Referring to FIG. 1D, since the oblique pocket-shaped ion implantation 112 of the present invention enters the substrate 100 through the flat triangular partition wall 104a, the position and doping of the pocket-shaped doped region can be controlled more precisely than the known method. quality distribution. Therefore, the proximity of the pocket doped regions to the source and drain extension regions can be controlled.

3. The present invention utilizes the acute-angle spacer to reduce the depth of ion implantation, and controls the implantation conditions of the inclined-angle ion implantation to form shallower source and drain extensions in the substrate under the gate side and the spacer district. Therefore, the lateral diffusion (Lateral Diffusion) phenomenon of the source and drain extension regions can be alleviated, and the junction depth (Junction Depth) will not become too deep due to the thermal process, so the purpose of suppressing the short channel effect can be achieved.

4. The present invention can cooperate with the subsequent thermal cycle process to more precisely adjust the junction depth and doping profile of the source and drain extension regions.

Although the present invention has been described above with the embodiments, it is not intended to limit the present invention. Anyone familiar with this technology can make some changes and modifications without departing from the spirit and scope of the present invention. Therefore, the present invention The scope of protection is based on the claims.

Claims (17)

1. A method for manufacturing a metal oxide semiconductor transistor, characterized in that it comprises: providing a substrate, on which a gate has been formed, and a partition wall has been formed on the side wall of the gate; forming a source and drain region in the substrate at the sides of the spacer; forming a plurality of salicide layers on the exposed surfaces of the gate and the source and drain regions; using an etching step to remove part of the partition to make it an acute-angle partition; performing an oblique pocket-shaped ion implantation on the substrate to form a pocket-shaped doped region in the substrate on the side of the gate, and controlling the energy and angle of the local ion implantation to make the pocket-shaped doped region a region proximate to the substrate surface; and An oblique angle ion implantation is performed on the substrate to form a source and drain extension region in the substrate below the gate side and the acute angle spacer. 2 . The method for manufacturing a metal oxide semiconductor transistor as claimed in claim 1 , wherein a cross section of the acute-angle partition wall is triangular. 3 . 3 . The method for fabricating a metal oxide semiconductor transistor as claimed in claim 1 , wherein the formation order of the pocket-shaped doped region and the source and drain extension regions is reversed. 4 . 4. The method for manufacturing metal oxide semiconductor transistors as claimed in claim 1, further comprising performing a thermal cycle process to adjust the source and drain after forming the source and drain extension regions Junction depth and doping profile of the extension region. 5. The method for manufacturing a metal oxide semiconductor transistor according to claim 1, wherein the step of forming the salicide layer comprises: forming a metal layer on the substrate and covering the gate; performing a heat treatment step to react the metal layer with the gate and the source and drain regions to form the salicide layer; and The unreacted metal layer is removed. 6. The method for manufacturing a metal oxide semiconductor transistor as claimed in claim 5, wherein the material of the metal layer comprises titanium. 7. The method of manufacturing a metal oxide semiconductor transistor as claimed in claim 1, wherein the dopant of the source and drain extension regions is one of phosphorus and arsenic. 8 . The method for manufacturing a metal oxide semiconductor transistor as claimed in claim 1 , wherein the dopant in the pocket-shaped doped region is one of gallium and indium. 9. A method for manufacturing a metal oxide semiconductor transistor, characterized by: comprising: providing a substrate, on which a gate has been formed, and a partition wall has been formed on the side wall of the gate; forming a source and drain region in the substrate at the sides of the spacer; using an etching step to remove part of the partition to make it an acute-angle partition; performing an oblique pocket-shaped ion implantation on the substrate to form a pocket-shaped doped region in the substrate on the side of the gate, and controlling the energy and angle of the local ion implantation to make the pocket-shaped doped region a region proximate to the substrate surface; and An oblique angle ion implantation is performed on the substrate to form a source and drain extension region in the substrate below the gate side and the acute angle spacer. 10 . The method for manufacturing a metal oxide semiconductor transistor as claimed in claim 9 , wherein the cross section of the acute-angle partition wall is triangular. 11 . 11 . The method for fabricating a metal oxide semiconductor transistor as claimed in claim 9 , wherein the formation order of the pocket-shaped doped region and the source and drain extension regions is reversed. 12 . 12. The method for manufacturing metal oxide semiconductor transistors according to claim 9, characterized in that: after the step of forming the partition walls, further comprising forming a plurality of self-pairs on the gate and the source and drain regions metalloid silicide layer. 13. The method for manufacturing a metal oxide semiconductor transistor according to claim 12, wherein the step of forming the salicide layer comprises: forming a metal layer on the substrate and covering the gate; performing a heat treatment step to react the metal layer with the gate and the source and drain regions to form the salicide layer; and The unreacted metal layer is removed. 14. The method of manufacturing a metal oxide semiconductor transistor as claimed in claim 13, wherein the material of the metal layer comprises titanium. 15. The method of manufacturing a metal oxide semiconductor transistor as claimed in claim 9, further comprising performing a thermal cycle process to adjust the source and drain after forming the source and drain extension regions Junction depth and doping profile of the extension region. 16. The method of manufacturing a metal-oxide-semiconductor transistor as claimed in claim 9, wherein the dopant of the source and drain extension regions is one of phosphorus and arsenic. 17 . The method for manufacturing a metal oxide semiconductor transistor as claimed in claim 9 , wherein the dopant in the pocket-shaped doped region is one of gallium and indium.

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