CN118888564B - Preparation method of indium column array with regular shape - Google Patents
Preparation method of indium column array with regular shape Download PDFInfo
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- CN118888564B CN118888564B CN202411365742.4A CN202411365742A CN118888564B CN 118888564 B CN118888564 B CN 118888564B CN 202411365742 A CN202411365742 A CN 202411365742A CN 118888564 B CN118888564 B CN 118888564B
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- 229910052738 indium Inorganic materials 0.000 title claims abstract description 77
- APFVFJFRJDLVQX-UHFFFAOYSA-N indium atom Chemical compound [In] APFVFJFRJDLVQX-UHFFFAOYSA-N 0.000 title claims abstract description 77
- 238000002360 preparation method Methods 0.000 title claims abstract description 8
- 238000000034 method Methods 0.000 claims abstract description 56
- 229910052751 metal Inorganic materials 0.000 claims abstract description 52
- 239000002184 metal Substances 0.000 claims abstract description 52
- 239000000758 substrate Substances 0.000 claims abstract description 50
- 230000008569 process Effects 0.000 claims abstract description 37
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 36
- 230000004048 modification Effects 0.000 claims abstract description 12
- 238000012986 modification Methods 0.000 claims abstract description 12
- 238000000576 coating method Methods 0.000 claims abstract description 8
- 238000004140 cleaning Methods 0.000 claims abstract description 6
- 238000000206 photolithography Methods 0.000 claims abstract 6
- 238000001259 photo etching Methods 0.000 claims description 52
- 238000001704 evaporation Methods 0.000 claims description 17
- 230000008020 evaporation Effects 0.000 claims description 13
- XKRFYHLGVUSROY-UHFFFAOYSA-N Argon Chemical compound [Ar] XKRFYHLGVUSROY-UHFFFAOYSA-N 0.000 claims description 10
- 229910052737 gold Inorganic materials 0.000 claims description 8
- 238000001883 metal evaporation Methods 0.000 claims description 8
- 238000001020 plasma etching Methods 0.000 claims description 7
- 238000004381 surface treatment Methods 0.000 claims description 6
- 229910052786 argon Inorganic materials 0.000 claims description 5
- 229910052782 aluminium Inorganic materials 0.000 claims description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 claims description 3
- 238000003851 corona treatment Methods 0.000 claims description 3
- 238000010884 ion-beam technique Methods 0.000 claims description 3
- 238000001755 magnetron sputter deposition Methods 0.000 claims description 3
- 238000005566 electron beam evaporation Methods 0.000 claims description 2
- 238000007747 plating Methods 0.000 claims 2
- 238000007740 vapor deposition Methods 0.000 description 9
- 238000010586 diagram Methods 0.000 description 6
- 238000001459 lithography Methods 0.000 description 4
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 4
- 239000000853 adhesive Substances 0.000 description 3
- 230000001070 adhesive effect Effects 0.000 description 3
- 238000003466 welding Methods 0.000 description 3
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 description 2
- 239000008367 deionised water Substances 0.000 description 2
- 229910021641 deionized water Inorganic materials 0.000 description 2
- 238000010438 heat treatment Methods 0.000 description 2
- 238000000265 homogenisation Methods 0.000 description 2
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Chemical compound O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 2
- 238000003491 array Methods 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 230000001808 coupling effect Effects 0.000 description 1
- 230000007547 defect Effects 0.000 description 1
- 238000001514 detection method Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000010894 electron beam technology Methods 0.000 description 1
- 230000008018 melting Effects 0.000 description 1
- 238000002844 melting Methods 0.000 description 1
- 239000002923 metal particle Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000005272 metallurgy Methods 0.000 description 1
- 229910052757 nitrogen Inorganic materials 0.000 description 1
- 238000000059 patterning Methods 0.000 description 1
- 239000011148 porous material Substances 0.000 description 1
- 238000012797 qualification Methods 0.000 description 1
- 238000002390 rotary evaporation Methods 0.000 description 1
- 238000002791 soaking Methods 0.000 description 1
- 239000002904 solvent Substances 0.000 description 1
- 238000006467 substitution reaction Methods 0.000 description 1
- 230000007704 transition Effects 0.000 description 1
- 238000005019 vapor deposition process Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/10—Bump connectors ; Manufacturing methods related thereto
- H01L24/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/114—Manufacturing methods by blanket deposition of the material of the bump connector
- H01L2224/11444—Manufacturing methods by blanket deposition of the material of the bump connector in gaseous form
- H01L2224/1145—Physical vapour deposition [PVD], e.g. evaporation, or sputtering
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/11—Manufacturing methods
- H01L2224/1147—Manufacturing methods using a lift-off mask
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02P—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN THE PRODUCTION OR PROCESSING OF GOODS
- Y02P70/00—Climate change mitigation technologies in the production process for final industrial or consumer products
- Y02P70/50—Manufacturing or production processes characterised by the final manufactured product
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- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Photometry And Measurement Of Optical Pulse Characteristics (AREA)
Abstract
本发明提供了一种形状规整的铟柱阵列制备方法，属于红外探测器技术领域；解决了现有铟柱生长和回流工艺存在的生长高度不达标、形状不均匀的问题，包括以下步骤：在基片表面匀胶、光刻后形成光刻孔阵列；对完成光刻工艺后的基片进行表面改性处理；在经过表面改性处理的基片的表面采用镀膜工艺形成一层均匀的金属层；在完成金属生长的基片的表面采用镀膜工艺形成一层均匀的铟层；采用剥离、清洗工艺处理生长铟层后的基片，将光刻孔阵列侧壁的金属层和光刻胶以及光刻胶顶部的金属层、铟层剥离，从而得到生长高度大、形状规整的铟柱阵列；本发明应用于铟柱阵列制备。
The invention provides a method for preparing an indium column array with a regular shape, belonging to the technical field of infrared detectors; the method solves the problems of substandard growth height and uneven shape existing in the existing indium column growth and reflow processes, and comprises the following steps: forming a photolithography hole array after photolithography on the surface of a substrate; performing surface modification treatment on the substrate after the photolithography process; forming a uniform metal layer on the surface of the substrate after the surface modification treatment by adopting a coating process; forming a uniform indium layer on the surface of the substrate after metal growth by adopting a coating process; treating the substrate after the indium layer is grown by adopting a stripping and cleaning process, stripping the metal layer and photoresist on the side wall of the photolithography hole array and the metal layer and indium layer on the top of the photoresist, thereby obtaining an indium column array with a large growth height and a regular shape; the invention is applied to the preparation of an indium column array.
Description
Technical Field
The invention provides a preparation method of an indium column array with a regular shape, and belongs to the technical field of infrared focal plane detectors.
Background
The infrared focal plane detector is forward to the development of large-scale area array and small-size pixels at the front, wherein the indium columns play a role in connecting an infrared focal plane array chip and a readout circuit to enable the infrared focal plane array chip and the readout circuit to be well conducted, blind pixels are easy to cause after the indium columns with low height and uneven morphology are subjected to flip-chip interconnection, short circuit defects are increased, and therefore the indium columns with consistent height and regular shape are required to be grown so as to ensure the connection quality of the indium columns after flip-chip interconnection.
The existing indium column growth process is to prepare an indium column array by carrying out evaporation after negative photoresist patterning, and the reason for adopting negative photoresist evaporation is that if a photoetching open pore is in a positive trapezoid shape, the upper mask layer is easier to strip. In the growth process, as the side wall of the photoetching hole has high-density micropores and rough interface characteristics, a thicker indium layer gradually grows transversely on the side wall of the photoetching hole along with the evaporation process, the photoetching hole is gradually blocked along with the increase of time, and the diameter of the top layer of the indium column is smaller and smaller, so that the top layer spike cone characteristics of low growth height and poor uniformity after the indium column is stripped are caused. Meanwhile, the development directions of large-scale area arrays and small-size pixels lead the growth conditions of indium columns to be more and more harsh, and the indium columns with unqualified growth heights and uneven shapes increase the difficulty of the interconnection process, so that the interconnection qualification rate is reduced, and the good hybrid interconnection coupling effect between chips and circuits is difficult to ensure.
Although the existing indium column reflow process can improve the uniformity of indium column growth by melting, soaking and surface tension treatment of the indium column, for the detector process below the pixel spacing of 10 μm, the whole indium quantity is low due to the influence of the transverse growth characteristic of the indium column, and the growth height is reduced after the indium column reflow process, so that the development of the indium column growth process with large growth height and regular shape is necessary.
Disclosure of Invention
The invention provides a preparation method of an indium column array with a regular shape, which aims to solve the problems of the existing indium column growth and reflow process that the growth height is not up to standard and the shape is not uniform.
In order to solve the technical problems, the technical scheme adopted by the invention is that the preparation method of the indium column array with the regular shape comprises the following steps:
S1, uniformly photoresist on the surface of a substrate and photoetching to form a photoetching hole array;
S2, carrying out surface modification treatment on the substrate after the photoetching process is completed;
S3, forming a uniform metal layer on the surface of the substrate subjected to surface modification treatment by adopting a coating process;
s4, forming a uniform indium layer on the surface of the substrate with the metal growth completed by adopting a coating process;
And S5, treating the substrate after the indium layer is grown by adopting a stripping and cleaning process, and removing the metal layer and the photoresist on the side wall of the photoetching hole array and the metal layer and the indium layer on the top of the photoresist, thereby obtaining the indium column array with large growth height and regular shape.
In the step S1, a photoresist homogenizing machine and a photoetching machine are adopted to form a photoetching hole array on a substrate through a photoetching process.
Each photoetching hole in the photoetching hole array is in an isosceles trapezoid shape after being molded, and the inner angles of the long bottom edges of the isosceles trapezoids are 70-85 degrees.
In the step S1, NR9-6000PY negative photoresist is selected to form a photoetching hole array.
In the step S2, the substrate is subjected to argon plasma surface treatment by adopting a plasma photoresist remover or is subjected to modification treatment by adopting flame treatment, RIE plasma etching treatment and corona discharge treatment.
The metal layer coating process of the step S3 and the indium layer coating process of the step S4 are completed by adopting ion beam evaporation, electron beam evaporation or magnetron sputtering evaporation processes.
In the step S3, the substrate is rotated 180 degrees in the vertical direction at a constant speed during metal evaporation, so that a metal layer with a specified thickness is evaporated on the bottom and the side wall of the photoetching hole.
The metal layer formed by vapor deposition in the step S3 adopts Ti/Pt/Au, cr/Au, ti/Au or Ti/Ni/Au combined metal.
The thickness of the indium layer formed in the step S4 is 6-8 μm.
The indium layer in step S4 can be replaced with an aluminum layer.
Compared with the prior art, the invention has the following beneficial effects:
1. The invention can increase the adhesive force between the metal layer and the side wall of the photoetching hole by carrying out argon plasma modification treatment on the surface of the photoetching hole array, can increase the metal evaporation incidence angle of the side wall of the photoetching hole by carrying out uniform rotation on the substrate of metal evaporation in the vertical direction, and can generate a relatively uniform and compact smooth metal layer on the side wall of the photoetching hole with high-density micropores and rough interfaces;
2. The invention can simultaneously complete the growth of the metal layer and the indium layer through one-time photoetching and two-time evaporation (metal and indium) processes, the metal layer at the bottom of the indium column is used as the UBM layer, wherein the UBM layer ( Under Bump Metallurgy) is a metallization transition layer between the chip bonding pad and the bump, better welding contact and conductivity can be provided for the chip and the indium column, no overlay deviation between the indium column array and the UBM layer caused by secondary photoetching is generated, and the metal layer on the side wall can be removed through stripping, so that the subsequent process is not negatively influenced.
Drawings
The invention is further described below with reference to the accompanying drawings:
FIG. 1 is a schematic diagram of a lithographic aperture array structure after the lithography of step S1 of the method of the present invention;
FIG. 2 is a schematic diagram of the method of the present invention in which the surface of the array of lithography holes is plasma treated in step S2;
FIG. 3 is a schematic diagram showing the metal vapor deposition process in step S3 of the method of the present invention;
FIG. 4 is a schematic diagram of metal vapor deposition on the right sidewall of the photolithographic hole in step S3 of the method of the present invention;
FIG. 5 is a schematic view of metal vapor deposition on the left sidewall of the lithographic aperture in step S3 of the method of the present invention;
FIG. 6 is a schematic diagram showing the structure of the substrate after the metal vapor deposition is completed in step S3 of the method of the present invention;
FIG. 7 is a schematic diagram showing the structure of a substrate subjected to indium vapor deposition after step S4 of the method of the present invention;
FIG. 8 is a schematic view of an indium column array structure after stripping and cleaning steps in step S5 of the method of the present invention;
In the figure, 1 is a substrate, 2 is a photoetching hole array, 3 is photoresist, 4 is a metal evaporation source, 5 is a metal layer, 6 is an indium layer and 7 is an indium column array.
Detailed Description
As shown in fig. 1 to 8, the present invention provides a method for preparing an indium column array with regular shape, which comprises the steps of uniformly growing a compact smooth metal layer 5 on the side wall of a photoetching hole by modifying photoresist on a substrate 1 and rotationally evaporating metal, evaporating an indium layer 6, stripping the photoresist 3 from the metal layer by stripping the metal layer, wherein the smooth metal layer 5 on the side wall of the photoetching hole can inhibit the lateral growth of indium columns, so as to obtain an indium column array 7 with uniform growth height and regular morphology. The specific implementation steps are as follows:
s1, uniformly photoresist on the surface of a substrate 1 and photoetching to form a photoetching hole array 2;
s2, carrying out surface treatment on the substrate 1 after the photoetching process is completed;
S3, uniformly evaporating a metal layer 5 on the surface of the substrate 1 subjected to surface treatment;
s4, uniformly evaporating an indium layer 6 on the surface of the substrate 1 on which metal growth is completed;
S5, the substrate 1 after the indium layer 6 is grown is treated by adopting a stripping and cleaning process, and the metal layer 5 and the photoresist 3 on the side wall of the photoetching hole array 2 and the metal layer 5 and the indium layer 6 on the top of the photoresist 3 are removed, so that the indium column array 7 with large growth height and regular shape is obtained.
Wherein the substrate 1 is a chip of an infrared focal plane array of a metal layer 5 (UBM layer), an indium column array 7 to be prepared.
In the specific step S1, a photoresist homogenizer and photoetching are adopted to form a photoetching hole array 2 on a substrate 1 through a photoetching process, and the implementation steps are as follows:
selecting NR9-6000PY negative photoresist to form a photoetching hole array 2, uniformly dripping the NR9-6000PY negative photoresist at the center of a substrate 1, then running at a rotating speed of 300-800 rpm for 3-5 s, then running at a rotating speed of 1000-1500rpm for 30s to perform photoresist homogenization, placing the substrate 1 after photoresist homogenization on a heating plate, baking at a temperature of 120 ℃ for 300s to evaporate the solvent of the photoresist, performing local exposure on the photoresist at an exposure dose of 400-800 mj by using a contact mode (Hard) of an ultraviolet photoetching machine to define a graph (the graph is in an isosceles trapezoid shape), and placing the substrate 1 after the local exposure on the heating plate for baking at a temperature of 100-120 ℃ for 90-180 s to solidify the primer. And then placing the exposed substrate 1 into a tetramethyl ammonium hydroxide (2.38% TMAH) solution diluted by deionized water, developing for 40-80 s, taking out, placing into deionized water, fixing for 30-60 s, taking out the substrate 1, and drying by nitrogen, wherein an array of isostearic holes 2 is formed on the substrate 1. Each lithography hole in the lithography hole array 2 is in an isosceles trapezoid shape, and the inner angle of the long bottom edge of the isosceles trapezoid is 70-85 degrees.
In the specific step S2, a plasma photoresist remover can be adopted to carry out argon plasma surface treatment on the substrate 1, the implementation steps are that the substrate 1 after the photoetching process is put into the plasma photoresist remover, and the surface of the substrate 1 is treated by argon plasma with the flow of 300sccm and the power of 70W for 30-45S, as shown in FIG. 2, the purpose is to carry out surface modification on the side wall of the photoetching hole, and the adhesive force of the metal layer 5 in the step S3 when the side wall of the photoetching hole grows is increased.
The surface treatment of the substrate 1 in step S2 may be performed by flame treatment, RIE ( Reactive Ion Etching) plasma etching treatment, corona discharge treatment, or the like.
The substrate 1 after the photoetching process is fixed on a carrying table of an evaporation machine, the substrate 1 is uniformly rotated in the vertical direction, a metal layer 5 with a specified thickness is evaporated on the bottom and the side wall of a photoetching hole, namely Ti/Pt/Au is sequentially evaporated through a metal evaporation source 4, the thicknesses of the three are respectively 50/50/300nm, the substrate 1 is controlled to rotate in the vertical direction at a uniform speed in the evaporation process, a rotating arrow shown in fig. 3 is the rotating direction, the rotating evaporation process is shown in fig. 4-5, and the aim is to increase the evaporation incidence angle of metal particles emitted by the metal evaporation source 4 on the side wall of the photoetching hole, so that the adhesive force and compactness of the metal layer 5 grown on the side wall of the photoetching hole in different directions are further ensured.
Specifically, in the step S4, the substrate 1 after metal evaporation is fixed on a stage of an evaporator to evaporate an indium layer 6 with a thickness of 6-8 μm, and the purpose of the substrate is to grow an indium column array 7 in the photoetching hole array 2.
In a specific step S5, the substrate 1 after the growth of the indium layer 6 is subjected to a stripping and cleaning process, so as to strip and remove the metal layer 5 and the photoresist 3 on the sidewall of the photo-etching hole array 2 and the metal layer 5 and the indium layer 6 on the top of the photoresist 3, thereby obtaining an indium column array 7 with large growth height (the height is 6-8 μm), good morphology and regular shape, as shown in fig. 8.
The metal vapor deposition and indium vapor deposition methods in the steps S3 and S4 can adopt ion beam vapor deposition, electron beam vapor deposition or magnetron sputtering and other processes, and the vapor deposited metal can also be Cr/Au, ti/Au or Ti/Ni/Au combined metal.
The preparation method is also suitable for preparing the welding spots of aluminum by adopting a welding spot process.
In summary, the indium pillar array prepared by the method of the present invention has the following advantages:
1. Through modification of the side wall of the photoetching hole and a rotary evaporation metal process, a compact smooth metal layer 5 can be uniformly grown on the side wall of the photoetching hole, so that the appearance of the indium column array 7 can be greatly improved without a reflow process, and the subsequent interconnection performance is enhanced;
2. the pressure to be overcome by stripping is changed from the adhesion between the indium layer 6 and the photoresist 3 to the adhesion between the metal layer 5 and the photoresist 3, so that the efficiency of the stripping process can be increased, the thickness of the photoresist grown by the conventional indium column can be reduced from more than twice the height of the target indium column to 1.2-1.5 times the height of the target indium column, and the effect of saving the photoresist consumption is achieved;
3. the growth of the two structures of the UBM layer and the indium layer 6 can be simultaneously carried out by only one photoetching;
4. The invention can be compatible with the chip end process and the circuit end process of the infrared detection device with the pixel spacing of 7.5-50 mu m.
It should be noted that the above embodiments are merely for illustrating the technical solution of the present invention and not for limiting the same, and although the present invention has been described in detail with reference to the above embodiments, it should be understood by those skilled in the art that the technical solution described in the above embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or substitutions do not make the essence of the corresponding technical solution deviate from the scope of the technical solution of the embodiments of the present invention.
Claims (7)
1. The preparation method of the indium column array with the regular shape is characterized by comprising the following steps:
S1, uniformly photoresist on the surface of a substrate, and photoetching to form a photoetching hole array, wherein each photoetching hole in the photoetching hole array is isosceles trapezoid after being molded, and the inner angle of the long bottom edge of each isosceles trapezoid is 70-85 degrees;
S2, carrying out surface modification treatment on the substrate after the photoetching process is completed;
s3, forming a uniform metal layer on the surface of the substrate subjected to surface modification treatment by adopting a coating process, wherein in the step S3, the substrate is simultaneously rotated at a constant speed for 180 degrees in the vertical direction during metal evaporation, so that a metal layer with a specified thickness is evaporated on the bottom and the side wall of a photoetching hole;
the metal layer formed by evaporation in the step S3 adopts Ti/Pt/Au, cr/Au, ti/Au or Ti/Ni/Au combined metal;
s4, forming a uniform indium layer on the surface of the substrate with the metal growth completed by adopting a coating process;
And S5, treating the substrate after the indium layer is grown by adopting a stripping and cleaning process, and removing the metal layer and the photoresist on the side wall of the photoetching hole array and the metal layer and the indium layer on the top of the photoresist, thereby obtaining the indium column array with large growth height and regular shape.
2. The method of claim 1, wherein the step S1 is performed by using a spin coater and a photolithography machine to form a patterned array of holes on the substrate by photolithography.
3. The method of claim 2, wherein NR9-6000PY negative photoresist is selected to form the array of photolithographic holes in step S1.
4. The method of claim 1, wherein the step S2 is to perform argon plasma surface treatment on the substrate by using a plasma photoresist remover or to perform modification treatment on the surface of the substrate by using flame treatment, RIE plasma etching treatment and corona discharge treatment.
5. The method of claim 1, wherein the metal layer plating process of step S3 and the indium layer plating process of step S4 are performed by ion beam evaporation, electron beam evaporation or magnetron sputtering evaporation.
6. The method of claim 1, wherein the thickness of the indium layer formed in the step S4 is 6-8 μm.
7. The method of claim 1 to 6, wherein the indium layer in the step S4 can be replaced by an aluminum layer.
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| CN120727592B (en) * | 2025-08-29 | 2025-11-14 | 浙江焜腾红外技术股份有限公司 | A method for preparing high-indium pillars with small aperture |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101118886A (en) * | 2007-08-22 | 2008-02-06 | 中国科学院上海技术物理研究所 | Composite indium column for infrared focal plane device and preparation method thereof |
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| US6388322B1 (en) * | 2001-01-17 | 2002-05-14 | Aralight, Inc. | Article comprising a mechanically compliant bump |
| US8567658B2 (en) * | 2009-07-20 | 2013-10-29 | Ontos Equipment Systems, Inc. | Method of plasma preparation of metallic contacts to enhance mechanical and electrical integrity of subsequent interconnect bonds |
| CN102543846B (en) * | 2011-08-15 | 2014-04-02 | 上海华力微电子有限公司 | Surface treatment method for strengthening aluminum process metal layer and light resistance adhesive force |
| CN106024982A (en) * | 2016-07-11 | 2016-10-12 | 中国科学院上海技术物理研究所 | Preparation method for indium column of infrared focal plane chip |
| CN112490137A (en) * | 2020-11-30 | 2021-03-12 | 安徽光智科技有限公司 | Preparation method of focal plane flip interconnection indium column |
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| CN101118886A (en) * | 2007-08-22 | 2008-02-06 | 中国科学院上海技术物理研究所 | Composite indium column for infrared focal plane device and preparation method thereof |
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