CN118885218A - Instruction processing method and device for out-of-order multi-issue processor - Google Patents

Abstract

In an embodiment of the present application, an instruction processing method and device for an out-of-order multi-issue processor are provided, the method comprising: acquiring and caching a target instruction and its corresponding operands emitted by a preset instruction emission queue; storing multiple target instructions and their corresponding operands in a preset first-in-first-out queue; for each target instruction and its corresponding operand in the first-in-first-out queue, when a corresponding first synchronization signal is sent to a delivery module of the out-of-order multi-issue processor and a second synchronization signal sent by the delivery module is received at the same time, executing the target instruction and sending the execution result to a write-back module of the out-of-order multi-issue processor, and when instructions in the entire pipeline may be cleared due to an exception, an interruption or a branch prediction error, it is possible to determine which instructions in the out-of-order multi-issue processor can be executed and which instructions cannot be executed.

Description

Instruction processing method and device for out-of-order multi-issue processor

Technical Field

The present application relates to the technical field of out-of-order processors, and in particular, to an instruction processing method and apparatus for an out-of-order multi-issue processor, a computer device, and a storage medium.

Background Art

Currently, the functions of the pipeline of an out-of-order multi-issue processor include but are not limited to instruction fetching and branch prediction, instruction decoding, analyzing data dependencies between instructions and eliminating false data hazards, issuing instructions to functional units, executing instructions in parallel, and updating machine status in the original order of instructions. During the execution of instructions, if an instruction has any of branch prediction errors, interruptions and exceptions, the instructions in the entire pipeline will be cleared, which may lead to the problem of being unable to determine which instructions in the out-of-order multi-issue processor can be executed and which cannot be executed.

Summary of the invention

Embodiments of the present application provide an instruction processing method and apparatus for an out-of-order multi-issue processor, a computer device, and a storage medium.

A first aspect of an embodiment of the present application provides an instruction processing method for an out-of-order multi-issue processor, comprising:

Obtain and cache the CSR instructions and their corresponding operands issued by the preset instruction issuance queue;

storing a plurality of CSR instructions and their corresponding operands into a preset first-in-first-out queue;

For each CSR instruction and its corresponding operand in the first-in-first-out queue, when the corresponding first synchronization signal is sent to the delivery module of the out-of-order multi-issue processor and the second synchronization signal sent by the delivery module is received at the same time, the CSR instruction is executed and the execution result is sent to the write back module of the out-of-order multi-issue processor. The delivery module sends the CSR instruction delivery result to the write back module of the out-of-order multi-issue processor.

In an optional embodiment of the present application, the obtaining and caching of the CSR instructions and their corresponding operands issued by the preset instruction issue queue includes:

Get the CSR instruction sent by the preset instruction sending queue;

Determine the operand corresponding to the CSR instruction;

The CSR instructions and their corresponding operands issued by the preset instruction issue queue are cached.

In an optional embodiment of the present application, determining the operand corresponding to the CSR instruction according to the CSR instruction includes:

Obtaining an address of a specified operand register in a CSR instruction, wherein the specified operand register stores an operand corresponding to the CSR instruction;

According to the address of the designated operand register, the operand corresponding to the CSR instruction is read from the designated register.

In an optional embodiment of the present application, storing the plurality of CSR instructions and their corresponding operands into a preset first-in-first-out queue includes:

According to the order of reading operands, different CSR instructions and their corresponding operands are stored in a preset first-in-first-out queue.

In an optional embodiment of the present application, the first synchronization signal is used to control the read and write operations of the CSR instruction, and the second synchronization signal is used to deliver the instruction.

In an optional embodiment of the present application, executing the CSR instruction and sending the execution result to the write-back module of the out-of-order multi-issue processor includes:

Update the value of the CSR instruction, generate a corresponding clear signal, and store the updated value of the CSR instruction and the clear signal in a preset register, wherein the clear signal is a signal for flushing the pipeline;

The update value of the CSR instruction, the clear signal, and the storage record of the preset register are sent to the write-back module.

In an optional embodiment of the present application, before executing the CSR instruction, the method further includes:

When the CSR instruction is a read-write operation instruction and the destination register is the general integer register x0, the CSR is only written but not read;

When the CSR instruction is a read and set operation instruction or a read and clear operation instruction, and the operand register is the general integer register x0, the CSR is only read but not written;

When the CSR instruction is an immediate value extension instruction of a read and set operation or an immediate value extension instruction of a read and clear operation, and the immediate value is 0, the CSR is only read but not written.

According to a second aspect of an embodiment of the present application, there is provided an instruction processing device for an out-of-order multi-issue processor, comprising:

A first buffer area is used to obtain and cache target instructions and corresponding operands issued by a preset instruction issue queue;

A second cache area, for storing a plurality of target instructions and their corresponding operands into a preset first-in-first-out queue;

A transceiver module, for each target instruction and its corresponding operand in the first-in-first-out queue, when sending a corresponding first synchronization signal to a delivery module of the out-of-order multi-issue processor and receiving a second synchronization signal sent by the delivery module, executes the target instruction and sends the execution result to a write-back module of the out-of-order multi-issue processor;

The delivery module is used to send the target instruction delivery result to the write-back module of the out-of-order multi-issue processor.

According to a third aspect of an embodiment of the present application, a computer device is provided, comprising: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of any of the above methods when executing the computer program.

A fourth aspect of the embodiments of the present application provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program implements the steps of any of the above methods when executed by a processor.

BRIEF DESCRIPTION OF THE DRAWINGS

The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

FIG1 is a flow chart of an instruction processing method for an out-of-order multi-issue processor provided by an embodiment of the present application;

FIG2 is a flow chart of a CSR instruction in an out-of-order multi-issue processor provided by an embodiment of the present application;

FIG3 is a flow chart of an instruction processing method for an out-of-order multi-issue processor provided by another embodiment of the present application;

FIG4 is a flow chart of VPU instructions in an out-of-order multi-issue processor provided by an embodiment of the present application;

FIG5 is a schematic diagram of the structure of an instruction processing device for an out-of-order multi-issue processor provided by an embodiment of the present application;

FIG. 6 is a schematic diagram of the structure of a computer device provided in one embodiment of the present application.

DETAILED DESCRIPTION

In the process of implementing the present application, the inventors discovered that, currently during the execution of instructions, if an instruction encounters any of a branch prediction error, interruption, and exception, the instructions in the entire pipeline will be cleared, which may lead to the problem of being unable to determine which instructions have been executed and which have not been executed in an out-of-order multi-issue processor.

In response to the above problems, an embodiment of the present application provides an instruction processing method for an out-of-order multi-issue processor, which obtains and caches CSR (Control and Status Register) instructions and their corresponding operands emitted by a preset instruction emission queue; stores multiple CSR instructions and their corresponding operands in a preset first-in-first-out queue; for each CSR instruction and its corresponding operand in the first-in-first-out queue, when a corresponding first synchronization signal is sent to a delivery module of the out-of-order multi-issue processor and a second synchronization signal sent by the delivery module is received, the CSR instruction is executed, and the execution result is sent to the write-back module of the out-of-order multi-issue processor, and the delivery module sends the CSR instruction delivery result to the write-back module of the out-of-order multi-issue processor. When the instructions in the entire pipeline may be cleared due to an exception, interruption or branch prediction error, it can be determined which instructions in the out-of-order multi-issue processor can be executed and which instructions cannot be executed.

In order to make the technical solutions and advantages in the embodiments of the present application more clearly understood, the exemplary embodiments of the present application are further described in detail below in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present application, rather than an exhaustive list of all the embodiments. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other without conflict.

Referring to FIG. 1 , the instruction processing method for an out-of-order multi-issue processor provided in an embodiment of the present application includes the following steps S1 to S4:

S1, obtaining and caching the target instruction and its corresponding operand issued by the preset instruction issue queue.

In an optional embodiment of the present application, in step S1, obtaining and caching the target instruction and its corresponding operand issued by the preset instruction issue queue includes:

Get the target instruction sent by the preset instruction sending queue;

Determine the operand corresponding to the target instruction according to the target instruction;

The cache presets the target instructions and their corresponding operands issued by the instruction issue queue.

In an optional embodiment of the present application, determining an operand corresponding to the target instruction according to the target instruction includes:

Obtaining an address of a specified operand register in a target instruction, wherein the specified operand register stores an operand corresponding to the target instruction;

According to the address of the designated operand register, an operand corresponding to the target instruction is read from the designated register.

S2, storing the plurality of target instructions and their corresponding operands into a preset first-in-first-out queue.

In an optional embodiment of the present application, in step S2, storing the plurality of target instructions and their corresponding operands into a preset first-in-first-out queue includes:

According to the order of reading the operands, different target instructions and their corresponding operands are stored in a preset first-in-first-out queue.

S3. For each target instruction and its corresponding operand in the first-in-first-out queue, when the corresponding first synchronization signal is sent to the delivery module of the out-of-order multi-issue processor and the second synchronization signal sent by the delivery module is received at the same time, the target instruction is executed and the execution result is sent to the write back module of the out-of-order multi-issue processor, wherein there is no order between the sending of the first synchronization signal and the receiving of the second synchronization signal, and the first synchronization signal may be sent first and then the second synchronization signal is received, or the second synchronization signal may be received first and then the first synchronization signal is sent.

In an optional embodiment of the present application, the first synchronization signal is used to control the read and write operations of the target instruction, and the second synchronization signal is used to deliver the instruction, wherein the condition for delivering the instruction is that the instruction preceding the current instruction has no branch prediction error, interruption or exception.

In an optional embodiment of the present application, in step S3, the instruction is a CSR (Control and Status Register) instruction, and executing the target instruction and sending the execution result to the write-back module of the out-of-order multi-issue processor includes:

Update the value of the target instruction, generate a corresponding clear signal (a signal indicating that the pipeline needs to be flushed), and store the updated value of the target instruction and the clear signal in a preset register;

The updated value of the target instruction, the clear signal, and the storage record of the preset register are sent to the write-back module.

In an optional embodiment of the present application, the instruction is a CSR instruction, and before executing the target instruction, the method further includes:

When the CSR instruction is a read-write operation instruction and the destination register is the general integer register x0, CSR is only written but not read, where xreg is a general integer register, represented by the code x0~x31 or x0~x15. Whether it is 32 registers or 16 registers is affected by the currently used subset. The value of the general integer register x0 is usually reserved as a constant 0, which means that writing to x0 is invalid.

When the CSR instruction is a read and set operation instruction or a read and clear operation instruction, and the operand register is the general integer register x0, the CSR is only read but not written;

When the CSR instruction is an immediate value extension instruction of a read and set operation or an immediate value extension instruction of a read and clear operation, and the immediate value is 0, the CSR is only read but not written.

S4, the delivery module sends the target instruction delivery result to the write-back module of the out-of-order multi-issue processor.

Referring to FIG. 2 , the flow of instructions in the instruction processing method for an out-of-order multi-issue processor disclosed in the present invention is as follows:

The left side of Figure 2 shows the execution path of the CSR instruction, and the right side shows the path of the delivery module and the write-back module. When the CSR instruction appears in the instruction queue (instruction queue) for instruction emission, it passes through the instruction queue buffer iqbuf (instuction queue buffer, used to optimize timing, Inst Queue and iqbuf are both before reading operands), the operand buffer opbuf (opcode buffer, all operands need to be obtained at this stage), and reaches the encapsulation module csr_wrapper (used to encapsulate the N-depth-FIFO of the first-in-first-out buffer area with a depth of N for modules directly related to csr, the instruction control module csr_ctrl and the instruction update module csr_update, the instruction control module is used to control the reading and writing of the csr register, and the instruction update module is used to update the value of the csr register). Among them, the operand must be obtained before it comes out of opbuf, otherwise it will be stuck and wait until it is obtained. When the CSR instruction enters csr_wrapper, it first enters an N-depth fifo cache (N-depth-fifo, a first-in-first-out cache area with a depth of N, which can cache multiple CSR instructions sent from the upstream). At the exit of the fifo cache, it is necessary to wait for the csr cmt signal sent by the delivery module in Figure 2 before continuing to enter the instruction control module csr_ctrl. If there is no csr cmt signal (csr commit signal, sent by the cmt module, notifying the csr_ctrl module that the instruction can be delivered, cmt is the commit instruction delivery module), it is necessary to wait until it is received. At the same time, on the main pipeline on the right side of Figure 2, it is necessary to wait for the csr rslv signal sent by the instruction control module csr_ctrl (informing the delivery module that the CSR instruction has reached the csr_ctrl module), that is, the CSR instruction has reached the csr_ctrl module normally, before it can continue to move to the downstream module. When the CSR instruction enters the csr_ctrl module, the update of the CSR instruction can be completed. The corresponding clear signal is generated while updating the CSR instruction. At the same time, the read data is saved in the register and sent to the write-back module (writing the calculation result of the instruction back to the general register group regfile), and written back after arbitration.

In this embodiment, the csr_ctrl module and the delivery module are forced to be synchronized, and both sides wait for each other until the conditions are met. The forced synchronization is to ensure that the current CSR instruction can be safely executed and will not be cleared by other instructions. When the instructions preceding the current CSR instruction are cleared due to an exception, interruption or branch prediction error, the execution status of the current CSR instruction can be determined, that is, whether it can be executed safely.

Please refer to FIG. 3 , the target instruction is a VPU (Vector Process Unit) instruction. The instruction processing method for an out-of-order multi-issue processor provided in the embodiment of the present application further includes the following steps S31 to S35:

S31, obtaining and caching instructions issued by a preset instruction issuing queue.

In an optional embodiment of the present application, the instructions issued by the dispatch module of the execution unit are grouped, and not each group of instructions has a separate instruction issuance queue, but multiple groups of instructions share the instruction issuance queue, taking into account the area and function of the cache area.

S32, extracting VPU instructions from the instructions, and decoding the instructions.

In an optional embodiment of the present application, the decoding information obtained by decoding the instruction is related to the general integer register, operand register and destination register index of the VPU instruction.

S33, grouping the extracted VPU instructions according to the decoding information of the instructions.

In an optional embodiment of the present application, the decoding information is related to the general integer register, operand register and destination register index of the VPU instruction, and the grouping of the extracted VPU instructions according to the decoding information of the instruction includes:

The extracted VPU instructions are divided into memory access instructions and non-memory access instructions according to instruction decoding information, and each VPU instruction is divided into multiple minimum operation units. The operand register and destination register of the VPU instruction can be general integer registers or vector registers.

S34, determining whether the grouping of the VPU instructions is completed when the operands corresponding to the VPU instructions and the instruction delivery signal are obtained.

In an optional embodiment of the present application, obtaining the operand corresponding to the VPU instruction includes:

Obtaining an address of a VPU instruction designated operand register, wherein the designated operand register stores an operand corresponding to the VPU instruction;

According to the address of the designated operand register, the operand corresponding to the VPU instruction is read from the designated register.

In an optional embodiment of the present application, reading the operand corresponding to the VPU instruction from the designated register includes:

When the designated register is a general integer register and the operand corresponding to the VPU instruction has a dependency relationship with the general integer register, reading of the operand is suspended until the operand corresponding to the VPU instruction has no dependency relationship with the general integer register.

In an optional embodiment of the present application, the step of obtaining an instruction delivery signal corresponding to the VPU instruction includes:

Sending instructions to a delivery module of an out-of-order multi-issue processor;

The receiving and committing module sends an instruction commit signal in response to the instruction, wherein the instruction commit signal is generated when no branch prediction error, interruption, or exception occurs in an instruction preceding the instruction.

S35, when the VPU instructions have been grouped and the memory access address corresponding to the memory access instruction obtained by the grouping has been obtained, the memory access operation is performed according to the memory access instruction according to the memory access address, and the memory access operation result is written back to the specified register through the write-back module, and the non-memory access instruction is directly executed.

In an optional embodiment of the present application, directly executing a non-memory access instruction includes:

For non-memory access instructions, the corresponding multiple minimum operation units are executed and the execution results are sent to the write-back module.

In an optional embodiment of the present application, the memory access address corresponding to the memory access instruction obtained by the acquisition group includes:

The offset memory access address in the memory access instruction is calculated according to the operand corresponding to the memory access instruction to obtain the memory access address corresponding to the memory access instruction.

Referring to FIG. 4 , the flow of VPU instructions in the instruction processing method for an out-of-order multi-issue processor disclosed in the present invention is as follows:

The VPU instruction comes out of the dispatch module of the pipeline execution unit (used to dispatch instructions to different computing units for execution) and is divided into two paths, one is the delivery module (instruction delivery means that the instruction is no longer in the predicted execution state in the pipeline, it is determined that it can be actually executed in the processor and can affect the processor state), and the other is the execution path, where the predicted execution state is: if the previous instruction of an instruction B is a branch jump instruction A, then instruction B is in the predicted execution state. When the previous branch jump instruction A passes through the execution stage, if the prediction is wrong, then instruction B will be cancelled and will not be executed; if the prediction is correct, then instruction B will not be cancelled and can be executed, and the predicted execution state is released, and it can be truly delivered. An instruction is dispatched from the dispatch module of the execution unit, and the parsed instruction information is sent to the queue for instruction issuance (in an out-of-order multi-issue processor, instructions can be issued out of order). Depending on the timing, it may need to enter the queue (used to optimize timing) cache when it comes out of the queue. In the queue stage and queue cache stage, VPU instructions and other instructions such as AGU (Address Generate Unit) instructions are shared. Then the VPU instructions are separated. The instructions enter the vpu separator (in the same stage as the vpu parser, used to extract the VPU instructions from the mixed instruction stream) and the vpu parser (which performs decoding work related to the vector registers and indexes of the VPU instructions, and is used by the downstream instruction dispatch module to perform uop segmentation and grouping of instructions), and then go to the instruction dispatch module (which is used to group the VPU instructions and perform instruction uop (the full name of uop is micro operation. For SIMD instructions such as VPU instructions, the official instruction set manual requires that they must be split during specific implementation. The full name of SIMD is Single Instruction Multiple Data, that is, an instruction needs to process multiple data. If it is not split, it is impossible to process a large amount of data at one time. uop is the division of the smallest operation unit of the instruction) and enters the operand cache at the same time. The VPU instruction is obtained in the instruction dispatch module stage, and the instruction dispatch module stage and the operand cache stage are strongly aligned. The VPU instruction in the instruction dispatch module stage needs to meet two conditions to be sent down: if xreg (xreg refers to a general integer register) is needed, the dependency of xreg is released in the operand cache stage; it is also necessary to wait for the delivery information of this VPU instruction itself (the premise that an instruction can be successfully delivered is that its predecessor instruction has no branch prediction error, interruption or exception). If the dependency is not released, or there is no delivery information, it is necessary to wait. When the VPU instruction reaches the instruction dispatch module, a dependency check is performed. When the dependency is released, it continues to be sent down. According to the principle of vpu grouping, they are assigned to different instruction groups. The instructions assigned to the memory access instruction group are memory access instructions, and they must maintain strong alignment with the first vector address generation unit (the address used for memory access is calculated based on the address offset) at the memory access instruction group stage. The memory access instruction group needs to inform the first vector address generation unit whether the grouping and other related information have been completed, and the first vector address generation unit also needs to inform the memory access instruction group whether the address and other information are ready. If one side has not completed the relevant operation, the other side needs to wait. When both sides are ready, they will go to the second vector address generation unit together (the information sent by the first vector address generation unit and the memory access instruction group needs to be obtained at the same time). When the memory access instruction arrives at the second vector address generation unit, the memory access instruction is sent to the memory access unit for memory access operation, and finally the memory access result is written back to the general register group through the write-back unit (used to write the calculation result of the instruction back to the general register group).

It should be understood that, although the various steps in the flow chart are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear description in this article, the execution of these steps is not strictly limited in order, and these steps can be executed in other orders. Moreover, at least a portion of the steps in the figure may include multiple sub-steps or multiple stages, and these sub-steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these sub-steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a portion of the sub-steps or stages of other steps.

Referring to FIG. 5 , an embodiment of the present application provides an instruction processing device for an out-of-order multi-issue processor, including:

The first buffer area 11 is used to obtain and cache the CSR instructions and their corresponding operands issued by the preset instruction issue queue;

The second buffer area 12 is used to store a plurality of CSR instructions and their corresponding operands into a preset first-in-first-out queue;

The transceiver module 13 is used for, for each CSR instruction and its corresponding operand in the first-in-first-out queue, sending a corresponding first synchronization signal to the delivery module of the out-of-order multi-issue processor and receiving a second synchronization signal sent by the delivery module, executing the CSR instruction and sending the execution result to the write-back module of the out-of-order multi-issue processor;

The delivery module 14 is used to send the CSR instruction delivery result to the write-back module of the out-of-order multi-issue processor.

In an optional embodiment of the present application, the first buffer area is further used for:

Get the CSR instruction sent by the preset instruction sending queue;

Determine the operand corresponding to the CSR instruction;

The CSR instructions and their corresponding operands issued by the preset instruction issue queue are cached.

In an optional embodiment of the present application, the first buffer area is further used for:

Obtaining an address of a specified operand register in a CSR instruction, wherein the specified operand register stores an operand corresponding to the CSR instruction;

According to the address of the designated operand register, the operand corresponding to the CSR instruction is read from the designated register.

In an optional embodiment of the present application, the second buffer area is further used for:

According to the order of reading operands, different CSR instructions and their corresponding operands are stored in a preset first-in-first-out queue.

In an optional embodiment of the present application, in the transceiver module, the first synchronization signal is used to control the read and write operations of the CSR instruction, and the second synchronization signal is used to deliver the instruction.

In an optional embodiment of the present application, the transceiver module is further used for:

Update the value of the CSR instruction, generate a corresponding clear signal, and store the updated value of the CSR instruction and the clear signal in a preset register, wherein the clear signal is a signal for flushing the pipeline;

The update value of the CSR instruction, the clear signal, and the storage record of the preset register are sent to the write-back module.

In an optional embodiment of the present application, the transceiver module is further used for:

When the CSR instruction is a read-write operation instruction and the destination register is the general integer register x0, the CSR is only written but not read;

When the CSR instruction is a read and set operation instruction or a read and clear operation instruction, and the operand register is the general integer register x0, the CSR is only read but not written;

When the CSR instruction is an immediate value extension instruction of a read and set operation or an immediate value extension instruction of a read and clear operation, and the immediate value is 0, the CSR is only read but not written.

For the specific definition of the above-mentioned instruction processing device for the out-of-order multi-issue processor, please refer to the definition of the instruction processing method for the out-of-order multi-issue processor above, which will not be repeated here. Each module in the above-mentioned instruction processing device for the out-of-order multi-issue processor can be implemented in whole or in part by software, hardware and a combination thereof. The above-mentioned modules can be embedded in or independent of the processor in the computer device in the form of hardware, or can be stored in the memory of the computer device in the form of software, so that the processor can call and execute the operations corresponding to the above modules.

In one embodiment, a computer device is provided, and the internal structure diagram of the computer device can be shown in Figure 6. The computer device includes a processor, a memory, a network interface and a database connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system, a computer program and a database. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The database of the computer device is used to store data. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, an instruction processing method for a disordered multi-issue processor as described above is implemented. It includes: including a memory and a processor, the memory stores a computer program, and when the processor executes the computer program, any step in the instruction processing method for a disordered multi-issue processor as described above is implemented.

In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, any step of the above instruction processing method for an out-of-order multi-issue processor can be implemented.

Those skilled in the art will appreciate that the embodiments of the present application may be provided as methods, systems, or computer program products. Therefore, the present application may adopt the form of a complete hardware embodiment, a complete software embodiment, or an embodiment in combination with software and hardware. Moreover, the present application may adopt the form of a computer program product implemented in one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) that include computer-usable program code.

The present application is described with reference to the flowchart and/or block diagram of the method, device (system) and computer program product according to the embodiment of the present application. It should be understood that each process and/or box in the flowchart and/or block diagram, and the combination of the process and/or box in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and/or one box or multiple boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

Although the preferred embodiments of the present application have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications falling within the scope of the present application.

Obviously, those skilled in the art can make various changes and modifications to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

Claims (10)

1. An instruction processing method for an out-of-order multi-issue processor, comprising: Obtain and cache the target instructions and their corresponding operands issued by the preset instruction issuance queue; storing a plurality of target instructions and their corresponding operands into a preset first-in-first-out queue; For each target instruction and its corresponding operand in the first-in-first-out queue, when a corresponding first synchronization signal is sent to the delivery module of the out-of-order multi-issue processor and a second synchronization signal sent by the delivery module is received at the same time, the target instruction is executed and the execution result is sent to the write-back module of the out-of-order multi-issue processor, and the delivery module sends the target instruction delivery result to the write-back module of the out-of-order multi-issue processor. 2. The method according to claim 1, wherein the step of obtaining and caching the target instruction issued by the preset instruction issue queue and its corresponding operand comprises: Get the target instruction sent by the preset instruction sending queue; Determine the operand corresponding to the target instruction according to the target instruction; The cache presets the target instructions and their corresponding operands issued by the instruction issue queue. 3. The method according to claim 2, wherein determining the operand corresponding to the target instruction comprises: Obtaining an address of a specified operand register in a target instruction, wherein the specified operand register stores an operand corresponding to the target instruction; According to the address of the designated operand register, an operand corresponding to the target instruction is read from the designated register. 4. The method according to claim 3, wherein storing the plurality of target instructions and their corresponding operands into a preset first-in-first-out queue comprises: According to the order of reading the operands, different target instructions and their corresponding operands are stored in a preset first-in-first-out queue. 5. The method according to claim 1 is characterized in that the first synchronization signal is used to control the read and write operations of the target instruction, and the second synchronization signal is used to deliver the instruction. 6. The method according to claim 1, wherein the target instruction is a CSR instruction, and executing the target instruction and sending the execution result to a write-back module of the out-of-order multi-issue processor comprises: Update the value of the target instruction, generate a corresponding clear signal, and store the updated value of the target instruction and the clear signal in a preset register, wherein the clear signal is a signal for flushing the pipeline; The updated value of the target instruction, the clear signal, and the storage record of the preset register are sent to the write-back module. 7. The method according to claim 6, characterized in that, before executing the target instruction, the method further comprises: When the CSR instruction is a read-write operation instruction and the destination register is the general integer register x0, the CSR is only written but not read; When the CSR instruction is a read and set operation instruction or a read and clear operation instruction, and the operand register is the general integer register x0, the CSR is only read but not written; When the CSR instruction is an immediate value extension instruction of a read and set operation or an immediate value extension instruction of a read and clear operation, and the immediate value is 0, the CSR is only read but not written. 8. An instruction processing device for an out-of-order multi-issue processor, comprising: A first buffer area is used to obtain and cache target instructions and corresponding operands issued by a preset instruction issue queue; A second cache area, for storing a plurality of target instructions and their corresponding operands into a preset first-in-first-out queue; A transceiver module, for each target instruction and its corresponding operand in the first-in-first-out queue, when sending a corresponding first synchronization signal to a delivery module of the out-of-order multi-issue processor and receiving a second synchronization signal sent by the delivery module, executes the target instruction and sends the execution result to a write-back module of the out-of-order multi-issue processor; The delivery module is used to send the target instruction delivery result to the write-back module of the out-of-order multi-issue processor. 9. A computer device, comprising: a memory and a processor, wherein the memory stores a computer program, wherein the processor implements the steps of the instruction processing method for an out-of-order multi-issue processor as claimed in any one of claims 1 to 7 when executing the computer program. 10. A computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the steps of the instruction processing method for an out-of-order multi-issue processor according to any one of claims 1 to 7 are implemented.