CN118862773A - Fault information determination method, device and terminal equipment - Google Patents

Abstract

The embodiment of the present application provides a method, device and terminal device for determining fault information. The method includes: obtaining configuration information of a memory, the configuration information including a first address of the memory and a unit address of each storage unit in the memory; obtaining test information obtained by testing the memory, the test information including at least one storage data corresponding to each storage unit in the memory, the operation order of each storage unit, and the second address of the memory; determining fault information existing in the test process of the memory according to the configuration information of the memory and the test information of the memory. The accuracy of determining whether there is a fault during chip testing is improved.

Description

Fault information determination method, device and terminal equipment

Technical Field

The embodiments of the present application relate to the field of chip technology, and in particular, to a method, apparatus and terminal device for determining fault information.

Background Art

The chip and the test circuit can be connected via a shared access path (sharebus) interface, so that the memory in the chip can be tested via the test circuit.

Before testing the memory in the chip through the test circuit, simulation testing can be performed through simulation testing tools (for example, electronic design automation (EDA)) to verify the entire test process. In the related art, testing can be performed through simulation testing tools in the following manner: obtaining description files of each memory in the chip. The tester determines the test process and configuration file of the test chip based on the description files of each memory. According to the test process and configuration file of the test chip, simulation testing is performed through simulation testing to obtain test results.

In the above process, the test process and configuration file of the test chip are manually determined based on the description files of each memory. There is a situation where the test circuit is inaccurate due to inaccurate configuration files, causing the memory in the chip to not be fully tested or the internal fault of the memory to not be accurately tested. As a result, the accuracy of determining whether there is a fault during the chip test is low.

Summary of the invention

The embodiments of the present application provide a method, apparatus and terminal device for determining fault information, which are used to solve the problem of low accuracy in determining whether a fault exists during chip testing.

In a first aspect, an embodiment of the present application provides a method for determining fault information, including:

Acquire configuration information of a memory, the configuration information including a first address of the memory and a unit address of each storage unit in the memory;

Acquire test information obtained by testing the memory, the test information including at least one storage data corresponding to each storage unit in the memory, an operation order of each storage unit, and a second address of the memory;

Fault information existing in a test process of the memory is determined according to the configuration information of the memory and the test information of the memory.

In a possible implementation manner, determining fault information existing in a test process of the memory according to the configuration information of the memory and the test information of the memory includes:

Determining address fault information existing in a test process of the memory according to a first address of the memory, an operation order of each storage unit in the memory, and a second address of the memory;

Determine data fault information and sequence fault information existing in a test process of the memory according to a unit address of each memory unit in the memory, at least one storage data corresponding to each memory unit, and an operation order of each memory unit;

The fault information existing in the test process of the memory is determined to include any one or more of the following: the address fault information, the data fault information and the sequence fault information.

In a possible implementation manner, determining address fault information existing in a test process of the memory according to a first address of the memory, an operation order of each storage unit in the memory, and a second address of the memory includes:

obtaining a test period of the memory;

Determining at least one operation period of each memory according to the operation order of each storage unit in the memory;

According to the test period of the memory and at least one operation period of the memory in the memory, address fault information existing in the test process of the memory is determined.

In a possible implementation manner, determining address fault information of a memory existing in a test process of the memory according to a test period of the memory and at least one running period of a memory in the memory includes:

If there is at least one of the operating time periods that does not match the test time periods, the operating time periods that do not match the test time periods are determined as target time periods;

Determining the address fault information includes an identification of the memory, a test period of the memory, and the target period.

In a possible implementation manner, determining data fault information and sequence fault information existing in a test process of the memory according to a unit address of each storage unit in the memory, at least one storage data corresponding to each storage unit, and an operation order of each storage unit includes:

Determining the sequential fault information according to the unit addresses of the storage units in the memory and the operation order of the storage units;

The data fault information is determined according to at least one storage data corresponding to each storage unit.

In a possible implementation manner, determining the sequential fault information according to the unit address of each storage unit in the memory and the operation order of each storage unit includes:

Determining a test order of each unit in the memory according to a unit address of each storage unit in the memory;

If the test sequence does not match the running sequence, determining at least one target storage unit in the test sequence that does not match the running sequence;

Determining the sequential fault information includes at least one target storage unit, a first ranking of each target storage unit in the test sequence, and a second ranking of each target storage unit in the run sequence.

In a possible implementation manner, the stored data includes first stored data and second stored data; and determining the data fault information according to at least one stored data corresponding to each storage unit includes:

Acquire at least one test data of each storage unit, wherein the test data includes first test data and second test data;

Acquire data signals corresponding to each storage unit;

Data fault information of the memory is determined according to a data signal corresponding to each storage unit, at least one test data of each storage unit and at least one storage data of each storage unit.

In a possible implementation, determining data fault information of the memory according to a data signal corresponding to each storage unit, at least one test data of each storage unit, and at least one storage data of each storage unit includes:

If among the data signals corresponding to the storage units, there is a data signal that is a preset signal, determining at least one storage unit corresponding to the preset signal as a first storage unit to be selected;

For any storage unit, if the first test data does not match the first storage data, and/or the second test data does not match the second storage data, the storage unit is determined as a second storage unit to be selected, and at least one second storage unit to be selected is obtained;

The data fault information is determined to include the at least one first storage unit to be selected, the at least one second storage unit to be selected, and at least one test data and at least one storage data corresponding to each second storage unit to be selected.

In a possible implementation, the method further includes:

Get the preset storage path;

According to the preset storage path, the fault information corresponding to the memory is stored and tested.

In a second aspect, an embodiment of the present application provides a device for determining fault information, the device comprising:

A first acquisition module, used to acquire configuration information of a memory, wherein the configuration information includes a first address of the memory and a unit address of each storage unit in the memory;

A second acquisition module, configured to acquire test information obtained by testing the memory, wherein the test information includes at least one storage data corresponding to each storage unit in the memory, an operation order of each storage unit, and a second address of the memory;

The determination module is used to determine the fault information existing in the test process of the memory according to the configuration information of the memory and the test information of the memory.

In a possible implementation manner, the determining module is specifically configured to:

Determining address fault information existing in a test process of the memory according to a first address of the memory, an operation order of each storage unit in the memory, and a second address of the memory;

Determine data fault information and sequence fault information existing in a test process of the memory according to a unit address of each memory unit in the memory, at least one storage data corresponding to each memory unit, and an operation order of each memory unit;

The fault information existing in the test process of the memory is determined to include any one or more of the following: the address fault information, the data fault information and the sequence fault information.

In a possible implementation manner, the determining module is specifically configured to:

obtaining a test period of the memory;

Determining at least one operation period of each memory according to the operation order of each storage unit in the memory;

According to the test period of the memory and at least one operation period of the memory in the memory, address fault information existing in the test process of the memory is determined.

In a possible implementation manner, the determining module is specifically configured to:

If there is at least one of the operating time periods that does not match the test time periods, the operating time periods that do not match the test time periods are determined as target time periods;

Determining the address fault information includes an identification of the memory, a test period of the memory, and the target period.

In a possible implementation manner, the determining module is specifically configured to:

Determining the sequential fault information according to the unit addresses of the storage units in the memory and the operation order of the storage units;

The data fault information is determined according to at least one storage data corresponding to each storage unit.

In a possible implementation manner, the determining module is specifically configured to:

Determining a test order of each unit in the memory according to a unit address of each storage unit in the memory;

If the test sequence does not match the running sequence, determining at least one target storage unit in the test sequence that does not match the running sequence;

Determining the sequential fault information includes at least one target storage unit, a first ranking of each target storage unit in the test sequence, and a second ranking of each target storage unit in the run sequence.

In a possible implementation manner, the determining module is specifically configured to:

Acquire at least one test data of each storage unit, wherein the test data includes first test data and second test data;

Acquire data signals corresponding to each storage unit;

Data fault information of the memory is determined according to a data signal corresponding to each storage unit, at least one test data of each storage unit and at least one storage data of each storage unit.

In a possible implementation manner, the determining module is specifically configured to:

If among the data signals corresponding to the storage units, there is a data signal that is a preset signal, determining at least one storage unit corresponding to the preset signal as a first storage unit to be selected;

For any storage unit, if the first test data does not match the first storage data, and/or the second test data does not match the second storage data, the storage unit is determined as a second storage unit to be selected, and at least one second storage unit to be selected is obtained;

The data fault information is determined to include the at least one first storage unit to be selected, the at least one second storage unit to be selected, and at least one test data and at least one storage data corresponding to each second storage unit to be selected.

In a possible implementation manner, the device further includes a storage module.

Wherein, the storage module is used for:

Get the preset storage path;

According to the preset storage path, the fault information corresponding to the memory is stored and tested.

In a third aspect, the present application provides a chip having a computer program stored thereon, wherein when the computer program is executed by the chip, the method as described in any one of the first aspects is implemented.

In a fourth aspect, the present application provides a chip module having a computer program stored thereon, wherein when the computer program is executed by the chip module, the method as described in any one of the first aspects is implemented.

In a fifth aspect, an embodiment of the present application provides a terminal device, including:

at least one processor; and

a memory communicatively connected to the at least one processor; wherein,

The memory stores instructions that can be executed by the at least one processor, and the instructions are executed by the at least one processor so that the at least one processor can perform any method described in the first aspect.

In a sixth aspect, an embodiment of the present application provides a non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to enable the computer to execute any one of the methods described in the first aspect.

In a seventh aspect, an embodiment of the present application provides a computer program product, including a computer program, which implements any method in the first aspect when executed by a processor.

The fault information determination method, device and terminal device provided in the embodiment of the present application obtain the configuration information of the memory, and the configuration information includes the first address of the memory and the unit address of each storage unit in the memory. The test information obtained by testing the memory is obtained, and the test information includes at least one storage data corresponding to each storage unit in the memory, the operation order of each storage unit, and the second address of the memory. According to the configuration information of the memory and the test information of the memory, the fault information existing in the test process of the memory is determined. In the above process, the fault information existing in the test process of the memory can be determined according to the configuration information of the memory and the test information of the memory. It is avoided that the test process and configuration file of the test chip are determined artificially according to the description files of each memory, so that there is an inaccurate configuration file, which leads to an inaccurate test circuit, causing the memory in the chip to fail to be fully tested or the internal fault of the memory cannot be accurately tested. The accuracy of determining whether there is a fault during the chip test process is improved.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of an application scenario provided by an embodiment of the present application;

FIG2 is a schematic diagram of a flow chart of a method for determining fault information provided in an embodiment of the present application;

FIG3 is a schematic diagram of a process for obtaining a description file provided in an embodiment of the present application;

FIG4 is a schematic diagram of a flow chart of another method for determining fault information provided in an embodiment of the present application;

FIG5 is a schematic diagram of a process for determining sequential fault information provided by an embodiment of the present application;

FIG6 is a schematic diagram of a process of obtaining data signals corresponding to each storage unit according to an embodiment of the present application;

FIG7 is a schematic diagram of a process for determining a second storage unit to be selected according to an embodiment of the present application;

FIG8 is a schematic diagram of a fault information determination process provided in an embodiment of the present application;

FIG9 is a schematic diagram of the structure of a fault information determination device provided in an embodiment of the present application;

FIG10 is a schematic diagram of the structure of another fault information determination device provided in an embodiment of the present application;

FIG. 11 is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application.

DETAILED DESCRIPTION

Exemplary embodiments will be described in detail herein, examples of which are shown in the accompanying drawings. When the following description refers to the drawings, the same numbers in different drawings represent the same or similar elements unless otherwise indicated. The implementations described in the following exemplary embodiments do not represent all implementations consistent with the present application. Instead, they are merely examples of devices and methods consistent with some aspects of the present application as detailed in the appended claims.

It should be noted that, in this article, the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, an element defined by the sentence "comprises a ..." does not exclude the existence of other identical elements in the process, method, article or device including the element.

It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant laws, regulations and standards, and provide corresponding operation entrances for users to choose to authorize or refuse.

For ease of understanding, the application scenarios applicable to the embodiments of the present application are described below in conjunction with FIG. 1 .

FIG1 is a schematic diagram of an application scenario provided by an embodiment of the present application. Please refer to FIG1, which includes a chip 101 and a test circuit 102. The chip 101 is provided with a sharebus interface, two 32×64 physical memories, and two 64×32 physical memories. The test circuit 101 can transmit data with each memory in the chip 101 through the sharebus interface, thereby testing each memory in the chip 101. Before testing the memory in the chip 101 through the test circuit 102, the entire process can be simulated by a simulation test tool.

In the related art, the following method can be used to perform testing through a simulation test tool: obtain the description file of each memory in the chip. The tester determines the test process and configuration file of the test chip based on the description file of each memory. According to the test process and configuration file of the test chip, a simulation test is performed through a simulation test to obtain a test result. In the above process, the test process and configuration file of the test chip are determined manually based on the description files of each memory. There is a situation where the test circuit generated is inaccurate due to inaccurate configuration files, resulting in the failure of all memories in the chip to be tested or the internal fault of the memory to be accurately tested. As a result, the accuracy of determining whether there is a fault during the chip testing process is low.

In an embodiment of the present application, configuration information of a memory is obtained, and the configuration information includes a first address of the memory and a unit address of each storage unit in the memory. Test information obtained by testing the memory is obtained, and the test information includes at least one storage data corresponding to each storage unit in the memory, an operation order of each storage unit, and a second address of the memory. According to the configuration information of the memory and the test information of the memory, fault information existing in the test process of the memory is determined. In the above process, the fault information existing in the test process of the memory can be determined according to the configuration information of the memory and the test information of the memory. It is avoided that the test process and configuration file of the test chip are determined artificially according to the description files of each memory, so that there is an inaccurate configuration file, which leads to an inaccurate test circuit, causing the memory in the chip to fail to be fully tested or the internal fault of the memory cannot be accurately tested. The accuracy of determining whether there is a fault during the chip test process is improved.

The method shown in the present application is described below through specific embodiments. It should be noted that the following embodiments can exist independently or in combination with each other, and the same or similar contents will not be described repeatedly in different embodiments.

FIG2 is a flow chart of a method for determining fault information provided by an embodiment of the present application. Referring to FIG2 , the method may include:

S201. Obtain memory configuration information.

The execution subject of the embodiment of the present application may be a terminal device, or a chip, a chip module, or a fault information determination device set in the terminal device. The fault information determination device may be implemented by software, or by a combination of software and hardware. The terminal device may be a computer.

The configuration information includes a first address of the memory and a unit address of each storage unit in the memory.

The first address of the memory is the address of the physical memory, and the unit address of each storage unit in the memory may include at least one or more of the following: a row address, a column address, and a block address of each storage unit in the physical memory.

The configuration information of each memory in the chip can be determined according to the description file (memlib) of the chip. The memory is a physical memory. The description file may include a memory cluster description file (cluster memlib), a logical memory description file (logical memlib) and a physical memory description file (phyiscal memlib). Among them, the memory cluster description file is used to describe the access method that can be accessed to each logical memory through the same sharebus interface. The logical memory description file is used to describe the physical memories and access methods included in the logical memory. The physical memory description file is used to describe the internal structure and parameters of the physical memory.

Each memory cluster includes at least one logical memory, and the logical memory includes at least one physical memory.

Below, in conjunction with Figure 3, the process of obtaining a description file is explained. Figure 3 is a schematic diagram of the process of obtaining a description file provided in an embodiment of the present application. Please refer to Figure 3, which includes interfaces 301 to 302. Interfaces 301 to 302 may be pages provided for a terminal device. Please refer to interface 301. The user clicks on the icon corresponding to the test application in the terminal device, and the terminal device displays an operation page in response to the user's click operation. The operation page includes a drop-down selection menu corresponding to a memory cluster description file, a drop-down selection menu corresponding to at least one logical memory description file, a drop-down selection menu corresponding to at least one physical memory description file, and a text input box.

Referring to interface 302, the user determines that the memory cluster description file is description file A in the drop-down selection menu corresponding to the memory cluster description file, determines that the logical memory description file is description file A1 in the drop-down selection menu corresponding to the logical memory description file 1, determines that the description file of the physical memory 1 is description file A11 in the drop-down selection menu corresponding to the physical memory description file 1, determines that the description file of the physical memory 2 is description file A12 in the drop-down selection menu corresponding to the physical memory description file 2, and clicks the OK icon. In response to the user's input selection operation, the terminal device obtains description file A, description file A1, description file A11, and description file A12.

A first script for determining fault information can be generated by a preset computer language, and the first script includes fields such as address bits, data bits, and address bits of each internal storage unit corresponding to the physical memory and the sharebus interface. After determining the first chip to be tested and the test process, the address bits, data bits, and address bits of each internal storage unit corresponding to the physical memory and the sharebus interface can be filled into the corresponding fields in the first script according to the multiple description files and test processes corresponding to the first chip to generate a test monitoring script. The sharebus interface and each physical memory in the first chip can be monitored subsequently by the test monitoring script.

The test monitoring script includes a sharebus monitoring script and a memory monitoring script corresponding to each physical memory. At least one physical memory is arranged in the first chip.

S202: Acquire test information obtained by testing the memory.

The test information includes at least one storage data corresponding to each storage unit in the memory, the operation sequence of each storage unit, and the second address of the memory.

The second address of the memory may be an address for accessing the actual physical memory during the chip testing process.

The test monitoring script can be used to obtain test information obtained by testing the memory.

S203: Determine fault information existing in the test process of the memory according to the configuration information of the memory and the test information of the memory.

The test information obtained by testing the memory can be obtained in the following manner: determining address fault information existing in the test process of the memory according to a first address of the memory, an operating order of each storage unit in the memory and a second address of the memory; determining data fault information and sequence fault information existing in the test process of the memory according to a unit address of each storage unit in the memory, at least one storage data corresponding to each storage unit and an operating order of each storage unit; determining that the fault information existing in the test process of the memory includes any one or more of the following: address fault information, data fault information and sequence fault information.

The address fault information is used to indicate that the physical memory accessed by the memory during the test is different from the set physical memory. For example, during the operation period A1, the set physical memory accessed is memory A1. However, the physical memory accessed during the test is memory A2.

The data fault information is used to indicate that during the test process, the read data of the storage unit in the memory is different from the set read data, and/or the written data of the storage unit in the memory is different from the set write data.

The sequence fault information is used to indicate that the operation sequence of each storage unit of the memory during the test is different from the set operation sequence.

The fault information determination method provided in the embodiment of the present application obtains the configuration information of the memory. The test information obtained by testing the memory is obtained. According to the configuration information of the memory and the test information of the memory, the fault information existing in the test process of the memory is determined. In the above process, the fault information existing in the test process of the memory can be determined according to the configuration information of the memory and the test information of the memory. It is avoided that the test process and configuration file of the test chip are manually determined according to the description files of each memory, so that the test circuit generated by the inaccurate configuration file is inaccurate, causing the memory in the chip to not be fully tested or the internal fault of the memory cannot be accurately tested. The accuracy of determining whether there is a fault during the chip testing process is improved.

Based on any one of the above embodiments, the detailed process of the fault information determination method is described below in conjunction with FIG. 4 .

FIG4 is a flow chart of another method for determining fault information provided by an embodiment of the present application. Referring to FIG4 , the method includes:

S401. Obtain storage configuration information.

It should be noted that the execution process of S401 can refer to S201 and will not be repeated here.

S402: Acquire test information obtained by testing the memory.

It should be noted that the execution process of S402 can refer to S202 and will not be repeated here.

S403: Obtain a test period of the memory.

The test period of each memory can be determined according to the configuration file. The user can set the configuration file for this test according to the description file and store the configuration file in the preset storage space of the terminal device.

For example, the test circuit B is connected to the memory cluster B through the sharebus interface. The memory cluster B includes the physical memory B1 and the physical memory B2. The terminal device obtains the configuration file in the preset storage space, and determines the test period corresponding to each physical memory in the configuration file as shown in Table 1:

Table 1

S404: Determine at least one operating period of each memory according to the operating sequence of each storage unit in the memory.

By testing the memory monitoring script corresponding to the physical memory in the monitoring script, the operation order of each storage unit in the memory can be obtained, thereby determining at least one operation period of each memory.

For example, the at least one operating time period of each memory determined by the terminal device may be specifically as shown in Table 2:

Table 2

S405: Determine address fault information existing in the test process of the memory according to the test period of the memory and at least one operation period of the memory in the memory.

The address fault information existing in the test process of the memory can be determined according to the test period of the memory and at least one operation period of the memory in the memory in the following manner: if there is at least one operation period that does not match the test period, the operation period that does not match the test period is determined as the target period; the address fault information is determined to include the identifier of the memory, the test period of the memory and the target period.

For example, according to the above example, at least one operating period of the physical memory B1 does not match the test period, and the operating period 2024/07/03 15:01 to 2024/07/03 15:00:02 that does not match the test period is determined as the target period. The operating period of the physical memory B2 does not match the test period. Since the physical memory B2 does not have a target period, the target period is determined to be 0. Therefore, the terminal device determines that the address fault information includes the physical memory B1, the test period of the physical memory B1 is 2024/07/03 15:01 to 2024/07/03 15:00:02, and the target period is 2024/07/03 15:02 to 2024/07/03 15:00:03. And the physical memory B2, the test period of the physical memory B2 is 2024/07/03 15:02 to 2024/07/03 15:00:03, and the target period of the physical memory B2 is 0.

S406: Determine a test order of each unit in the memory according to the unit address of each storage unit in the memory.

According to the test scenario and test requirements, the access time of each unit address is determined. And according to the access time of each unit address, the test order of each storage unit in the memory is determined.

S407: If the test sequence and the running sequence do not match, determine at least one target storage unit in the test sequence that does not match the running sequence.

For any storage unit, if the running order of the storage unit during the running process is different from the first order in the test cycle sequence, it can be determined that the test sequence and the running order do not match.

S408. Determine that the sequential fault information includes at least one target storage unit, a first ranking of each target storage unit in the test sequence, and a second ranking of each target storage unit in the run sequence.

Below, in conjunction with Figure 5, the process of determining sequential fault information is described. Figure 5 is a schematic diagram of the process of determining sequential fault information provided by an embodiment of the present application. Please refer to Figure 5, which includes a test sequence 501 and an operation sequence 502. The test sequence 501 is the access sequence of each storage unit in the physical memory determined according to the test scenario and test requirements. The operation sequence 502 is the access sequence of each storage unit in the physical memory during the test. Assume that the order of the test operation is to traverse the row address of each storage unit, traverse the column address of each storage unit, and traverse the block address of each storage unit. Assume that the 5-bit address bit of the memory is [block [0], column [1:0], row [1:0]], and the test sequence 501 of storage units 1 to 32 corresponds to 1 to 32 in the test sequence 501 respectively. In the operation sequence 502, the second sorting of storage units 5 to 24 does not match the test sequence 501. The second rankings of storage units 5 to 24 are 9 to 12, 17 to 20, 25 to 28, 5 to 8, 13 to 16, and 21 to 24, respectively. Therefore, the terminal device determines that at least one target storage unit includes storage units 5 to 24. The first rankings of storage units 5 to 24 are 5 to 24, respectively, and the second rankings are 9 to 12, 17 to 20, 25 to 28, 5 to 8, 13 to 16, and 21 to 24, respectively.

S409: Obtain at least one test data of each storage unit.

The test data includes first test data and second test data. The test data is determined according to the configuration file and should be read into the storage unit during the test, and should be written into the storage unit during the test.

S410 , obtaining data signals corresponding to each storage unit.

The data signal is used to indicate whether the storage unit performs a read or write operation. If the storage unit performs a read or write operation, the level corresponding to the data signal corresponding to the storage unit will change. If the storage unit does not perform a read or write operation, the level corresponding to the data signal corresponding to the storage unit remains unchanged.

Below, in conjunction with Figure 6, the process of obtaining the data signal corresponding to each storage unit is described. Figure 6 is a schematic diagram of the process of obtaining the data signal corresponding to each storage unit provided in an embodiment of the present application. Please refer to Figure 6, including a memory 601, and the memory 601 can be a physical memory in the chip. The memory 601 transmits the control signal, address signal and data signal corresponding to each storage unit during the test. If the level corresponding to the data signal changes, it indicates that the storage unit performs a read and write operation. If the level corresponding to the data signal remains unchanged, it indicates that the storage unit does not perform a read and write operation.

S411 . Determine data fault information of the memory according to a data signal corresponding to each storage unit, at least one test data of each storage unit, and at least one storage data of each storage unit.

The storage data includes first storage data and second storage data. The storage data is the first storage data actually read into the storage unit during the test and the second storage data actually written into the storage unit during the test.

The data fault information of the memory can be determined according to the data signal corresponding to each storage unit, at least one test data of each storage unit and at least one storage data of each storage unit in the following manner: if there is a data signal that is a preset signal among the data signals corresponding to each storage unit, then at least one storage unit corresponding to the preset signal is determined to be a first storage unit to be selected; for any storage unit, if the first test data does not match the first storage data, and/or the second test data does not match the second storage data, then the storage unit is determined to be a second storage unit to be selected, and at least one second storage unit to be selected is obtained; it is determined that the data fault information includes at least one first storage unit to be selected, at least one second storage unit to be selected, and at least one test data and at least one storage data corresponding to each second storage unit to be selected.

A preset signal can be set in advance and stored in a preset storage space of the terminal device. The level corresponding to the preset signal changes. If the data signal is a preset signal, it indicates that the storage unit performs a read and write operation, and it can be determined that the storage unit has been tested. If the data signal is not a preset signal, it indicates that the storage unit does not perform a read and write operation, and it can be determined that the storage unit has not been tested.

Below, in conjunction with Figure 7, the process of determining the second storage unit to be selected is explained. Figure 7 is a schematic diagram of the process of determining the second storage unit to be selected provided in an embodiment of the present application. It includes a memory 701, and the memory 701 can be a physical memory in row 4/column 4 in the chip. The memory 701 includes 16 storage units. The black storage unit indicates that data 1 is written during the test process, and the white storage unit indicates that data 0 is written during the test process. It can be determined that the first test data of storage unit 5 is 0. If the first storage data of storage unit 5 is 1, it can be determined that the first test data does not match the first storage data. Therefore, the terminal device can determine that the second selected unit of memory 701 is storage unit 5.

S412: Determine that the fault information existing in the test process of the memory includes any one or more of the following: address fault information, data fault information, and sequence fault information.

The fault information may include any one or more of address fault information, data fault information and sequence fault information, which is not limited in the present application.

If it is determined that there is no address fault information, data fault information, and sequence fault information, it indicates that there is no fault during the chip test. At this time, the terminal device generates prompt information and stores or displays the prompt information. The prompt information is used to indicate that there is no fault in this chip test.

S413, storing fault information existing in the test process of the memory.

The fault information existing in the test process of the memory may be stored in the following manner: obtaining a preset storage path; and storing the fault information corresponding to the test of the memory according to the preset storage path.

A preset storage path may be set in advance and stored in a preset storage space of the terminal device. In the terminal device, the user obtains fault information existing in the memory test process through the preset storage path.

The fault information determination method provided by the embodiment of the present application obtains the configuration information of the memory. The test information obtained by testing the memory is obtained. The test period of the memory is obtained. According to the operation order of each storage unit in the memory, at least one operation period of each storage unit is determined. According to the test period of the memory and at least one operation period of the memory in the memory, the address fault information existing in the test process of the memory is determined. According to the unit address of each storage unit in the memory, the test order of each unit in the memory is determined. If the test order and the operation order do not match, at least one target storage unit that does not match the operation order is determined in the test order. The sequence fault information is determined to include at least one target storage unit, the first order of each target storage unit in the test order, and the second order of each target storage unit in the operation order. At least one test data of each storage unit is obtained. The data signal corresponding to each storage unit is obtained. According to the data signal corresponding to each storage unit, at least one test data of each storage unit and at least one storage data of each storage unit, the data fault information of the memory is determined. The fault information is determined to include address fault information, data fault information and sequence fault information. In the above process, the fault information existing in the test process of the memory can be determined according to the configuration information of the memory and the test information of the memory. Avoid manually determining the test process and configuration file of the test chip based on the description file of each memory, which may cause inaccurate configuration files to lead to inaccurate test circuits, resulting in failure to test all memories in the chip or inability to accurately test internal memory faults. Improve the accuracy of determining whether there is a fault during chip testing.

Based on any one of the above embodiments, the process of determining fault information is described below by way of example in conjunction with FIG. 8 .

FIG8 is a schematic diagram of the fault information determination process provided by an embodiment of the present application. Please refer to FIG8, which includes a terminal device 801. The terminal device 801 can be a computer, and the terminal device 801 includes a memory cluster monitoring module, a memory monitoring module 1, and a memory monitoring module 2. The memory cluster, sharebus interface, and test circuit in the chip can be generated in advance through description files and configuration files in the simulation test tool of the terminal device to generate corresponding simulation modules. And through the memory cluster monitoring module of the terminal device 801, the physical memory accessed at each time during the test process is obtained. And through each memory monitoring module of the terminal device 801, the test information of the memory is obtained. The terminal device 801 obtains the configuration information of the memory as shown in Table 3:

Table 3

The terminal device 801 controls the test circuit to perform simulation test on each memory in the memory cluster through the sharebus interface according to the configuration file. The test information obtained by the memory monitoring module 1 and the memory monitoring module 2 can be specifically shown in Table 4:

Table 4

The at least one operating time period of each memory determined by the terminal device 801 may be specifically as shown in Table 5:

Table 5

The terminal device 801 obtains the test period of the physical memory B1 and the test period of the physical memory B2 as shown in Table 6:

Table 6

Physical Memory Testing period Physical memory B1 2024/07/03 15:46～2024/07/03 15:00:47 Physical memory B2 2024/07/03 15:48～2024/07/03 15:00:49

According to Table 5 and Table 6, it can be determined that the test period of the physical memory B1 matches the operating period, and the test period of the physical memory B2 matches the operating period. Therefore, the terminal device 801 can determine that there is no address failure during the test process.

The terminal device 801 determines the test order of each unit in the memory according to the unit address of each storage unit in the memory, which can be specifically shown in Table 7:

Table 7

The terminal device 801 determines that the test sequence and the running sequence of the physical memory B2 do not match according to Table 4 and Table 7. Then, in the test sequence, at least one target storage unit that does not match the running sequence includes storage unit B7 and storage unit B8. Therefore, the terminal device 801 determines that the sequence fault information can be specifically shown in Table 8:

Table 8

Target storage unit First sort Second sort Storage unit B7 7 8 Storage unit B8 8 7

The terminal device 801 determines that there is no fault in the data according to at least one storage data corresponding to each storage unit. Therefore, the terminal device 801 determines that the fault information existing in the test process of the memory includes the sequential fault information shown in Table 8. The terminal device 801 obtains the preset storage path A in the preset storage space, and stores the fault information according to the preset storage path A.

The fault information determination process provided by the embodiment of the present application obtains the configuration information of the memory. The test information obtained by testing the memory is obtained. The test period of the memory is obtained. According to the operation order of each storage unit in the memory, at least one operation period of each memory is determined. According to the test period of the memory and at least one operation period of the memory in the memory, the address fault information existing in the test process of the memory is determined. According to the unit address of each storage unit in the memory, the test order of each unit in the memory is determined. If the test order and the operation order do not match, at least one target storage unit that does not match the operation order is determined in the test order. The sequence fault information is determined to include at least one target storage unit, the first order of each target storage unit in the test order, and the second order of each target storage unit in the operation order. At least one test data of each storage unit is obtained. The data signal corresponding to each storage unit is obtained. According to the data signal corresponding to each storage unit, at least one test data of each storage unit and at least one storage data of each storage unit, the data fault information of the memory is determined. The fault information is determined to include address fault information, data fault information and sequence fault information. In the above process, the fault information existing in the test process of the memory can be determined according to the configuration information of the memory and the test information of the memory. Avoid manually determining the test process and configuration file of the test chip based on the description file of each memory, which may cause inaccurate configuration files to lead to inaccurate test circuits, resulting in failure to test all memories in the chip or inability to accurately test internal memory faults. Improve the accuracy of determining whether there is a fault during chip testing.

FIG9 is a schematic diagram of the structure of a fault information determination device provided in an embodiment of the present application. The fault information determination device may be a chip or a chip module. Referring to FIG9 , the fault information determination device 10 may include:

A first acquisition module 11, used to acquire configuration information of a memory, wherein the configuration information includes a first address of the memory and a unit address of each storage unit in the memory;

A second acquisition module 12, used to acquire test information obtained by testing the memory, wherein the test information includes at least one storage data corresponding to each storage unit in the memory, an operation order of each storage unit, and a second address of the memory;

The determination module 13 is used to determine the fault information existing in the test process of the memory according to the configuration information of the memory and the test information of the memory.

In a possible implementation manner, the determining module 13 is specifically configured to:

Determining address fault information existing in a test process of the memory according to a first address of the memory, an operation order of each storage unit in the memory, and a second address of the memory;

Determine data fault information and sequence fault information existing in a test process of the memory according to a unit address of each memory unit in the memory, at least one storage data corresponding to each memory unit, and an operation order of each memory unit;

The fault information existing in the test process of the memory is determined to include any one or more of the following: the address fault information, the data fault information and the sequence fault information.

In a possible implementation manner, the determining module 13 is specifically configured to:

obtaining a test period of the memory;

Determining at least one operation period of each memory according to the operation order of each storage unit in the memory;

According to the test period of the memory and at least one operation period of the memory in the memory, address fault information existing in the test process of the memory is determined.

In a possible implementation manner, the determining module 13 is specifically configured to:

If there is at least one of the operating time periods that does not match the test time periods, the operating time periods that do not match the test time periods are determined as target time periods;

Determining the address fault information includes an identification of the memory, a test period of the memory, and the target period.

In a possible implementation manner, the determining module 13 is specifically configured to:

Determining the sequential fault information according to the unit addresses of the storage units in the memory and the operation order of the storage units;

The data fault information is determined according to at least one storage data corresponding to each storage unit.

In a possible implementation manner, the determining module 13 is specifically configured to:

Determining a test order of each unit in the memory according to a unit address of each storage unit in the memory;

If the test sequence does not match the running sequence, determining at least one target storage unit in the test sequence that does not match the running sequence;

Determining the sequential fault information includes at least one target storage unit, a first ranking of each target storage unit in the test sequence, and a second ranking of each target storage unit in the run sequence.

In a possible implementation manner, the determining module 13 is specifically configured to:

Acquire at least one test data of each storage unit, wherein the test data includes first test data and second test data;

Acquire data signals corresponding to each storage unit;

Data fault information of the memory is determined according to a data signal corresponding to each storage unit, at least one test data of each storage unit and at least one storage data of each storage unit.

In a possible implementation manner, the determining module 13 is specifically configured to:

If among the data signals corresponding to the storage units, there is a data signal that is a preset signal, determining at least one storage unit corresponding to the preset signal as a first storage unit to be selected;

For any storage unit, if the first test data does not match the first storage data, and/or the second test data does not match the second storage data, the storage unit is determined as a second storage unit to be selected, and at least one second storage unit to be selected is obtained;

The data fault information is determined to include the at least one first storage unit to be selected, the at least one second storage unit to be selected, and at least one test data and at least one storage data corresponding to each second storage unit to be selected.

The fault information determination device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

Fig. 10 is a schematic diagram of the structure of another fault information determination device provided in an embodiment of the present application. Based on the embodiment shown in Fig. 9 , referring to Fig. 10 , the fault information determination device 10 further includes a storage module 14 .

Wherein, the storage module 14 is used for:

Get the preset storage path;

According to the preset storage path, the fault information corresponding to the memory is stored and tested

The fault information determination device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

Fig. 11 is a schematic diagram of the structure of a terminal device provided in an embodiment of the present application. Referring to Fig. 11, the terminal device 20 may include: a memory 21 and a processor 22. Exemplarily, the memory 21 and the processor 22 are interconnected via a bus 23.

The memory 21 is used to store program instructions;

The processor 22 is used to execute the program instructions stored in the memory, so as to enable the terminal device 20 to execute the method shown in the above method embodiment.

The terminal device provided in the embodiment of the present application can execute the technical solution shown in the above method embodiment, and its implementation principle and beneficial effects are similar, which will not be repeated here.

An embodiment of the present application provides a computer-readable storage medium, in which computer-executable instructions are stored. When the computer-executable instructions are executed by a processor, they are used to implement the above method.

The embodiment of the present application may also provide a computer program product, including a computer program, which can implement the above method when executed by a processor.

All or part of the steps of the above-mentioned method embodiments can be completed by hardware related to program instructions. The above-mentioned program can be stored in a readable memory. When the program is executed, the steps of the above-mentioned method embodiments are executed; and the above-mentioned memory (storage medium) includes: read-only memory (ROM), random access memory (RAM) and any combination thereof.

The present application embodiment is described with reference to the flowchart and/or block diagram of the method, device (system) and computer program product according to the present application embodiment. It should be understood that each process and/or box in the flowchart and/or block diagram and the combination of the process and/or box in the flowchart and/or block diagram can be realized by computer program instructions. These computer program instructions can be provided to the processing unit of a general-purpose computer, a special-purpose computer, an embedded processor or other programmable data processing device to produce a machine, so that the instructions executed by the processing unit of the computer or other programmable data processing device produce a device for realizing the function specified in one process or multiple processes in the flowchart and/or one box or multiple boxes in the block diagram.

These computer program instructions may also be stored in a computer-readable memory that can direct a computer or other programmable data processing device to work in a specific manner, so that the instructions stored in the computer-readable memory produce a manufactured product including an instruction device that implements the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

These computer program instructions may also be loaded onto a computer or other programmable data processing device so that a series of operational steps are executed on the computer or other programmable device to produce a computer-implemented process, whereby the instructions executed on the computer or other programmable device provide steps for implementing the functions specified in one or more processes in the flowchart and/or one or more boxes in the block diagram.

Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the embodiments of the present application fall within the scope of the claims of the present application and their equivalents, the present application is also intended to include these modifications and variations.

In the present application, the term "include" and its variations may refer to non-restrictive inclusion; the term "or" and its variations may refer to "and/or". The terms "first", "second", etc. in the present application are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. In the present application, "plurality" refers to two or more. "And/or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and/or B may mean: A exists alone, A and B exist at the same time, and B exists alone. The character "/" generally indicates that the previously associated objects are in an "or" relationship.

Claims (13)

1. A method for determining fault information, comprising: Acquire configuration information of a memory, the configuration information including a first address of the memory and a unit address of each storage unit in the memory; Acquire test information obtained by testing the memory, the test information including at least one storage data corresponding to each storage unit in the memory, an operation order of each storage unit, and a second address of the memory; Fault information existing in a test process of the memory is determined according to the configuration information of the memory and the test information of the memory. 2. The method according to claim 1, characterized in that determining the fault information existing in the test process of the memory according to the configuration information of the memory and the test information of the memory comprises: Determining address fault information existing in a test process of the memory according to a first address of the memory, an operation order of each storage unit in the memory, and a second address of the memory; Determine data fault information and sequence fault information existing in a test process of the memory according to a unit address of each memory unit in the memory, at least one storage data corresponding to each memory unit, and an operation order of each memory unit; The fault information existing in the test process of the memory is determined to include any one or more of the following: the address fault information, the data fault information and the sequence fault information. 3. The method according to claim 2, characterized in that determining address fault information existing in the test process of the memory according to the first address of the memory, the operation order of each storage unit in the memory and the second address of the memory comprises: obtaining a test period of the memory; Determining at least one operation period of each memory according to the operation order of each storage unit in the memory; According to the test period of the memory and at least one operation period of the memory in the memory, address fault information existing in the test process of the memory is determined. 4. The method according to claim 3, characterized in that determining address fault information of the memory existing in the test process of the memory according to the test period of the memory and at least one operation period of the memory in the memory comprises: If there is at least one of the operating time periods that does not match the test time periods, the operating time periods that do not match the test time periods are determined as target time periods; Determining the address fault information includes an identification of the memory, a test period of the memory, and the target period. 5. The method according to any one of claims 2 to 4, characterized in that, according to the unit address of each storage unit in the memory, at least one storage data corresponding to each storage unit and the operation order of each storage unit, determining the data fault information and the sequence fault information existing in the test process of the memory comprises: Determining the sequential fault information according to the unit addresses of the storage units in the memory and the operation order of the storage units; The data fault information is determined according to at least one storage data corresponding to each storage unit. 6. The method according to claim 5, characterized in that determining the sequential fault information according to the unit address of each storage unit in the memory and the operation order of each storage unit comprises: Determining a test order of each unit in the memory according to a unit address of each storage unit in the memory; If the test sequence does not match the running sequence, determining at least one target storage unit in the test sequence that does not match the running sequence; Determining the sequential fault information includes at least one target storage unit, a first ranking of each target storage unit in the test sequence, and a second ranking of each target storage unit in the run sequence. 7. The method according to claim 5, characterized in that the stored data includes first stored data and second stored data; and determining the data fault information according to at least one stored data corresponding to each storage unit comprises: Acquire at least one test data of each storage unit, wherein the test data includes first test data and second test data; Acquire data signals corresponding to each storage unit; Data fault information of the memory is determined according to a data signal corresponding to each storage unit, at least one test data of each storage unit and at least one storage data of each storage unit. 8. The method according to claim 7, characterized in that determining the data fault information of the memory according to the data signal corresponding to each storage unit, at least one test data of each storage unit and at least one storage data of each storage unit comprises: If among the data signals corresponding to the storage units, there is a data signal that is a preset signal, determining at least one storage unit corresponding to the preset signal as a first storage unit to be selected; For any storage unit, if the first test data does not match the first storage data, and/or the second test data does not match the second storage data, the storage unit is determined as a second storage unit to be selected, and at least one second storage unit to be selected is obtained; The data fault information is determined to include the at least one first storage unit to be selected, the at least one second storage unit to be selected, and at least one test data and at least one storage data corresponding to each second storage unit to be selected. 9. The method according to any one of claims 1 to 8, characterized in that the method further comprises: Get the preset storage path; According to the preset storage path, the fault information corresponding to the memory is stored and tested. 10. A device for determining fault information, characterized in that the device comprises: A first acquisition module, used to acquire configuration information of a memory, wherein the configuration information includes a first address of the memory and a unit address of each storage unit in the memory; A second acquisition module, configured to acquire test information obtained by testing the memory, wherein the test information includes at least one storage data corresponding to each storage unit in the memory, an operation order of each storage unit, and a second address of the memory; The determination module is used to determine the fault information existing in the test process of the memory according to the configuration information of the memory and the test information of the memory. 11. A terminal device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein, The memory stores instructions executable by the at least one processor, and the instructions are executed by the at least one processor to enable the at least one processor to perform the method according to any one of claims 1 to 9. 12. A non-transitory computer-readable storage medium storing computer instructions, wherein the computer instructions are used to cause a computer to execute the method according to any one of claims 1 to 9. 13. A computer program product, comprising a computer program, characterized in that when the computer program is executed by a processor, the method according to any one of claims 1 to 9 is implemented.