CN118860273A

CN118860273A - System, method and apparatus for storage device

Info

Publication number: CN118860273A
Application number: CN202410446191.8A
Authority: CN
Inventors: R·皮楚马尼; 奇亮奭; 李宗旺; M·M·阮; 张通
Original assignee: Samsung Electronics Co Ltd
Current assignee: Samsung Electronics Co Ltd
Priority date: 2023-04-28
Filing date: 2024-04-15
Publication date: 2024-10-29

Abstract

An apparatus may include a cache medium, a storage medium, a communication interface configured to communicate with the cache medium and the storage medium, and at least one control circuit configured to configure a portion of the storage medium as visible storage and a portion of the cache medium as a cache for the portion of the storage medium. The portion of the storage medium may be a first portion of the storage medium, and the at least one control circuit may be configured to configure a second portion of the storage medium to reside in the portion of the cache medium. The portion of the storage medium may be a first portion of the storage medium, and the at least one control circuit may be configured to configure the second portion of the storage medium as visible storage.

Description

System, method and apparatus for a device for storage

Citation of related application

The present application claims priority and benefit from U.S. provisional patent application No.63/462,965, filed on 28 at 4 at 2023, which is incorporated herein by reference.

Technical Field

The present disclosure relates generally to devices having memory and storage, and more particularly, to systems, methods, and apparatus for devices having memory and storage configurations.

Background

A storage device (storage device) may include one or more storage media configured to store data received at the storage device. The storage device may communicate with hosts, storage systems, etc. using a storage interface, storage protocol, etc. An application or other user may use read and/or write commands to access a storage medium at a storage device.

The above information disclosed in this background section is only for enhancement of understanding of the background of the invention and therefore it may contain information that does not form the prior art.

Disclosure of Invention

A device may include a cache medium, a storage medium, a communication interface, and at least one control circuit configured to receive a first memory access request to access a portion of the storage medium using the communication interface; receiving a second memory access request to access the portion of the storage medium using the communication interface; accessing the portion of the storage medium based on the first memory access request; and accessing a portion of the cache medium based on the second memory access request. The portion of the cache medium may include a first cache, and the at least one control circuit may be configured to access the portion of the storage medium by reading data from the portion of the storage medium, storing the data in a second cache, and loading at least a portion of the data from the second cache based on the first memory access request. The at least one control circuit may be configured to write at least a portion of the cache medium to the portion of the storage medium. The portion of the storage medium may be a first portion of the storage medium and the at least one control circuit may be configured to receive a storage access request to access a second portion of the storage medium using the communication interface and to access the second portion of the storage medium based on the storage access request. The at least one control circuit may be configured to receive the first memory access request using a first protocol and to receive the memory access request using a second protocol. The at least one control circuit may be configured to operate the portion of the cache medium and the first portion of the storage medium as a first logical device and the second portion of the storage medium as a second logical device. The at least one control circuit may be configured to receive a storage access request to access the portion of the storage medium using the communication interface and to access the portion of the storage medium based on the storage access request. The at least one control circuit may be configured to receive a first memory access request using a first protocol and to receive a memory access request using a second protocol. The first protocol may include a memory access protocol and the second protocol may include a memory access protocol. The at least one control circuit may be configured to perform a consistency (coherency) operation associated with the portion of the storage medium. The portion of the storage medium may be a first portion of the storage medium and the at least one control circuit may be configured to write at least a portion of the cache medium to a second portion of the storage medium. The at least one control circuit may include working logic configured to receive a command and to perform a data movement operation or an operation associated with the portion of the cache medium based on the command.

A device may include a memory medium, a storage medium, a communication interface, and at least one control circuit configured to receive a memory access request to access a portion of the memory medium using the communication interface, access the portion of the memory medium based on the memory access request, and write the portion of the memory medium to the portion of the storage medium. The portion of the storage medium may be a first portion of the storage medium and the at least one control circuit may be configured to receive a storage access request to access a second portion of the storage medium using the communication interface and to access the second portion of the storage medium based on the storage access request. The at least one control circuit may be configured to operate the portion of the memory medium and the first portion of the storage medium as a first logic device and the second portion of the storage medium as a second logic device. The portion of the memory medium may be a first portion of the memory medium and the at least one control circuit may be configured to access a second portion of the memory medium based on the memory access request.

A device may include a medium including a cache medium and a storage medium, a communication interface, and at least one control circuit configured to receive a first memory access request using the communication interface, access a first portion of the medium based on the first memory access request, receive the first memory access request using the communication interface, access a second portion of the medium based on the first memory access request, receive a second memory access request using the communication interface, receive the second memory access request using the communication interface, access a third portion of the medium based on the second memory access request, and access the third portion of the medium based on the second memory access request. The first portion of the medium may comprise a portion of the cache medium, and the at least one control circuit may be configured to write data from the portion of the cache medium to a portion of the storage medium. The at least one control circuit may be configured to map a first portion of the medium to a second portion of the medium. The at least one control circuit may be configured to access a portion of the cache medium based on the first storage access request.

Drawings

The figures are not necessarily to scale and elements of similar structure or function may generally be represented by like reference numerals or parts thereof throughout the figures for illustrative purposes. The drawings are only intended to facilitate the description of the various embodiments described herein. The drawings do not depict every aspect of the teachings disclosed herein and are not intended to limit the scope of the disclosure. In order to prevent the drawing from becoming obscure, not all components, connections, etc. may be shown and not all components have reference numerals. However, the manner in which the components are configured may be clearly apparent from the accompanying drawings. The accompanying drawings illustrate example embodiments of the present disclosure and, together with the description, serve to explain the principles of the disclosure.

Fig. 1 illustrates an embodiment of a device having a memory and a storage medium according to an example embodiment of the present disclosure.

Fig. 2 illustrates another embodiment of a device having memory and storage medium according to an example embodiment of the present disclosure.

Fig. 3 illustrates a first example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure.

Fig. 4 illustrates a second example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure.

Fig. 5 illustrates a third example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure.

Fig. 6 illustrates a fourth example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure.

Fig. 7 illustrates a fifth example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure.

Fig. 8 illustrates a sixth example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure.

Fig. 9 illustrates a seventh example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure.

Fig. 10 illustrates an embodiment of a dual mode memory access scheme according to an example embodiment of the present disclosure.

FIG. 11 illustrates another embodiment of a dual mode memory access scheme according to an example embodiment of the present disclosure.

Fig. 12 illustrates an example embodiment of a host device that may be used to implement host functionality according to example embodiments of the present disclosure.

Fig. 13 illustrates an example embodiment of a storage device that may be used to implement device functionality according to example embodiments of the present disclosure.

Fig. 14 shows a first example embodiment of a device configuration scheme according to an example embodiment of the present disclosure.

Fig. 15 illustrates a second example embodiment of a device configuration scheme according to an example embodiment of the present disclosure.

Fig. 16 illustrates an example embodiment of a device configuration scheme with hot plug (hot plug) functionality according to an example embodiment of the present disclosure.

Fig. 17 illustrates an example embodiment of a device configuration scheme with hot-unplug (hot unplug) functionality, according to an example embodiment of the present disclosure.

Fig. 18 illustrates an example embodiment of a hot extraction method for a device according to an example embodiment of the present disclosure.

Detailed Description

Computing systems may include memory media that may have relatively short access times but relatively high cost and/or low capacity compared to storage media. To provide extended memory capacity at a relatively low cost, the operating system may implement memory using a storage medium. For example, an operating system may implement memory mapped files, which may be located on a storage device, but may appear as memory to applications or other users. However, depending on implementation details, memory mapped files may have relatively long access times and/or may involve operating system overhead.

A storage device according to example embodiments of the present disclosure may include a storage medium that may be accessed as a memory. The storage device may also include a memory medium, which may be configured as a cache for the storage medium. In some embodiments, at least a portion of the storage medium may be configured to appear as volatile memory. Thus, depending on implementation details, some embodiments may present a relatively large storage medium as a volatile memory space that may be mapped, for example, to system memory. Furthermore, a memory medium that may be configured as a cache for a storage medium may reduce access time (e.g., latency) of volatile memory space.

In some embodiments, at least a portion of the storage medium may be configured to appear as persistent memory. Thus, depending on implementation details, some embodiments may present a relatively large storage medium as persistent memory space. Further, a memory medium, which may be configured as a cache, may be persisted (e.g., written to) to, for example, a storage medium (e.g., based on a power down event). Depending on implementation details, a memory medium that may be configured as a cache may reduce access time (e.g., latency) of persistent memory space.

In some embodiments, at least a portion of the storage medium may be configured to appear as memory or storage. For example, a storage device may implement a first access method in which at least a portion of a storage medium may be accessed as storage space. The storage device may also implement a second access method in which a portion (e.g., the same portion) of the storage medium may be accessed as a memory space. The storage device may also include a memory medium, which may be configured as a cache for the storage medium. The storage medium, if accessed as a memory space, may be configured to appear as volatile and/or persistent memory. In some embodiments, a memory medium, which may be configured as a cache, may be persisted (e.g., based on a power down event) to, for example, a storage medium. Depending on implementation details, embodiments in which the first access method and the second access method may be implemented (which may be referred to as multi-mode or dual-mode operation) may enable a user to create, manage, use any storage device as a configuration of memory (store-as-memory configuration).

Alternatively or additionally, a storage device according to example embodiments of the present disclosure may include a memory medium (e.g., a volatile memory medium) that may be configured to appear as persistent memory. In some embodiments, the memory medium may be persisted (e.g., based on a power down event) to a storage medium in, for example, a storage device. Thus, depending on implementation details, some embodiments may present a relatively large amount of volatile memory as persistent memory space.

In some embodiments, a storage device may implement multiple memories and/or storage spaces (e.g., memory space and storage space) in the same device. In some embodiments, different spaces may be implemented as different logic devices. In a first example embodiment, a first portion of the storage medium may be configured to appear as volatile memory in a first logic device. Also in the first example embodiment, the second portion of the storage medium may be configured to appear as storage space in the second logical device. In a second example embodiment, a first portion of the storage medium may be configured to appear as persistent memory in the first logical device. Also in the second example embodiment, the second portion of the storage medium may be configured to appear as storage space in the second logic device.

In some embodiments, the storage device may enable a user to configure the memory medium and/or storage medium to implement any configuration described herein and/or other configurations. Such embodiments may be referred to as combinable (composable) devices and/or may be characterized as having combinable memory, storage, and/or storage as memory. In some embodiments, combinable may refer to aspects of a device, a memory medium, a storage medium, a controller, etc., capable of being configured, for example, by a user. For example, the storage device may enable a user to configure one or more portions of the storage medium as memory space (e.g., volatile and/or persistent), storage space, or a combination thereof. As another example, a storage device may enable a user to configure one or more portions of a memory medium as a cache for the storage medium, as volatile and/or persistent memory space, etc., or a combination thereof. As yet another example, a storage device may enable a user to configure one or more portions of a storage medium to be accessed as a memory space or storage space, for example, using different access methods.

In some embodiments, the storage device may implement one or more commands for cache operations (e.g., prefetch, invalidate, write back, etc.), data movement (e.g., move data between host system memory and memory space in the storage device), etc. Depending on implementation details, one or more commands implemented by the storage device may offload (offload) one or more operations (e.g., memory transfer) operations) from the host or other user.

The present disclosure encompasses numerous aspects related to an apparatus having a memory and storage configuration. The aspects disclosed herein may have independent utility and may be embodied separately, and not every embodiment may utilize every aspect. In addition, these aspects may also be embodied in various combinations, some of which may synergistically amplify some of the benefits of the various aspects.

For purposes of explanation, some embodiments may be described in the context of some specific implementation details, such as devices implemented as storage devices that may use specific interfaces, protocols, and the like. However, aspects of the disclosure are not limited to these or any other implementation details.

Fig. 1 illustrates an embodiment of a device having a memory and a storage medium according to an example embodiment of the present disclosure. The device 100 shown in fig. 1 may include a memory medium 102, a storage medium 104, one or more communication interfaces 106, and/or control logic 108. The communication interface 106 may be configured to enable a user to access the memory medium 102 (as indicated by arrow 103) and/or the storage medium 104 (as indicated by arrow 107).

A portion (e.g., some or all) of the storage medium 104 may be configured to appear as memory, e.g., visible to (e.g., accessible by) a user through the communication interface 106. A portion of the memory medium 102 may be configured as a cache 110 for a portion of the storage medium 104.

Control logic 108 may implement, facilitate, control, etc., one or more schemes for configuration, operation, etc., of one or more components of device 100. Control logic 108 may include various types of logic such as cache logic 112, access control logic 114, persistence logic 116, configuration logic 118, and the like. Not every embodiment of control logic 108 may include every type of logic, and some embodiments may include additional types of logic not shown in FIG. 1. Any or all of the control logic 108 may be implemented as a single component (e.g., with a single processor), or may be implemented with separate components, operations, etc., e.g., using separate processors, logic circuits, etc.

In some embodiments, control logic 108 may include cache logic 112, which may configure and/or control the operation of cache portion 110 of memory medium 102. Examples of cache control operations may include implementing one or more cache maps, data write policies (e.g., write through, write back, etc.), cache replacement policies, and so forth.

In some embodiments, a cache may be used to improve one or more aspects (e.g., latency, power, etc.) of accessing data in the underlying medium. For example, the cache logic 112 may configure the cache portion 110 of the memory medium 102 to operate as a cache for a portion of the storage medium 104. In such a configuration, the control logic 108 may receive a storage access request to write user data in the portion of the storage medium 104. However, the cache logic 112 may store copies of the user data in the cache portion 110 of the memory medium 102 based on the storage access request (e.g., write request). In some embodiments, the cache logic 112 may also proceed (e.g., without delay) to write user data to the portion of the storage medium 104 (as indicated by arrow 107), for example, if the cache logic 112 implements a write-through policy, or the cache logic 112 may wait until the user data is evicted from the cache portion 110 of the storage medium 102 to write the user data to the portion of the storage medium 104 (as indicated by arrow 105), for example, if the cache logic 112 implements a write-back policy. In some embodiments, the cache logic 112 may implement a cache policy (e.g., a prediction policy, an eviction policy, etc.), wherein the cache logic 112 may copy user data from the storage medium 104 to the cache portion 110 of the memory medium 102 when the user data is expected to be accessed by a user. Depending on implementation details, the cache logic 112 may evict other user data from the cache portion 110 of the memory medium 102 to make room for user data copied from the storage medium 104.

When control logic 108 receives a storage access request to read user data from a portion of storage medium 104, cache logic 112 may service the storage access request (e.g., a read request) by loading user data from cache portion 110 of memory medium 102 (as indicated by arrow 103) instead of reading user data from that portion of storage medium 104. In some embodiments, the cache portion 110 of the memory medium 102 may be implemented with the memory medium 102 that may have a lower access latency than the portion of the storage medium 104. Thus, depending on implementation details, the use of caches may reduce latency associated with accessing data from the underlying media. Additionally or alternatively, the use of caches may reduce the amount of power consumption associated with performing access operations to access data (e.g., page reads) from the underlying medium, as the data may already be available in the cache portion 110 of the memory medium 102.

In some embodiments, the control logic 108 may include access control logic 114 that may configure and/or control the operation of the memory medium 102 and/or the storage medium 104 (or one or more portions thereof) to be visible or invisible to a user; may be accessed as a memory, as a storage device, or a combination thereof, etc. For example, in some embodiments, the access control logic 114 may operate to cause a portion of the storage medium 104 (which may have a local block-based interface scheme) to appear as visible memory (e.g., volatile memory and/or persistent memory). For example, if device 100 receives a load command to access bytes of data stored in storage medium 104 (e.g., using a memory access protocol via communication interface 106), and the requested data is not stored in cache 110, access control logic 114 may read from storage medium 104 the page in which the requested bytes may be located. The access control logic 114 may obtain the requested byte from the page in response to the load command and return the requested byte (e.g., again using a memory access protocol through the communication interface 106). In some embodiments, the memory access interface and/or protocol may access data in cache line (e.g., 64 bytes) units, and thus, the access control logic 114 may return the cache line of requested data from the page read from the storage medium 104.

As another example, the access control logic 114 may configure and/or control operation of the memory medium 102 to be accessible as visible memory (e.g., using a memory access protocol through the communication interface 106). In some embodiments, the access control logic 114 may implement a dual mode access scheme in which a portion of the storage medium 104 may be accessed as memory or storage.

In some embodiments, the control logic 108 may include persistence logic 116 that may configure and/or control operation of a portion of the memory medium 102 to be persisted (e.g., copied to non-volatile memory) to, for example, the storage medium 104 (e.g., based on a power loss event). For example, in embodiments of the invisible cache 110 in which a portion of the memory medium 102 may be configured as a portion of the storage medium 104 that may be configured as visible persistent memory, the persistence logic 116 may flush (e.g., copy) the contents of the cache 110 to the storage medium 104 in response to a power down event. Example embodiments of persistent memory space that may be implemented with an invisible cache in a memory medium for a visible memory space in the memory medium are described below with respect to fig. 4 and 5.

In some embodiments, control logic 108 may include configuration logic 118, which may enable a user to configure one or more of the components, operations, etc. of device 100. For example, configuration logic 118 may receive commands, instructions, etc. from a user (e.g., via communication interface 106) that may enable the user to specify the size of cache 110, whether cache 110 operates as volatile memory and/or persistent memory, how much of storage medium 104 may be accessible as storage, how much of storage medium 104 may be used to persist (e.g., store in a non-volatile medium) some or all of cache 110, and so forth.

In some embodiments, while all or a portion of the medium may be referred to as being configured as cached, configured to be visible, configured to be invisible, etc., in some implementations, the one or more controllers may actually be configured to use the medium in a manner that may cause the medium to appear as cached, appear visible, appear invisible, etc. Thus, in some embodiments, reference to a medium configured in a manner may refer to an arrangement in which a controller (e.g., control logic) may be configured to cause the medium to operate as if configured in that manner. For example, in an embodiment in which a portion of the storage medium 104 may be configured as a visible memory accessible to a user (e.g., in units of 64 byte cache lines using a memory access protocol through the communication interface 106), the user may not directly access the portion of the storage medium 104. Instead, the control logic 108 may act as an intermediary (e.g., in units of pages and/or blocks, using an underlying page and/or block-based interface, e.g., using a flash translation layer (FLT) in a Solid State Drive (SSD)) to access the portion of the storage medium 104 on behalf of the user. In such a configuration, control logic 108, cache logic 112, access control logic 114, persistence logic 116, configuration logic 118, and the like may convert one or more access requests of a first type to one or more access requests of a second type. For example, memory load and/or store requests that may be used to access a storage medium may be translated into and/or from memory read and/or write requests that may be used to access a storage medium.

Further, in such a configuration, one or more underlying caches (e.g., hidden caches other than the medium configured to appear as a visible cache to the user) may be used to implement the one or more translations. For example, in a configuration in which a portion of the storage medium 104 may be configured as visible memory, the control logic 108 may receive a memory access request from a user from a cache line (e.g., a 64-bit cache line) of the portion of the storage medium 104 configured as visible memory that loads data. However, the storage medium can be accessed only in units of 4 kbyte pages. Thus, to execute a memory access request, control logic 108 may convert the memory access request to a storage read request that may read a page containing the requested cache line from storage medium 104 and store it in a cache that may be hidden from the user. Control logic 108 may then load the cache line of the requested data from the hidden cache in response to the memory access request and return it to the user.

The embodiment shown in fig. 1 may be used, for example, to implement a device having a memory medium and/or storage medium of various configurations, which may be referred to as modes of operation. Depending on implementation details, some embodiments may present a relatively large storage medium as volatile memory space, persistent memory space, storage space, or a combination thereof.

Arrows 103, 105, and/or 107 shown in fig. 1 may illustrate a data flow, which may illustrate an end-to-end data flow, depending on implementation details, and may not illustrate one or more intermediate components through which data may flow, such as a memory device interface, a storage device interface, a conversion apparatus (e.g., flash Translation Layer (FTL)), a buffer, a controller, etc., for simplicity of the drawing. For example, in some embodiments, data that may be transferred between the communication interface 106 and the storage medium 104 (e.g., using a non-volatile memory express (NVMe) protocol) as indicated by arrow 107 may be passed through a storage protocol controller in the control logic 108 (e.g., an NVMe controller as shown in fig. 7-9). As another example, data that may be transferred between the communication interface 106 and the memory medium 102 (e.g., using the CXL protocol) as indicated by arrow 103 may be passed through a memory protocol controller in the control logic 108 (e.g., a CXL interface controller as shown in fig. 5-9). As another example, data that may be transferred between the memory medium 102 and the storage medium 104, as indicated by arrow 105, may be passed through a memory protocol controller (e.g., a CXL interface controller) and/or a storage protocol controller (e.g., an NVMe controller) in the control logic 108.

Fig. 2 illustrates another embodiment of a device having memory and storage medium according to an example embodiment of the present disclosure. The device 200 shown in fig. 2 may include one or more elements similar to the embodiment shown in fig. 1, where similar elements may be indicated by and/or include reference numerals ending in the same number, letter, etc.

Referring to fig. 2, device 200 may include a memory medium 202, a storage medium 204, a communication interface 206, and/or control logic 208 that may operate in a manner similar to corresponding components in fig. 1. However, in the embodiment illustrated in FIG. 2, access control logic 214 may configure and/or control memory medium 202 as persistent memory that appears to be visible to (e.g., accessible by) a user through communication interface 206. The persistence logic 216 can configure and/or control the memory medium 202 (e.g., based on a power loss event) to be persisted to, for example, the storage medium 204. In some embodiments, access control logic 214 may implement substantially the entire visible persistent memory space, wherein a portion of memory medium 202 may be reserved to storage medium 204. Depending on implementation details, this may result in a relatively high performance (e.g., low latency) persistent memory space, because, for example, substantially all access requests to the persistent memory space may be serviced by the memory medium 202 without involving access to the storage medium 204. Example embodiments of persistent memory space that may be implemented with visible memory space in a memory medium and invisible persistent space in a storage medium are described below with respect to fig. 6 and 7.

The embodiment shown in fig. 2 may be used, for example, to implement a device having a memory medium and/or storage medium of various configurations, which may be referred to as modes of operation.

Arrows 203 and/or 205 shown in fig. 2 may illustrate a data flow, which may illustrate an end-to-end data flow, depending on implementation details, and may not illustrate one or more intermediate components through which data may flow, such as a memory device interface, a storage device interface, a conversion apparatus (e.g., a Flash Translation Layer (FTL)), a buffer, a controller, etc., for simplicity of the drawing. For example, in some embodiments, data that may be transferred between the communication interface 206 and the memory medium 202 (e.g., using the CXL protocol) as indicated by arrow 203 may pass through a memory protocol controller (e.g., a CXL interface controller) in the control logic 208. As another example, data that may be transferred between the memory medium 202 and the storage medium 204, as indicated by arrow 205, may be passed through a memory protocol controller (e.g., a CXL interface controller) and/or a storage protocol controller (e.g., an NVMe controller) in the control logic 208.

In some embodiments, the memory medium may be implemented with volatile memory media such as Dynamic Random Access Memory (DRAM), static Random Access Memory (SRAM), etc., while the storage medium may be implemented with nonvolatile memory media such as magnetic media, solid state nonvolatile memory media (e.g., flash memory that may include non-AND (NAND) flash memory AND NOR flash memory, cross-grid nonvolatile memory, memory with bulk resistance change, phase Change Memory (PCM), etc.), optical media, etc.

In some embodiments, the memory medium may be addressable in relatively small units (such as bytes, words, cache lines, etc.), while the storage medium may be addressable in relatively large units (such as pages, blocks, sectors, etc.).

In some embodiments, the memory medium may be accessed by software using load and/or store instructions, and the storage medium may be accessed by software using read and/or write instructions.

In some embodiments, the memory medium may be accessed using a memory interface and/or protocol such as Double Data Rate (DDR) (e.g., DDR4, DDR5, etc.), direct Memory Access (DMA), remote DMA (RDMA), open Memory Interface (OMI), computing fast link (CXL), gen-Z, etc., while the storage medium may be accessed using a storage interface and/or protocol such as serial ATA (SATA), small Computer System Interface (SCSI), serial Attached SCSI (SAS), nonvolatile memory express (NVMe), NVMe over fabrics (NVMe-oF), etc. In some embodiments, the memory interface and/or protocol may access data in relatively small units (such as bytes, words, cache lines, etc.), while the memory interface and/or protocol may access data in relatively large units (such as pages, blocks, sectors, etc.).

Any of the devices 100 and/or 200, as well as any other device disclosed herein, may be implemented in any form, such as a storage device, accelerator, network interface card and/or Network Interface Controller (NIC), etc., having any physical form factor including one or more form factors for a storage device, such as a peripheral component interconnect express (PCIe) add-in card, 3.5 inch drive, 2.5 inch drive, 1.8 inch drive, m.2 drive, U.2 and/or U.3 drive, any of the enterprise and data center SSD form factors (EDSFF) drive, SFF-TA-100X form factor (e.g., SFF-TA-1002), NF1, etc., using any connector configuration such as SATA, SCSI, SAS, m.2, U.2, U.3, etc. In some embodiments, the device may be implemented in any other form, for example, as a collection of one or more components on a circuit board (e.g., integrated into a server motherboard, backplane, midplane, etc.).

While some embodiments may be described in the context of a cache medium that may be implemented in a memory medium, such as DRAM, in other embodiments, other types of media (e.g., storage media) may be used for the cache medium. For example, in some embodiments, some or all of caches 110 and/or 210 may be implemented with a medium other than a memory medium, which may have one or more relative characteristics (e.g., with respect to storage medium 104 and/or 204) that may make one or both of them more suitable for their respective functions. For example, in some embodiments, storage media 104 and/or 204 may be implemented with magnetic media, which may have a relatively high capacity, lower cost, etc., while some or all of caches 110 and/or 210 may be implemented with NAND flash memory, which may have a relatively low access latency, which may make it relatively more suitable for use as a cache.

Any of the devices 100 and/or 200, as well as any other devices disclosed herein, may be used in conjunction with one or more personal computers, smart phones, tablet computers, servers, server enclosures, server racks, data rooms, data centers, edge data centers, mobile edge data centers, and/or any combination thereof.

Any of the communication interfaces 106 and/or 206, as well as any other communication interfaces disclosed herein, may be implemented with any interconnect interface and/or protocol, such as PCIe, NVMe, NVMe key-value (NVMe-KV), SATA, SAS, SCSI, computing fast link (CXL) and/or one or more CXL protocols, such as cxl.mem, cxl.cache, and/or cxl.io, gen-Z, consistent Accelerator Processor Interface (CAPI), cache consistent interconnect for accelerators (CCIX), etc., or any combination thereof. Alternatively or additionally, any of the communication interfaces 106 and/or 206, as well as any other communication interfaces disclosed herein, may be implemented with any network interface and/or protocol, such as ethernet, transmission control protocol/internet protocol (TCP/IP), remote Direct Memory Access (RDMA), RDMA over converged ethernet (RDMA over Converged Ethernet, roCE), fibre channel, infiniband (IB), iWARP, NVMe-over-fabrics (NVMeoF), or the like, or any combination thereof.

Fig. 3 illustrates a first example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure. The embodiment shown in fig. 3 may be used to implement an apparatus such as that shown in fig. 1 and/or may be implemented with an apparatus such as that shown in fig. 1, wherein like elements may be referred to by reference numerals ending in and/or containing the same numerals, letters, etc.

Referring to fig. 3, device 300 may include a memory medium 302, in this example, memory medium 302 may be implemented with DRAM, but in other embodiments memory medium 302 may be implemented with other types of memory media (e.g., volatile media that may have a relatively high access speed (e.g., relatively low latency)). The device 300 may also include a storage medium 304, in this example, the storage medium 304 may be implemented with NAND flash memory, but in other embodiments the storage medium 304 may be implemented with other types of storage media (e.g., non-volatile media, which may have relatively high capacity and/or relatively low cost).

Device 300 may also include a communication interface 306, in which example communication interface 306 may implement one or more CXL protocols, but in other embodiments communication interface 306 may implement or be implemented with any other interface, protocol, etc. (e.g., DDR, OMI, gen-Z, DMA, RDMA, etc.) that may enable a user to access data, such as in memory. The CXL (or other) protocol can operate with any underlying transport scheme (e.g., physical layer, transport layer, etc.), including, for example, PCIe, ethernet, infiniband, etc.

The device 300 may also include cache and/or prefetch logic 312 that may configure and/or control the operation of the cache portion 310 of the memory medium 302. Examples of cache control operations may include implementing one or more cache maps, data write policies (e.g., write through, write back, etc.), cache replacement policies, and so forth.

Device 300 may also include access control logic 314, which may be implemented at least in part with memory protocol controller 320, in which embodiment memory protocol controller 320 may implement CXL (e.g., as a CXL interface controller), but in other embodiments memory protocol controller 320 may be implemented with any other type of protocol controller that may enable a user to access data, such as in memory. The access control logic 314 may include a memory controller 324324, in which example, the memory controller 324 may be implemented with a DRAM controller that may control the DRAM that may be used to implement the memory medium 302. The access control logic 314 may also include a memory controller 326, in which example, the memory controller 326 may be implemented with a Flash Translation Layer (FTL) and/or a NAND controller (e.g., a NAND channel controller) that may control NAND flash memory that may be used to implement the storage medium 304. Examples of operations that may be implemented by access control logic 314 may include any of the memory and/or storage medium access schemes disclosed herein, including those described and illustrated with respect to fig. 1-11.

In some embodiments, device 300 may also include configuration logic 318, which may enable a user to configure one or more of the components and/or operations shown in fig. 3, e.g., based on configuration information 319. In embodiments where the communication interface 306 may implement CXL, the configuration information 319 may be received from the user, for example, using the cxl.io protocol. Examples of configuration information 319 may include an amount, type, etc. of configuration logic 318 may be used to configure memory medium 302, storage medium 304, invisible cache space 310, visible memory space 304A and/or invisible endurance space 304B, one or more cache policies, etc. of the medium and/or space shown in fig. 3.

In some embodiments, device 300 may also include a device translation look-aside buffer (TLB) 328 that may cache address translations, e.g., to enable device 300 to support Shared Virtual Memory (SVM) by processing data from an application address space (e.g., directly).

In some embodiments, device 300 may also include work logic 330 that may enable device 300 to perform one or more operations related to data movement, cache management, memory management, storage management, and the like. Examples of operations that may be implemented by the work logic 330 may include Artificial Intelligence (AI) and/or Machine Learning (ML) training, reasoning, classification, generation, and so forth. The work logic 330 may include a work accepting unit 332 (which may also be referred to as a work submitting unit), one or more work schedulers 334, and/or one or more work executing units 336. Work acceptance unit 332 may include one or more work queues 333 (which may also be referred to as commit queues) that may accept commands to invoke any operations implemented by work logic 330. The work execution unit may perform any operations implemented by the work logic 330 based on the commands received at the work accepting unit 332. Work scheduler 334 may obtain an entry from work queue 333 and pass the entry to work execution unit 336 for execution. Work scheduler 334 may determine the order of execution of commands based on various factors such as availability, capacity, capabilities, etc. of one or more work execution units 336, type of commands and/or operations, one or more priorities, privileges, etc.

Examples of commands and/or operations related to data movement may include moving data to and/or from visible (which may also be referred to as being exposed to and/or accessible by a user) memory, storage, etc., moving data from visible (which may also be referred to as being exposed to and/or accessible by a user) memory, storage, etc. (e.g., moving data between visible memory space in host system memory and storage devices), prefetching data from storage medium 304 to cache 310, etc. In some embodiments, work execution unit 336 may perform data transfer operations using, for example DMA, RDMA, roCE or the like.

Examples of commands and/or operations related to cache management may include prefetching data and/or invalidating data for use in writing back data (e.g., to storage medium 304) and/or discarding portions of data in cache 310. Examples of commands and/or operations related to storage management may include invalidating data, e.g., to inform storage controller 326 that data in storage medium 304 may be invalid and thus may be deleted from storage medium 304 and/or garbage collected.

In some embodiments, one or more commands and/or operations implemented by work logic 330 may be offloaded from a host and/or other user. Thus, depending on implementation details, the work logic 330 may provide a relatively efficient and/or low overhead scheme for moving data in user mode, kernel mode, and the like.

Alternatively or additionally, some embodiments may implement one or more commands and/or operations similar to the work logic 330 using, for example, a relatively simple mechanism, such as implementing the commands using one or more cxl.io mechanisms (e.g., vendor-defined cxl.io mechanisms).

Any or all of access logic 314, cache and/or prefetch logic 312, configuration logic 318, working logic 330, translation look aside buffer 328, etc. may be characterized and/or referred to collectively and/or individually as control logic.

In the embodiment shown in fig. 3, a portion of the storage medium 304 may be configured as a visible memory space 304A that may be exposed to a user as memory space 303 (e.g., a volatile memory space). A portion of the memory medium 302 may be configured as a (to the user) invisible cache space 310 for the visible memory space 304A. The cache space 310 may be used, for example, to reduce access time for frequently used data (which may be placed in the cache space 310 by the cache and/or prefetch logic 312) and/or data that may be prefetched into the cache space 310 (e.g., by the cache and/or prefetch logic 312, for example, based on receiving a prefetch work command 335 from a user).

A user may access memory space 303 using one or more memory load and/or store (load/store) instructions 307, which instructions 307 may be sent to access logic 314 over communication interface 306 using, for example, the cxl.mem protocol. If the data to be accessed is located in the cache space 310 for a load instruction or a store instruction (e.g., a cache hit), the cache and/or prefetch logic 312 may load the data from the cache space 310 or store the data to the cache space 310 using the memory controller 324.

For example, if the access is a store and a previous version of the data at the specified memory address already exists in cache space 310 (e.g., a cache hit), then cache and/or prefetch logic 312 may store a new version of the data in invisible cache space 310 and/or visible memory space 304A depending on the cache replacement and/or eviction policy. For example, if the cache and/or prefetch logic 312 implements a Least Recently Used (LRU) eviction policy, the cache and/or prefetch logic 312 may store new data in the cache space 310 (e.g., because the most recently used data may be accessed again soon). The cache and/or prefetch logic 312 may also store a copy of the new data in the visible memory space 304A in the storage medium 304 without delay if the cache and/or prefetch logic 312 implements a write-through policy, or may store a copy of the new data in the visible memory space 304A in the storage medium 304 at a later time (e.g., when the new data is later evicted) if the cache and/or prefetch logic 312 implements a write-back policy (e.g., opportunistic write-back). However, if the cache and/or prefetch logic 312 implements a Most Recently Used (MRU) eviction policy, the cache and/or prefetch logic 312 may not store new data in the cache space 310 in the memory medium 302 (e.g., because the most recently used data may be unlikely to be accessed again in a relatively long period of time). Instead, the cache and/or prefetch logic 312 may store new data in the visible memory space 304A in the storage medium 304.

As another example, if the access is a load and the previous version of the data at the specified memory address already exists in the cache space 310 (e.g., a cache hit), the cache and/or prefetch logic 312 may load the requested data from the cache space 310.

However, if the accessed data is not located in the cache space 310 (e.g., a cache miss), the access logic 314 may use the memory controller 326 to read data from the visible memory space 304A or write data to the visible memory space 304A. Depending on implementation details, access logic 314 and/or memory controller 326 may access pages, blocks, sectors, etc. containing the requested data from visible memory space 304A and extract or insert the requested data, which may be bytes, words, cache lines, etc. If the access is a store, the access logic 314 and/or the memory controller 326 may write back the modified page, block, sector, etc. to the visible memory space 304A. Copies of the accessed data may also be stored in cache space 310 depending on the cache replacement policy implemented by cache and/or prefetch logic 312. If the access is a load, the access logic 314 and/or the memory controller 326 may return (e.g., send to the user sending the request) the requested data, which may be bytes, words, cache lines, etc. In some embodiments, access logic 314 and/or storage controller 326 may store (e.g., temporarily) a page, block, sector, etc. containing the requested data in the second cache after reading it from visible memory space 304A in storage medium 304. The access logic 314 and/or the memory controller 326 may then retrieve the requested data from the second cache. The second cache may be implemented, for example, as part of the invisible cache space 310, within the access logic 314, and so on.

In some embodiments, a portion of the storage medium 304 may be configured as an invisible endurance space (e.g., reserved (overprovisioning, OP) space) 304B (to a user), e.g., to enhance endurance of the portion of the storage medium 304 implemented as the visible memory space 304A. In some embodiments, the invisible endurance space 304B may be implemented with a relatively large number of storage media to compensate for the relatively large number of write cycles (cycles) that may be encountered by the visible memory space 304A exposed to memory.

Depending on implementation details, the embodiment shown in fig. 3 may expose a relatively large amount of storage medium 304 as volatile memory space 303 at a relatively low cost. Furthermore, the portion of memory medium 302 configured as cache space 310 may reduce the access time (e.g., latency) of memory space 303.

The memory and/or storage space shown in fig. 3 is not limited to any particular size. However, for purposes of illustrating some aspects of the present disclosure, in one example embodiment, visible memory space 304A and invisible durable space 304B may each be implemented with a 1TB storage medium, memory space 303 may be implemented as a 1TB memory space, and invisible cache space 310 may be implemented as a 16GB cache space.

Depending on implementation details, memory space 303 may be suitable to be mapped as system memory (e.g., general purpose memory that may be allocated using an operating system (e.g., linux) memory allocation command such as malloc).

Depending on implementation details, a user, such as an application, may use the memory space 303 implemented in the embodiment shown in FIG. 3 without any knowledge of the underlying configuration of the memory medium 302 and/or the storage medium 304 and/or without the ability to manipulate the underlying configuration of the memory medium 302 and/or the storage medium 304. For example, the host may run an operating system, virtual machine manager, or the like, which may configure memory space 303 and allocate memory from memory space 303 to applications, virtual machines, or the like running on the host. Applications, virtual machines, etc. may use the allocated memory from memory space 303 without knowing that the allocated memory may be implemented with storage medium 304 and/or cache space 310 in storage medium 302.

In some embodiments, a user (e.g., host, application, process, service, operating system, additional device, etc.) that is aware of the underlying configuration of memory medium 302 and/or storage medium 304 and/or is able to manipulate the underlying configuration of memory medium 302 and/or storage medium 304 may use one or more functions to enhance performance, durability, etc. of the device shown in FIG. 3. For example, if a user is to access data currently stored in the visible memory space 304 of the storage medium 304 and a copy of the data is not stored in the cache space 310, the user may send a prefetch request to the cache and/or prefetch logic 312 (e.g., by submitting a work command 335 to the work accepting unit 332) to cause the cache and/or prefetch logic 312 to store the copy of the data in the cache space 310.

As another example, if the user is no longer to access data currently in cache space 310, the user may send a cache invalidation request to cache and/or prefetch logic 312 (e.g., by submitting work command 335 to work accepting unit 332) to invalidate the data in the corresponding locations in cache space 310 and/or visible memory space 304 by cache and/or prefetch logic 312. Depending on implementation details, this may enable the storage controller 326 to garbage collect data in the storage medium 304.

As another example, if the user is to use data currently stored in system memory at the host, the user may send a data transfer request to transfer data from system memory to memory space 303 (e.g., by submitting work command 335 to work accepting unit 332). The work scheduler 334 may schedule data transfer requests to be performed, for example, by a work execution unit, which may transfer data, for example, using RDMA operations.

In some embodiments, one or more functions for enhancing performance, durability, etc. (e.g., prefetch commands, data transfer requests, cache invalidate commands, etc.) may be used by middleware at the host or other user.

Fig. 4 illustrates a second example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure. The embodiment shown in fig. 4 may be used to implement an apparatus such as that shown in fig. 1 and/or may be implemented with an apparatus such as that shown in fig. 1, wherein like elements may be referred to by reference numerals ending in and/or containing the same numerals, letters, etc. The apparatus 400 shown in fig. 4 may include one or more elements similar to the embodiment shown in fig. 3, where similar elements may be indicated by and/or include reference numerals ending in the same number, letter, etc.

In some aspects, the configuration and/or operation of the device 400 shown in fig. 4 may be similar to the configuration and/or operation of the device 300 shown in fig. 3. However, in the embodiment shown in FIG. 4, at least a portion of memory space 403 that is exposed to the user may be implemented as a persistent memory space. Persistent memory space 403 may be implemented with a visible memory space 404A in storage medium 404, which visible memory space 404A may be inherently persistent.

Persistent memory space 403 may also be implemented with an invisible cache space 410 within memory medium 402, which invisible cache space 410 may be configured as a cache for visible memory space 404A in storage medium 404. To provide persistence to the invisible cache space 410, the device 400 may configure a portion of the storage medium 404 as the invisible persistent space 404C. Device 400 may also include persistent logic 416 and/or a persistent power supply 417. In response to a power down event, persistence logic 416 can perform a data transfer operation to flush the contents of invisible cache space 410 to invisible persistent space 404C. Persistent power supply 417 may be configured to provide power to one or more portions of persistent logic 416, memory medium 402, storage medium 404, and/or any other component that may be involved in flushing data from invisible cache space 410 to invisible persistent space 404C.

In some embodiments, the persistent power supply 417 may be implemented with one or more capacitors (e.g., supercapacitors), internal and/or external batteries, and the like. In some embodiments, persistence logic 416 can be implemented with or as a global persistence flush (Global Persistency Flush, GPF) unit, e.g., as part of a CXL.

Any or all of access logic 414, cache and/or prefetch logic 412, configuration logic 418, work logic 430, translation look aside buffer 428, persistence logic 416, and the like may be characterized and/or referred to collectively and/or individually as control logic.

Depending on implementation details, the embodiment shown in FIG. 4 may expose a relatively large amount of storage medium 404 as persistent memory space 403 at a relatively low cost. Furthermore, the portion of the memory medium 402 configured as the cache space 410 may reduce access time (e.g., latency) of the persistent memory space 403. As with the embodiment shown in fig. 3, access logic 414 in device 400 may enable a user to access visible memory space 404A in storage medium 404 as memory, for example, using cxl.mem through communication interface 406.

In some embodiments, persistent memory space 403 may be implemented as private memory (which may also be referred to as protected memory or restricted memory). For example, if device 400 is accessed using an operating system such as Linux, some or all of persistent memory space 403 may be mapped as private memory that, depending on implementation details, may prevent it from being allocated as system (e.g., general purpose) memory using a memory allocation command such as malloc.

The memory and/or storage space shown in fig. 4 is not limited to any particular size. However, for purposes of illustrating some aspects of the present disclosure, in one example embodiment, visible memory space 404A may be implemented with a 1TB storage medium, persistent memory space 403 may be implemented as a 1TB memory space, invisible durable space 404B may be implemented with a 894GB storage medium, and invisible cache space 410 may be implemented with a 16GB storage medium 402.

Fig. 5 illustrates a third example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure. The embodiment shown in fig. 5 may be used to implement an apparatus such as that shown in fig. 1 and/or may be implemented with an apparatus such as that shown in fig. 1, wherein like elements may be referred to by reference numerals ending in and/or containing the same numerals, letters, etc. The apparatus 500 shown in fig. 5 may include one or more elements similar to the embodiments shown in fig. 3 and/or 4, where similar elements may be indicated by and/or include reference numerals ending in the same number, letter, etc.

In some aspects, the configuration and/or operation of the device 500 shown in fig. 5 may be similar to the configuration and/or operation of the device 400 shown in fig. 4. However, in the embodiment shown in FIG. 5, a first portion of the storage medium 504 may be configured as the visible memory space 504A and a second portion of the storage medium 504 may be configured as the visible memory space 504B. Thus, portions of storage medium 504 may be exposed as both persistent memory space 503 and storage space 505.

A first portion of the memory medium 502 may be configured as an invisible cache space 510A for a visible memory space 504A (which may be exposed as a persistent memory space 503). Although the visible storage space 504B may operate without a cache, in some embodiments, the second portion of the memory medium 502 may be configured as an invisible read cache space 510B for the visible storage space 504B.

In some embodiments, a portion 504D of the storage medium 504 may be configured as an invisible persistent space for the invisible cache space 510A. Additionally or alternatively, portion 504D of storage medium 504 may be configured as an invisible endurance space for visible memory space 504A. In some embodiments, a portion of the storage medium 504 may be configured as an invisible durable space 504C for the visible storage space 504B.

To provide access to the visible storage space 504B as a storage device, the access logic 514 may include a storage protocol controller 521, in which embodiment the storage protocol controller 521 may be implemented with an NVMe controller, but in other embodiments the storage protocol controller 521 may be implemented with any other type of protocol controller that may enable a user to access data, for example, using a Logical Block Address (LBA) such as in a storage device. In some embodiments, the NVMe protocol may be implemented with a cxl.io-based underlying transport scheme.

A user may access the storage space 505 using one or more storage read/write (write) instructions 509, which storage read/write instructions 509 may be sent to the access logic 514 through the communication interface 506 using, for example, a storage protocol such as NVMe (e.g., NVMe-orf, etc.), which may also be referred to as a storage access protocol. If the accessed data is located in cache space 510B (e.g., a cache hit), then access logic 514 may use memory controller 524 to read data from cache space 510B or write data to cache space 510B. If the access is a write, the corresponding memory location in the visible memory space 504B in the storage medium 504 may be updated using a write-back operation 569 (e.g., opportunistic write-back), write-through operation, etc., which may be controlled, for example, by the cache and/or prefetch logic 512.

However, if the accessed data is not located in cache space 510B (e.g., a cache miss), then access logic 514 may use memory controller 526 to read data from visible memory space 504B or write data to visible memory space 504B. If the access is a write, the access logic 514 and/or the memory controller 526 may write data (e.g., pages, blocks, sectors, etc.) to the visible memory space 504B. Depending on the cache replacement policy implemented by the cache and/or prefetch logic 512, a copy of the accessed data may be stored in the cache space 510B.

Thus, in some embodiments, device 500 may expose memory space 503 (which may be accessed using a memory access protocol such as CXL) and memory space 505 (which may be accessed using a memory access protocol such as NVMe), both of which may be implemented with storage medium 504. Either or both of memory space 503 and/or storage space 505 may also implement a cache (e.g., cache space 510A for memory space 503 and/or cache space 510B for storage space 505).

In some embodiments, memory space 503 and storage space 505 may be implemented using separate logic devices. For example, the storage protocol controller 520 may be implemented with a CXL interface controller, and the storage protocol controller 521 may be implemented with an NVMe controller. Further, in some embodiments, the communication interface 506 may be implemented with a single underlying transmission scheme (e.g., PCIe, cxl.io, ethernet, infiniband, etc.), connector, and so forth. Thus, in some embodiments, a user may access memory space 503 as a first logical device using memory load/store commands and a memory access protocol such as CXL and access memory space 505 as a second logical device using memory read/write commands and a memory protocol such as NVMe through the same slot, connector, etc.

Depending on implementation details, the embodiment shown in FIG. 5 may expose a relatively large amount of storage medium 504 as persistent memory space 503 at a relatively low cost. Further, to the extent that storage medium 504 may include more capacity than may be used to reserve cache space 510A, excess storage medium 504 may be implemented as visible storage space 504B, which may be exposed as storage space 505. Furthermore, one or more portions of memory medium 502 configured as cache spaces 510A and/or 510B may reduce access time (e.g., latency) of persistent memory space 503 and/or storage space 505.

In some embodiments, persistent memory space 503 may be implemented as private memory. For example, if device 500 is accessed using an operating system such as Linux, some or all of persistent memory space 503 may be mapped as private memory that, depending on implementation details, may prevent it from being allocated as system (e.g., general purpose) memory using a memory allocation command such as malloc.

The memory and/or storage space shown in fig. 5 is not limited to any particular size. However, for purposes of illustrating some aspects of the present disclosure, in one example embodiment, visible memory space 504A may be implemented with 256GB of storage media, persistent memory space 503 may be implemented with 256GB of storage media, invisible persistent and/or durable space 504D may be implemented with 256GB of storage media, invisible cache space 510A may be implemented with 12GB of storage media, visible memory space 504B may be implemented with 1TB of storage media, storage space 505 may be implemented with 1TB of storage space, invisible durable space 504C may be implemented with 512GB of storage media, and invisible read cache space 510B may be implemented with 4GB of storage media.

Any or all of access logic 514, cache and/or prefetch logic 512, configuration logic 518, work logic 530, translation look aside buffer 528, persistence logic 516, and the like may be characterized and/or referred to collectively and/or individually as control logic.

Fig. 6 illustrates a fourth example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure. The embodiment shown in fig. 6 may be used to implement an apparatus such as that shown in fig. 2 and/or may be implemented with an apparatus such as that shown in fig. 2, wherein like elements may be referred to by reference numerals ending in and/or containing the same numerals, letters, etc. The device 600 shown in fig. 6 may include one or more elements similar to the embodiments shown in fig. 3, 4, and/or 5, where like elements may be indicated by and/or include like numbers ending in like numerals, letters, etc.

In some aspects, the configuration and/or operation of the device 600 shown in fig. 6 may be similar to the configuration and/or operation of the device 400 shown in fig. 4. However, in the embodiment shown in FIG. 6, a portion of the memory medium 602 may be configured as a visible memory space 611, which may be exposed as a persistent memory space 603. A portion of the storage medium 604 may be configured as an invisible persistent space 604A for the visible memory space 611. Some or all of the contents of visible memory space 611 may be persisted (e.g., flushed) to invisible persistent space 604A, for example, by persistent logic 616 (e.g., based on a power down event) using power supplied by persistent power supply 617.

The user may access the persistent memory space 603 using one or more memory load/store instructions 607, which one or more memory load/store instructions 607 may be sent to the access logic 614 over the communication interface 606 using, for example, the cxl.mem protocol.

Depending on implementation details, device 600 may use a relatively low cost combination of memory medium 602 (e.g., DRAM) and storage medium 604 (e.g., NAND flash) to provide relatively high performance (e.g., low latency and/or high bandwidth) persistent memory space 603. In some embodiments, access control logic 614 may implement substantially the entire persistent memory space 603 with visible memory space 611, which visible memory space 611 may be implemented with relatively high performance DRAM. Depending on implementation details, this may result in a relatively high performance (e.g., low latency) persistent memory space 603, because, for example, substantially all access requests to the persistent memory space 603 may be serviced by the memory medium 602 without involving access to the storage medium 604.

In some embodiments, persistent memory space 603 may be implemented as private memory.

The memory and/or storage space shown in fig. 6 is not limited to any particular size. However, for purposes of illustrating some aspects of the present disclosure, in one example embodiment, visible memory space 611 may be implemented with 16GB of memory medium, persistent memory space 603 may be implemented as 16GB of memory space, and invisible persistent space 604A may be implemented with 1TB of storage medium 604.

Any or all of access logic 614, cache and/or prefetch logic 612, configuration logic 618, working logic 630, translation look aside buffer 628, persistence logic 616, and the like may be characterized and/or referred to collectively and/or individually as control logic.

Fig. 7 illustrates a fifth example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure. The embodiment shown in fig. 7 may be used to implement an apparatus such as that shown in fig. 2 and/or may be implemented with an apparatus such as that shown in fig. 2, wherein like elements may be referred to by reference numerals ending in and/or containing the same numerals, letters, etc. The device 700 shown in fig. 7 may include one or more elements similar to the embodiments shown in fig. 3, 4, 5, and/or 6, where similar elements may be indicated by ending with and/or containing the same numbers, letters, etc.

In some aspects, the configuration and/or operation of the device 700 shown in fig. 7 may be similar to the configuration and/or operation of the device 500 shown in fig. 5. However, in the embodiment shown in FIG. 7, a portion of the memory medium 702 may be configured as a visible memory space 711, which may be exposed as a persistent memory space 703. A portion of storage medium 704 may be configured as invisible persistent space 704A for visible memory space 711. Some or all of the contents of visible memory space 711 can be persisted (e.g., flushed) to invisible persistent space 704A, for example, by persistent logic 716 (e.g., based on a power down event) using power supplied by persistent power supply 717.

Depending on implementation details, device 700 may use a relatively low cost combination of memory medium 702 (e.g., DRAM) and storage medium 704 (e.g., NAND flash) to provide relatively high performance (e.g., low latency and/or high bandwidth) persistent memory space 703 for persistence. In some embodiments, access control logic 714 may implement substantially the entire persistent memory space 703 with visible memory space 711, and visible memory space 711 may be implemented with relatively high performance DRAM. Depending on implementation details, this may result in a relatively high performance (e.g., low latency) persistent memory space 703 because, for example, substantially all access requests to the persistent memory space 703 may be serviced by the memory medium 702 without involving access to the storage medium 704.

As with the device 500 shown in fig. 5, the device 700 shown in fig. 7 may implement the persistent memory space 703 with a first logical device and the storage space 705 with a second logical device. Thus, in some embodiments, a user may access the memory space 703 as a first logical device of relatively high performance using memory load/store commands and a memory access protocol such as CXL and the memory space 705 as a second logical device using memory read/write commands and a memory protocol such as NVMe through the same slot, connector, etc. Further, storage medium 704 may include more capacity than invisible persistent space 704A may use to persist visible memory space 711. Thus, excess storage media may be used to implement visible storage 704B, which may be exposed as storage 705. Further, although the visible memory space 711 may be exposed as a memory space 705 without a cache, if a portion of the memory medium 702 is configured as a cache space 711, it may reduce the access time (e.g., latency) of the memory space 705.

In some embodiments, persistent memory space 703 may be implemented as private memory.

The memory and/or storage space shown in fig. 7 is not limited to any particular size. However, for purposes of illustrating some aspects of the present disclosure, in one example embodiment, visible memory space 711 may be implemented with 12GB of memory medium, persistent memory space 703 may be implemented as 12GB of memory space, invisible persistent space 704A may be implemented with 128GB of memory medium, invisible read cache space 710 may be implemented with 4GB of memory medium, memory space 705 may be implemented as 1TB of memory space, and visible memory space 704B may be implemented with 1TB of memory medium. And invisible durable space 704C may be implemented with 894GB of storage medium.

Any or all of access logic 714, cache and/or prefetch logic 712, configuration logic 718, working logic 730, translation look aside buffer 728, persistence logic 716, and the like may be characterized and/or referred to collectively and/or individually as control logic.

Fig. 8 illustrates a sixth example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure. The embodiment shown in fig. 8 may be used to implement an apparatus such as that shown in fig. 1 and/or may be implemented with an apparatus such as that shown in fig. 1, wherein like elements may be referred to by reference numerals ending in and/or containing the same numerals, letters, etc. The device 800 shown in fig. 8 may include one or more elements similar to the embodiments shown in fig. 3, 4, 5, 6, and/or 7, where similar elements may be indicated by ending in and/or containing the same numerals, letters, etc.

In some aspects, the configuration and/or operation of device 800 shown in fig. 8 may be similar to the configuration and/or operation of device 400 shown in fig. 4. However, in the embodiment illustrated in FIG. 8, a portion of storage medium 804 may be configured as visible memory and/or storage space 804A, which may be exposed as memory and/or storage space 840, which may be accessed as storage and/or as memory. For example, it is seen that memory and/or storage space 804A can be accessed as memory using memory load/store instructions (e.g., in embodiments in which memory protocol controller 820 is implemented with a CXL controller) that are sent to access logic 814 using a memory access protocol such as CXL. Additionally or alternatively, the visible memory and/or storage space 804A may be accessed as storage using storage read/write instructions (e.g., in embodiments in which the storage protocol controller 821 is implemented with an NVMe controller) sent to the access logic 814 using a storage access protocol such as NVMe.

In some embodiments, visible memory and/or storage 804A, which may be accessed as storage and/or memory, and memory and/or storage 840 may be implemented, for example, using a dual mode access scheme as described below.

In some embodiments, the visible memory and/or storage space 804A may be configured without caching. However, in some embodiments, a portion of the memory medium 802 may be configured as an invisible cache space 810 for visible memory and/or storage space 804A. To prevent data loss (e.g., based on a power down event), persistence logic 816 can flush data in invisible cache space 810 to a portion of storage medium 804 that can be configured as invisible persistent space 804C. Another portion of the storage medium 804 may be configured as an invisible endurance space for the visible memory and/or storage space 804A.

Because a portion of memory and/or storage space 840 may be configured to be accessed as both memory and storage using different access mechanisms, it may be beneficial in some embodiments to configure the memory as dedicated memory. Depending on implementation details, this may prevent the operating system from allocating memory (which may also be accessed as storage) as general purpose memory.

In some embodiments, memory and/or storage 840 may be implemented primarily as storage, e.g., memory and/or storage 840 is configured as visible storage by default. One or more portions of memory and/or storage space 840 may additionally be configured as a visible memory space (e.g., for dual mode access) as needed, according to use, when requested by a user, etc. In some embodiments, the memory and/or storage space 840 may be controlled by an NVMe drive, file system, or the like, which may be referred to as an owner (owner). For example, the owner may determine which of one or more portions of memory and/or storage 840 may be accessed by one or more particular users and for one or more particular amounts of time.

In some embodiments, an owner of a portion of memory and/or storage 840 may configure, operate (e.g., in addition to a CPU cache), one or more additional caches, e.g., in a system memory (e.g., DRAM) at the host. In such embodiments, the owner may implement a coherency scheme between one or more portions of memory and/or storage space 840 configured as memory and one or more additional caches.

Some embodiments may implement one or more functions for data consistency (e.g., using NVMe) between data accessed as in a storage device and data accessed as in memory (e.g., using CXL). For example, if a device is implemented as a memory buffer (e.g., as a CXL type 3 device and/or using the CXL 3.0 protocol), a host (or an application, process, service, VM manager, etc. running on the host) may implement one or more schemes for data coherency and/or consistency for explicit CPU or accelerator cache flushing for one or more memory accesses and for barrier and/or barrier synchronization mechanisms.

In some embodiments, an apparatus that is part of a storage access memory and/or storage space 840 may perform one or more data coherency and/or consistency operations. For example, if a device is implemented as an accelerator (e.g., as a CXL type 2 device and/or using the CXL 2.0 protocol), the device may be configured to issue an ownership request (e.g., using a cxl.cache) based on writing (e.g., NVMe writing) to memory and/or storage space 840 for a storage. As another example, for a device that uses a memory access protocol (e.g., CXL 3.0) with reverse invalidation snoop (back-invalidation snoop) capabilities, the device may be configured to use reverse invalidation snoops (e.g., using cxl.cache and/or cxl.mem) based on writes to memory and/or storage 840 (e.g., NVMe writes) as storage.

Although the embodiment shown in fig. 8 is not limited to any particular use, application, etc., in one example use case, device 800 may be used to implement a memory mapped storage (memory mapped storage), for example, using a dual mode access scheme. Depending on implementation details, such embodiments may provide improved performance (e.g., lower latency) as compared to memory mapped storage schemes (such as mmap in Linux) that may be implemented in an operating system, for example.

Any or all of access logic 814, cache and/or prefetch logic 812, configuration logic 818, work logic 830, translation look aside buffer 828, persistence logic 816, and the like may be characterized and/or referred to collectively and/or individually as control logic.

Fig. 9 illustrates a seventh example embodiment of a scheme for configuring and/or operating a device having a memory medium and a storage medium according to example embodiments of the present disclosure. The embodiment shown in fig. 9 may be used to implement an apparatus such as that shown in fig. 1 and/or may be implemented with an apparatus such as that shown in fig. 1, wherein like elements may be referred to by ending with and/or containing like numerals, letters, etc. The device 900 shown in fig. 9 may include one or more elements similar to the embodiments shown in fig. 3, 4, 5, 6, 7, and/or 8, where like elements may be indicated by and/or include reference numerals ending in the same numbers, letters, etc.

In some aspects, the configuration and/or operation of the device 900 shown in fig. 9 may be similar to the configuration and/or operation of the device 800 shown in fig. 8. However, the embodiment illustrated in FIG. 9 may not include persistent logic and/or a persistent power supply. Thus, the device 900 may provide one or more commands to the user (e.g., using the work logic 930), such as a cache flush command, to enable the user to manage the persistence of data in the invisible cache space 910. Such embodiments may be used, for example, in implementations where an external power source is used to provide backup power to device 900 and the user is aware of a power loss event.

In some embodiments, a dual mode access scheme may refer to an access scheme in which a portion of a storage medium may be accessed using a memory access method as memory and a storage access method as a storage device.

Fig. 10 illustrates an embodiment of a dual mode memory access scheme according to an example embodiment of the present disclosure. The embodiment shown in fig. 10 may include a host 1001 and a storage device 1000. The host 1001 may include one or more processors that may run an operating system 1046 and applications 1044.

The storage device 1000 may include a memory medium 1002 (e.g., DRAM), a storage medium 1004 (e.g., NAND flash memory), a communication interface 1042, and a cache controller 1012. In some embodiments, the memory medium 1002 may be addressable in relatively small units (such as bytes, words, cache lines, etc.), while the storage medium 1004 may be addressable in relatively large units (such as pages, blocks, sectors, etc.). The storage device 1000 may be configured to enable a host to access the storage medium 1004 using the first data transfer mechanism 1048 as a storage device or to access the storage medium 1004 using the second data transfer mechanism 1050 as a memory. In one example embodiment, the communication interface 1042 may implement a first data transfer mechanism 1048 using cxl.io and a second data transfer mechanism using cxl.mem. The configuration shown in fig. 10 may enable an operating system (e.g., linux) 1046 to access the storage medium 1004 as a storage device, for example, using a file system based access scheme that supports NVMe protocol running on cxl.io. For example, a file system in the operating system 1046 can access data in the storage medium 1004 using NVMe read and/or write commands that can read data from the storage medium 1004 and/or write data to the storage medium 1004 in units of one or more pages.

The configuration shown in fig. 10 may also enable applications 1044 to access storage medium 1004 with memory load/store instructions, e.g., using cxl.mem. In some embodiments, cache controller 1012 may configure a portion of memory medium 1002 as a cache for storage medium 1004. For example, because memory load and/or store commands may access data in relatively small units (such as bytes, words, cache lines, etc.), and because memory read and/or write commands may access storage medium 1004 in relatively large units (such as pages, blocks, sectors, etc.), storage device 1000 may service memory load commands for data (e.g., bytes, words, cache lines, etc.) in storage medium 1004 by reading pages, blocks, sectors, etc. containing requested data from storage medium 1004 and storing the pages, blocks, sectors, etc. in cache (e.g., in a portion of storage medium 1002). The storage device 1000 may then fetch the requested data from the cache and return the requested data in response to the memory load command.

The embodiment shown in fig. 10 may be used, for example, to implement a memory mapped storage arrangement according to an example embodiment of the present disclosure. Depending on implementation details, such an approach may improve performance (e.g., reduce latency) compared to, for example, a memory mapped file approach implemented by an operating system. For example, an operating system such as Linux may implement a memory mapped file scheme in which, in order for an application running at a host to read data in a file stored in a storage medium at a storage device as memory, the operating system may read sectors from the storage medium using NVMe protocol as a storage device. The operating system may then store the sectors in main memory (e.g., DRAM) from which the application may load the requested data.

However, in the dual mode access scheme shown in fig. 10, the operating system 1046 can be configured to enable the application 1044 to access files stored in the storage medium 1004 relatively directly as memory, e.g., by bypassing one or more operations of the operating system 1046 and using a second data transfer mechanism 1050 (e.g., CXL). For example, in an example storage access operation, an application 1044 may send a memory load command (e.g., using a CXL that may bypass the operating system 1046) to the storage device 1000 to request data bytes in the storage medium 1004. If the requested data byte is stored in a cache (e.g., in a portion of memory medium 1002), cache controller 1012 may read the requested data from the cache and return the requested data in response to a memory load command. However, even though the requested data is not stored in the cache, and the cache controller 1012 uses the store read command to read the page containing the requested data byte from the storage medium 1004 (which may then be stored in the cache from which the memory load command may be serviced), the memory load command may still bypass the operating system 1046. Depending on implementation details, this may reduce overhead, power consumption, latency, etc. associated with the operating system transferring sectors to host memory. The use of the second data transfer mechanism 1050 (e.g., cxl.mem) may also result in faster data transfer than, for example, the use of a storage protocol (such as NVMe) running over a relatively slow PCIe or cxl.io transmission scheme.

FIG. 11 illustrates another embodiment of a dual mode memory access scheme according to an example embodiment of the present disclosure. For purposes of illustration, the embodiment shown in FIG. 11 may be described in the context of a storage device 1100 that may access data in units of sectors. However, other embodiments may access the storage medium in units of pages, blocks, and the like.

The embodiment shown in fig. 11 may include a storage device 1100 having a storage medium 1104 and a DMA engine 1152. Data can be stored in storage medium 1104 as sectors 1154-0, 1154-1, …, 1154-N-1 (which can be collectively and/or individually referred to as 1154). A sector may include 512 bytes, numbered 0 through 511, for example. Memory mapped file 1156 may be stored in one or more sectors 1154 including sector 1154-a, sector 1154-a may include the data of interest stored in byte 1.

The host 1101 may include a system memory space 1158 having a main memory area 1162, the main memory area 1162 may be implemented, for example, with dual in-line memory modules (DIMMS) on a circuit board (e.g., host motherboard). Some or all of the storage media 1104 may be mapped to an area of the system memory space 1158 using a memory access protocol such as CXL as host managed device memory (HDM) 1162.

The host 1101 (or an application, process, service, virtual Machine (VM), VM manager, etc. running on the host) may access data in the memory mapped file 1156 using a first access mode (which may also be referred to as a method) as a storage device or using a second access mode as memory.

The first mode may be implemented by an operating system running on the host 1101. The operating system may implement the first mode using a storage access protocol such as NVMe using an NVMe driver 1164 at the host 1101. The NVMe protocol may be implemented with an underlying transport scheme based on cxl.io, which may use the PCIe physical layer, for example. The NVMe driver 1164 may use portions 1066 of the system memory 1158 for PCIe configuration (PCI CFG), base Address Registers (BARs), etc.

An application (or other user) may access the data in file 1156 in sectors (or blocks, pages, etc.) using one or more store read/write instructions 1168. For example, to read data stored in byte 1 in sector 1154-a of file 1156, an application (or other user) may issue a storage read command 1168 to NVMe drive 1164 for sector 1154-a including byte 1. The NVMe drive 1164 may initiate DMA transfers of the DMA engine 1152, as indicated by arrow 1170. DMA engine 1152 may transfer sector 1154-a to main memory area 1160 of system memory 1158, as indicated by arrow 1172. Then, the application may access byte 1 by reading byte 1 from main memory area 1160.

The second mode may be implemented with a memory access protocol, such as CXL, that may map the storage medium 1104 as a host managed device memory (HDM) 1162 to an area of the system memory space 1158. Thus, sectors 1154-A including byte 1 may be mapped to HDM region 1162.

An application (or other user) may also access data in file 1156 in bytes (or words, cache lines, etc.) using one or more memory load/store instructions 1174. For example, to read the data stored in byte 1 of file 1156, an application (or other user) may issue a memory load command 1174. As indicated by arrows 1176 and 1178, the data stored in byte 1 may be transferred to an application using, for example, the cxl.mem protocol.

Depending on implementation details, accessing data stored in byte 1 of file 1156 using the second mode (e.g., using CXL) may reduce latency (particularly, in some embodiments, when accessing data in relatively small units), increase bandwidth, reduce power consumption, etc., for any of a number of reasons. In the CXL scheme, sectors may be mapped rather than copied to system memory, thereby reducing data transfer. In the CXL scheme, the data may be byte-addressable, thereby reducing the amount of data transferred to access the data of interest in byte 1, as compared to copying an entire sector to system memory. The CXL scheme may provide applications or other users with more direct access to data, for example, by bypassing some or all of the operating systems, as also shown in fig. 10. As with the embodiment described above with respect to FIG. 10, in the embodiment illustrated in FIG. 11, a cache, which may be implemented with a memory medium that may be located, for example, in storage device 1100, system memory space 1158, etc., may be used to access data accessed in sector 1154 using memory load/store instructions 1174. Such a cache configuration may be used, for example, because sectors 1154 or other storage media in a storage device may be accessible only in sectors, blocks, pages, etc., while memory load/store commands 1174 may access data in bytes, words, cache lines, etc.

Fig. 12 illustrates an example embodiment of a host device that may be used to implement any of the functions of the hosts (or other users, such as applications, processes, services, operating systems, VMs, VM managers, etc.) disclosed herein, according to example embodiments of the disclosure. The host device 1200 shown in fig. 12 may include a processor 1202 that may include a memory controller 1204, a system memory 1206, host logic 1208, and/or a communication interface 1210. Any or all of the components shown in fig. 12 may communicate over one or more system buses 1212. In some embodiments, one or more of the components shown in fig. 12 may be implemented using other components. For example, in some embodiments, the host logic 1208 may be implemented by the processor 1202 executing instructions stored in the system memory 1206 or other memory. In some embodiments, host logic 1208 can be used to implement any user functionality related to configuring, operating, etc. a device as disclosed herein. For example, host logic 1208 may be configured to send one or more commands to configure the device (e.g., using configuration logic), send one or more commands to perform data movement operations, cache management operations, etc., send one or more memory access requests, etc.

Fig. 13 illustrates an example embodiment of a storage device that may be used to implement any of the device functions disclosed herein that may be implemented with the storage device, according to example embodiments of the present disclosure. The storage device 1300 may include a device controller 1302, a media conversion layer 1304 (e.g., FTL), a storage and/or memory medium 1306, processing control logic 1316, and a communication interface 1310. The components shown in fig. 13 may communicate via one or more device buses 1312. In some embodiments, where flash memory may be used for some or all of the media 1306, the media conversion layer 1304 may be implemented partially or fully as a flash conversion layer (FTL). In some embodiments, the process control logic 1316 may be used to implement any of the control logic disclosed herein, such as access control logic, cache logic, persistence logic, configuration logic, working logic, and the like.

Fig. 14 shows a first example embodiment of a device configuration scheme according to an example embodiment of the present disclosure. The embodiment shown in fig. 14 may be used to implement and/or may be implemented with, for example, any of the apparatus and/or schemes disclosed herein, wherein like elements may be referred to by reference numerals ending in and/or containing the same numerals, letters, etc.

The embodiment shown in fig. 14 may include a device 1400, and the device 1400 may include a cache medium 1402 and/or a storage medium 1404. Device 1400 may include configuration logic 1418, as shown in fig. 14, where configuration logic 1418 may be implemented, for example, with a device boot Read Only Memory (ROM) (e.g., CXL device boot ROM). The device 1400 may be configured, for example, during a power-up process (e.g., power-up self test (power on self test, POST)) as shown on the left side of fig. 14. A power-up process, which may be initiated, performed, etc., by, for example, a host or other user, may begin at operation 1481-1, where power may be applied to device 1400 at operation 1481-1. At operation 1481-2, a host or other user may execute basic input and/or output service (BIOS) code, which may load and/or execute device boot ROM 1418, for example, by one or more processors or other circuitry at device 1400.

The device boot ROM 1418 may enable a user to configure the device 1400, for example, using a BIOS User Interface (UI) 1480 (e.g., a configuration screen may be provided for various menus, configuration settings, etc.). The device boot ROM 1418 can configure the cache medium 1402 and/or the storage medium 1404 at the device 1400 based on one or more configuration parameters provided via the UI 1480. Examples of configuration settings may include the amount, type, etc. of cache medium 1402, storage medium 1404, invisible cache space and/or visible memory space within cache medium 1402, visible storage space within storage medium 1404, invisible persistent space, etc., one or more cache policies, etc. for one or more virtual devices within device 1400. For example, in some embodiments, device boot ROM 1418 may configure device 1400 to implement one or more virtual devices that may have various amounts of cache media 1402 and/or storage media 1404.

In the example embodiment shown in fig. 14, the device boot ROM 1418 may configure the first virtual device 1400-1 as a first type of device (e.g., a PMEM device) that may include the first portion 1402-1 of the cache medium 1402 and/or the first portion 1404-1 of the storage medium 1404. The device boot ROM 1418 may also configure the second virtual device 1400-2 as a second type of device (e.g., a dual mode storage device with cache) that may include the second portion 1402-2 of the cache medium 1402 and/or the second portion 1404-2 of the storage medium 1404. The device boot ROM 1418 may also configure a third virtual device 1400-3 as a third type of device (e.g., a dual mode storage device) that may include a third portion 1404-3 of the storage medium 1404.

At operation 1481-3, based on completion of at least a portion of the configuration operation, the host or other user and device 1400 may load and/or launch one or more operating systems. At operations 1481-4, some or all of the configuration process may be completed, and device 1400 may continue to operate, for example, by processing access requests. In some embodiments, the configuration scheme shown in fig. 14 may be characterized as a static scheme, as depending on implementation details, one or more of the devices and/or virtual devices may be configured using boot ROM at power up (e.g., only at power up).

Fig. 15 illustrates a second example embodiment of a device configuration scheme according to an example embodiment of the present disclosure. The embodiment shown in fig. 15 may be used to implement and/or may be implemented with, for example, any of the apparatus and/or schemes disclosed herein, wherein like elements may be referred to by reference numerals ending in and/or containing the same numerals, letters, etc.

In the embodiment shown in fig. 15, as shown in fig. 15, configuration logic 1518 may be implemented, for example, with a device configuration agent (e.g., a CXL device configuration agent). The device configuration agent 1518 may be accessed, for example, as a device for an operating system (e.g., at a host or other user 1583), such as a file/dev/cxlmgmt 0 that may be used to configure the device 1500. The device configuration agent 1518 may configure and/or partition the device 1500 and the cache medium 1502 and/or storage medium 1504 to implement a physical device and/or one or more virtual devices, such as virtual devices 1500-1, 1500-2, and/or 1500-3, for purposes of illustration, the virtual devices 1500-1, 1500-2, and/or 1500-3 may be similar to those shown in fig. 14, but may be implemented in any other configuration.

The embodiment shown in fig. 15 may also include a physical and/or virtual switch 1582 (e.g., a virtual CXL switch) that may enable a host or other user 1583 to access one or more of the virtual devices 1500-1, 1500-2, and/or 1500-3. In this example embodiment, virtual devices 1500-1, 1500-2, and/or 1500-3 may be configured as PMEM devices, dual mode devices with caches, and/or dual mode devices, respectively. Thus, in some embodiments, virtual devices 1500-1, 1500-2, and/or 1500-3 may be accessed using an operating system as files/dev/cxl/pmem 0,/dev/cxlnvme 1, and/or/dev/cxlnvme, respectively. The virtual devices Dev 1, dev 2 and Dev 3 shown in fig. 15 may be regarded as virtual in the sense of being mapped to different addresses. Thus, virtual devices may be accessed by different virtual machines, for example, through an operating system that may run a hypervisor (hypervisor) supporting the virtual machines as different files (e.g.,/dev/cxl/pmem 0,/dev/cxlnvme 1 and/or/dev/cxlnvme 2).

In some embodiments, the configuration scheme shown in fig. 15 may be characterized as a dynamic scheme in that, depending on implementation details, one or more of the devices and/or virtual devices may be configured using the device configuration agent 1518 while the devices are operating, e.g., to implement functions such as hot plug, hot unplug, etc., for the device 1500.

Fig. 16 illustrates an example embodiment of a device configuration scheme with hot plug functionality according to an example embodiment of the present disclosure. The embodiment shown in fig. 16 may be used to implement and/or may be implemented with, for example, the scheme shown in fig. 15 and/or any apparatus and/or scheme disclosed herein, wherein like elements may be referred to by ending with and/or containing like numerals, letters, etc.

Referring to fig. 16, the example hot-plug process shown on the left side of fig. 16 may involve an Operating System (OS) 1684 and/or system firmware 1685, where time may advance in a downward direction. The hot plug process may include an operation 1686-1, at which operation 1686-1 the device Dev1 (e.g., virtual device) may be configured and/or the hot plug process may be initiated, for example, by the device configuration agent 1618 based on detecting a hot plug of the device 1600. At operation 1686-2, the system firmware 1685 may add the PMEM implemented by the device Dev1 to an address space (e.g., physical address space). At operation 1686-3, the system firmware 1685 may notify the operating system 1684 to install the device Dev1, the device Dev1 may be accessible, for example, as a file/Dev/cxl/pmem 0.

At operation 1686-4, the device configuration agent 1618 may configure the device Dev2 (e.g., virtual device). At operation 1686-5, the system firmware 1685 may notify the operating system 1684 to install the device Dev2, the device Dev2 may be accessible, for example, as a file/Dev/cxlnvme 1. At operation 1686-6, the device configuration agent 1618 may configure the device Dev3 (e.g., virtual device). At operations 1686-7, the system firmware 1685 may notify the operating system 1684 to install the device Dev3, the device Dev3 may be accessible, for example, as a file/Dev/cxlnvme 2. At operations 1686-8, the hot plug detection and/or configuration process may be completed and the device may continue to process access requests, for example, from the operating system 1684, host, and/or other users.

Fig. 17 illustrates an example embodiment of a device configuration scheme with hot-pull functionality according to an example embodiment of the present disclosure. The embodiment shown in fig. 17 may be used to implement and/or may be implemented with any apparatus and/or scheme such as that shown in fig. 15 and/or disclosed herein, where like elements may be referred to by ending with and/or containing like numerals, letters, etc.

Referring to fig. 17, the example hot-pull process shown on the left side of fig. 17 may involve an operating system 1784 and/or system firmware 1785, where time may advance in a downward direction. The hot-pull process may include operation 1787-1, at which operation 1787-1, the operating system 1784 may cease one or more (e.g., all) accesses to the device 1700. At operation 1787-2, the preparation to take the device 1700 offline may include, for example, closing one or more files, synchronizing one or more buffers, flushing one or more CPU caches, flushing one or more device buffers, and the like.

At operation 1787-3, the operating system 1784 may notify the device configuration agent 1718 to initiate the hot-pull process, for example, by flushing one or more internal buffers. At operation 1787-4, the operating system 1784 and/or firmware 1785 may remove one or more portions of memory (e.g., PMEM) associated with the device 1700 from an address space (e.g., physical address space). At operation 1787-5, the operating system 1784 and/or firmware 1785 may send a request to the device configuration agent 1718 to take the device 1700 offline.

At operation 1787-6, the device configuration agent 1718 may remove the device Dev1. At operation 1787-7, the system firmware 1785 may notify the operating system 1784 that the device Dev1 has been removed. At operation 1787-8, the device configuration agent 1718 may remove the device Dev2. At operation 1787-9, the system firmware 1785 may inform the operating system 1784 that the device Dev2 has been removed. At operation 1787-10, the device configuration agent 1718 may remove the device Dev3. At operation 1787-11, the system firmware 1785 may inform the operating system 1784 that the device Dev3 has been removed. At operations 1787-12, a hot pull event may be detected and the device 1700 may be powered down. At operations 1787-13, the device 1700 may be removed, for example, from a slot, chassis, rack, or the like.

Fig. 18 illustrates an example embodiment of a hot extraction method for a device according to an example embodiment of the present disclosure. The embodiment shown in fig. 18 may be used to implement, for example, the scheme shown in fig. 15, 17, and/or any apparatus and/or scheme disclosed herein and/or may be implemented with, for example, the scheme shown in fig. 15, 17, and/or any apparatus and/or scheme disclosed herein, wherein like elements may be indicated by ending with and/or including the same numbers, letters, etc. For purposes of illustration, the method shown in fig. 18 may be described in the context of an implementation with the apparatus 1700 shown in fig. 17, but the method shown in fig. 18 is not limited to the details shown in fig. 17.

Referring to FIG. 18, the method may begin at operation 1888-1, the operating system 1784 may close one or more device files and/or flush one or more buffers associated with the hot-swapped out device 1700. At operation 1888-2, operating system 1784, system firmware 1785, and the like, may flush one or more CPU caches associated with device 1700 (and/or one or more virtual devices 1700-1, 1700-2, and/or 1700-3 implemented with device 1700). At operation 1888-3, the operating system 1784, system firmware 1785, etc. may send a flush request to the device 1700, e.g., to flush one or more caches, buffers, etc. associated with the device 1700 (and/or one or more virtual devices 17001, 1700-2, and/or 1700-3). At operation 1888-4, the device 1700 may complete the one or more flushing operations requested at operation 1888-3.

At operation 1888-5, operating system 1784, system firmware 1785, etc. may remove device 1700 (and/or one or more virtual devices 1700-1, 1700-2, and/or 1700-3) from the managed resources, e.g., to prevent use of device 1700 and/or to allocate resources to device 1700. At operation 1888-6, the operating system 1784, system firmware 1785, and the like, may send a request to the device 1700 to take the device offline. At operation 1888-7, device 1700 may be offline and/or powered down. At operation 1888-8, the device 1700 may be removed, for example, from a slot, chassis, rack, or the like.

Any of the functions described herein, including any user functions, device functions, etc. (e.g., any control logic), may be implemented in hardware, software, firmware, or any combination thereof (including, for example, hardware and/or software combinational logic, sequential logic, timers, counters, registers, state machines, volatile memory (such as DRAM and/or SRAM), non-volatile memory (including flash memory), persistent memory (such as cross-grid non-volatile memory), memory with body resistance variations, PCM, etc., and/or any combination thereof, complex Programmable Logic Devices (CPLDs), field Programmable Gate Arrays (FPGAs), application specific circuits (ASICs), central Processing Units (CPUs) (including CISC processors such as x86 processors and/or RISC processors such as ARM processors), graphics Processing Units (GPUs), neural Processing Units (NPUs), tensor Processing Units (TPUs), data Processing Units (DPUs), etc.). In some embodiments, one or more components may be implemented as a system on a chip (SOC).

Some embodiments disclosed above have been described in the context of various implementation details, but the principles of the present disclosure are not limited to these or any other specific details. For example, some functions have been described as being implemented by certain components, but in other embodiments, functions may be distributed among different systems and components at different locations and with various user interfaces. Certain embodiments have been described as having particular processes, operations, etc., but these terms also encompass embodiments in which a particular process, operation, etc., may be implemented with multiple processes, operations, etc., or embodiments in which multiple processes, operations, etc., may be integrated into a single process, step, etc. References to a component or element may refer to only a portion of the component or element. For example, a reference to a block may refer to an entire block or one or more sub-blocks. The use of terms such as "first" and "second" in this disclosure may be used solely for the purpose of distinguishing between their modified elements and may not indicate any spatial or temporal order unless otherwise indicated clearly from the context. In some embodiments, reference to an element may refer to at least a portion of the element, e.g., "based on" may refer to "based at least in part on" and the like. The reference to a first element may not imply the presence of a second element. The principles disclosed herein have independent utility and may be embodied separately and not every embodiment may utilize every principle. However, these principles may also be embodied in various combinations, some of which may amplify the benefits of the various principles in a synergistic manner. The various details and embodiments described above may be combined to obtain additional embodiments according to the inventive principles of this patent disclosure.

In some embodiments, a portion of an element may refer to less than or all of the element. The first portion of the element and the second portion of the element may refer to the same portion of the element. The first portion of the element and the second portion of the element may overlap (e.g., a portion of the first portion may be the same as a portion of the second portion).

Since the inventive principles of this patent disclosure may be modified in arrangement and detail without departing from the inventive concepts, such changes and modifications are considered to be within the scope of the disclosure.

Claims

1. An apparatus for storage, comprising:

A cache medium;

A storage medium;

A communication interface; and

At least one control circuit configured to:

Receiving a first memory access request to access a portion of a storage medium using a communication interface;

receiving a second memory access request to access the portion of the storage medium using the communication interface;

Accessing the portion of the storage medium based on the first memory access request; and

A portion of the cache medium is accessed based on the second memory access request.

2. The apparatus of claim 1, wherein:

the portion of the cache medium includes a first cache; and

The at least one control circuit is configured to access the portion of the storage medium based on the first memory access request by:

reading data from the portion of the storage medium;

storing the data in a second cache; and

At least a portion of the data is loaded from the second cache.

3. The device of claim 1, wherein the at least one control circuit is configured to write at least a portion of the cache medium to the portion of the storage medium.

4. The apparatus of claim 1, wherein:

the portion of the storage medium is a first portion of the storage medium; and

The at least one control circuit is configured to:

Receiving a storage access request to access a second portion of the storage medium using the communication interface; and

Based on the storage access request, a second portion of the storage medium is accessed.

5. The device of claim 4, wherein the at least one control circuit is configured to:

receiving a first memory access request using a first protocol; and

A storage access request is received using a second protocol.

6. The device of claim 4, wherein the at least one control circuit is configured to:

Operating the portion of the cache medium and the first portion of the storage medium as a first logical device; and

The second portion of the storage medium is operated as a second logical device.

7. The device of claim 1, wherein the at least one control circuit is configured to:

receiving a storage access request to access the portion of the storage medium using the communication interface; and

The portion of the storage medium is accessed based on the storage access request.

8. The device of claim 7, wherein the at least one control circuit is configured to:

receiving a first memory access request using a first protocol; and

A storage access request is received using a second protocol.

9. The apparatus of claim 8, wherein:

the first protocol includes a memory access protocol; and

The second protocol includes a storage access protocol.

10. The device of claim 7, wherein the at least one control circuit is configured to perform a coherency operation associated with the portion of the storage medium.

11. The apparatus of claim 1, wherein:

the portion of the storage medium is a first portion of the storage medium; and

The at least one control circuit is configured to write at least a portion of the cache medium to a second portion of the storage medium.

12. The device of claim 1, wherein the at least one control circuit comprises a work logic unit configured to:

Receiving a command; and

Based on the command, a data movement operation or an operation associated with the portion of the cache medium is performed.

13. An apparatus for storage, comprising:

A memory medium;

A storage medium;

A communication interface; and

At least one control circuit configured to:

Receiving, using a communication interface, a memory access request to access a portion of a memory medium;

Accessing the portion of the memory medium based on the memory access request; and

The portion of the memory medium is written to a portion of the storage medium.

14. The apparatus of claim 13, wherein:

the portion of the storage medium is a first portion of the storage medium; and

The at least one control circuit is configured to:

15. The device of claim 14, wherein the at least one control circuit is configured to:

Operating the portion of the memory medium and the first portion of the storage medium as a first logic device; and

16. The apparatus of claim 14, wherein:

The portion of the memory medium is a first portion of the memory medium; and

The at least one control circuit is configured to access a second portion of the memory medium based on the memory access request.

17. An apparatus for storage, comprising:

Media, including cache media and storage media;

A communication interface; and

At least one control circuit configured to:

receiving a first memory access request using a communication interface;

Accessing a first portion of the medium based on the first memory access request;

Receiving a first storage access request using a communication interface;

Accessing a second portion of the medium based on the first storage access request;

receiving a second memory access request using the communication interface;

Receiving a second storage access request using the communication interface;

accessing a third portion of the medium based on the second memory access request; and

Based on the second storage access request, a third portion of the medium is accessed.

18. The apparatus of claim 17, wherein:

The first portion of media comprises a portion of cache media; and

The at least one control circuit is configured to write data from the portion of the cache medium to a portion of the storage medium.

19. The device of claim 17, wherein the at least one control circuit is configured to map a first portion of the medium to a second portion of the medium.

20. The device of claim 17, wherein the at least one control circuit is configured to access a portion of the cache medium based on the first storage access request.