CN118868801B - Two-stage cascaded high-gain amplifier based on adaptive bias and cascode compensation - Google Patents
Two-stage cascaded high-gain amplifier based on adaptive bias and cascode compensationInfo
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- CN118868801B CN118868801B CN202410835429.6A CN202410835429A CN118868801B CN 118868801 B CN118868801 B CN 118868801B CN 202410835429 A CN202410835429 A CN 202410835429A CN 118868801 B CN118868801 B CN 118868801B
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- H—ELECTRICITY
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- H03F1/00—Details of amplifiers with only discharge tubes, only semiconductor devices or only unspecified devices as amplifying elements
- H03F1/02—Modifications of amplifiers to raise the efficiency, e.g. gliding Class A stages, use of an auxiliary oscillation
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- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
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- H03F3/68—Combinations of amplifiers, e.g. multi-channel amplifiers for stereophonics
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Abstract
The invention discloses a two-stage cascade high-gain amplifier based on self-adaptive bias and common-source common-gate compensation, which adopts a basic structure of the two-stage cascade amplifier, wherein the first stage adopts a common-source common-gate floating inverting amplifier structure of the self-adaptive bias, the gain is obviously improved through cross coupling bias, simultaneously, larger current is obtained to improve the bandwidth and the slew rate, an external bias circuit and an additional common-mode feedback circuit are omitted, and the second stage adopts an inverting amplifier structure of current source bias, realizes higher current efficiency through current multiplexing and obtains larger output swing. In addition, the invention uses the cascode compensation circuit to omit the zeroing resistor required by the Miller compensation, and has the advantages of high gain and high speed as a whole.
Description
Technical Field
The invention belongs to the technical field of amplifiers, and particularly relates to a two-stage cascade high-gain amplifier based on self-adaptive bias and cascode compensation.
Background
Signals generated in nature and recognizable by humans belong to Analog signals, and high-performance signal processing is mostly performed in digital domain by computers today, so Analog-to-digital converters (ADC) that convert Analog signals with continuous amplitude and time into digital signals with discrete amplitude and time have been widely used. As an important part in a signal chain, the precision, the speed and the power consumption of the analog-digital converter become determinants of the signal processing precision, the speed and the power consumption, and along with the rapid development of the fields of mobile communication, sensors, biomedical treatment, the Internet of things and the like, the requirements on precise and high-quality data information are higher and higher, so the requirements on the high-precision ADC are also greatly increased.
Common high-precision ADCs comprise a Delta-Sigma ADC and PIPELINE ADC, the Delta-Sigma ADC is used for inhibiting quantization noise in a signal bandwidth through an oversampling and noise shaping technology to achieve a high signal-to-noise ratio, and PIPELINE ADC is used for realizing high-speed operation while realizing higher precision through cascading a plurality of sub-ADCs with lower precision. However, delta-Sigma ADCs have very high requirements on the gain, bandwidth, slew rate and linearity of the amplifier in the first stage integrator, while PIPELINE ADC has similar requirements on the residual amplifier performance in the first stage integrator, and the performance of the amplifier in both ADCs determines the performance and energy efficiency of the whole ADC.
With the continuous reduction of the feature size of integrated circuits, the implementation of high-gain and high-performance amplifiers is becoming a hotspot and difficulty in integrated circuit design, and the conventional cascode amplifier can achieve very high gain, but the swing is greatly limited, and the two-stage amplifier using miller compensation can achieve high gain and better stability, but generally needs zero-setting resistance and consumes larger power consumption. The floating inverting amplifier proposed in recent years achieves dynamic operation and does not require an additional common mode feedback circuit, however, the gain thereof is generally low, and it is difficult to satisfy the requirement of high gain and high performance.
For example, literature [R.S.Ashwin Kumar,N.Krishnapura,and P.Banerjee,"Analysis and design of a discrete-time delta-sigma modulator using a cascoded floating-inverter-based dynamic amplifier,"IEEE J.Solid-State Circuits,vol.57,no.11,pp.3384-3395,Nov.2022] proposes a cascode floating inverter amplifier based on VCM bias that eliminates the extra bias circuit by using VCM bias technology and improves the gain by using cascode technology, but the amplifier is a single stage amplifier with limited gain and the cascode structure limits the output swing that the amplifier can provide. Document [Y.Choi,W.Lee,S.Park,C.Kim,H.Jung and C.Kim,"A 101.6-dB-SNDR Fully Dynamic Zoom ADC Using Miller-Compensated Floating Inverter Amplifiers,"in IEEE Transactions on Circuits and Systems II:Express Briefs,doi:10.1109/TCSII.2024.3392909] proposes a two-stage cascade floating inverting amplifier based on miller compensation, which improves the gain by using a two-stage cascade technique, improves the stability of the two-stage cascade amplifier by using a miller compensation technique, and has an output swing higher than that of a single-stage cascode structure, but both stages of the amplifier use a common floating inverting amplifier structure without a cascode, so that the gain provided by the amplifier is only slightly higher than that provided by a VCM biased amplifier, the gain is limited, and the miller compensation technique requires a larger miller capacitance and an additional zero-setting resistance. Thus, there is a need for a high gain amplifier with higher gain, higher output swing, simple biasing techniques and compensation techniques.
Disclosure of Invention
In view of the above, the invention provides a two-stage cascade high-gain amplifier based on adaptive bias and cascode compensation, which utilizes a floating inverting amplifier with adaptive bias and an inverting amplifier with current source bias to cascade, thereby realizing high gain and avoiding the influence of a cascode structure on swing.
A two-stage cascade high-gain amplifier based on self-adaptive bias and cascode compensation is formed by cascade of two-stage amplifiers, wherein the first-stage amplifier forms self-adaptive bias through a cross coupling mode to improve system gain, and the second-stage amplifier realizes higher current efficiency through current multiplexing to further improve system gain and output swing.
Further, the first-stage amplifier adopts an adaptive bias cascode floating inverting amplifier circuit, and the second-stage amplifier adopts a current source biased inverting amplifier circuit. The self-adaptive bias common-gate floating inverting amplifier changes bias into cross-coupled self-adaptive bias to improve gain and speed based on the traditional common-source common-gate floating inverting amplifier biased by V CM, omits an external bias circuit and an additional common-mode feedback circuit, keeps the advantages of low noise and low power consumption, and obtains larger current to improve bandwidth and slew rate.
Further, the self-adaptive bias common-gate floating inverting amplifier circuit comprises four PMOS tubes M1, M2, M5, M6, four NMOS tubes M3, M4, M7, M8, a capacitor C RES and six switches S1-S6, wherein one end of S1 is connected with a power supply voltage VDD, the other end of S1 is connected with one end of S3 and one end of C RES, the other end of S3 is connected with the source electrode of M1 and the source electrode of M2, the grid electrode of M1 is connected with the grid electrode of M3 and serves as an inverting voltage input end of a first-stage amplifier, the grid electrode of M2 is connected with the grid electrode of M4 and serves as a positive-phase voltage input end of the first-stage amplifier, the drain electrode of M1 is connected with the source electrode of M5 and the grid electrode of M8, the drain electrode of M2 is connected with the source electrode of M6 and the grid electrode of M7, the grid electrode of M5 is connected with the source electrode of M8 and the drain electrode of M4, the grid electrode of M6 is connected with the source electrode of M7 and the drain electrode of M3, the grid electrode of M5 is connected with the drain electrode of M5 and the drain electrode of M7, the other end of M5 is connected with the drain electrode of M5 and the other end of M4 is connected with the positive-phase voltage of the other end of M4 and the drain electrode of M4 is connected with the positive-phase voltage of the first-stage amplifier, the other end of the grid electrode of M2 is connected with the drain electrode of the first-stage amplifier, the positive-phase voltage of the grid electrode of S35 is connected with the other end of the grid electrode of M3 is connected with the grid electrode of the other end of the grid electrode of M3 is connected with the grid electrode is connected with the positive-phase voltage of the grid electrode of the S3; the control electrodes of the switches S1, S2, S5 and S6 are connected with clock signalsThe control poles of the switches S3 and S4 are connected with clock signals
Further, the current source biased inverting amplifier circuit comprises three PMOS tubes M9, M10, M13, three NMOS tubes M11, M12, M14 and two switches S7-S8, wherein the source electrode of M13 is connected with the power supply voltage VDD, the grid electrode of M13 is externally connected with the bias voltage V BP, the drain electrode of M13 is connected with the source electrode of M9 and the source electrode of M10, the grid electrode of M9 is connected with the grid electrode of M11 and is used as the positive phase voltage input end of the second-stage amplifier, the grid electrode of M10 is connected with the grid electrode of M12 and is used as the inverting voltage input end of the second-stage amplifier, the drain electrode of M9 is connected with the drain electrode of M11 and one end of S8 and is used as the inverting voltage output end of the second-stage amplifier, the drain electrode of M10 is connected with one end of S7 and is used as the positive phase voltage output end of the second-stage amplifier, the other end of S7 is connected with the other end of S8 and is externally connected with the common mode voltage V CM, the source electrode of M11 is connected with the source electrode of M12 and the drain electrode of M14, the grid electrode of M14 is connected with the common mode voltage V CMFB, and the common mode voltage of S7 is connected with the drain electrode of S8
Further, the clock signalFor closing the switch during the reset phase of the system, clock signalFor closing the switch during the system amplification phase,And (3) withThe phases are complementary and there is some dead time.
Further, the common mode feedback voltage V CMFB is generated and provided by a common mode feedback circuit, the common mode feedback circuit includes two resistors R1 to R2 and an amplifier AMP1, wherein one end of R1 is connected to the positive phase voltage output end of the second stage amplifier, one end of R2 is connected to the negative phase voltage output end of the second stage amplifier, the other end of R1 is connected to the other end of R2 and the positive phase input end of AMP1, the negative phase input end of AMP1 is connected to the common mode voltage V CM, and the output end of AMP1 generates the common mode feedback voltage V CMFB.
Further, a cascode compensation circuit is arranged between the two stages of amplifiers and is used for providing frequency compensation for the two stages of amplifiers, and the cascode compensation circuit comprises four capacitors C1-C4, wherein one end of C1 is connected with the drain electrode of M3, one end of C2 is connected with the drain electrode of M1, the other end of C1 is connected with the other end of C2 in parallel with the reverse voltage output end of the second stage amplifier, one end of C3 is connected with the drain electrode of M4, one end of C4 is connected with the drain electrode of M2, and the other end of C3 is connected with the other end of C4 in parallel with the positive voltage output end of the second stage amplifier. The compensation circuit provides frequency compensation for the two-stage amplifier, so that the amplifier is stable, and the zeroing resistance required by Miller compensation can be eliminated and the system stability can be ensured while the main pole and the secondary pole are separated.
Compared with the prior art, the invention adopts a basic structure of a two-stage cascade amplifier, wherein the first stage adopts a self-adaptive bias cascode floating inverting amplifier structure, the gain is obviously improved through cross coupling bias, simultaneously, larger current is obtained to improve the bandwidth and the slew rate, an external bias circuit and an additional common mode feedback circuit are omitted, and the second stage adopts a current source bias inverting amplifier structure, thereby realizing higher current efficiency and larger output swing through current multiplexing. In addition, the invention uses the cascode compensation circuit to omit the zeroing resistor required by the Miller compensation, and has the advantages of high gain and high speed as a whole.
Drawings
Fig. 1 is a block diagram of a two-stage cascade high gain amplifier of the present invention.
Fig. 2 is a schematic diagram of a first stage self-adaptive biased cascode floating inverter amplifier circuit.
Fig. 3 is a schematic diagram of an inverting amplifier circuit with second stage current source bias.
Fig. 4 (a) is a schematic structural diagram of a common mode feedback circuit.
Fig. 4 (b) is a schematic structural diagram of a cascode compensation circuit.
FIG. 5 is a schematic diagram of two-phase non-overlapping clock signals used in the amplifier structure of the present invention.
Detailed Description
In order to more particularly describe the present invention, the following detailed description of the technical scheme of the present invention is provided with reference to the accompanying drawings and the specific embodiments.
As shown in fig. 1, the two-stage cascade high gain amplifier based on adaptive bias and cascode compensation of the present invention provides high gain by cascading a first stage amplifier and a second stage amplifier. The first stage amplifier adopts a self-adaptive bias common-source common-gate floating inverting amplifier circuit, the bias is changed into cross-coupled self-adaptive bias to improve the gain and the speed, an external bias circuit is omitted, meanwhile, the advantages of low noise and low power consumption are maintained, the second stage amplifier adopts a current source biased inverting amplifier to further improve the gain on the basis of the first stage amplifier, and the common-source common-gate compensation is utilized to ensure the stability while eliminating the zeroing resistance.
Examples
The two-stage cascade high gain amplifier in this embodiment is composed of a first-stage self-adaptively biased floating inverting amplifier circuit, a second-stage current source biased inverting amplifier circuit, a cascode compensation circuit, and a common mode feedback circuit. As shown in FIG. 2, the first stage self-adaptive bias common-gate floating inverter amplifier circuit comprises a PMOS tube M1, a PMOS tube M2, a PMOS tube M5, a PMOS tube M6, an NMOS tube M3, an NMOS tube M4, an NMOS tube M7, an NMOS tube M8, a capacitor C RES, a switch S1, a switch S2, a switch S3, a switch S4, a switch S5 and a switch S6, wherein M2 and M4 are used as positive input ends, M1 and M3 are used as negative input ends, M6 and M8 are used as loads of M2 and M4 respectively and used as negative output ends, M5 and M7 are used as loads of M1 and M3 respectively and used as positive output ends, S1, S2, S5 and S6 are closed in the reset stage of the amplifier, S1 and S2 respectively connect the upper and lower polar plates of C RES to VDD and GND, S5 and S6 respectively connect the positive output end and the negative output end to V CM, S3 and S4 are closed in the amplification stage of the amplifier, respectively connect the upper and lower polar plates of C RES to the V SP end and the V SN end, and supply power for the cascode floating inverting amplifier circuit. The upper plates of C RES are connected to the source terminals of VDD and M1 and M2 via S1 and S3, respectively, the lower plates of C RES are connected to the source terminals of GND and M3 and M4 via S2 and S4, respectively, the gate terminals of M1 and M2 are connected to the negative input terminal V IN and the positive input terminal V IP of differential input signals, respectively, the source terminals V SP of M1 and M2 are connected to the upper plates of C RES via S3, respectively, the drain terminals V BN1 and V BN2 of M1 and M2 are connected to the source terminals of M5 and M6, respectively, the drain terminals of M5 and M6 are connected to the source terminals of M8 and M7, respectively, the drain terminals of M5 and M6 are connected to the positive output terminals V OP1 and the negative output terminals V ON1 of differential input signals, respectively, the gate terminals of M3 and M4 are connected to the negative input terminals V IN and the positive input terminals V IP, respectively, the source terminals V SN of M3 and M4 are connected to the drain terminals of C37 and the drain terminals of M6, respectively, the drain terminals of M5 and M6 are connected to the positive output terminals V OP1 and V978 and the drain terminals of differential input signals, respectively, the drain terminals of M3 and M6 are connected to the drain terminals of M3 and M3.
As shown in fig. 3, the inverting amplifier circuit biased by the second-stage current source includes a PMOS transistor M9, a PMOS transistor M10, a PMOS transistor M13, an NMOS transistor M11, an NMOS transistor M12, an NMOS transistor M14, a switch S7, and a switch S8, wherein gate terminals of M9 and M11 are connected to a positive output terminal V OP1 of the differential output signal of the first-stage amplifier while being positive input terminals of the differential input signal of the second-stage amplifier, drain terminals of M9 and M11 are connected to a negative output terminal V ON of the differential output signal, gate terminals of M10 and M12 are connected to a negative output terminal V ON1 of the differential output signal of the first-stage amplifier while being negative input terminals of the differential input signal of the second-stage amplifier, the drain terminals of M10 and M12 are connected to the positive output terminal V OP of the differential output signal, the source terminals of M9 and M10 are connected to the drain terminal of M13, the source terminals of M11 and M12 are connected to the drain terminal of M14, the gate terminal of M13 is connected to V BP to generate a reference current to provide a constant current bias for the second stage amplifier, the source terminal of M13 is connected to VDD, the gate terminal of M14 is connected to the output terminal V CMFB of the amplifier AMP1 in the common mode feedback circuit to provide common mode feedback for the second stage amplifier, the source terminal of M14 is connected to GND, V OP and V ON are connected to V CM via S7 and S8, respectively, and S7 and S8 are closed during the reset phase of the amplifier.
As shown in fig. 4 (b), the cascode compensation circuit includes a capacitor C1, a capacitor C2, a capacitor C3, and a capacitor C4, wherein an upper plate of C1 is connected to V BP1, a lower plate of C1 is connected to V ON, an upper plate of C2 is connected to V BN1, a lower plate of C2 is connected to V ON, an upper plate of C3 is connected to V BP2, a lower plate of C3 is connected to V OP, an upper plate of C4 is connected to V BN2, and a lower plate of C4 is connected to V OP, providing frequency compensation for the two-stage amplifier, stabilizing the amplifier, and eliminating the need for a zeroing resistor while separating a main pole and a sub pole.
As shown in fig. 4 (a), the common mode feedback circuit includes a resistor R1, a resistor R2, and a double-ended input single-ended output amplifier AMP1, wherein the left end of R1 is connected to V OP, the right end of R1 is connected to V SENSE and to the left end of R2, the right end of R2 is connected to V ON, the positive input end of AMP1 is connected to voltage V SENSE generated by R1 and R2, the negative input end of AMP1 is connected to V CM, and the output end V CMFB of AMP1 is connected to the gate end of M14 to provide the voltage required for the common mode feedback for the second stage amplifier.
The two-stage cascade high gain amplifier of this embodiment operates as follows:
The gate terminals of M1 and M3, M2 and M4 are differential input terminals of the first stage, the drain terminals of M5, M7, M6 and M8 are differential output terminals of the first stage, and M1, M3, M2 and M4 receive the input voltage signal and generate a small signal output current g m*vin through their transconductance g m, which flows through the common gate loads M5, M7, M6 and M8 and is converted to an output voltage at the output terminals through an output impedance. The common gates M5, M7, M6 and M8 amplify the output impedance of the common source input transistors M1 and M3, M2 and M4 by a factor g m*ro, where r o is the small signal output resistance of the transistor.
As shown in fig. 5, in the reset phaseS1 and S2 are closed, the upper and lower plates of C RES are connected to VDD and GND respectively, and charged, at the same time S5, S6, S7 and S8 are closed, the outputs of first-stage amplifier and second-stage amplifier are connected to V CM for resetting, and in the amplifying stageS1, S2, S5, S6, S7 and S8 are open, while S3 and S4 are closed, and the upper and lower plates of C RES are connected to V SP and V SN, respectively, to provide power to the first stage amplifier.
Unlike the conventional mode of biasing the common-gate transistors M5, M7, M6 and M8 by V CM, the present embodiment adopts a cross-coupled adaptive bias mode to bias the common-gate transistors M5, M7, M6 and M8, specifically, the sources of M8 and M6 provide bias for the gates of M5 and M7 respectively, and the sources of M7 and M5 provide bias for the gates of M6 and M8 respectively, so that the bias voltages V BN1、VBN2、VBP1 and V BP2 are adaptively adjusted along with the operation of the amplifier, and have good robustness to PVT variation. Meanwhile, the overdrive voltage V OV generated in the way is larger than that of the overdrive voltage V OV generated in the way in the prior art, so that all transistors are ensured to work in a saturation region, the speed of the amplifier is increased, and the amplifier realizes larger drain current and higher slew rate than those of the amplifier in the way in which the overdrive voltages of M5, M7, M6 and M8 are increased. The self-adaptive bias is adopted, so that the input signal received by the common-source common-gate tube is from two parts, one part is that the amplification generated by the input tube g m on the input signal is input from the source end of the common-source common-gate tube, the other part is from the signal for providing the gate end bias, the source end of the common-source common-gate tube of the other half circuit is the drain end of the input tube of the other half circuit, and the other half input tube inputs the amplified input signal to the gate end of the common-source common-gate tube. According to the analysis and calculation, the gain of the floating inverting amplifier with the first stage self-adaptive bias is gm5ro5(gm1ro1+gm4ro4)+gm1ro1+gm7ro7(gm3ro3+gm2ro2)+gm3ro3,, which is far greater than that of the floating inverting amplifier adopting the traditional bias mode.
The second-stage amplifier is provided with bias current by M13 through V BP, the grid ends of M9, M11, M10 and M12 form a differential input end of the second stage, the drain ends of M9, M11, M10 and M12 form a differential output end of the second stage, M9, M11, M10 and M12 form a current multiplexing structure, the current utilization efficiency is greatly improved, the second-stage amplifier has higher output swing amplitude, the grid end of M14 automatically adjusts and maintains the common mode stability of the second-stage amplifier through the output of AMP1 in a common mode feedback circuit, and the output common mode voltage is perceived by two resistors R1 and R2. The gain of the second stage amplifier is (g m9+gm11)(ro9||ro11), so the total gain of the two-stage cascade amplifier is (gm9+gm11)(ro9||ro11)[gm5ro5(gm1ro1+gm4ro4)+gm1ro1+gm7ro7(gm3ro3+gm2ro2)+gm3ro3],, achieving the goal of high gain.
In order to maintain the stability of the two-stage cascade amplifier, the embodiment uses C1, C2, C3 and C4 to form a cascode compensation circuit, one end of the capacitor is connected to the output of the second-stage amplifier, the other end of the capacitor is connected to the source electrode of the load tube in the first-stage amplifier in a bridging way, and the feedforward path is cut off, so that the zero setting resistor required by the Miller compensation is eliminated while the stability is maintained.
The embodiments described above are described in order to facilitate the understanding and application of the present invention to those skilled in the art, and it will be apparent to those skilled in the art that various modifications may be made to the embodiments described above and that the general principles described herein may be applied to other embodiments without the need for inventive faculty. Therefore, the present invention is not limited to the above-described embodiments, and those skilled in the art, based on the present disclosure, should make improvements and modifications within the scope of the present invention.
Claims (5)
1. The two-stage cascade high-gain amplifier based on self-adaptive bias and cascode compensation is characterized by comprising two-stage amplifier cascades, wherein the first-stage amplifier forms self-adaptive bias through a cross coupling mode to improve the system gain, and the second-stage amplifier realizes higher current efficiency through current multiplexing to further improve the system gain and output swing;
The first-stage amplifier adopts a self-adaptive bias cascode floating inverting amplifier circuit, and the second-stage amplifier adopts a current source bias inverting amplifier circuit;
The self-adaptive bias common-gate floating inverting amplifier circuit comprises four PMOS tubes M1, M2, M5 and M6, four NMOS tubes M3, M4, M7 and M8, a capacitor C RES and six switches S1-S6, wherein one end of S1 is connected with a power supply voltage VDD, the other end of S1 is connected with one end of S3 and one end of C RES, the other end of S3 is connected with the source of M1 and the source of M2, the grid of M1 is connected with the grid of M3 and serves as an inverting voltage input end of a first-stage amplifier, the grid of M2 is connected with the grid of M4 and serves as a positive-phase voltage input end of the first-stage amplifier, the drain of M1 is connected with the source of M5 and the grid of M8, the drain of M2 is connected with the source of M6 and the grid of M7, the grid of M5 is connected with the source of M8, the grid of M6 is connected with the drain of M7, the drain of M5 is connected with the source of M7 and the drain of M3, the drain of M5 is connected with the drain of S7, the drain of M5 is connected with the drain of M4 and the other end of S4 is connected with the drain of the other end of M4 and the positive-phase voltage output end of the first-stage amplifier, the drain of M4 is connected with the other end of S4 and the positive-phase voltage of the first-phase voltage of M4 is connected with the drain of the first-stage amplifier, the drain of the positive-phase voltage of S4 is connected with the drain of the other end of S2; the gates of switches S1, S2, S5, S6 are coupled to clock signal φ 1, and the gates of switches S3, S4 are coupled to clock signal φ 2.
2. The two-stage cascade high gain amplifier according to claim 1, wherein the current source biased inverting amplifier circuit comprises three PMOS transistors M9, M10, M13, three NMOS transistors M11, M12, M14 and two switches S7-S8, wherein the source electrode of M13 is connected with the power supply voltage VDD, the grid electrode of M13 is externally connected with the bias voltage V BP, the drain electrode of M13 is connected with the source electrode of M9 and the source electrode of M10, the grid electrode of M9 is connected with the grid electrode of M11 and serves as the non-inverting voltage input end of the second stage amplifier, the grid electrode of M10 is connected with the grid electrode of M12 and serves as the inverting voltage input end of the second stage amplifier, the drain electrode of M9 is connected with one end of M11 and one end of S8 and serves as the inverting voltage output end of the second stage amplifier, the other end of S7 is connected with the other end of S8 and externally connected with the common mode voltage V CM, the grid electrode of M11 and the source electrode of M14 are connected with the drain electrode of M14, the drain electrode of M35 is connected with the drain electrode of M14, and the drain electrode of M35 is connected with the drain electrode of M14 of the second stage amplifier.
3. The two-stage cascade high gain amplifier according to claim 1 or 2, wherein the clock signal phi 1 is used to close the switch during the system reset phase, the clock signal phi 2 is used to close the switch during the system amplification phase, phi 1 is phase-complementary to phi 2 and has a dead time.
4. The two-stage cascade high gain amplifier according to claim 2, wherein the common mode feedback voltage V CMFB is generated by a common mode feedback circuit, the common mode feedback circuit comprises two resistors R1-R2 and an amplifier AMP1, wherein one end of R1 is connected with the positive phase voltage output end of the second stage amplifier, one end of R2 is connected with the negative phase voltage output end of the second stage amplifier, the other end of R1 is connected with the other end of R2 and the positive phase input end of AMP1, the negative phase input end of AMP1 is connected with a common mode voltage V CM, and the output end of AMP1 generates a common mode feedback voltage V CMFB.
5. The two-stage cascade high gain amplifier according to claim 1, wherein a cascode compensation circuit is provided between the two-stage amplifiers for providing frequency compensation for the two-stage amplifiers, and the cascode compensation circuit comprises four capacitors C1-C4, wherein one end of C1 is connected with the drain electrode of M3, one end of C2 is connected with the drain electrode of M1, the other end of C1 is connected with the other end of C2 in parallel with the inverting voltage output end of the second-stage amplifier, one end of C3 is connected with the drain electrode of M4, one end of C4 is connected with the drain electrode of M2, and the other end of C3 is connected with the other end of C4 in parallel with the non-inverting voltage output end of the second-stage amplifier.
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| US5847600A (en) * | 1996-04-26 | 1998-12-08 | Analog Devices, Inc. | Multi-stage high-gain high-speed amplifier |
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| US8441287B2 (en) * | 2004-09-20 | 2013-05-14 | The Trustees Of Columbia University In The City Of New York | Low voltage track and hold circuits |
| US7279974B2 (en) * | 2005-06-10 | 2007-10-09 | Texas Instruments Incorporated | Fully differential large swing variable gain amplifier |
| CN103825565B (en) * | 2012-11-16 | 2016-10-26 | 上海华虹宏力半导体制造有限公司 | Operational amplifier |
| CN103199807B (en) * | 2013-03-26 | 2015-09-09 | 电子科技大学 | Division based on inverter input structure compensates two-stage calculation amplifier |
| CN205681381U (en) * | 2016-06-06 | 2016-11-09 | 京东方科技集团股份有限公司 | Two-stage calculation amplifier |
| CN109672418A (en) * | 2018-12-19 | 2019-04-23 | 佛山臻智微芯科技有限公司 | A kind of high gain operational amplifier using feedforward compensation |
| CN114362688B (en) * | 2022-01-18 | 2025-08-19 | 芯聚威科技(成都)有限公司 | Rail-to-rail amplifier with dynamic bias current common mode feedback |
| CN115514332A (en) * | 2022-10-17 | 2022-12-23 | 成都微光集电科技有限公司 | Cascode amplifier |
| CN118868801B (en) * | 2024-06-26 | 2025-10-14 | 浙江大学 | Two-stage cascaded high-gain amplifier based on adaptive bias and cascode compensation |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5847600A (en) * | 1996-04-26 | 1998-12-08 | Analog Devices, Inc. | Multi-stage high-gain high-speed amplifier |
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| WO2026001762A1 (en) | 2026-01-02 |
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