CN118819732A - Interrupt virtualization processing method, device, equipment, and storage medium - Google Patents

Abstract

The present invention relates to an interrupt virtualization processing method, device, equipment, and storage medium, including writing a target virtual machine identifier and current state information of a target virtual machine entering interrupt processing into a virtual machine control structure; when controlling the target virtual machine to start, writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier; and controlling the target virtual machine to read the current state information of the target virtual machine from the target shadow register, so that the target virtual machine is restored to the state before the interrupt processing according to the current state information. The embodiment of the present invention improves the concurrent processing capability.

Description

Interrupt virtualization processing method, device, equipment, and storage medium

Technical Field

The present invention relates to the field of virtualization technology, and in particular to an interrupt virtualization processing method, device, equipment, and storage medium.

Background Art

In the specific implementation, when peripheral devices (such as keyboards, mice, printers, network interface cards, etc.) need the CPU (Central Processing Unit) in the physical device to process their needs, they enter interrupt processing, so that the CPU suspends the currently executing task so that the needs of the peripheral devices can be met in time. For example, assuming that the CPU is currently executing a computer hardware scanning task, when the user presses a key on the keyboard, the keyboard controller will send an interrupt request to notify the CPU that there is keyboard input data that needs to be processed. At this time, the CPU suspends the current computer hardware scanning task and enters interrupt processing.

Among them, when interrupt processing is implemented in a virtualized environment, interrupt processing can be called interrupt virtualization processing. A virtualized environment refers to a computing environment that includes one or more virtual machines (VMs), which are created and managed by a virtual machine monitor (VMM). In a virtualized environment, in response to an event in which an interrupt processing is triggered by a peripheral device, the attention of the vCPU (Virtual Central Processing Unit) assigned to the virtual machine by the virtual machine monitor needs to be attracted. The vCPU then enters interrupt processing so that the vCPU can prioritize the execution of peripheral device events. However, traditional interrupt processing methods may cause performance bottlenecks in the physical device (host machine) of the virtual machine, especially when interrupts to multiple virtual machines occur simultaneously.

Summary of the invention

The object of the present invention is to provide an interrupt virtualization processing method, which can reduce the impact of interrupt processing on the virtual machine performance of a physical device when interrupts of multiple virtual machines occur simultaneously.

In order to achieve the above object, an embodiment of the present invention provides an interrupt virtualization processing method, which is applied to a physical device, wherein the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and the virtual machines respectively have corresponding virtual machine identifiers, and the method includes:

Writing the target virtual machine identifier and current state information of the target virtual machine entering the interrupt processing into the virtual machine control structure;

When controlling the target virtual machine to start, writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier;

The target virtual machine is controlled to read the current state information of the target virtual machine from the target shadow register, so that the target virtual machine is restored to a state before interrupt processing according to the current state information.

Optionally, writing the target virtual machine identifier and current state information of the target virtual machine entering the interrupt processing into the virtual machine control structure includes:

When the target virtual machine is triggered to perform interrupt processing through the virtual machine monitor, the current status information of the target virtual machine is written into the virtual machine control structure of the target virtual machine before the target virtual machine exits, and the target virtual machine identifier and current status information of the target virtual machine are written into the virtual machine control structure.

Optionally, when the target virtual machine is triggered to perform interrupt processing through the virtual machine monitor, controlling the target virtual machine to write the current state information of the target virtual machine into the virtual machine control structure of the target virtual machine before exiting, and writing the target virtual machine identifier of the target virtual machine into the virtual machine control structure includes:

During the execution of the virtual machine, if the target virtual machine receives an interrupt signal sent by the virtual machine monitor, the target virtual machine is triggered to switch from the virtual machine mode to the virtual machine monitor mode;

Before controlling the target virtual machine to exit, the current state information of the target virtual machine is saved in a virtual machine control structure, and the target virtual machine identifier of the target virtual machine is written into the virtual machine control structure.

Optionally, the step of saving the current state information of the target virtual machine into a virtual machine control structure, and writing a target virtual machine identifier of the target virtual machine into the virtual machine control structure, comprises:

The current state information of the target virtual machine is saved in the client state area of the virtual machine control structure, and the target virtual machine identifier of the target virtual machine is written into the interrupt information field register of the virtual machine control structure.

Optionally, the method further comprises:

The virtual machine control structure of the virtual machine is configured.

Optionally, the virtual machine control structure of configuring the virtual machine includes:

configuring a control domain of the virtual machine control structure of the virtual machine;

The guest state area of the virtual machine control structure of the virtual machine is configured.

Optionally, before controlling the target virtual machine to exit, the method further includes:

The target virtual machine identifies an interrupt source and determines an interrupt type number according to the interrupt source;

According to the interrupt type number, the entry address of the corresponding interrupt service program is queried from the interrupt descriptor table of the shadow register, so as to jump to the interrupt service program for interrupt processing according to the entry address.

Optionally, the method further comprises:

The virtual machine startup instruction of the virtual machine is modified; when the modified virtual machine startup instruction is executed, the virtual machine identifier is read from the virtual machine control structure of the started virtual machine.

Optionally, when controlling the target virtual machine to start, reading the target virtual machine identifier of the target virtual machine from the virtual machine control structure of the target virtual machine includes:

When executing the modified virtual machine startup instruction to control the startup of the target virtual machine, triggering the target virtual machine to switch from the virtual machine monitor mode to the virtual machine mode;

A target virtual machine identifier of the target virtual machine is read from the virtual machine control structure of the target virtual machine.

Optionally, reading the target virtual machine identifier of the target virtual machine from the virtual machine control structure of the target virtual machine includes:

The virtual machine read instruction is executed to read the target virtual machine identifier of the target virtual machine from the interrupt information field register of the virtual machine control structure of the target virtual machine.

Optionally, after writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier, the method further includes:

Writing other contents of the virtual machine control structure of the target virtual machine into corresponding other registers; the other contents at least include the contents of the segment register.

Optionally, the number of the target virtual machines is one or more, and the number of the shadow registers is one or more.

An embodiment of the present invention also discloses an interrupt virtualization processing device, which is applied to a physical device, wherein the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and each virtual machine has a corresponding virtual machine identifier. The device is used to implement the method described in the embodiment of the present invention.

An embodiment of the present invention further discloses an electronic device, comprising at least one processor and a memory communicatively connected to the at least one processor;

The memory is used to store computer programs;

The processor is used to implement the method described in the embodiment of the present invention when executing the program stored in the memory.

The embodiment of the present invention further discloses a computer-readable storage medium on which a computer program is stored. When executed by one or more processors, the processors are enabled to execute the method described in the embodiment of the present invention.

Beneficial effects of the present invention:

The embodiment of the present invention is applied to a physical device, the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and the virtual machines have corresponding virtual machine identifiers. When one or more virtual machines trigger interrupt processing, the virtual machine entering the interrupt processing is used as the target virtual machine, and the current state information of the target virtual machine and the target virtual machine identifier are written into the virtual machine control structure; when the target virtual machine is controlled to start, the current state information of the virtual machine control structure of the target virtual machine is written into the target shadow register corresponding to the target virtual machine identifier, and the target virtual machine is controlled to read the current state information of the target virtual machine from the target shadow register, so that the target virtual machine is restored to the state before the interrupt processing according to the current state information. The embodiment of the present invention configures physical shadow registers for the processors of each virtual machine of the physical device respectively, and when one or more virtual machines enter the interrupt processing, they can be restored to the state before the interrupt processing in parallel through their corresponding shadow registers, thereby improving the concurrent processing capability of the physical device and reducing the impact of the interrupt processing on the performance of the virtual machines of the physical device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a method for generating interrupts of a conventional peripheral device in an Arm architecture;

FIG2 is a schematic diagram of a method for generating interrupts of a new peripheral device in an Arm architecture;

FIG3 is a schematic diagram of a hardware interrupt processing process under x86;

FIG4 is a schematic diagram of an implementation of hardware-assisted virtualization technology under x86;

FIG5 is a schematic diagram of a current implementation of interrupt virtualization of multiple virtual machines;

FIG6 is a flowchart of a method for processing interrupt virtualization provided in an embodiment of the present invention;

7 is a schematic diagram of an implementation of parallel interrupt virtualization of multiple virtual machines provided in an embodiment of the present invention;

FIG8 is a schematic diagram of a region of a VMCS provided in an embodiment of the present invention;

FIG9 is a schematic diagram of a control domain configuration of a VMCS provided in an embodiment of the present invention;

FIG10 is a second schematic diagram of a control domain configuration of a VMCS provided in an embodiment of the present invention;

FIG11 is a schematic diagram of a GUEST STATE AREA provided in an embodiment of the present invention;

FIG. 12 is a schematic diagram of the structure of an electronic device provided by an embodiment of the present invention.

DETAILED DESCRIPTION

The following will describe the embodiments of the present invention with reference to the accompanying drawings and preferred embodiments. Those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be understood that the preferred embodiments are only for illustrating the present invention, not for limiting the scope of protection of the present invention.

Referring to Fig. 1, it is a schematic diagram of an interrupt generation method of a traditional peripheral device in an Arm architecture provided in an embodiment of the present invention, wherein the peripheral device is connected to an interrupt controller via an interrupt connection line, and the peripheral device triggers an interrupt by sending an interrupt signal to the interrupt controller. Among them, IRQ is Interrupt Request, i.e., interrupt request, FIQ is Fast Interrupt Request, i.e., fast interrupt request, and Privileged Execution (PE) can be used to execute privileges such as IRQ and FIQ.

2 is a schematic diagram of a new interrupt generation method for a peripheral device in an Arm architecture provided in an embodiment of the present invention, wherein the peripheral device transmits an interrupt by means of a message (sending an interrupt message), and the message is transmitted to the bus.

The improvement of the above new solution is to pass the virtual interrupt generated by the virtual device to the interrupt controller in the form of a physical interrupt. However, in order to achieve this goal, a new hardware device is added. This device converts the interrupt information of the virtual timer (vTimer) into a physical interrupt signal, and then sends it to the interrupt controller through a message mechanism. The interrupt controller then sends it to the vCPU (Virtual Central Processing Unit) to implement the interrupt. The defects of this solution are as follows: First, new hardware devices need to be added, which increases the virtualization cost; second, the operating mechanism of the interrupt virtualization itself has not changed. Different virtual machines run virtual interrupts at the same time, and the interrupt handler can only be executed serially. The implementation of the hardware virtualization mechanism itself restricts the performance of interrupt virtualization.

3 is a schematic diagram of a hardware interrupt processing process under x86 provided in an embodiment of the present invention, and the specific process includes:

1) The CPU executes an instruction; 2) An interrupt occurs, and an interrupt signal is generated inside the CPU; 3) The CPU determines the source of the interrupt and generates an interrupt type code N; 4) The current CS/IP/PSW is pushed onto the stack; 5) IF and TF are cleared; 6) The new value of CS/IP is obtained (via IDT); 7) Enter the interrupt service routine; 8) Open the interrupt; 9) The IRET instruction pops the old CS/IP/PSW off the stack; 10) Return to the interrupted program. Among them, the CPU includes CS: code segment register; IP: Instruction Pointer, IP is also called EIP; FLAGS: flag register, among which the flag register includes carry flag (CF), zero flag (ZF), sign flag (SF), interrupt flag (IF), debug flag (TF), etc. PSW is Program Status Word. The IRET instruction is an instruction to return from an exception handler or interrupt service routine (ISR).

In practice, the interrupt handling process implemented by physical devices is as follows: 1. Turn off interrupts: the CPU turns off interrupt response, that is, it no longer receives other external interrupt requests; 2. Save breakpoints: push the instruction address where the interrupt occurs into the stack so that it can return correctly after the interrupt is processed; 3. Identify the interrupt source: the CPU identifies the source of the interrupt, determines the interrupt type number, and finds the entry address of the corresponding interrupt service program through the interrupt descriptor table (IDT); 4. Protect the scene: push the relevant registers where the interrupt occurs (registers to be used in the interrupt service program) and the contents of the flag register into the stack; 5. Execute the interrupt service program: jump to the entry address of the interrupt service program to start execution, and reopen the interrupt at an appropriate time to allow corresponding higher priority external interrupts; 6. Restore the scene and return: bounce the information pushed into the stack when "protecting the scene" back to the original register, and then return to execute the interrupt return instruction, thereby returning to the main program to continue running;

Among them, the storage address of the interrupt service program is located in the IDT (interrupt descriptor table). The interrupt vector number (interrupt type number) transmitted to the CPU by the interrupt finds the corresponding ISR (Interrupt Service Routine). Among them, IDT is globally unique. All CPUs share one IDT. After receiving an interrupt, the multi-core CPU will query the corresponding ISR (interrupt service program) in the IDT, because the interrupt service program of the entire X86 hardware is shared by the kernel programs running on all CPUs, and the same interrupt is handled in the same way.

Traditional hardware-assisted virtualization is implemented by interrupt injection. Although the performance is higher than that of pure software implementation, there is still a performance bottleneck. Taking X86 interrupt injection virtualization as an example, referring to FIG4 , which is a schematic diagram of an implementation of a hardware-assisted virtualization technology under x86 provided in an embodiment of the present invention, the specific process includes:

Step 1: The virtual interrupt controller uses the inter-processor interrupt (IPI) to return the virtual machine from the guest mode (virtual machine mode) to the host mode (VMM virtual machine monitor mode). The virtual machine now enters the hypervisor (virtual machine monitor) mode.

Step 2: Write the interrupt vector information, mainly the interrupt vector table vector information, into the vmcs (Virtual Machine Control Structure Region) area;

Step 3: Start the virtual machine through the vmresume or vmlaunch instruction; vmresume or vmlaunch is an instruction used for virtualization technology in the x86 architecture, and is used by a virtual machine monitor (Hypervisor) or a virtual machine manager (VMM) for startup and management.

The above is the injection process of virtual interrupts. The factors that affect the performance of the virtual machine are as follows: 1. First, the virtual machine needs to exit due to the virtual interrupt; 2. The implementation of virtual interrupt injection requires writing interrupt vector-related information to the interruptionfield in the memory area pointed to by the VMCS register; 3. Then it is necessary to schedule the interrupt injection through the operating system's process scheduling until the next time the virtual machine runs. For interrupt injection, the content of the GUEST STATE AREA (customer status area) in VMCS must first be restored to the physical CPU register, among which the IDTR (Interrupt Descriptor Table Register) register is related to the interrupt, and then the interrupt service program is found through IDTR and vector, and the corresponding interrupt service program is executed to handle the interrupt.

In summary, in the above interrupt virtualization, the problem that has a serious impact on performance is (virtual machine interrupt serialization, that is, virtual machines can only process interrupts in sequence). For example, referring to FIG5, a schematic diagram of the implementation of interrupt virtualization of multiple virtual machines at present is shown. The IDTR register (physical CPU-IDTR) is a global register, which is equivalent to only one virtual machine (vCPU-IDTR) or host machine occupying it at a time. That is to say, when a virtual machine uses the IDTR register, the remaining virtual machines or host machines can only wait for the next operation to use it. In particular, if the host machine frequently has interrupts, it will cause the virtual machine to exit frequently, and the virtual machine needs to frequently wait for the operation of the interrupt service program, which affects the performance of the virtual machine. Since the IDTR register is a physical global register of the CPU, there is only one. Therefore, when multiple virtual machines trigger interrupt processing, only one virtual machine in the multiple CPU cores can process the interrupt, converting parallel to serial, even if different virtual machines are running on different CPU cores, that is, multiple virtual interrupts of multiple virtual machines occur at the same time, these virtual interrupts are also performed in sequence.

In response to the above problems, an embodiment of the present invention provides an interrupt virtualization processing method for multiple virtual machines, which sets an IDTR shadow register for the CPU (vCPU) of each virtual machine of the physical device, that is, sets a set of IDTR register sets on the physical device. In this way, even if interrupts of multiple virtual machines occur at the same time, the virtual interrupts can be executed simultaneously, thereby ensuring concurrency and improving performance.

6, a flowchart of a method for processing interrupt virtualization provided in an embodiment of the present invention is shown, which is applied to a physical device, wherein the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and each virtual machine has a corresponding virtual machine identifier, and specifically includes the following steps:

Step 601: Write the target virtual machine identifier and current state information of the target virtual machine entering interrupt processing into the virtual machine control structure.

In an embodiment of the present invention, referring to FIG. 7, a schematic diagram of a multi-virtual machine parallel interrupt virtualization implementation provided in an embodiment of the present invention is provided. A physical device (host machine) may include multiple virtual machines, each virtual machine has its corresponding vCPU (processor), and a physically existing shadow register (IDTR Shadow) is set for the vCPU of each virtual machine. Each virtual machine or vCPU has a corresponding virtual machine identifier (CPUID), and the corresponding virtual machine in the physical device can be uniquely found based on the virtual machine identifier. Specifically, the shadow register is IDTR (Interrupt Descriptor Table Register), which is a special register in the x86 architecture, used to store the base address and limit of the interrupt descriptor table (Interrupt Descriptor Table, IDT), wherein the interrupt descriptor table is a key data structure, a key component used by the operating system kernel to manage interrupts and exception handling, and can be used to store the entry address of the interrupt service routine (Interrupt Service Routine, ISR). When the virtual machine triggers interrupt processing through the virtual machine monitor, the IDT is used to find the corresponding entry address to jump to the corresponding interrupt service routine. It can be seen that the shadow register of the embodiment of the present invention is a set of IDTR registers, and corresponds to each virtual machine respectively. In this way, even if the interrupt processing of multiple virtual machines occurs at the same time, the interrupt processing of the virtual machines can be executed at the same time, thereby ensuring concurrency and improving performance.

Optionally, the virtual machine monitor may be a type 2-hypervisor, which is a virtualization software running on top of an operating system. Unlike a Type 1 Hypervisor, a Type 2 Hypervisor does not run directly on the hardware of a physical device, but runs as an application on the operating system of the physical device.

The virtual machine has a VMCS (Virtual Machine Control Structure), which is a key data structure in the x86 architecture and is used to store and manage the state information of the virtual machine. VMCS is a mechanism used by the virtual machine monitor to control the execution of the virtual machine, allowing the virtual machine monitor to efficiently switch between the virtual machine and the host machine while maintaining the state isolation and integrity of the virtual machine. Among them, VMCS includes multiple domains (areas), referring to Figure 8, which can specifically include the following areas: CONTROL FIELDS (control domain): contains multiple control fields for configuring the execution behavior of the virtual machine, such as virtual interrupt control, virtual machine exit control, etc.; among them, CONTROL FIELDS includes VM-EXIT CONTROLFIELDS (virtual machine exit control field) and VM-EXIT INFORMATION FIELDS (virtual machine exit information field), among which VM-EXIT CONTROL FIELDS is used to control the behavior of the virtual machine exit, and VM-EXIT INFORMATION FIELDS is used to store relevant information when the virtual machine exits. Of course, VMCS can also include the following areas: GUEST STATE AREA area (guest state area): stores the state information of the virtual machine (Guest) during execution. The state information may include general registers, segment registers, flag registers, instruction pointers, stack pointers and other information. Based on this state information, it can be restored to the state before interrupt processing. When the virtual machine exits to the virtual machine monitor state, the current state information of the virtual machine will be saved in VMCS; VM Entry Controls (virtual machine entry control domain): contains settings for controlling the entry of the virtual machine, such as whether to enable virtual interrupts, whether to allow specific instructions to execute, etc. VMCS operates through a series of instructions that allow the virtual machine monitor to read and write data in VMCS, so that it can be based on the data in VMCS (such as the state information of the virtual machine) and control the execution of the virtual machine.

In one embodiment of the present invention, the step 601 of writing the target virtual machine identifier and current state information of the target virtual machine entering the interrupt processing into the virtual machine control structure includes:

When the target virtual machine is triggered to perform interrupt processing through the virtual machine monitor, the current state information of the target virtual machine is written into the virtual machine control structure of the target virtual machine before the target virtual machine exits, and the target virtual machine identifier of the target virtual machine is written into the virtual machine control structure.

In an embodiment of the present invention, when one or more virtual machines are triggered to perform interrupt processing through a virtual machine monitor (VMM), the virtual machine entering the interrupt processing is used as the target virtual machine, and the current state information of each target virtual machine is controlled to be written into its VMCS before exiting. At the same time, the target virtual machine identifier (CPUID) of the target virtual machine is written into its VMCS.

Step 602: When controlling the target virtual machine to start, write the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier.

In an embodiment of the present invention, when controlling the startup of the target virtual machine, for example, after the corresponding interrupt service program completes interrupt processing, the target virtual machine identifier (CPUID) saved before the target virtual machine exits can be obtained from the VMCS of the target virtual machine. In addition, the current state information of the VMCS of the target virtual machine is written into the target shadow register corresponding to the target virtual machine identifier (CPUID).

Step 603: Control the target virtual machine to read the current state information of the target virtual machine from the target shadow register, so that the target virtual machine is restored to the state before the interrupt processing according to the current state information.

In the embodiment of the present invention, according to the foregoing, the target shadow register of the target virtual machine has saved the current state information of the target virtual machine read from the VMCS. At this time, the target virtual machine can be controlled to read the current state information of the target virtual machine from the target shadow register, and then, the state before the interrupt processing can be restored based on the current state information.

The embodiment of the present invention is applied to a physical device, the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and the virtual machines have corresponding virtual machine identifiers. When one or more virtual machines trigger interrupt processing, the virtual machine entering the interrupt processing is used as the target virtual machine, and the current state information of the target virtual machine and the target virtual machine identifier are written into the virtual machine control structure; when the target virtual machine is controlled to start, the current state information of the virtual machine control structure of the target virtual machine is written into the target shadow register corresponding to the target virtual machine identifier, and the target virtual machine is controlled to read the current state information of the target virtual machine from the target shadow register, so that the target virtual machine is restored to the state before the interrupt processing according to the current state information. The embodiment of the present invention configures physical shadow registers for the processors of each virtual machine of the physical device respectively, and when one or more virtual machines enter the interrupt processing, they can be restored to the state before the interrupt processing in parallel through their corresponding shadow registers, thereby improving the concurrent processing capability of the physical device and reducing the impact of the interrupt processing on the performance of the virtual machines of the physical device.

In an embodiment of the present invention, when the target virtual machine is triggered to perform interrupt processing by the virtual machine monitor, controlling the target virtual machine to write the current state information of the target virtual machine into the virtual machine control structure of the target virtual machine before exiting, and writing the target virtual machine identifier of the target virtual machine into the virtual machine control structure, comprises:

During the execution of the virtual machine, if the target virtual machine receives an interrupt signal sent by the virtual machine monitor, the target virtual machine is triggered to switch from the virtual machine mode to the virtual machine monitor mode;

Before controlling the target virtual machine to exit, the current state information of the target virtual machine is saved in a virtual machine control structure, and the target virtual machine identifier is written into the virtual machine control structure.

In an embodiment of the present invention, during the execution of a virtual machine in a physical device, if one or more virtual machines (i.e., the target virtual machine) receives an interrupt signal sent by a virtual machine monitor (VMM), the target virtual machine will be triggered to switch from virtual machine mode (Guset mode) to virtual machine monitor mode (kernel mode), wherein, before controlling the target virtual machine to exit, the current state information of the target virtual machine can be saved in the VMCS, and the target virtual machine identifier (CPUID) of the target virtual machine can be written into the VMCS.

In the above example, before the target virtual machine exits, its current state information (i.e., registers, segment registers, flag registers, instruction pointer, stack pointer, etc.) is saved to VMCS. In this way, when the virtual machine is resumed again, its state can be restored by using VMCS and shadow registers, so that the virtual machine can seamlessly continue the previous execution process, thereby improving the stability of the virtualization environment.

In an embodiment of the present invention, the step of saving the current state information of the target virtual machine into a virtual machine control structure and writing the target virtual machine identifier into the virtual machine control structure comprises:

The current state information of the target virtual machine is saved in the client state area of the virtual machine control structure, and the target virtual machine identifier is written into the interrupt information field register of the virtual machine control structure.

Specifically, in the embodiment of the present invention, the current state information of the target virtual machine is saved in the GUESTSTATE AREA area of the VMCS, and the CPUID of the target virtual machine is written into the interruption-information field (interruption information field register) of the VMCS VM-Entry.

In one embodiment of the present invention, the method may further include:

The virtual machine control structure of the virtual machine is configured.

In a specific implementation, the VMCS of the virtual machine does not originally perform the processing of the embodiment of the present invention, such as storing the CPUID and writing the current state information of the virtual machine into the shadow register. Therefore, the embodiment of the present invention can configure the VMCS of the virtual machine before the virtual machine performs interrupt processing, so that it can implement the logic of multiple virtual machines executing interrupt processing in parallel in the embodiment of the present invention. It can be understood that since only the VMCS of the virtual machine needs to be configured, the embodiment of the present invention does not need to consume too much research and development costs.

In one embodiment of the present invention, the virtual machine control structure of configuring the virtual machine includes:

A control domain of the virtual machine control structure of the virtual machine is configured.

In an embodiment of the present invention, configuring the virtual machine control structure of the virtual machine may include configuring an interrupt control domain (control domain). Exemplarily, the interrupt vector configuration content of the interrupt control domain may include:

1) First, configure the control domain of VMCS, and operate the vmcs through the VMREAD and VMWRITE instructions: Specifically, referring to Figure 9, the relevant domains of VMCS are operated through the VMREAD and VMWRITE instructions. The control domain of vmcs is configured in the figure, so [11:10] is set to 0. The processor corresponding to the server is 64bit, so [14:13] is configured to 1.

2) Configure the interrupt vector number to be injected into the virtual machine: Specifically, referring to Figure 10, when interrupt injection is performed, the interrupt vector number that the virtual machine needs to execute is written to the 0-7 bits of the interruption-information field register of the VMCS VM-Entry, and the [10:8] bit is specified as 1, representing an external interrupt.

Due to the existence of the shadow register IDT (shadow page table/interrupt descriptor table), the content of the VMCS GUESTSTATE AREA area needs to be loaded into the shadow page table of the virtual machine (vCPU), which means that each virtual machine corresponds to an IDT. Therefore, it is necessary to clarify which vCPU the interrupt corresponds to. Therefore, the original registers need to be modified. The modified form is shown in the following table:

Among them, the position [30:26] corresponds to the CPUID of the logical CPU. Therefore, the IDTR register in the GUEST STATEAREA corresponding to this VMCS is loaded into the IDTR shadow page table of the shadow register of the physical CPU corresponding to the CPUID.

In one embodiment of the present invention, the virtual machine control structure of configuring the virtual machine includes:

The guest state area of the virtual machine control structure of the virtual machine is configured.

In an embodiment of the present invention, configuring the virtual machine control structure of the virtual machine may include configuring a guest state area. Exemplarily, the configuration of the content in the guest state area in the VMCS may include:

Referring to Figure 11, it is a schematic diagram of a GUEST STATE AREA area provided in an embodiment of the present invention. The GUEST STATE AREA area in the VMCS is configured by the vmwrite instruction, such as registers cs (Code Segment), ss (Stack Segment), ds (Data Segment), es (ExtraSegment) and other registers. These registers are not globally unique. The registers may also include an IDTR register. The above registers are all corresponding to a memory address on the host machine. The IDTR register address is filled with the host machine memory address. When the vmalunch instruction is executed, the register content in the GUEST STATE AREA stored in the VMCS memory address is filled into the register corresponding to the physical CPU.

In an embodiment of the present invention, before controlling the target virtual machine to exit, the method further includes:

The target virtual machine identifies an interrupt source and determines an interrupt type number according to the interrupt source;

According to the interrupt type number, the entry address of the corresponding interrupt service program is queried from the interrupt descriptor table of the shadow register, so as to jump to the interrupt service program for interrupt processing according to the entry address.

In an embodiment of the present invention, when the target virtual machine receives an interrupt signal from the VMM, the target virtual machine first needs to identify the interrupt source, where the interrupt source can be an external device, a timer, a software exception, etc., and then the interrupt type number can be determined based on the interrupt source. The interrupt type number (interrupt vector number) is a unique identifier. The interrupt type number can be used to index the entry address of the corresponding interrupt service routine (ISR) in the interrupt descriptor table (IDT) of the corresponding shadow register, and then jump to the corresponding ISR to execute the interrupt processing logic. In the above embodiment, the target virtual machine identifies the interrupt source and determines the interrupt type number, so that the virtual machine can accurately handle different interrupt sources and ensure that the interrupts can receive corresponding response processing.

In one embodiment of the present invention, the method may further include:

The virtual machine startup instruction of the virtual machine is modified; when the modified virtual machine startup instruction is executed, the virtual machine identifier is read from the virtual machine control structure of the started virtual machine.

In a specific implementation, a virtual machine startup instruction (vmlaunch instruction) can only start the execution of a virtual machine, wherein the vmlaunch instruction can be sent by a virtual machine monitor (VMM) to a virtual machine to control the execution process of the virtual machine. The embodiment of the present invention transforms the vmlaunch instruction so that in the embodiment of the present invention, when a virtual machine is started based on the vmlaunch instruction, the CPUID stored in the VMCS of the virtual machine can be written into the write shadow register to the current state information stored in the VMCS to achieve interrupt recovery of the virtual machine.

Specifically, the modified vmlauch instruction will perform the following operations:

1. The CPU switches from kernel mode to guest mode; 2. The interruption-information field [30:26] CPUID of VMCS VM-Entry (virtual machine resumes execution) is read through the vmread instruction; 3. The contents of the GUEST STATE AREA in VMCS are loaded into the corresponding registers of the physical CPU, such as cs is loaded into the cs segment selection register of the physical CPU, and ss is loaded into the stack selection register of the physical CPU. The change is that according to the CPUID mentioned above, the contents of the IDTR in the GUEST STATE AREA area of VMCS are loaded into the shadow register of the physical CPU core mapped by the virtual machine, so that interrupt processing of multiple virtual machines can be implemented based on the shadow register.

In an embodiment of the present invention, when controlling the target virtual machine to start, reading the target virtual machine identifier of the target virtual machine from the virtual machine control structure of the target virtual machine includes:

When executing the modified virtual machine startup instruction to control the startup of the target virtual machine, triggering the target virtual machine to switch from the virtual machine monitor mode to the virtual machine mode;

A target virtual machine identifier of the target virtual machine is read from the virtual machine control structure of the target virtual machine.

In an embodiment of the present invention, when the modified vmlauch instruction is executed to control the startup of the virtual machine, the original vmlaunch instruction will be operated as follows: the CPU (virtual machine) switches from kernel mode to guest mode, and the CPUID in the VMCS is read through the vmread instruction. Subsequently, the embodiment of the present invention will load the content in the IDTR in the GUESTSTATE AREA area of the VMCS into the shadow register corresponding to the physical CPU core CPUID mapped by the virtual machine according to the CPUID read from the VMCS.

In an embodiment of the present invention, the step of reading the target virtual machine identifier of the target virtual machine from the virtual machine control structure of the target virtual machine includes:

The virtual machine read instruction is executed to read the target virtual machine identifier of the target virtual machine from the interrupt information field register of the virtual machine control structure of the target virtual machine.

Specifically, the CPU (virtual machine) switches from kernel mode to guest mode, and reads [30:26]CPUID in the interruption-information field (interrupt information field register) of VMCSVM-Entry (virtual machine resume execution) through the vmread instruction.

In an embodiment of the present invention, after writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier, the method further includes:

Writing other contents of the virtual machine control structure of the target virtual machine into corresponding other registers; the other contents at least include the contents of the segment register.

In an embodiment of the present invention, other contents in the GUEST STATE AREA in the VMCS except the current state information and CPUID can be loaded into the corresponding registers of the physical CPU, such as cs is loaded into the cs segment selection register of the physical CPU, and ss is loaded into the stack selection register of the physical CPU.

It should be noted that, for the sake of simplicity, the method embodiments are described as a series of action combinations, but those skilled in the art should be aware that the embodiments of the present invention are not limited by the order of the actions described, because according to the embodiments of the present invention, certain steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions involved are not necessarily required by the embodiments of the present invention.

An embodiment of the present invention also discloses an interrupt virtualization processing device, which is applied to a physical device, wherein the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and the virtual machines respectively have corresponding virtual machine identifiers, and the device is used to execute the steps of the above-mentioned method embodiment.

The embodiment of the present invention is applied to a physical device, the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and the virtual machines respectively have corresponding virtual machine identifiers. When the target virtual machine is triggered to perform interrupt processing through the virtual machine monitor, the current state information of the target virtual machine is written into the virtual machine control structure of the target virtual machine before the target virtual machine is controlled to exit, and the target virtual machine identifier of the target virtual machine is written into the virtual machine control structure; when the target virtual machine is controlled to start, the target virtual machine identifier of the target virtual machine is read from the virtual machine control structure of the target virtual machine; the current state information of the virtual machine control structure of the target virtual machine is written into the target shadow register corresponding to the target virtual machine identifier; the target virtual machine is controlled to read the current state information of the target virtual machine from the target shadow register, so that the target virtual machine is restored to the state before the interrupt processing according to the current state information. The embodiment of the present invention configures physical shadow registers for the processors of each virtual machine of the physical device respectively, and when multiple virtual machines enter interrupt processing, they can be restored to the state before the interrupt processing in parallel through their corresponding shadow registers, thereby improving the concurrent processing capability of the physical device and reducing the impact of interrupt processing on the performance of the virtual machines of the physical device.

As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

The embodiment of the present invention also provides an electronic device, as shown in FIG12, including a processor 801, a device interface 802, and a memory.

803 and bus 804;

Memory 803, used for storing computer programs;

The processor 801 is used to execute the program stored in the memory 803, and implements the following steps:

When the target virtual machine is triggered to perform interrupt processing through the virtual machine monitor, the current state information of the target virtual machine is written into the virtual machine control structure of the target virtual machine before the target virtual machine exits, and the target virtual machine identifier and current state information of the target virtual machine entering the interrupt processing are written into the virtual machine control structure;

When controlling the target virtual machine to start, reading the target virtual machine identifier of the target virtual machine from the virtual machine control structure of the target virtual machine;

Writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier;

The target virtual machine is controlled to read the current state information of the target virtual machine from the target shadow register, so that the target virtual machine is restored to a state before interrupt processing according to the current state information.

The bus mentioned in the above terminal can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

The memory may include a random access memory (RAM) or a non-volatile memory, such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

The above-mentioned processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components.

The present invention also provides a storage medium. When the instructions in the storage medium are executed by the processor of the electronic device, the electronic device can execute the interrupt virtualization processing method of the above embodiment.

As for the device embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment.

The algorithm and display provided herein are not inherently related to any particular computer, virtual device or other equipment. According to the above description, it is obvious that the structure required for constructing this type of device is. In addition, the present invention is not directed to any specific programming language. It should be understood that various programming languages can be utilized to realize the content of the present invention described herein, and the description of the above specific language is to disclose the best mode of the present invention.

In the description provided herein, a large number of specific details are described. However, it is understood that embodiments of the present invention can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

Similarly, it should be understood that in order to streamline the present invention and aid in understanding one or more of the various inventive aspects, in the above description of exemplary embodiments of the present invention, various features of the present invention are sometimes grouped together into a single embodiment, figure, or description thereof. However, this disclosed method should not be interpreted as reflecting the following intention: that the claimed invention requires more features than those expressly recited in each claim. Rather, as reflected in the claims below, inventive aspects lie in less than all of the features of the individual embodiments disclosed above. Therefore, the claims that follow the detailed description are hereby expressly incorporated into the detailed description, with each claim itself serving as a separate embodiment of the present invention.

Those skilled in the art will appreciate that the modules in the devices in the embodiments may be adaptively changed and arranged in one or more devices different from the embodiments. The modules or units or components in the embodiments may be combined into one module or unit or component, and in addition they may be divided into a plurality of submodules or subunits or subcomponents. Except that at least some of such features and/or processes or units are mutually exclusive, all features disclosed in this specification (including the accompanying claims, abstracts and drawings) and all processes or units of any method or device disclosed in this manner may be combined in any combination. Unless otherwise expressly stated, each feature disclosed in this specification (including the accompanying claims, abstracts and drawings) may be replaced by an alternative feature providing the same, equivalent or similar purpose.

The various component embodiments of the present invention may be implemented in hardware, or in software modules running on one or more processors, or in a combination thereof. It should be understood by those skilled in the art that a microprocessor or digital signal processor (DSP) may be used in practice to implement some or all of the functions of some or all of the components in the sorting device according to the present invention. The present invention may also be implemented as a device or apparatus program for executing part or all of the methods described herein. Such a program for implementing the present invention may be stored on a computer-readable medium, or may be in the form of one or more signals. Such a signal may be downloaded from an Internet website, or provided on a carrier signal, or provided in any other form.

It should be noted that the above embodiments illustrate the present invention rather than limit it, and that those skilled in the art may devise alternative embodiments without departing from the scope of the appended claims. In the claims, any reference symbol between brackets shall not be construed as a limitation on the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "one" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present invention may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of devices, several of these devices may be embodied by the same hardware item. The use of the words first, second, and third, etc., does not indicate any order. These words may be interpreted as names.

Those skilled in the art can clearly understand that, for the convenience and brevity of description, the specific working processes of the above-described devices, apparatuses and units can refer to the corresponding processes in the aforementioned method embodiments and will not be repeated here.

The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the protection scope of the present invention.

The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any person skilled in the art can easily think of changes or substitutions within the technical scope disclosed by the present invention, which should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

It should be noted that the various data-related processes in the embodiments of the present application are all carried out in compliance with the corresponding data protection laws and policies of the country where the device is located, and with the authorization given by the owner of the corresponding device.

Claims (15)

1. An interrupt virtualization processing method, which is applied to a physical device, wherein the physical device comprises a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and the virtual machines respectively have corresponding virtual machine identifiers, and the method comprises:

Writing a target virtual machine identifier and current state information of a target virtual machine entering interrupt processing into the virtual machine control structure;

when the target virtual machine is controlled to start, writing the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identifier;

And controlling the target virtual machine to read the current state information of the target virtual machine from the target shadow register so as to enable the target virtual machine to recover the state before interrupt processing according to the current state information.

2. The method of claim 1, wherein writing the target virtual machine identification and current state information of the target virtual machine entering interrupt processing to the virtual machine control structure comprises:

When the virtual machine monitor triggers a target virtual machine to perform interrupt processing, the current state information of the target virtual machine is controlled to be written into a virtual machine control structure of the target virtual machine before the target virtual machine exits, and a target virtual machine identifier of the target virtual machine is controlled to be written into the virtual machine control structure.

3. The method according to claim 2, wherein controlling the writing of current state information of a target virtual machine into a virtual machine control structure of the target virtual machine before the target virtual machine exits and writing a target virtual machine identification of the target virtual machine into the virtual machine control structure when a target virtual machine is triggered by the virtual machine monitor for interrupt processing includes:

In the process of executing the virtual machine, if the target virtual machine receives an interrupt signal sent by the virtual machine monitor, triggering the target virtual machine to switch from a virtual machine mode to a virtual machine monitor mode;

Before the target virtual machine is controlled to exit, the current state information of the target virtual machine is stored in a virtual machine control structure, and a target virtual machine identification of the target virtual machine is written in the virtual machine control structure.

4. The method of claim 3, wherein the saving of the current state information of the target virtual machine into a virtual machine control structure and the writing of the target virtual machine identification of the target virtual machine into the virtual machine control structure comprises:

storing the current state information of the target virtual machine into a client state area of a virtual machine control structure, and writing a target virtual machine identification of the target virtual machine into an interrupt information field register of the virtual machine control structure.

5. The method according to claim 4, wherein the method further comprises:

and configuring the virtual machine control structure of the virtual machine.

6. The method of claim 5, wherein said configuring the virtual machine control structure of the virtual machine comprises:

configuring a control domain of the virtual machine control structure of the virtual machine;

The guest state area of the virtual machine control structure of the virtual machine is configured.

7. The method of claim 1, wherein prior to controlling the target virtual machine to exit, the method further comprises:

the target virtual machine identifies an interrupt source and determines an interrupt type number according to the interrupt source;

And inquiring an entry address of a corresponding interrupt service routine from an interrupt descriptor table of the shadow register according to the interrupt type number so as to jump to the interrupt service routine according to the entry address to perform interrupt processing.

8. The method according to claim 1, wherein the method further comprises:

modifying a virtual machine starting instruction of the virtual machine; and when the modified virtual machine starting instruction is executed, reading a virtual machine identifier from a virtual machine control structure of the started virtual machine.

9. The method of claim 8, wherein the reading the target virtual machine identification of the target virtual machine from the virtual machine control structure of the target virtual machine when controlling the target virtual machine to boot comprises:

triggering the target virtual machine to switch from a virtual machine monitor mode to a virtual machine mode when the virtual machine starting instruction after the modification is executed controls the target virtual machine to start;

and reading a target virtual machine identification of the target virtual machine from the virtual machine control structure of the target virtual machine.

10. The method of claim 9, wherein the reading the target virtual machine identification of the target virtual machine from the virtual machine control structure of the target virtual machine comprises:

And executing a virtual machine reading instruction to read a target virtual machine identification of the target virtual machine from an interrupt information field register of the virtual machine control structure of the target virtual machine.

11. The method of claim 1, wherein after the writing of the current state information of the virtual machine control structure of the target virtual machine into a target shadow register corresponding to the target virtual machine identification, the method further comprises:

Writing other contents of the virtual machine control structure of the target virtual machine into corresponding other registers; the other content includes at least the content of the segment register.

12. The method of claim 1, wherein the target virtual machine is one or more and the shadow register is one or more.

13. Interrupt virtualization processing apparatus, applied to a physical device, where the physical device includes a virtual machine monitor, each virtual machine of the physical device is configured with a shadow register, and each virtual machine has a corresponding virtual machine identifier, and the apparatus is configured to perform an interrupt virtualization processing method according to any one of claims 1 to 12.

14. An electronic device, comprising:

A processor;

A memory for storing processor-executable instructions;

wherein the processor is configured to execute the instructions to implement the interrupt virtualization processing method of any one of claims 1 to 12.

15. A computer readable storage medium, characterized in that instructions in said storage medium, when executed by a processor of a mobile terminal, enable the mobile terminal to perform the interrupt virtualization processing method according to any one of claims 1 to 12.