CN118819383A - Data storage method, device, storage device and computer readable storage medium - Google Patents

Abstract

The application discloses a data storage method, a data storage device and a computer readable storage medium. The data storage method comprises the following steps: acquiring a programming command sent by a flash memory conversion layer; acquiring a target hardware array stripe distributed by a target logic array stripe corresponding to the programming command; judging whether the target hardware array strip is matched with the target logic array strip or not; if not, performing memory export operation on the target hardware array stripe; the program command is executed with the target hardware array stripe. The scheme can effectively support the simultaneous programming of a plurality of logic array strips.

Description

Data storage method, device, storage equipment and computer readable storage medium

Technical Field

The present application relates to the field of storage technologies, and in particular, to a data storage method, apparatus, storage device, and computer readable storage medium.

Background

NAND FLASH is used as a nonvolatile storage medium, and has the advantages of low cost, high speed, low power consumption and the like, so that better experience is brought to users, and NAND FLASH is widely applied to various storage devices. In a solid state disk system, especially an enterprise-level solid state disk, according to the characteristics of a NAND memory, in order to protect user data and key system data in the hard disk to a greater extent, redundancy check data parity needs to be generated through a group RAID STRIPE (array stripe) to realize data protection. The algorithm for generating the parity in the solid state disk RAID STRIPE is LUN0XOR LUN1 XOR LUN2 XOR … … XOR LUNx =parity; assuming that the data of the LUN1 is wrong, the data of the LUN1 can be recovered by the data of other LUNs (logical units) and the parity, that is, lun1=lun0 XOR lun2 XOR … … XOR LUNx XOR parity, where RAID STRIPE is consistent in length, that is, the number of the RAID LUNs in the group is consistent, and the specific location of the parity may not be fixed.

The fact that RAID STRIPE is composed of multiple LUN programming data requires that the solid state disk provide a block of RAID BUFFER (array cache) during programming to write different NAND LUN data as the space for the middle parity during cache programming of each RAID STRIPE, which block of RAID BUFFER can only be used by the next RAID STRIPE after the parity of RAID STRIPE is also written to NAND. The more RAID STRIPE are programmed simultaneously, the larger the required RAID BUFFER is, which causes high cost, and the more RAID STRIPE are required to be programmed simultaneously in the solid state disk system due to the existence of user thermal data, GC (Garbage Collection ), equalization and system data programming. There is therefore a need to provide a data storage method, apparatus, storage device and computer readable storage medium to address this RAID STRIPE programming implementation problem in the case of relatively tight RAID BUFFER resources of the storage controller.

Disclosure of Invention

The application mainly solves the technical problem of providing a data storage method, a data storage device and a computer readable storage medium, which can effectively support the simultaneous programming of a plurality of logic array strips.

In order to solve the above problems, a first aspect of the present application provides a data storage method, including: acquiring a programming command sent by a flash memory conversion layer; acquiring a target hardware array stripe distributed by a target logic array stripe corresponding to the programming command; judging whether the target hardware array strip is matched with the target logic array strip or not; if not, performing memory export operation on the target hardware array stripe; the program command is executed with the target hardware array stripe.

The obtaining the programming command sent by the flash memory conversion layer includes: distributing a programming unit for programming management of data to be written, and acquiring address information of the programming unit; determining an array command correspondingly executed by a target logic unit according to the target logic unit in the programming unit; updating information of a target logic array stripe to which the target logic unit belongs in a logic array stripe management table; and generating the programming command according to the address information of the programming unit, the information of the target logic array strip and the type of the data to be written, and sending the programming command to the back-end hardware through the flash memory conversion layer.

The updating, in the logical array stripe management table, the information of the target logical array stripe to which the target logical unit belongs includes: and when the target logic unit is the initial logic unit of the target logic array stripe, a new logic array stripe identifier is allocated for the target logic array stripe, and a corresponding external memory buffer is allocated for the new logic array stripe identifier.

The obtaining the target hardware array stripe allocated by the target logic array stripe corresponding to the programming command includes: judging whether the target logic array strip is distributed with a hardware array strip or not; if the target logic array strip is not allocated with the hardware array strip, allocating the target hardware array strip for the target logic array strip; and if the target logical array stripe is allocated to the target hardware array stripe, executing the step of judging whether the target hardware array stripe is matched with the target logical array stripe.

Wherein said allocating said target hardware array stripe for said target logical array stripe comprises: judging whether an idle hardware array strip exists or not; if so, allocating idle target hardware array strips for the target logic array strips; and if the target hardware array stripe does not exist, selecting to perform memory swap operation on the target hardware array stripe, and then distributing the target hardware array stripe to the target logic array stripe.

Wherein said executing said programming command with said target hardware array stripe comprises: judging whether the target logic array strip is in a memory swap-out state or not; if the target logic array stripe is not in the memory swap-out state, completing the programming operation of the data to be written by utilizing the target hardware array stripe; and if the target logic array strip is in the memory swap-out state, performing memory swap-in operation on the target hardware array strip, and then completing programming operation of data to be written by utilizing the target hardware array strip.

The data storage method further comprises the following steps: and after the exclusive OR operation corresponding to the target logic array stripe is completed, writing the redundancy check data in the target hardware array stripe into the corresponding logic unit, and releasing the target hardware array stripe.

In order to solve the above-described problems, a second aspect of the present application provides a data storage device comprising: the acquisition module is used for acquiring a programming command sent by the flash memory conversion layer and acquiring a target hardware array strip distributed by a target logic array strip corresponding to the programming command; the judging module is used for judging whether the target hardware array strip is matched with the target logic array strip or not; the processing module is used for performing memory swap-out operation on the target hardware array stripe when the target hardware array stripe is not matched with the target logic array stripe; and executing the programming command with the target hardware array stripe.

To solve the above-described problems, a third aspect of the present application provides a storage device including a processor and a memory connected to each other; the memory is configured to store program instructions and the processor is configured to execute the program instructions to implement the data storage method of the first aspect.

In order to solve the above-mentioned problems, a fourth aspect of the present application provides a computer-readable storage medium having stored thereon program instructions which, when executed by a processor, implement the data storage method of the first aspect described above.

The beneficial effects of the application are as follows: in comparison with the prior art, the method and the device have the advantages that the target hardware array strips distributed by the target logic array strips corresponding to the programming commands are obtained, whether the target hardware array strips are matched with the target logic array strips or not is judged, when the target hardware array strips are not matched with the target logic array strips, memory swap-out operation is carried out on the target hardware array strips, and then the programming commands are executed by utilizing the target hardware array strips. Under the condition that the hardware array cache resources inside the controller are limited, the hardware array cache inside the controller is combined with the memory outside the controller, and a plurality of logic array stripes can be effectively supported to be programmed simultaneously through RAID memory exchange operation.

Drawings

FIG. 1 is a flow chart of an embodiment of a data storage method of the present application;

FIG. 2 is a schematic diagram illustrating the division of array stripes in an application scenario of the present application;

FIG. 3 is a schematic diagram illustrating the partitioning of a hardware array stripe in an application scenario of the present application;

FIG. 4 is a flowchart illustrating an embodiment of step S11 in FIG. 1;

FIG. 5 is a flowchart illustrating an embodiment of step S12 in FIG. 1;

FIG. 6 is a flowchart illustrating an embodiment of step S122 in FIG. 5;

FIG. 7 is a flowchart of the step S15 in FIG. 1;

FIG. 8 is a flow chart of a method of data storage in an application scenario of the present application;

FIG. 9 is a schematic diagram illustrating the structure of an embodiment of a data storage device according to the present application;

FIG. 10 is a schematic diagram illustrating the structure of an embodiment of a memory device of the present application;

FIG. 11 is a schematic diagram of a computer-readable storage medium according to an embodiment of the present application.

Detailed Description

The following describes embodiments of the present application in detail with reference to the drawings.

In the following description, for purposes of explanation and not limitation, specific details are set forth such as the particular system architecture, interfaces, techniques, etc., in order to provide a thorough understanding of the present application.

The terms "system" and "network" are often used interchangeably herein. The term "and/or" is herein merely an association relationship describing an associated object, meaning that there may be three relationships, e.g., a and/or B, may represent: a exists alone, A and B exist together, and B exists alone. In addition, the character "/" herein generally indicates that the front and rear associated objects are an "or" relationship. Further, "a plurality" herein means two or more than two.

Referring to fig. 1, fig. 1 is a flowchart illustrating an embodiment of a data storage method according to the present application. The data storage method in this embodiment includes the following steps:

step S11: and acquiring a programming command sent by the flash memory conversion layer.

Step S12: and acquiring a target hardware array stripe distributed by a target logic array stripe corresponding to the programming command.

The data storage method can be applied to solid state disks, and can also be applied to other storage devices taking NAND FLASH as storage media. The data storage method of the application mainly realizes RAID function of a storage controller, and a hardware array cache memory (HW RAID BUFFER memory) is required to be arranged in the controller and used as a storage space for redundancy check data (parity) in the exclusive or (XOR) operation process of an array stripe (RAID STRIPE). The system data existing in the solid state disk is generally SLC mode programming, the user data is generally TLC mode programming or QLC mode programming according to the NAND used, and the programming command unit of the FTL (flash translation layer) is that a plurality of pages on the WL (Word Line) are programmed together, and each page of the WL performs RAID operation by using different array cache IDs. Therefore, the size of the hardware array cache memory in the controller at least meets the size of an array stripe cache of one SLC programming unit plus one TLC programming unit, and the array cache memory is divided into small blocks according to the size of a NAND page to be managed, and the hardware array cache memory is bound with an array cache ID when in use, and only the array cache ID needs to be configured when firmware sends a RAID programming command.

Referring to fig. 2 in combination, fig. 2 is a schematic diagram illustrating the division of an array stripe in an application scenario of the present application, a page of a plurality of LUNs is bound to an array stripe (RAID STRIPE), the lengths of each group RAID STRIPE are consistent, i.e. the numbers of LUNs in each group RAID STRIPE are consistent, the parity is generated according to data exclusive or written into other LUNs, the data used for protecting the written data of the other LUNs may not be fixed in the specific location of the parity in each group RAID STRIPE. For example, when a request for writing data to be written is received, the data to be written may be sequentially written into LUNs 1 to LUNx of RAID STRIPE, and XOR (exclusive or) operation is performed on the data to be written, and when the XOR operation is completed on the data to be written to obtain redundancy check data (parity), the redundancy check data may be written into LUNy; thus, the data to be written and the redundancy check data together form a raid group (redundant array of disks) which can be recovered by other data and the redundancy check data when any one of the data to be written has an error.

Referring to fig. 3, fig. 3 is a schematic diagram illustrating division of hardware array stripes in an application scenario of the present application, where the structure of a hardware array cache in a storage controller of a storage device of the present application is shown in fig. 3, the hardware array cache is divided into a plurality of hardware array cache IDs for management, each cache ID corresponds to a buffer space with a page size, and when in use, the cache IDs are grouped into M hardware array stripes according to RAID PLANE numbers (number of array planes), and the hardware array stripes are allocated to a logic array stripe by a Back end for performing RAID exclusive-or operation. For example, when the hardware array cache size is 256KB, one PLANE PAGE is 16KB, and NAND is programmed with multiple planes, if RAID PLANE number is 4 planes, then the supportable hardware array stripe is 4.

Step S13: and judging whether the target hardware array strip is matched with the target logic array strip or not. If not, step S14 is executed, and if so, the target hardware array stripe is directly utilized to complete the programming operation of the data to be written.

Step S14: and if the target hardware array stripes are not matched, performing memory export operation on the target hardware array stripes.

Step S15: the program command is executed with the target hardware array stripe.

It can be appreciated that, upon receiving a programming command from the FTL, parsing a target logical array stripe from the programming command and determining a target hardware array stripe allocated for the target logical array stripe, then checking whether the target hardware array stripe matches the target logical array stripe, if so, indicating that the target logical array stripe matches the target hardware array stripe, then directly executing the programming command with the target hardware array stripe, and continuing the XOR operation programming; if the target hardware array stripe is not matched, performing memory SWAP-OUT operation on the target hardware array stripe, performing old stripe in the SWAP OUT target hardware array stripe, and then executing a programming command by using the target hardware array stripe.

According to the scheme, the target hardware array strips distributed by the target logic array strips corresponding to the programming commands are obtained, whether the target hardware array strips are matched with the target logic array strips or not is judged, when the target hardware array strips are not matched with the target logic array strips, memory swap-out operation is carried out on the target hardware array strips, and then the programming commands are executed by utilizing the target hardware array strips. Under the condition that the hardware array cache resources inside the controller are limited, the hardware array cache inside the controller is combined with the memory outside the controller, and a plurality of logic array stripes can be effectively supported to be programmed simultaneously through RAID memory exchange operation.

Specifically, the controller in the present application supports firmware to manage relevant commands of RAID operation, including the following RAID commands (RAID command):

Firmware FW needs to ensure that the stripe issues programming commands in the START, XOR, XOR, XOR, parity out order, the controller's storage controller can support out-of-order data transfer, XOR data command may arrive RAID ENGINE (RAID engine) earlier than RAID START command (RAID start command), but the first command of RAID STRIPE must be RAID START command, so RAID ENGINE can support adjusting RAID command. The controller automatically checks the execution status of the RAID operation related commands and the RAID BUFFER status, for example, when performing RAID memory SWAP operations, the firmware directly sends RAID STRIPE END commands, RAID SWAP OUT commands, SWAP IN commands and XOR commands to RAID ENGINE of the storage controller without the firmware checking whether the last RAID command is completed between each operation command.

Referring to fig. 4, fig. 4 is a flowchart illustrating an embodiment of step S11 in fig. 1. In an embodiment, the step S11 specifically includes:

step S111: and distributing a programming unit for programming management of data to be written, and acquiring address information of the programming unit.

Step S112: and determining an array command correspondingly executed by the target logic unit according to the target logic unit in the programming unit.

Step S113: and updating information of the target logic array strip to which the target logic unit belongs in a logic array strip management table.

Step S114: and generating the programming command according to the address information of the programming unit, the information of the target logic array strip and the type of the data to be written, and sending the programming command to the back-end hardware through the flash memory conversion layer.

The data storage method of the application realizes the management of the logic RAID STRIPE through the FTL, the FTL RAID module is set to support N logics RAID STRIPE, and the logic RAID STRIPE table A (namely a logic array strip management table) is used for management, and the information structure of each logic RAID STRIPE is maintained in the table A as follows:

FTL needs to support user host data writing, GC, balanced data writing, and various types of management data writing of the system, which will be written in different NAND blocks (memory blocks) and possibly at the same time. FTLs will therefore program them with different blocks, managing each type of data programming with cursor (i.e., different programming blocks allocated for different types of data), each cursor programming requires a respective XOR operation per RAID STRIPE to obtain a respective parity. The FTL executes the following program flow: firstly, distributing PU (polyurethane) for cursor applications to be written, namely address information of the program unit, including block, LUN, page, block bad bitmap (bad block table mapping) and other information; then, according to the LUN address in the PU, RAID command which should be executed by the LUN is calculated from an array stripe composition algorithm of the RAID module, and information such as RAID command, XOR LUN count and the like in a corresponding logic array stripe ID in the table A is updated; and then composing a programming message command of the FTL to the BE according to the PU address, the logic array stripe ID and the type of the data to BE written. It can be understood that, after the FTL receives the response of completing the programming message command, ready LUN count information in the corresponding logical array stripe ID in the table a is updated in real time; the logical array stripe ID is released when the data and parity of all LUNs in the logical array stripe ID are programmed.

In an embodiment, the step S113 may specifically include: and when the target logic unit is the initial logic unit of the target logic array stripe, a new logic array stripe identifier is allocated for the target logic array stripe, and a corresponding external memory buffer is allocated for the new logic array stripe identifier. Specifically, when the LUN address is the starting LUN of RAID STRIPE, a new logical array stripe ID is allocated, and External memory buffer (external memory buffer, which is the storage space allocated on DRAM for RAID buffer) is allocated for the allocated logical array stripe ID.

Referring to fig. 5, fig. 5 is a flowchart of an embodiment of step S12 in fig. 1. In an embodiment, the step S12 specifically includes:

Step S121: and judging whether the target logic array strip is allocated with a hardware array strip or not. If the target logical array stripe is not allocated with a hardware array stripe, step S122 is performed, and if the target logical array stripe is allocated with the target hardware array stripe, step S13 is performed.

Step S122: the target hardware array stripe is allocated for the target logical array stripe.

In the RAID module at the back end of the BE, after receiving a programming command sent by the FTL, whether a corresponding hardware array stripe is allocated to a target logic array stripe corresponding to the programming command needs to BE checked, and if not, the corresponding hardware array stripe is allocated to the target logic array stripe for the parity in the storage process.

Referring to fig. 6, fig. 6 is a flowchart illustrating an embodiment of step S122 in fig. 5. In an embodiment, the step S122 specifically includes:

Step S1221: it is determined whether there is a free hardware array stripe. If there is a free hardware array stripe, step S1222 is performed, and if there is no free hardware array stripe, step S1223 is performed.

Step S1222: and allocating idle target hardware array stripes to the target logic array stripes.

Step S1223: and selecting to perform memory swap-out operation on the target hardware array strip, and distributing the target hardware array strip to the target logic array strip.

It can be appreciated that when the target logical array stripe corresponding to the program command does not allocate a corresponding hardware array stripe, the corresponding hardware array stripe needs to be allocated to the target logical array stripe, firstly, whether a free hardware array stripe exists needs to be checked, and if the free target hardware array stripe exists, the free target hardware array stripe is allocated to the current target logical array stripe; if no spare target hardware array stripe is available for allocation, then the target hardware array stripe is selected for a SWAP operation, specifically, the old stripe information in the SWAP OUT target hardware array stripe is available, and then the target hardware array stripe is allocated for use by the received target logical array stripe.

Referring to fig. 7, fig. 7 is a flowchart of an embodiment of step S15 in fig. 1. In an embodiment, the step S15 specifically includes:

step S151: and judging whether the target logic array strip is in a memory swap-out state or not. If the target logical array stripe is not in the memory swap-out state, step S152 is performed, and if the target logical array stripe is in the memory swap-out state, step S153 is performed.

Step S152: and completing the programming operation of the data to be written by utilizing the target hardware array stripe.

Step S153: and performing memory swap-in operation on the target hardware array strip, and then completing programming operation of data to be written by utilizing the target hardware array strip.

After the target logical array stripe and the target hardware array stripe are determined to be matched with each other, the target hardware array stripe can be used for storing the redundancy of the target logical array stripe IN the XOR operation programming process, but before the programming operation is performed, whether the target logical array stripe is IN a memory SWAP-out state needs to be judged, namely whether the related information about the target logical array stripe originally stored IN the target hardware array stripe is swapped out needs to be determined, if so, the SWAP IN operation is performed firstly to SWAP the related information about the target logical array stripe into the target hardware array stripe, then the XOR operation programming is continuously performed, and otherwise, the XOR operation programming can be continuously performed directly.

The data storage method of the application realizes the management of the hardware array BUFFER (HW RAID BUFFER) and the operation implementation of the RAID and SWAP related commands through BE, the BE manages the HW RAID BUFFER by using table B, and the information structure of each hardware array strip (HW RAID STRIPE) is maintained in the table B as follows:

Referring to fig. 8, fig. 8 is a schematic flow chart of a data storage method in an application scenario, and a BE RAID control flow is as follows:

(1) After the BE receives the programming message Command from the FTL, logic RAID STRIPE ID (ID identification corresponding to the logic array stripe) and RAID Command from the message Command are analyzed;

(2) In the RAID module of BE, checking whether HW RAID STRIPE ID (ID identifier corresponding to hardware array stripe) corresponding to received logic RAID STRIPE ID in table A is 0xFF, if yes, allocating HW RAID STRIPE ID to the logic RAID STRIPE ID, and continuing to execute according to step (3); if not, checking whether the logic RAID STRIPE ID stored in the table B corresponding to HW RAID STRIPE ID is matched with the logic RAID STRIPE ID in the message command, if yes, the logic strip and the HW strip can be matched, if not, performing XOR operation programming directly, if not, performing swap operation on HW RAID STRIPE ID, SWAP OUT old stripe, updating HW RAID STRIPE ID of the logic RAID STRIPE ID in the table a to 0xFF, updating status to swap state, updating command status in the table B, and then performing execution continuously according to (5);

(3) Checking whether there is free HW RAID STRIPE ID, if yes HW RAID STRIPE ID, allocating free HW RAID STRIPE ID to the current logic RAID STRIPE ID, updating table a and table B, and then continuing execution according to (5); if no spare HW RAID STRIPE ID is allocable, then execute as (4);

(4) When no free HW RAID STRIPE ID is available, one HW RAID STRIPE ID is selected for swap, SWAP OUT old stripe, and HW RAID STRIPE ID is updated to 0xFF in table A, status is updated to the swap state, and logic RAID STRIPE ID and status in table B are updated. Then assign HW RAID STRIPE ID for use by received logic RAID STRIPE ID, after which execution continues as in (5);

(5) Checking table a to see if received logic RAID STRIPE ID is IN SWAP status, if so, then first performing SWAP IN operation, then continuing to directly perform XOR operation programming, otherwise, continuing to directly perform XOR operation programming, and updating table a and table B.

It is understood that the management logic RAID STRIPE table a in FTL and HW RAID STRIPE table B of the controller-based HW RAID BUFFER resource in BE are managed, and table B maintains the usage status of the HW RAID BUFFER. When the BE receives a programming command from the FTL, HW RAID STRIPE ID is allocated to logic RAID STRIPE ID corresponding to the FTL programming command, and it is determined whether RAID SWAP operations are required. When HW RAID STRIPE ID is not available, the BE can timely judge that RAID SWAP is started, intermediate parity data SWAP OUT in HW RAID STRIPE ID to BE used is sent to a DRAM memory, and then the available HW RAID STRIPE ID can BE used for carrying OUT XOR operation and programming on the LUNs of the new logic RAID STRIPE ID. When the LUN programming of the old logic RAID STRIPE ID is to be rewritten, the intermediate PARITY SWAP IN operation is firstly performed, and then the XOR operation and programming are performed, so that the purpose of efficiently multiplexing the HW RAID BUFFER through the RAID SWAP is achieved.

Further, the data storage method of the present application further comprises the steps of: and after the exclusive OR operation corresponding to the target logic array stripe is completed, writing the redundancy check data in the target hardware array stripe into the corresponding logic unit, and releasing the target hardware array stripe. Specifically, in the process of performing the data storage method of the present application, when it is checked that the RAID command is a parity out, after sending a parity out instruction, the HW will automatically complete the parity programming, and then the firmware may release the corresponding HW RAID STRIPE ID.

Under the condition that the HW RAID BUFFER resources inside the controller are limited, the internal HW RAID BUFFER is combined with the external DRAM memory, and a plurality of logics RAID STRIPE can be effectively supported to be programmed simultaneously through RAID SWAP operation; SWAP IN and SWAP OUT of RAID SWAP operation are realized through controller chip hardware, the participation of firmware is reduced, and the method can also meet the QOS (Quality of Service ) requirement of a solid state disk system; in addition, reducing the HW RAID BUFFER reduces the chip power consumption and cost.

Referring to fig. 9, fig. 9 is a schematic structural diagram of a data storage device according to an embodiment of the application. The data storage device 90 in this embodiment includes an acquisition module 900, a judgment module 902, and a processing module 904 that are connected to each other; the acquiring module 900 is configured to acquire a programming command sent by the flash memory conversion layer, and acquire a target hardware array stripe allocated to a target logic array stripe corresponding to the programming command; the judging module 902 is configured to judge whether the target hardware array stripe is matched with the target logic array stripe; the processing module 904 is configured to perform a memory export operation on the target hardware array stripe when the target hardware array stripe is not matched with the target logical array stripe; and executing the programming command with the target hardware array stripe.

In one embodiment, the obtaining module 900 performs the step of obtaining the programming command sent by the flash translation layer, including: distributing a programming unit for programming management of data to be written, and acquiring address information of the programming unit; determining an array command correspondingly executed by a target logic unit according to the target logic unit in the programming unit; updating information of a target logic array stripe to which the target logic unit belongs in a logic array stripe management table; and generating the programming command according to the address information of the programming unit, the information of the target logic array strip and the type of the data to be written, and sending the programming command to the back-end hardware through the flash memory conversion layer.

In one embodiment, the obtaining module 900 performs the step of updating information of the target logical array stripe to which the target logical unit belongs in a logical array stripe management table, including: and when the target logic unit is the initial logic unit of the target logic array stripe, a new logic array stripe identifier is allocated for the target logic array stripe, and a corresponding external memory buffer is allocated for the new logic array stripe identifier.

In one embodiment, the acquiring module 900 performs the step of acquiring the target hardware array stripe allocated by the target logic array stripe corresponding to the program command, including: judging whether the target logic array strip is distributed with a hardware array strip or not; if the target logic array strip is not allocated with the hardware array strip, allocating the target hardware array strip for the target logic array strip; if the target logical array stripe has been allocated the target hardware array stripe, then the step of determining if the target hardware array stripe matches the target logical array stripe is performed by a determination module 902.

In one embodiment, the acquiring module 900 performs the step of allocating the target hardware array stripe to the target logical array stripe, including: judging whether an idle hardware array strip exists or not; if so, allocating idle target hardware array strips for the target logic array strips; and if the target hardware array stripe does not exist, selecting to perform memory swap operation on the target hardware array stripe, and then distributing the target hardware array stripe to the target logic array stripe.

In an embodiment, the processing module 904 performs steps for executing the programming command with the target hardware array stripe, including: judging whether the target logic array strip is in a memory swap-out state or not; if the target logic array stripe is not in the memory swap-out state, completing the programming operation of the data to be written by utilizing the target hardware array stripe; and if the target logic array strip is in the memory swap-out state, performing memory swap-in operation on the target hardware array strip, and then completing programming operation of data to be written by utilizing the target hardware array strip.

In an embodiment, the processing module 904 is further configured to write redundancy check data in the target hardware array stripe into a corresponding logic unit and release the target hardware array stripe after the exclusive or operation corresponding to the target hardware array stripe is completed.

For details of implementing the data storage method by the data storage device 90 of the present application, please refer to the details of the embodiment of the data storage method, and the details are not repeated here.

Referring to fig. 10, fig. 10 is a schematic structural diagram of a memory device according to an embodiment of the application. The storage device 100 in the present embodiment includes a processor 1002 and a memory 1001 connected to each other; the memory 1001 is configured to store program instructions and the processor 1002 is configured to execute the program instructions stored in the memory 1001 to implement the steps of any of the data storage method embodiments described above. In one particular implementation scenario, storage device 100 may include, but is not limited to: microcomputer, server.

In particular, the processor 1002 is configured to control itself and the memory 1001 to implement the steps of any of the data storage method embodiments described above. The processor 1002 may also be referred to as a CPU (Central Processing Unit ). The processor 1002 may be an integrated circuit chip having signal processing capabilities. The Processor 1002 may also be a general purpose Processor, a digital signal Processor (DIGITAL SIGNAL Processor, DSP), an Application SPECIFIC INTEGRATED Circuit (ASIC), a Field-Programmable gate array (Field-Programmable GATE ARRAY, FPGA) or other Programmable logic device, a discrete gate or transistor logic device, a discrete hardware component. A general purpose processor may be a microprocessor or the processor may be any conventional processor or the like. In addition, the processor 1002 may be commonly implemented by an integrated circuit chip.

Referring to fig. 11, fig. 11 is a schematic structural diagram of an embodiment of a computer readable storage medium according to the present application. The computer readable storage medium 110 of the present application has program instructions 1100 stored thereon, which program instructions 1100 when executed by a processor implement the steps of any of the data storage method embodiments described above.

The computer readable storage medium 110 may be a medium such as a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disc, where the program instructions 1100 may be stored, or may be a server storing the program instructions 1100, where the server may send the stored program instructions 1100 to another device for execution, or may also self-execute the stored program instructions 1100.

In the several embodiments provided in the present application, it should be understood that the disclosed method, apparatus and device may be implemented in other manners. For example, the above-described apparatus and device embodiments are merely illustrative, e.g., the division of modules or units is merely a logical functional division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed over a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the embodiment.

In addition, each functional unit in the embodiments of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit. The integrated units may be implemented in hardware or in software functional units.

The integrated units, if implemented in the form of software functional units and sold or used as stand-alone products, may be stored in a computer readable storage medium. Based on such understanding, the technical solution of the present application may be embodied in essence or a part contributing to the prior art or all or part of the technical solution in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) or a processor (processor) to execute all or part of the steps of the methods of the embodiments of the present application. And the aforementioned storage medium includes: a usb disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (RAM, random Access Memory), a magnetic disk, or an optical disk, or other various media capable of storing program codes.

Claims (10)

1. A data storage method, the data storage method comprising:

Acquiring a programming command sent by a flash memory conversion layer;

acquiring a target hardware array stripe distributed by a target logic array stripe corresponding to the programming command;

judging whether the target hardware array strip is matched with the target logic array strip or not;

If not, performing memory export operation on the target hardware array stripe;

The program command is executed with the target hardware array stripe.

2. The data storage method according to claim 1, wherein the acquiring the program command sent by the flash translation layer includes:

Distributing a programming unit for programming management of data to be written, and acquiring address information of the programming unit;

determining an array command correspondingly executed by a target logic unit according to the target logic unit in the programming unit;

Updating information of a target logic array stripe to which the target logic unit belongs in a logic array stripe management table;

And generating the programming command according to the address information of the programming unit, the information of the target logic array strip and the type of the data to be written, and sending the programming command to the back-end hardware through the flash memory conversion layer.

3. The data storage method according to claim 2, wherein updating information of a target logical array stripe to which the target logical unit belongs in a logical array stripe management table includes:

and when the target logic unit is the initial logic unit of the target logic array stripe, a new logic array stripe identifier is allocated for the target logic array stripe, and a corresponding external memory buffer is allocated for the new logic array stripe identifier.

4. The method of claim 1, wherein the obtaining the target hardware array stripe allocated by the target logic array stripe corresponding to the program command comprises:

judging whether the target logic array strip is distributed with a hardware array strip or not;

If the target logic array strip is not allocated with the hardware array strip, allocating the target hardware array strip for the target logic array strip;

And if the target logical array stripe is allocated to the target hardware array stripe, executing the step of judging whether the target hardware array stripe is matched with the target logical array stripe.

5. The data storage method of claim 4, wherein the allocating the target hardware array stripe for the target logical array stripe comprises:

judging whether an idle hardware array strip exists or not;

If so, allocating idle target hardware array strips for the target logic array strips;

and if the target hardware array stripe does not exist, selecting to perform memory swap operation on the target hardware array stripe, and then distributing the target hardware array stripe to the target logic array stripe.

6. The data storage method of claim 1, wherein the executing the programming command with the target hardware array stripe comprises:

judging whether the target logic array strip is in a memory swap-out state or not;

if the target logic array stripe is not in the memory swap-out state, completing the programming operation of the data to be written by utilizing the target hardware array stripe;

And if the target logic array strip is in the memory swap-out state, performing memory swap-in operation on the target hardware array strip, and then completing programming operation of data to be written by utilizing the target hardware array strip.

7. The data storage method of claim 1, wherein the data storage method further comprises:

and after the exclusive OR operation corresponding to the target logic array stripe is completed, writing the redundancy check data in the target hardware array stripe into the corresponding logic unit, and releasing the target hardware array stripe.

8. A data storage device, the data storage device comprising:

The acquisition module is used for acquiring a programming command sent by the flash memory conversion layer and acquiring a target hardware array strip distributed by a target logic array strip corresponding to the programming command;

The judging module is used for judging whether the target hardware array strip is matched with the target logic array strip or not;

The processing module is used for performing memory swap-out operation on the target hardware array stripe when the target hardware array stripe is not matched with the target logic array stripe; and executing the programming command with the target hardware array stripe.

9. A memory device comprising a processor and a memory connected to each other;

The memory is configured to store program instructions and the processor is configured to execute the program instructions to implement the data storage method of any of claims 1-7.

10. A computer readable storage medium having stored thereon program instructions, which when executed by a processor implement the data storage method of any of claims 1 to 7.