CN118803447A - Analog-to-digital conversion circuit and image sensor - Google Patents

Abstract

The present invention provides an analog-to-digital conversion circuit and an image sensor, wherein a ramp generator outputs a ramp voltage, wherein the ramp voltage decreases at a preset rate over time; a plurality of comparators are electrically connected to a column circuit of a pixel array and the ramp generator, wherein the pixel voltage of the column circuit is input to an inverting input terminal of the comparator, and the ramp voltage is input to a non-inverting input terminal of the comparator; a comparator bias circuit is electrically connected to the comparator, and provides a first bias voltage and a second bias voltage to the comparator, wherein the comparator completes the comparison between the ramp voltage and the pixel voltage under the first bias voltage and the second bias voltage; and a plurality of counters, wherein the counters are electrically connected to the comparators, and the counters count the number of flips of a system clock signal until the ramp voltage drops to be equal to the input of the pixel voltage; wherein when the ramp voltage and the pixel voltage are equal, the output of the comparator flips, and the flip of the output of the comparator triggers the flip of an enable signal of the counter, and the counter stops counting.

Description

Analog-to-digital conversion circuit and image sensor

Technical Field

The present invention relates to the field of image sensing technology, and in particular to an analog-to-digital conversion circuit and an image sensor.

Background Art

The image sensor uses the photoelectric conversion function of the photoelectric device to convert the light image on the photosensitive surface into an electrical signal that is proportional to the light image. The image sensor includes multiple pixel units. After the electrical signal converted by the pixel unit is obtained through the photosensitive element, the analog signal is converted into a digital signal through analog-to-digital conversion.

As the number of pixel array columns increases, the power consumption caused by analog-to-digital conversion also increases. Moreover, when multiple pixel columns perform analog-to-digital conversion at the same time, they interfere with each other, resulting in increased noise and affecting the image quality. In addition, due to the high power consumption per unit, if you want to increase the number and quality of pixels, the chip area will inevitably increase.

Summary of the invention

The object of the present invention is to provide an analog-to-digital conversion circuit and an image sensor, which can reduce the power consumption of the image sensor and improve the image quality.

In order to solve the above technical problems, the present invention is achieved through the following technical solutions:

The present invention provides an analog-to-digital conversion circuit, comprising:

a ramp generator, the ramp generator outputting a ramp voltage, wherein the ramp voltage decreases at a preset rate over time;

A plurality of comparators, electrically connected to the column circuit of the pixel array and the ramp generator, wherein the pixel voltage of the column circuit is input to the inverting input terminal of the comparator, and the ramp voltage is input to the non-inverting input terminal of the comparator;

a comparator bias circuit, electrically connected to the comparator, and providing a first bias voltage and a second bias voltage to the comparator, wherein the comparator compares the ramp voltage with the pixel voltage under the first bias voltage and the second bias voltage; and

A plurality of counters, each of which is electrically connected to the comparator, and each of which counts the number of flips of the system clock signal until the ramp voltage drops to be equal to the input of the pixel voltage;

When the ramp voltage is equal to the pixel voltage, the output of the comparator is flipped, and the flip of the output of the comparator triggers the flip of the enable signal of the counter, and the counter stops counting.

In one embodiment of the present invention, the initial value of the ramp voltage is greater than the upper limit of the range of the pixel voltage, and the final value of the ramp voltage is less than the lower limit of the range of the pixel voltage.

In one embodiment of the present invention, the comparator includes a first-stage comparator, the non-inverting input terminal of the first-stage comparator is the input terminal of the pixel voltage, the inverting input terminal of the first-stage comparator is the input terminal of the ramp voltage, wherein the first-stage comparator has an analog output voltage, the value of the analog output voltage is a preset value, when the ramp voltage is greater than the pixel voltage, the output voltage of the first-stage comparator is greater than the preset value, and when the ramp voltage is less than or equal to the pixel voltage, the output voltage of the first-stage comparator is less than the preset value.

In one embodiment of the present invention, the comparator includes a second-stage comparator, and the second-stage comparator includes:

a common source transistor, wherein the gate of the common source transistor is electrically connected to the output terminal of the first-stage comparator, the source of the common source transistor is electrically connected to the power supply terminal, the drain of the common source transistor serves as the output terminal of the comparator, and outputs the count control timing signal; and

a first transistor, wherein a gate of the first transistor receives the second bias voltage, a source of the first transistor is grounded, a drain of the first transistor serves as an output terminal of the comparator, and when an enable signal of the counter is turned high, the first transistor is disconnected;

When the ramp voltage is less than or equal to the pixel voltage, the output of the second-stage comparator flips, and the output flip of the second-stage comparator triggers the flip of the enable signal of the counter, and the counter stops counting.

In an embodiment of the present invention, the comparator bias circuit includes a first bias circuit, which is electrically connected to the plurality of comparators, wherein the first bias circuit outputs the first bias voltage.

In one embodiment of the present invention, the analog-to-digital conversion circuit includes a coupling capacitor, and the coupling capacitor is electrically connected between the output terminal of the first-stage comparator and the gate of the common-source transistor of the second-stage comparator.

In one embodiment of the present invention, the comparator bias circuit includes a second bias circuit, the second bias circuit is electrically connected to the plurality of comparators, and the second bias circuit includes:

Current mirror;

a third transistor, a gate of the first transistor being electrically connected to an output terminal of the current mirror through the third transistor; and

A fourth transistor, the gate of the first transistor is grounded through the fourth transistor, wherein the gate levels of the third transistor and the fourth transistor are inverted, wherein when the value of the ramp voltage starts to decrease, the third transistor is turned off and the fourth transistor is turned on.

In one embodiment of the present invention, the comparator includes a control transistor, and when the value of the ramp voltage begins to decrease, the control transistor is disconnected, wherein one end of the control transistor is electrically connected to the first transistor, and the other end of the control transistor serves as the output end of the comparator.

In one embodiment of the present invention, the comparator bias circuit includes a second bias circuit, and the second bias circuit is arranged in the comparator, and the second bias circuit includes:

a fifth transistor, wherein the gate of the first transistor is electrically connected to the output terminal of the comparator through the fifth transistor; and

A grounding control transistor, wherein the gate of the first transistor is grounded through the grounding control transistor, and when the ramp voltage starts to decrease, the grounding control transistor is turned on.

The present invention provides an image sensor, comprising:

A pixel array, the pixel array comprising a plurality of pixel units, and the pixel units are arranged in columns to form a plurality of column circuits; and

An analog-to-digital conversion circuit as described above, wherein the analog-to-digital conversion circuit is electrically connected to the column circuit and receives a pixel signal from the column circuit, and the analog-to-digital conversion circuit outputs a pixel voltage after the pixel signal is analog-to-digital converted.

As described above, the present invention provides an analog-to-digital conversion circuit and an image sensor, which can reduce the power consumption of analog-to-digital conversion of each pixel column circuit, thereby reducing the total power consumption of the image sensor and reducing ground noise. Multiple columns of analog-to-digital conversion circuits are independent of each other and have little interference, thereby avoiding common terminal fluctuations caused by simultaneous flipping of multiple columns of analog-to-digital conversion circuits, improving the accuracy of analog-to-digital conversion, and thus improving the quality of image output. In addition, an analog-to-digital conversion circuit and an image sensor provided by the present invention are conducive to reducing the chip area of the image sensor.

Of course, any product implementing the present invention does not necessarily need to achieve all of the advantages described above at the same time.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings required for describing the embodiments will be briefly introduced below. Obviously, the accompanying drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other accompanying drawings can be obtained based on these accompanying drawings without paying creative work.

FIG. 1 is a schematic diagram of the structure of an image sensor in one embodiment of the present invention.

FIG. 2 is a schematic diagram of the structure of a counter and a latch in an embodiment of the present invention.

FIG. 3 is a schematic diagram of a control timing sequence of counting in an embodiment of the present invention.

FIG. 4 is a schematic diagram of the structure of a comparator in an embodiment of the present invention.

FIG. 5 is a schematic diagram of the structure of a comparator and a comparator bias circuit in an embodiment of the present invention.

FIG. 6 shows the changes of the second-stage current and the ground voltage in one embodiment of the present invention.

FIG. 7 is a schematic diagram of the structure of a comparator in another embodiment of the present invention.

FIG. 8 is a schematic diagram of the structure of a comparator in another embodiment of the present invention.

In the figure: 10, pixel array; 101, column circuit; 20, current source load circuit; 30, comparator; 40, analog-to-digital conversion module; 410, counter; 420, latch; 50, ramp generator; 60, comparator bias circuit; 610, first bias circuit; 620, second bias circuit.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present invention to clearly and completely describe the technical solutions in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

Please refer to FIG. 1 , the present invention provides. As shown in FIG. 1 , the image sensor includes a pixel array 10, a column readout circuit and an analog-to-digital conversion circuit. The analog-to-digital conversion circuit includes a current source load circuit 20, a comparator 30, an analog-to-digital conversion module 40, a ramp generator 50 and a comparator bias circuit 60. The pixel array 10 includes a plurality of pixel units, and the plurality of pixel units are arranged in an array according to rows and columns. In the present embodiment, the pixel array 10 includes a plurality of row circuits and a plurality of column circuits 101. When reading out the electrical signal of the pixel unit, the row to be read out is selected by the row scanning circuit, and then the pixel signal in the selected row is read out by the column readout circuit. In the present embodiment, the signals of a plurality of pixel units located in the same row are read out at the same time, and analog-to-digital conversion is performed at the same time. In the present embodiment, the column readout circuit is electrically connected to the current source load circuit 20, so as to output the pixel signal of the column circuit 101.

Please refer to FIG. 1 . In one embodiment of the present invention, the current source load circuit 20 includes a plurality of current sources, and the current sources are electrically connected to the column circuit 101. The structure of the amplifier circuit is not shown in this embodiment. The electrical signal output by the current source load circuit 20 is an amplified electrical signal, thereby improving the accuracy of analog-to-digital conversion. In this embodiment, the comparator 30 is electrically connected to the current source load circuit 20, the analog-to-digital conversion module 40, the ramp generator 50 and the comparator bias circuit 60. In this embodiment, the comparator bias circuit 60 provides a bias voltage for the comparator 30. The ramp generator 50 generates a ramp voltage V _RAMP and outputs the ramp voltage V _RAMP to the non-inverting input terminal of the comparator 30. The current source load circuit 20 outputs the pixel voltage V _PIX of the column circuit 101, and outputs the pixel voltage V _PIX to the inverting input terminal of the comparator 30. After the comparator 30 is reset, the comparator 30 starts to compare the ramp voltage V _RAMP and the pixel voltage V _PIX , and when the ramp voltage V _RAMP and the pixel voltage V _PIX are equal, the output of the comparator 30 flips. During the period when the output voltage of the ramp generator 50 starts to decrease and decreases to the period when the ramp voltage V _RAMP and the pixel voltage V _PIX are equal, that is, during the working time of the comparator 30, the analog-to-digital conversion module 40 counts the number of flips of the clock level and uses the count value as the value of the pixel voltage V _PIX .

Please refer to FIG. 1 to FIG. 3 , in one embodiment of the present invention, the analog-to-digital conversion module 40 includes a counter 410 and a latch 420. The output end of the comparator 30 is electrically connected to the counter 410. The output end of the counter 410 is electrically connected to the latch 420. Among them, the output signal of the comparator 30 is CMP_OUT. In this embodiment, when the ramp voltage V _RAMP is greater than the pixel voltage V _PIX , the output signal CMP_OUT of the comparator 30 is a low-level signal. When the ramp voltage V _RAMP is less than or equal to the pixel voltage V _PIX , the output signal CMP_OUT of the comparator 30 flips to a high-level signal. The counter 410 is controlled by the timing signal CNT_EN to start and stop counting. The high level of the timing signal CNT_EN is controlled by the timing signal CNT_CTL and CMP_OUT. Specifically, as shown in FIG. 3 , when the timing signal CNT_CTL flips to a high-level signal, the counter 410 is activated, and at this time, the timing signal CNT_EN flips to a high level, and counting starts. When the ramp voltage V _RAMP is less than or equal to the pixel voltage V _PIX , the comparator output signal CMP_OUT turns to a high level. At this time, the timing signal CNT_EN turns to a low level, the counter 410 is turned off, and the counting ends.

Please refer to FIG. 1 to FIG. 3. In one embodiment of the present invention, in FIG. 3, point c represents the start of control counting, and point d represents the start of counting. Whenever the clock signal CNT_CLK flips once, the counter 410 counts once. It should be noted that, as shown in FIG. 3, the clock signal CNT_CLK is an external signal, which can be a system clock signal of an external system, and the clock signal is not subject to the timing control restriction of the analog-to-digital conversion module 40. The counter 410 receives the clock signal CNT_CLK to count the number of flips of the clock signal CNT_CLK. The counter 410 receives the timing signal CNT_EN to control the opening and closing of the counter 410. The count value CNT_OUT of the counter 410 is stored in the latch 420, wherein the latch 420 outputs the count final value LAT_OUT. As shown in FIG. 3, the count level signal CNT_OUT flips 12 times, which means that the count value is 12. Then the count final value LAT_OUT output by the latch 420 is 12. It should be noted that the present invention is not limited to the algorithm structure of obtaining the corresponding pixel voltage value through the count value. In the present invention, obtaining the count value can be equivalent to obtaining the pixel voltage value of the image sensor.

Please refer to FIG. 1 to FIG. 3 . In one embodiment of the present invention, the ramp generator 50 outputs a ramp voltage V _RAMP . Before the node a, the ramp generator 50 is reset so that the value of the ramp voltage V _RAMP returns to a preset value. The preset value of the ramp voltage V _RAMP can be, for example, twice the standard pixel voltage. For example, if the pixel voltage is about 1V, the ramp voltage V _RAMP can be set to 2V. The present invention does not limit the error range of the ramp voltage V _RAMP . It should be noted that the value of the pixel voltage V _PIX is a black box value. Before the test output, the specific value of the pixel voltage V _PIX cannot be known, and only the range of the pixel voltage V _PIX can be known. At the node a, the ramp voltage V _RAMP is raised, so that the comparator 30 is reset. The raising range of the ramp voltage V _RAMP is, for example, 100mV to 200mV. At the node b, the quantization process of analog-to-digital conversion is started.

Please refer to FIG. 1 to FIG. 3 . In one embodiment of the present invention, after node b, the value of the ramp voltage V _RAMP decreases at a set rate until node e, when the ramp voltage V _RAMP is equal to the pixel voltage V _PIX . At this time, the output of the comparator 30 is flipped to a high level. At the same time, as shown in FIG. 3 , the timing signal CNT_EN is flipped to a low level, the counter 410 stops counting, and the output CNT_OUT no longer changes. The latch 420 latches and outputs the CNT_OUT after the counting stops as the count final value LAT_OUT. The output value is the quantized value of the pixel voltage V _PIX . In this embodiment, when the output of the comparator 30 is flipped to a high level, the value of the ramp voltage V _RAMP still decreases at a set rate until the value of the ramp voltage V _RAMP decreases to a preset value. At this time, the timing signal CNT_CTL is flipped to a low level.

Referring to FIG. 1 and FIG. 4 , in one embodiment of the present invention, the comparator 30 includes a first-stage comparator ST1, a second-stage comparator ST2, and a third coupling capacitor C3 coupled between the first-stage comparator ST1 and the second-stage comparator ST2. The first-stage comparator ST1 includes a tail current source tube N0, a ramp coupling transistor N1, a pixel input transistor N2, a first comparator reset tube P1, a second comparator reset tube P0, a first current mirror load P2, and a second current mirror load P3. The gate of the ramp coupling transistor N1 is electrically connected to the output end of the ramp generator 50 through the first coupling capacitor C1 to receive the ramp voltage V _RAMP . The gate of the pixel input transistor N2 is electrically connected to the output end of the current source load circuit 20 through the second coupling capacitor C2 to receive the pixel voltage V _PIX . In the first-stage comparator ST1, the tail current source tube N0 provides current for the first-stage comparator ST1. The gate of the tail current source tube N0 is electrically connected to the first bias circuit 610 to receive the first bias voltage VBIAS_ST1.

Please refer to FIG. 1 and FIG. 4 . In one embodiment of the present invention, in the first stage comparator ST1, the source of the tail current source tube N0 is grounded, and the drain of the tail current source tube N0 is electrically connected to the source of the ramp coupling transistor N1 and the source of the pixel input transistor N2. The drain of the ramp coupling transistor N1 is electrically connected to the source of the first comparator reset tube P1 and the drain of the first current mirror load P2. The source of the first current mirror load P2 is electrically connected to the power supply terminal AVDD, and the drain of the first current mirror load P2 is electrically connected to the gate. The drain of the first comparator reset tube P1 is electrically connected to the gate of the ramp coupling transistor N1. In this embodiment, the gate of the first comparator reset tube P1 receives the timing signal CMP_RST1B.

Please refer to FIG. 1 and FIG. 4 . In one embodiment of the present invention, in the first-stage comparator ST1, the drain of the pixel input transistor N2 is electrically connected to the drain of the second current mirror load P3 and the source of the second comparator reset tube P0. The source of the second current mirror load P3 is electrically connected to the power supply terminal AVDD, and the drain of the second current mirror load P3 is electrically connected to the gate. The drain of the second comparator reset tube P0 is electrically connected to the gate of the pixel input transistor N2. In this embodiment, the gate of the second-stage comparator reset tube P0 receives the timing signal CMP_RST1B. In this embodiment, the gate of the first current mirror load P2 and the gate of the second current mirror load P3 are electrically connected. And in this embodiment, the common end of the second current mirror load P3 and the pixel input transistor N2 serves as the first voltage output end V _OUT .

Please refer to FIG. 1 and FIG. 4 . In one embodiment of the present invention, the second stage comparator ST2 includes a first transistor N3, a second transistor N4 and a common source transistor P4. The gate of the first transistor N3 is electrically connected to the second bias circuit 620 to receive the first bias voltage VBIAS_ST2. The source of the first transistor N3 is grounded, and the drain of the first transistor N3 is electrically connected to the source of the second transistor N4 and the drain of the common source transistor P4. The gate of the second transistor N4 receives the timing signal CMP_RST2, and the drain of the second transistor N4 is electrically connected to the first voltage output terminal V _OUT through the third coupling capacitor C3. The gate of the common source transistor P4 is electrically connected to the first voltage output terminal V _OUT through the third coupling capacitor C3, and the source of the common source transistor P4 is electrically connected to the power supply terminal AVDD. As shown in FIG. 4 , the gate voltage input to the gate of the common source transistor P4 through the third coupling capacitor C3 is V1.

Please refer to FIG. 1 and FIG. 4 . In one embodiment of the present invention, when V _RAMP > V _PIX , V _OUT and V1 are high, P4 is turned off, and N3 is turned on, and the output CMP_OUT is pulled to a low level by N3. At this time, P4 is turned off, and the current of the second-stage comparator ST2 is 0, so there is no path from the power supply to the ground. As the value of the ramp voltage decreases downward, when V _RAMP ≤ VP _IX , V _OUT becomes a low level, and P4 is turned on. Since the pull-up capability of P4 is greater than that of N3, the output CMP_OUT is pulled to a high level. At this time, both P4 and N3 are turned on to generate a current from the power supply to the ground.

Please refer to FIG. 1 , FIG. 4 and FIG. 5 . In one embodiment of the present invention, the comparator bias circuit 60 includes a first bias circuit 610, and the first bias circuit 610 is electrically connected to the gate of the tail current source tube N0. In this embodiment, the first bias circuit 610 includes a first current source IBias1 and a first control transistor NB1. The source of the first control transistor NB1 is grounded, the drain of the first control transistor NB1 is electrically connected to the gate, and is electrically connected to the output end of the first current source IBias1. The gate of the first control transistor NB1 is electrically connected to the gate of the tail current source tube N0. In this embodiment, the first bias circuit 610 is an external circuit, which is electrically connected to the comparator 30 of each column, and outputs a uniform first bias voltage to each column of the comparator 30.

Please refer to FIG. 1, FIG. 4 and FIG. 5. In one embodiment of the present invention, the comparator bias circuit 60 includes a second bias circuit 620, and the second bias circuit 620 is electrically connected to the gate of the first transistor N3. In this embodiment, the second bias circuit 620 includes a second current source IBias2, a second control transistor NB2, a third transistor NB3 and a fourth transistor NB4. The source of the second control transistor NB2 is grounded, the drain of the second control transistor NB2 is electrically connected to the output end of the second current source IBias2, and the gate of the second control transistor NB2 is electrically connected to the drain of the third transistor NB3 and the drain of the fourth transistor NB4. The gate of the third transistor NB3 receives the voltage VB_CTL, the source of the third transistor NB3 is electrically connected to the output end of the second current source IBias2, and the drain of the third transistor NB3 is electrically connected to the gate of the first transistor N3. The gate of the fourth transistor NB4 receives the voltage VB_CTLB, the source of the fourth transistor NB4 is grounded, and the drain of the fourth transistor NB4 is electrically connected to the gate of the first transistor N3. The voltage VB_CTL and the voltage VB_CTLB are mutually inverted voltages. In this embodiment, the second bias circuit 620 is an external circuit, electrically connected to each column of the comparator 30, and outputs a uniform second bias voltage to each column of the comparator 30. In this embodiment, the drain of the first transistor N3 serves as the output terminal of the comparator 30, and outputs the timing signal CMP_OUT.

Please refer to FIG. 1, FIG. 4 and FIG. 6. In the present invention, the bias circuits for controlling the first-stage comparator ST1 and the second-stage comparator ST2 are separated, and the control of the second bias circuit 620 is added. After V _RAMP is raised, when the analog-to-digital conversion starts to quantize, the bias voltage of the second-stage comparator ST2 is pulled to the ground, so N3 is turned off. When V _RAMP ≤ V _PIX , V1 is pulled low and P4 is turned on, only CMP_OUT is pulled high, and no direct path from the power supply to the ground is generated. Therefore, no voltage rise is generated from the ground. As shown in FIG. 6, from the time when the comparator 30 starts to reset until the ramp voltage V _RAMP drops to a preset value, the second-stage current and the ground voltage will not change, thereby reducing the power consumption of the circuit. At the same time, due to the separation of the first bias circuit 610 and the second bias circuit 620, the influence of the CMP_OUT flip on the bias voltage will not affect the more sensitive first-stage comparator ST1.

Referring to FIG. 1 and FIG. 4 to FIG. 7 , in another embodiment of the present invention, the comparator bias circuit 60 includes a first bias circuit 610. In this embodiment, the first bias circuit 610 is an external circuit, electrically connected to each column of the comparator 30, and outputs a uniform first bias voltage to each column of the comparator 30. In this embodiment, the comparator 30 includes a first-stage comparator ST1 and a second-stage comparator ST2. The first-stage comparator ST1 has the same circuit structure as in the first embodiment of the present invention. With respect to the second-stage comparator ST2, based on the circuit structure in the first embodiment of the present invention, in this embodiment, the comparator bias circuit 60 also includes a second bias circuit 620, and the second bias circuit 620 is connected to the second-stage comparator ST2.

Please refer to FIG. 1 and FIG. 4 to FIG. 7. In another embodiment of the present invention, the second bias circuit 620 includes a transistor N4, a transistor N5 and a ground control transistor N6. The gate of the transistor N4 receives the voltage VBSH, the source of the transistor N4 is electrically connected to the drain of the first transistor N3, and the drain of the transistor N4 is electrically connected to the gate of the first transistor N3. The source and drain of the transistor N5 are both grounded, and the gate of the transistor N5 is electrically connected to the gate of the first transistor N3. The gate of the ground control transistor N6 receives VB_CTLB, the source of the ground control transistor N6 is grounded, and the drain of the ground control transistor N6 is electrically connected to the gate of the first transistor N3. In this embodiment, the drain of the first transistor N3 serves as the output terminal of the comparator 30 to output the timing signal CMP_OUT. When the comparator 30 is reset, the sampling and holding bias voltage VB2 of the transistor N4 and the transistor N5 is used. After the sampling and holding ends, VBSH is pulled low and the transistor N4 is turned off. The bias voltage of the second-stage comparator ST2 is equivalent to being maintained by the transistor N5. At this time, the ground control transistor N6 is added to control that after the ramp voltage _VRAMP is reset and the timing signal CMP_OUT is high, the bias voltage VB2 is pulled low, thereby achieving the same technical effect as that of the embodiment described in one embodiment of the present invention.

Please refer to FIG. 1, FIG. 4 to FIG. 6, and FIG. 8. In another embodiment of the present invention, the comparator bias circuit 60 includes a first bias circuit 610. In this embodiment, the first bias circuit 610 is an external circuit, which is electrically connected to the comparator 30 of each column and outputs a uniform first bias voltage to the comparator 30 of each column. In this embodiment, the comparator 30 includes a first-stage comparator ST1, a second-stage comparator ST2, and a third coupling capacitor C3 coupled between the first-stage comparator ST1 and the second-stage comparator ST2. The first-stage comparator ST1 has the same circuit structure as that in the first embodiment of the present invention. With respect to the second-stage comparator ST2, based on the circuit structure in the first embodiment of the present invention, in this embodiment, the second-stage comparator ST2 further includes a third control transistor N5. In this embodiment, the gate of the third control transistor N5 receives VB_CTL, the source of the third control transistor N5 is electrically connected to the drain of the first transistor N3, and the drain of the third control transistor N5 is electrically connected to the drain of the common source transistor P4. The drain of the third control transistor N5 serves as the output terminal of the comparator 30, and outputs the timing signal CMP_OUT. When the quantization process of the analog-to-digital conversion begins, that is, when the ramp voltage begins to decrease, that is, at the b node, the third control transistor N5 is turned off, thereby achieving the same technical effect as the embodiment described in the first embodiment of the present invention.

Please refer to FIG. 1 to FIG. 8. In one embodiment of the present invention, as shown in FIG. 6, the timing signal in the embodiment of the present invention is shown in FIG. 6. The first bias circuit 610 and the second bias circuit 620 are external bias circuits, wherein the output bias voltage of the first bias circuit 610 and the output bias voltage of the second bias circuit 620 are electrically connected to the comparator 30 of each column, and the circuit occupies a small area while achieving the effect of reducing power consumption. In another embodiment of the present invention, the second bias circuit 620 is arranged inside the second-stage comparator ST2, so as to realize the self-bias control of the second-stage comparator ST2, realize automatic control, reduce signal transmission time and loss, and have high control efficiency. In another embodiment of the present invention, the second-stage comparator ST2 and the first-stage comparator ST1 are biased independently of each other by a single transistor, and the control process is simple and easy to operate.

The present invention provides an analog-to-digital conversion circuit and an image sensor. The image sensor includes a pixel array and an analog-to-digital conversion circuit. The analog-to-digital conversion circuit includes a ramp generator, a plurality of comparators, a comparator bias circuit and a plurality of counters. The ramp generator outputs a ramp voltage, wherein the ramp voltage decreases at a preset rate over time. The comparator is electrically connected to a column circuit of the pixel array and the ramp generator, wherein the pixel voltage of the column circuit is input to the inverting input terminal of the comparator, and the ramp voltage is input to the non-inverting input terminal of the comparator. The comparator bias circuit is electrically connected to the comparator, and provides the comparator with a first bias voltage and a second bias voltage. Under the first bias voltage and the second bias voltage, the comparator works to complete the comparison between the ramp voltage and the pixel voltage. The comparator output flips to high when the ramp voltage and the pixel voltage are equal, and the comparator output controls the count enable signal to flip to low. During the period from when the ramp voltage starts to decrease to when the comparator output flips, the counter counts the number of flips of the system clock signal, and uses the count value as the pixel voltage after the pixel signal is analog-to-digital converted. The present invention can reduce the power consumption of the image sensor and improve the image quality.

The embodiments of the present invention disclosed above are only used to help illustrate the present invention. The embodiments do not describe all the details in detail, nor do they limit the invention to the specific embodiments described. Obviously, many modifications and changes can be made according to the content of this specification. This specification selects and specifically describes these embodiments in order to better explain the principles and practical applications of the present invention, so that those skilled in the art can understand and use the present invention well. The present invention is limited only by the claims and their full scope and equivalents.

Claims (10)

1. An analog-to-digital conversion circuit, comprising:

A ramp generator that outputs a ramp voltage, wherein the ramp voltage decreases with time at a preset rate;

the plurality of comparators are electrically connected with the column circuits of the pixel array and the slope generator, wherein the pixel voltages of the column circuits are input to the inverting input ends of the comparators, and the slope voltages are input to the non-inverting input ends of the comparators;

The comparator bias circuit is electrically connected with the comparator and provides a first bias voltage and a second bias voltage for the comparator, and the comparator finishes comparison of the ramp voltage and the pixel voltage under the first bias voltage and the second bias voltage; and

The counters are electrically connected to the comparators and count the turnover times of the system clock signals until the ramp voltage is reduced to be equal to the input of the pixel voltage;

When the ramp voltage and the pixel voltage are equal, the output of the comparator is inverted to trigger the enabling signal of the counter to be inverted, and the counter stops counting.

2. The analog-to-digital conversion circuit of claim 1, wherein an initial value of the ramp voltage is greater than an upper limit of the range of the pixel voltage and a final value of the ramp voltage is less than a lower limit of the range of the pixel voltage.

3. The analog-to-digital conversion circuit of claim 1, wherein the comparator comprises a first-stage comparator having an in-phase input terminal for the pixel voltage and an inverting input terminal for the ramp voltage, wherein the first-stage comparator has an analog output voltage having a value of a preset value, wherein the output voltage of the first-stage comparator is greater than the preset value when the ramp voltage is greater than the pixel voltage, and wherein the output voltage of the first-stage comparator is less than the preset value when the ramp voltage is less than or equal to the pixel voltage.

4. An analog to digital conversion circuit according to claim 3, wherein the comparator comprises a second stage comparator comprising:

The grid electrode of the common source transistor is electrically connected with the output end of the first-stage comparator, the source electrode of the common source transistor is electrically connected with the power supply end, and the drain electrode of the common source transistor is used as the output end of the comparator and outputs the counting control time sequence signal; and

A first transistor, a gate of which receives the second bias voltage, a source of which is grounded, a drain of which serves as an output terminal of the comparator, and which is turned off when an enable signal of the counter is turned high;

When the ramp voltage is smaller than or equal to the pixel voltage, the output of the second-stage comparator is turned over to trigger the enabling signal of the counter to be turned over, and the counter stops counting.

5. The analog-to-digital conversion circuit of claim 4, wherein said comparator bias circuit comprises a first bias circuit electrically connected to a plurality of said comparators, wherein said first bias circuit outputs said first bias voltage.

6. The analog-to-digital conversion circuit of claim 4, comprising a coupling capacitor electrically connected between an output of said first stage comparator and a gate of said second stage comparator common source transistor.

7. The analog-to-digital conversion circuit of claim 6, wherein said comparator bias circuit comprises a second bias circuit, said second bias circuit being electrically connected to a plurality of said comparators, said second bias circuit comprising:

a current mirror;

a third transistor, wherein the grid electrode of the first transistor is electrically connected with the output end of the current mirror through the third transistor; and

A fourth transistor through which a gate of the first transistor is grounded, wherein gate levels of the third transistor and the fourth transistor are inverted, wherein when a value of the ramp voltage starts to fall, the third transistor is turned off and the fourth transistor is turned on.

8. The analog-to-digital conversion circuit of claim 6, wherein said comparator comprises a control transistor, said control transistor being turned off when a value of said ramp voltage starts to decrease, wherein one end of said control transistor is electrically connected to said first transistor, and the other end of said control transistor is used as an output terminal of said comparator.

9. The analog-to-digital conversion circuit of claim 4, wherein said comparator bias circuit comprises a second bias circuit, said second bias circuit being disposed in said comparator, said second bias circuit comprising:

a fifth transistor, wherein the grid electrode of the first transistor is electrically connected to the output end of the comparator through the fifth transistor; and

And the grid electrode of the first transistor is grounded through the grounding control transistor, and when the slope voltage starts to drop, the grounding control transistor is conducted.

10. An image sensor is provided, which is capable of detecting a light source, characterized by comprising the following steps:

the pixel array comprises a plurality of pixel units, and the pixel units are arranged according to columns to form a plurality of column circuits: and

An analog-to-digital conversion circuit as claimed in any one of claims 1 to 9, wherein the analog-to-digital conversion circuit is electrically connected to the column circuit and receives a pixel signal of the column circuit, and the analog-to-digital conversion circuit outputs a pixel voltage after analog-to-digital conversion of the pixel signal.