CN118801889A - A ZOOM ADC with Adaptive Tracking - Google Patents

Abstract

The invention discloses a ZOOM ADC using adaptive tracking, which is applied to the field of analog-to-digital converters. The invention aims to solve the problem that during the coarse quantization period of the existing ZOOM ADC, due to non-ideal factors such as high bandwidth of an input signal or noise and offset of a circuit, a reference voltage reference selected for fine quantization deviates from the quantization range of an actual input signal, so that the fine quantization level of the ADC cannot be effectively quantized. The invention solves the over-range problem of the ZOOM ADC by integrating a digital code after repeated comparison of the LSB bits of the fine quantization level and feeding it back to a tracking capacitor array. Compared with the prior art, the ZOOM ADC proposed by the invention can effectively improve the resolution of the coarse quantization level, reduce the design requirements of the fine quantization level (such as using a lower oversampling rate and a lower order), and achieve higher precision and lower power consumption of the ZOOM ADC.

Description

A ZOOM ADC with Adaptive Tracking

Technical Field

The invention belongs to the field of integrated circuit design, and in particular relates to an analog-to-digital converter.

Background Art

Analog-to-Digital Converter (ADC) realizes the conversion of analog signals to digital signals. It is a key component of the interface between analog systems and digital systems and plays an important role in applications such as consumer electronics and industrial electronics. Oversampling ADC is a commonly used ADC architecture in high-precision applications. As shown in Figure 1, the oversampling ADC is usually composed of an ADC core and a digital filter. The digital filter filters the digital code converted by the ADC core to achieve functions such as improving accuracy.

Ideally, the output of the ADC is equal to the input signal, that is, D _out = _Vin . However, due to the non-ideality of the ADC core, various errors are introduced in the process of converting analog signals into digital signals, such as offset voltage, noise, quantization error, etc. It can be expressed as:

D _out =V _in +V _os +V _n +Q

Among them, D _out is the digital output signal, _Vin is the analog input signal, _Vos is the offset voltage, _Vn is the noise, and Q is the quantization error. A common oversampling ADC is the ΔΣ (Sigma-Delta) modulator. However, the traditional high-precision ΔΣ modulator has high power consumption and needs to be improved using low-power technology. ZOOM ADC (zoom ADC) combines the advantages of SAR ADC (Successive Approximation Register ADC) on the basis of ΔΣ modulator, and has the advantages of high precision, low power consumption, low noise, etc., and has good application prospects. The structural block diagram is shown in Figure 2.

The conversion steps of ZOOM ADC are divided into coarse quantization and fine quantization. When the input signal enters ZOOM ADC, coarse quantization is first performed. The coarse quantization result determines the reference voltage range (V _refn , V _refp ) for fine quantization. The ΔΣ modulator uses the obtained V _ref as the reference voltage to process the signal and complete the entire ZOOM ADC quantization.

The difference between the reference voltage and the input signal is the input of the integrator in the ΔΣ modulator. The ZOOM ADC selects the reference voltage for the ΔΣ modulator through coarse quantization to reduce the range between V _refp and V _refn , thereby reducing the input signal range of the integrator in the ΔΣ modulator, so that the integrator can use a larger gain factor. However, due to non-ideal factors of the SAR ADC, such as noise and offset voltage of capacitors or comparators, the reference voltage selected by coarse quantization deviates from the input signal, as shown in Figure 4, causing the ΔΣ modulator to exceed the range, thereby reducing the system accuracy.

In order to solve this problem, two methods have been proposed, one is to reduce the resolution of SAR ADC, the other is Over-Ranging (expanding the range). References "Y.Chae, K.Souri and KAAMakinwa,"A6.3μW 20bincremental ZOOM-ADC with 6ppm INL and 1μV offset,"2013IEEE InternationalSolid-State Circuits Conference Digest of Technical Papers,San Francisco,CA,USA,2013,pp.276-277""B. F.Sebastiano,R.van Veldhoven and KAAMakinwa,"A1.65mW 0.16mm2 dynamic ZOOM-ADC with 107.5dB DR in 20kHz BW,"2016IEEEInternational Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2016,pp.282-283"E.Eland,S.Karmakar,B. R. van Veldhoven and K. Makinwa,"A440μW,109.8dB DR,106.5dB SNDR Discrete-Time ZOOM ADC with a 20kHz BW,"2020IEEE Symposium on VLSI Circuits,Honolulu,HI,USA,2020,pp.1-2""Y. Liu et al.,"A 4.96μW 15b Self-Timed Dynamic-Amplifier-Based Incremental ZOOM ADC,"2022IEEE International Solid-State Circuits Conference(ISSCC),San Francisco,CA,USA,2022,pp.170-172"all use the first method. The resolution of SAR ADC is only 5 or 6 bits. The lower resolution makes the range between V _refp and V _refn of the coarse quantization selection larger. Even if the coarse quantization selection of the reference voltage is affected by non-ideal factors, the input signal can be included in the range between V _refp and V _refn range, ensuring the normal operation of the ΔΣ modulator. The resolution of the ZOOM ADC depends on the range of the quantization interval [V _refp ,V _refn ], as well as the order and oversampling rate of the modulator. A lower SAR ADC resolution will reduce the accuracy. To achieve the same accuracy, a higher OSR (Oversampling Ratio) is required, which increases the bandwidth requirements of the integrator and the power consumption of the ADC. The above four references also mention methods for expanding the range, as shown in Figure 5.

The overrange factor M is introduced to expand the range of the reference voltage selected by the coarse quantization from (V _refp -V _refn ) to M*(V _refp -V _refn ), so that the signal can be included in the range of the selected reference voltage. After the expansion, the reference voltage becomes:

V _refp =(K+M+1)·V _LSB

V _refn =(KM)·V _LSB

The expansion of the reference voltage range selected by coarse quantization relaxes the accuracy requirements of the SAR ADC and improves the robustness of the system. However, due to the limited conversion speed of the SAR ADC, during the coarse quantization selection of the ΔΣ modulator reference voltage, the input signal is still changing and may move out of the selected reference voltage range, making the ΔΣ modulator unable to work properly. The expansion of the range increases the input range of the integrator in the ΔΣ modulator. The integration loop becomes unstable due to the larger input, and also puts higher requirements on the linearity of the integrator.

ZOOM ADC combines the advantages of ΔΣ modulator and SAR ADC, and has the advantages of high precision, low power consumption, and low noise. However, due to non-ideal factors such as noise and offset voltage of SAR ADC, the input signal exceeds the range during fine quantization, and the accuracy of ZOOM ADC is suppressed. To solve this problem, one way is to reduce the accuracy of SAR ADC, but the ΔΣ modulator requires a higher OSR and a higher bandwidth for the integrator. Another way is to increase the reference voltage range of the ΔΣ modulator, but this increases the output signal swing of the integrator of the ΔΣ modulator, increases the linearity requirements, and increases the design difficulty.

Summary of the invention

To solve the above technical problems, the present invention proposes a ZOOM ADC using adaptive tracking, which solves the over-range error problem of the ZOOM ADC by accumulating digital codewords after repeated comparison of LSB (Least Significant Bit) and feeding them back to the tracking capacitor array.

One of the technical solutions adopted by the present invention is: a ZOOM ADC using adaptive tracking, a coarse quantization ADC capacitor array, a tracking capacitor array, an integrator, a comparator and a digital logic module; a complete working cycle of the ZOOM ADC includes three parts in sequence: sampling, a coarse quantization conversion cycle, and an adaptive tracking conversion cycle;

During sampling, the coarse quantization ADC capacitor array samples the input signal;

In the coarse quantization conversion cycle, the coarse quantization ADC capacitor array, comparator, and digital logic participate in the coarse quantization process; after the comparator quantizes the upper plate level of the coarse quantization ADC capacitor array, it is stored and transmitted to the lower plate of the coarse quantization ADC capacitor array through the digital logic module to generate the residual voltage of the next coarse quantization process; the coarse quantization process is performed M times, where M is the number of coarse quantization bits;

In the adaptive tracking conversion cycle, ZOOM ADC adopts adaptive tracking conversion, which includes OSR times of adaptive tracking conversion process; the tracking capacitor array, integrator, comparator and digital logic module participate in each adaptive tracking conversion process; the level of the upper plate of the tracking capacitor array is integrated on the integrator, quantized by the comparator, and then stored by the digital logic module to obtain the digital code DT, which is passed to the lower plate of the tracking capacitor array after digital domain integration of DT, and a new residual voltage is generated on the upper plate to participate in the next adaptive tracking conversion process;

The digital codeword obtained by coarse quantization is aligned and reorganized with the adaptive tracking conversion digital codeword DT to finally obtain the digital output of ZOOM ADC.

The second technical solution adopted by the present invention is: a ZOOM ADC using adaptive tracking, comprising: a coarse quantization ADC capacitor array, a tracking capacitor array, an integrator, a comparator and a digital logic module; a complete working cycle of the ZOOM ADC includes three parts in sequence: sampling, a coarse quantization conversion cycle, and an adaptive tracking conversion cycle;

During sampling, the coarse quantization ADC capacitor array samples the input signal;

In the coarse quantization conversion cycle, the coarse quantization ADC capacitor array, comparator, and digital logic participate in the coarse quantization process; after the comparator quantizes the upper plate level of the coarse quantization ADC capacitor array, it is stored and transmitted to the lower plate of the coarse quantization ADC capacitor array through the digital logic to generate the residual voltage of the next coarse quantization process; the coarse quantization process is performed M times, where M is the number of coarse quantization bits;

In the adaptive tracking conversion cycle, ZOOM ADC adopts adaptive tracking conversion, which includes OSR times of adaptive tracking conversion process; the tracking capacitor array, integrator, comparator and digital logic participate in each adaptive tracking conversion process; the level of the upper plate of the tracking capacitor array is integrated on the integrator, quantized by the comparator, and then stored by the digital logic module to obtain the digital code DT, which is converted into a binary signal through accumulation processing of DT, and the binary signal is transmitted to the lower plate of the tracking capacitor array, and a new residual voltage is generated on the upper plate to participate in the next precise quantization conversion;

The digital codeword obtained by coarse quantization is aligned and reorganized with the adaptive tracking conversion digital codeword DT to finally obtain the digital output of ZOOM ADC.

The third technical solution adopted by the present invention is: a ZOOM ADC using adaptive tracking, comprising: a capacitor array, an integrator, a comparator and a digital logic module; a complete working cycle of the ZOOM ADC includes three parts in sequence: sampling, a coarse quantization conversion cycle, and an adaptive tracking conversion cycle;

During sampling, the capacitor array collects the input signal;

In the coarse quantization conversion cycle, the capacitor array, comparator, and digital logic module participate in the coarse quantization process; after the comparator quantizes the upper plate level of the capacitor array, it is stored and transmitted to the lower plate of the coarse quantization capacitor array through the digital logic module to generate the residual voltage of the next coarse quantization process; this process is performed M times, where M is the number of coarse quantization bits;

In the adaptive tracking conversion cycle, the ZOOM ADC adopts adaptive tracking conversion, which includes OSR times of adaptive tracking conversion process; the capacitor array, integrator, comparator and digital logic module participate in each adaptive tracking conversion process; the level of the upper plate of the capacitor array is integrated on the integrator, quantized by the comparator, and then stored by the digital logic module to obtain the digital code DT, and the DT and the coarse quantization codeword are added in the digital domain, and the value is passed to the lower plate of the capacitor array, and a new residual voltage is generated on the upper plate to participate in the next adaptive tracking conversion process;

The digital codeword obtained by coarse quantization is aligned and reorganized with the adaptive tracking conversion digital codeword DT to finally obtain the digital output of ZOOM ADC.

Beneficial effects of the present invention: The ZOOM ADC proposed in the present invention, by adding a tracking capacitor array, integrates the digital code after repeated comparison of the LSB bit after quantization of the SAR ADC and feeds it back to the tracking capacitor array, can adaptively track the signal, solves the problem that the traditional ZOOM ADC is prone to overload, increases the effective number of bits of the SAR ADC, and can obtain higher accuracy under the same energy consumption.

The design embodiment of the adaptive tracking technology proposed in the present invention can effectively solve the over-range error problem during the fine conversion of the traditional ZOOM ADC, increase the effective number of bits of the SAR ADC, improve the accuracy of the ZOOM ADC, reduce circuit complexity, and reduce costs.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of an oversampling ADC;

FIG2 is a block diagram of the ZOOM ADC;

FIG3 is a schematic diagram of SAR ADC quantization operation and ΔΣ modulator reference voltage range selection;

FIG4 is a schematic diagram showing the effect of offset and noise on SAR conversion and ΔΣ modulator reference voltage;

FIG5 is a schematic diagram of expanding the reference voltage range of the ΔΣ modulator;

FIG6 is a schematic diagram of the structure of the adaptive tracking technology;

FIG7 is a schematic diagram of an adaptive tracking conversion process;

Figure 8 is a comparison of the SNDR of the two structures under ideal conditions;

Among them, (a) is the traditional ZOOM structure, (b) is the ZOOM structure with adaptive tracking;

Figure 9 is a comparison of the SNDR of the two structures under the influence of non-ideal factors;

Among them, (a) is the traditional ZOOM structure, (b) is the ZOOM structure with adaptive tracking;

FIG10 is a ZOOM ADC embodiment using adaptive tracking technology provided by an embodiment of the present invention;

FIG11 is a timing diagram of the circuit shown in FIG10 ;

FIG. 12 is a schematic diagram of a first alternative solution of the present invention.

FIG. 13 is a schematic diagram of a second alternative solution of the present invention.

DETAILED DESCRIPTION

To facilitate those skilled in the art to understand the technical content of the present invention, the present invention is further explained below with reference to the accompanying drawings.

The present invention proposes an Adaptive-Tracking technology. By accumulating the digital codewords after repeated comparison of LSB and feeding them back to the tracking capacitor array, the over-range error problem of the ZOOM ADC is solved. Compared with the two commonly used solutions described in the background technology, the method of the present invention can improve the resolution of the SAR ADC in the ZOOM ADC and reduce the design requirements of the ΔΣ modulator: small OSR, lower order, and improved accuracy of the ZOOM ADC. The method of the present invention has low circuit complexity and low implementation cost, and is suitable for high-precision ADC design in the fields of test measurement, sensing, industrial control, etc.

The Adaptive-Tracking technology structure proposed in the present invention is shown in FIG6 , and includes: a SAR quantizer, a ΔΣ quantizer, and a tracking capacitor array connected in series between the SAR quantizer and the ΔΣ quantizer.

After the SAR ADC coarse quantization is completed, the quantization result is finely quantized. The digital code DT obtained by fine quantization is accumulated and fed back to the tracking capacitor array, thereby achieving the effect of adaptive tracking. The adaptive tracking conversion process is shown in Figure 7.

As can be seen from Figure 7, even if the comparator error occurs during the SAR ADC conversion stage and adaptive tracking conversion, resulting in an over-range error, the adaptive tracking technology can keep the input of the ΔΣ modulator within the quantization range. For the traditional ZOOM ADC structure, if an error occurs in the SAR conversion stage, it may not converge in the fine quantization stage and the circuit cannot work effectively.

The traditional ZOOM ADC and the ZOOM ADC using adaptive tracking technology are simulated using MATLAB. When other conditions are the same, the same comparator noise is given to the two ZOOM ADCs with different structures as shown in Figures 2 and 6, and the output results of the two ZOOM ADCs are compared.

In the absence of non-ideal factors such as noise and offset voltage, the signal-to-noise-distortion ratio (SNDR) of the two ZOOM ADCs with different architectures as shown in Figures 2 and 6 is basically the same, and the MATLAB simulation results are shown in Figure 8. Given that the comparator noise voltage is about 0.5mV, the SNDR of the ZOOM ADC using the adaptive tracking structure proposed by the present invention is 29dB higher than the SNDR of the traditional ZOOM ADC structure, and the MATLAB simulation results are shown in Figure 9. In Figures 8 and 9, Spectrum represents the spectrum; input frequency represents the input frequency; SFDR is abbreviated as Spurious Free Dynamic range, which means spurious-free dynamic range; SNDR is abbreviated as Signal-to-Noise-and-Distortion Ratio, which means signal-to-noise-distortion ratio; ENOB is abbreviated as Effective Number of Bits, which means effective number of bits.

In order to verify the effect of the adaptive tracking technology, a ZOOM ADC architecture implementation example using the adaptive tracking technology is proposed here, and the specific structural block diagram is shown in FIG10 .

The circuit structure is a Nyquist sampling ADC structure. After sampling the input signal, M (M ≥ 10) bits of SAR ADC conversion and OSR times of adaptive tracking conversion are performed. The timing diagram of the circuit is shown in Figure 11:

During the sampling period, the sampling switch Φ _S is closed, the switch Φ _SAR connected in parallel with the integrator is disconnected, the capacitor Φ _track switch in the integrator is disconnected, and the capacitors in the SAR capacitor array collect the input voltage signal to the lower plate of the capacitor;

In the SAR conversion cycle, the sampling switch Φ _S is disconnected, the switch Φ _SAR connected in parallel with the integrator is closed, the capacitor Φ _track in the integrator is disconnected, and the signal collected by the SAR capacitor array is output by the digital logic after passing through the comparator. The digital code word D_SAR is fed back to the lower plate of the SAR capacitor array, causing the upper plate to generate a residual voltage.

In the adaptive tracking conversion cycle, the sampling switch Φ _S is disconnected, the switch Φ _SAR connected in parallel with the integrator is disconnected, and the capacitor Φ _track in the integrator is closed. The residual voltage obtained in the SAR quantization stage is sequentially outputted as a digital code word DT after passing through the integrator, comparator, and digital logic. The digital code word DT is fed back to the lower plate of the tracking array to accumulate the voltage on the upper plate.

The input signal of the integrator in the first tracking conversion cycle is the residual voltage obtained in the SAR quantization stage, and the input signals of the integrators in subsequent tracking conversion cycles are the accumulated voltages obtained in the previous tracking conversion cycle.

The digital codeword D_SAR after digital processing of the comparator result of the SAR conversion cycle and the digital codeword DT after digital processing of the comparator result of the tracking conversion cycle are connected to the filter for alignment and reorganization to obtain the output codeword D _{out of} the ZOOM ADC. The digital codeword DT is fed back to the lower plate of the tracking array to accumulate the voltage of the upper plate, thereby realizing the accumulation of tracking feedback signals in the analog domain. In the fine quantization part of the traditional ZOOM ADC, the ΔΣ modulator needs to sample the residual voltage and then integrate and compare it. The adaptive tracking technology proposed in the present invention directly integrates and compares the residual voltage, eliminating the sampling cycle time of the ΔΣ modulator and reducing the bandwidth requirement of the integrator.

The present invention proposes a simple and effective ZOOM ADC technology for improving ADC accuracy. The technology realizes adaptive tracking technology by reasonably increasing redundant unit DACs and using continuous time integrators. The method can adaptively track the quantization results of SAR ADC, thereby effectively solving the problem that the coarse quantization results in the traditional ZOOM ADC are not within the reference voltage range of the ΔΣ modulator, resulting in over-range errors. At the same time, due to the implementation of the adaptive tracking technology, the accuracy of the SAR ADC in the ZOOM ADC can be improved, and the bandwidth of the ZOOM ADC can be increased to achieve higher energy efficiency. As the examples listed in the embodiments, the method can effectively improve the accuracy of the ZOOM ADC, and has low circuit complexity and low implementation cost, and is suitable for high-precision ADC design in the fields of test measurement, sensing, industrial control, etc.

Compared with reducing the resolution of SAR ADC, this technology can improve the resolution of coarse quantization SAR ADC in ZOOM ADC to more than 10 bits, reduce the accuracy requirements of fine quantization ΔΣ modulator, and optimize the speed, power consumption and area of ZOOM ADC.

Compared with the method of expanding the range of the ΔΣ modulator reference voltage, this technology reduces the input signal amplitude of the ΔΣ modulator, reduces the output signal swing of the integrator, reduces the linearity requirement, and reduces the design difficulty. In addition, this technology uses the SAR ADC sampling conversion method to realize the oversampling function of the ΔΣ modulator, reduces the number of required bit cycles, and reduces the energy consumption of the ADC.

The ZOOM ADC embodiment of the present invention that applies the adaptive tracking technology performs accumulation processing on the tracking feedback signal in the analog domain, specifically: the digital codeword DT is fed back to the lower plate of the tracking array, so that the upper plate voltage is accumulated, and the accumulation of the tracking feedback signal in the analog domain is realized. In addition to this scheme, in order to reduce the layout area and reduce the number of adaptive tracking capacitors, it is possible to choose to accumulate the tracking feedback signal in the digital logic. After the accumulation processing of 32 tracking feedback signals, a five-bit binary signal DN<5:1> is obtained, and this signal is fed back to the capacitor array. The capacitor array only needs 5 unit capacitors, which is 27 unit capacitors less than the analog domain accumulation scheme, saving layout area. The specific implementation is shown in Figure 12. The timing diagram of the circuit is shown in Figure 11:

In the sampling period, the sampling switch Φ _S is closed, the switch Φ _SAR connected in parallel with the integrator is disconnected, the capacitor Φ _track in the integrator is disconnected, the clock signal of the comparator is at a low level, and the capacitors in the SAR capacitor array collect the input voltage signal to the lower plate of the capacitor;

In the SAR conversion cycle, the sampling switch Φ _S is disconnected, the switch Φ _SAR connected in parallel with the integrator is closed, the capacitor Φ _track in the integrator is disconnected, and the clock signal of the comparator is a periodic high and low level. After the signal collected by the SAR capacitor array passes through the comparator, the digital logic outputs the digital code word D_SAR; the digital code word D_SAR is fed back to the lower plate of the SAR capacitor array, so that the upper plate generates a residual voltage;

In the adaptive tracking conversion cycle, the sampling switch Φ _S is disconnected, the switch Φ _SAR connected in parallel with the integrator is disconnected, the capacitor Φ _track in the integrator is closed, and the clock signal of the comparator is a periodic high and low level. The residual voltage obtained in the SAR quantization stage is sequentially outputted as a digital code word DT after passing through the integrator, the comparator, and the digital logic. The binary signal obtained after the accumulation processing of the digital code word DT is fed back to the lower plate of the tracking array, so that the voltage of the upper plate is accumulated;

The input signal of the integrator in the first tracking conversion cycle is the residual voltage obtained in the SAR quantization stage, and the input signals of the integrators in subsequent tracking conversion cycles are the accumulated voltages obtained in the previous tracking conversion cycle.

In the above two schemes, the coarse quantization capacitor array and the adaptive tracking capacitor array work separately, and the feedback signal can be fed back to the same capacitor array in the coarse quantization cycle and the adaptive tracking cycle. This requires adding the coarse quantization feedback signal and the tracking feedback signal in the digital domain, and then feeding the signal back to the lower plate of the capacitor in the capacitor array to accumulate the voltage of the upper plate. The specific implementation is shown in Figure 13. The timing diagram of the circuit is shown in Figure 11:

In the sampling period, the sampling switch Φ _S is closed, the switch Φ _SAR connected in parallel with the integrator is disconnected, the capacitor Φ _track in the integrator is disconnected, the clock signal of the comparator is at a low level, and the capacitors in the SAR capacitor array collect the input voltage signal to the lower plate of the capacitor;

In the SAR conversion cycle, the sampling switch Φ _S is disconnected, the switch Φ _SAR connected in parallel with the integrator is closed, the capacitor Φ _track in the integrator is disconnected, and the clock signal of the comparator is a periodic high and low level. After the signal collected by the SAR capacitor array passes through the comparator, the digital logic outputs the digital code word D_SAR; the digital code word D_SAR is fed back to the lower plate of the SAR capacitor array, so that the upper plate generates a residual voltage;

In the adaptive tracking conversion cycle, the sampling switch Φ _S is disconnected, the switch Φ _SAR connected in parallel with the integrator is disconnected, the capacitor Φ _track in the integrator is closed, the clock signal of the comparator is a periodic high and low level, and the residual voltage obtained in the SAR quantization stage is sequentially outputted as a digital code word DT after passing through the integrator, the comparator, and the digital logic, and the result after the addition of the digital code word DT and the digital code word D_SAR is fed back to the lower plate of the SAR capacitor array, so that the voltage of the upper plate is accumulated;

The input signal of the integrator in the first tracking conversion cycle is the residual voltage obtained in the SAR quantization stage, and the input signals of the integrators in subsequent tracking conversion cycles are the accumulated voltages obtained in the previous tracking conversion cycle.

V _cm in Figures 10, 12, and 13 is the common mode voltage, which is a DC level and is half the power supply voltage.

Those skilled in the art will appreciate that the embodiments described herein are intended to help readers understand the principles of the present invention, and should be understood that the scope of protection of the present invention is not limited to such specific statements and embodiments. For those skilled in the art, the present invention may have various changes and variations. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present invention should be included in the scope of the claims of the present invention.

Claims (4)

1. A ZOOM ADC employing adaptive tracking, comprising: the digital circuit comprises a coarse quantization ADC capacitor array, a tracking capacitor array, an integrator, a comparator and a digital logic module; a complete duty cycle of the ZOOM ADC comprises three parts in sequence: sampling, coarse quantization conversion period and self-adaptive tracking conversion period;

During sampling, the coarse quantization ADC capacitor array collects an input signal;

In the coarse quantization conversion period, the coarse quantization ADC capacitor array, the comparator and the digital logic participate in the coarse quantization process; the comparator quantizes the level of the upper polar plate of the coarse quantization ADC capacitor array, registers and transmits the level to the lower polar plate of the coarse quantization ADC capacitor array through the digital logic module, and generates residual voltage in the next coarse quantization process; the coarse quantization process is performed M times, M being the number of coarse quantization bits;

In the self-adaptive tracking conversion period, the ZOOM ADC adopts self-adaptive tracking conversion, and the period comprises OSR times of self-adaptive tracking conversion process; the tracking capacitor array, the integrator, the comparator and the digital logic module participate in each self-adaptive tracking conversion process; the level of the upper polar plate of the tracking capacitor array is integrated on an integrator, quantized by a comparator, registered by a digital logic module to obtain a digital code DT, integrated by a digital domain of DT, and then transmitted to the lower polar plate of the tracking capacitor array, and a new residual voltage generated on the upper polar plate participates in the next self-adaptive tracking conversion process;

And (3) aligning and recombining the digital code word obtained by coarse quantization with the adaptive tracking conversion digital code word DT to finally obtain the digital output of the ZOOM ADC.

2. A ZOOM ADC employing adaptive tracking, comprising: the digital circuit comprises a coarse quantization ADC capacitor array, a tracking capacitor array, an integrator, a comparator and a digital logic module; a complete duty cycle of the ZOOM ADC comprises three parts in sequence: sampling, coarse quantization conversion period and self-adaptive tracking conversion period;

During sampling, the coarse quantization ADC capacitor array collects an input signal;

in the coarse quantization conversion period, the coarse quantization ADC capacitor array, the comparator and the digital logic participate in the coarse quantization process; the comparator quantizes the level of the upper polar plate of the coarse quantization ADC capacitor array, registers and transmits the level to the lower polar plate of the coarse quantization ADC capacitor array through digital logic, and generates residual voltage in the next coarse quantization process; the coarse quantization process is performed M times, M being the number of coarse quantization bits;

In the self-adaptive tracking conversion period, the ZOOM ADC adopts self-adaptive tracking conversion, and the period comprises OSR times of self-adaptive tracking conversion process; the tracking capacitor array, the integrator, the comparator and the digital logic participate in each self-adaptive tracking conversion process; the level of the upper polar plate of the tracking capacitor array is integrated on an integrator, quantized by a comparator, registered by a digital logic module to obtain a digital code DT, and the digital code DT is converted into a binary signal through accumulation treatment of the DT, and the binary signal is transmitted to the lower polar plate of the tracking capacitor array, so that a new residual voltage is generated on the upper polar plate to participate in the next fine quantization conversion;

And (3) aligning and recombining the digital code word obtained by coarse quantization with the adaptive tracking conversion digital code word DT to finally obtain the digital output of the ZOOM ADC.

3. A ZOOM ADC with adaptive tracking as recited in claim 2, wherein the number of capacitances in the tracking capacitance array is equal to the number of binary signal bits.

4. A ZOOM ADC employing adaptive tracking, comprising: a capacitor array, an integrator, a comparator and a digital logic module; a complete duty cycle of the ZOOM ADC comprises three parts in sequence: sampling, coarse quantization conversion period and self-adaptive tracking conversion period;

during sampling, the capacitor array collects input signals;

In the coarse quantization conversion period, the capacitor array, the comparator and the digital logic module participate in the coarse quantization process; after quantizing the upper polar plate level of the capacitor array, the comparator registers and transmits the quantized upper polar plate level to the lower polar plate of the coarse quantized capacitor array through the digital logic module to generate residual voltage of the next coarse quantization process; the process is carried out for M times, wherein M is the coarse quantization bit number;

in the self-adaptive tracking conversion period, the ZOOM ADC adopts self-adaptive tracking conversion, and the period comprises OSR times of self-adaptive tracking conversion process; the capacitor array, the integrator, the comparator and the digital logic module participate in each self-adaptive tracking conversion process; after the level of the upper polar plate of the capacitor array is integrated on the integrator, the level is quantized by the comparator, then the digital code DT is obtained by the register of the digital logic module, the value is transferred to the lower polar plate of the capacitor array by adding the DT and the coarse quantized code word in the digital domain, and a new residual voltage is generated on the upper polar plate to participate in the next self-adaptive tracking conversion process;

And (3) aligning and recombining the digital code word obtained by coarse quantization with the adaptive tracking conversion digital code word DT to finally obtain the digital output of the ZOOM ADC.