CN118800806B - A UMOSFET device with a protruding P-well and a method for manufacturing the same - Google Patents
A UMOSFET device with a protruding P-well and a method for manufacturing the same Download PDFInfo
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Abstract
The invention discloses a UMOSFET device with a protruding P well and a preparation method thereof, the UMOSFET device comprises a drift region and a channel region which is arranged above the drift region, the channel region comprises a groove, a first current transmission layer and corner accumulation regions which are arranged at two sides of the first current transmission layer are arranged at the bottom of the groove, a second current transmission layer is arranged below the first current transmission layer and is overlapped with the first current transmission layer, the second current transmission layer extends to the drift region from the lower surface of the first current transmission layer, the orthographic projection of the second current transmission layer is positioned in the middle of the orthographic projection of the first current transmission layer along the direction perpendicular to the drift region, the doping concentration of the second current transmission layer is smaller than that of the first current transmission layer, a gate dielectric layer is arranged above the first current transmission layer and the corner accumulation regions, the gate dielectric layer is of a U-shaped structure, and a gate electrode is arranged in the gate dielectric layer. The invention can improve the performance of the device.
Description
Technical Field
The invention belongs to the technical field of semiconductors, and particularly relates to a UMOSFET device with a protruding P-well and a preparation method thereof.
Background
With the rapid development of the power electronics industry, the decisive power semiconductor devices become a direct factor influencing the cost and efficiency of the power electronics. At present, semiconductor Silicon-based power devices are very mature, but as power semiconductors gradually develop to high power, high frequency and low power consumption, silicon (Si) based devices are difficult to be suitable for application scenes of high voltage, high temperature, high efficiency and high power density due to the limitation of physical characteristics of the Silicon (Si) based devices.
Because of their superior physical properties, siC (Siliconcarbide) materials have come to be widely focused by practitioners, so that SiC MOSFET (siliconcarbide metal oxide semiconductor FIELD EFFECT transmitter) technology has been developed, and compared with silicon-based devices, the characteristics of high thermal conductivity, large forbidden bandwidth, and the like of SiC materials determine the application scenarios of the SiC materials in high current density, high breakdown field strength, and high operating temperature. Compared with Si MOSFETs under the same level, the characteristic on-resistance and switching loss of the SiC MOSFETs are suitable for higher working frequency, the high-temperature stability is greatly improved due to the high heat conductivity, but the conventional UMOSFET (TRENCH GATE METAL Oxide Semiconductor FIELD EFFECT Transistor) device is easy to gather electric fields at the corners of a gate oxide layer, so that the problems of reliability of the oxide layer, service life reduction and the like are caused.
Accordingly, there is a need to improve the above-mentioned problems in the prior art.
Disclosure of Invention
In order to solve the above problems in the prior art, the present invention provides a UMOSFET device with an outstanding P-well and a method of fabricating the same. The technical problems to be solved by the invention are realized by the following technical scheme:
In a first aspect, the present invention provides a UMOSFET device with a protruding P-well, comprising:
A drift region;
The semiconductor device comprises a drift region, a channel region, a grid dielectric layer and a grid electrode, wherein the channel region is arranged above the drift region and is overlapped with the drift region, the channel region comprises a groove, a first current transmission layer and corner stacking regions positioned at two sides of the first current transmission layer are arranged at the bottom of the groove, a second current transmission layer is arranged below the first current transmission layer and is overlapped with the first current transmission layer, the second current transmission layer extends to the drift region from the lower surface of the first current transmission layer, orthographic projection of the second current transmission layer is positioned in the middle of orthographic projection of the first current transmission layer along the direction perpendicular to the drift region, the doping concentration of the second current transmission layer is smaller than that of the first current transmission layer, the grid dielectric layer is arranged above the first current transmission layer and the corner stacking regions, and the grid dielectric layer is of a U-shaped structure and is arranged in the grid dielectric layer.
In a second aspect, the present application also provides a method for manufacturing a UMOSFET device with protruding P-wells, comprising:
Providing a drift region;
The method comprises the steps of growing a channel region on a drift region, forming a groove in the channel region by etching, carrying out ion implantation on the bottom of the groove to form a first current transmission layer at the bottom of the groove, an ion implantation layer on the side wall of the groove and a corner accumulation region at the corner of the groove respectively, depositing a shielding layer on the upper surfaces of the first current transmission layer, the ion implantation layer and the corner accumulation region, etching away part of the shielding layer above the first current transmission layer to expose the first current transmission layer, carrying out ion implantation on the exposed first current transmission layer to form a second current transmission layer, extending the second current transmission layer from the lower surface of the first current transmission layer to the drift region, etching away the rest of the shielding layer, oxidizing part of the first current transmission layer, the ion implantation layer and part of the corner accumulation region to form a silicon dioxide sacrificial oxide layer, corroding the silicon dioxide sacrificial oxide layer to remove the ion implantation layer, depositing a gate dielectric layer in the processed groove to form a U-shaped structure, and depositing a gate electrode on the gate dielectric layer.
The invention has the beneficial effects that:
According to the UMOSFET device with the protruding P-well and the preparation method thereof, the trench gate is arranged in the channel region and is arranged on the gate dielectric layer, the gate dielectric layer is arranged in the trench in the channel region, in the prior art, the UMOSFET device is easy to collect an electric field at corners of the gate dielectric layer, so that defects on the gate dielectric layer are more, the reliability of the device is affected, and in the invention, the first current transmission layer and the second current transmission layer are arranged below the gate dielectric layer of the trench gate, the electric field originally collected at corners of the gate dielectric layer is pushed into a semiconductor, and it can be understood that the electric field collected at corners of the gate oxide layer can be pushed into a silicon carbide body due to the fact that the depth of the protruding P-type well region is larger than the depth of the gate oxide layer, meanwhile, the P-type well region is epitaxially grown, the problem of reliability of the gate oxide layer can be solved, other additional high-doped P-type regions are not needed, the cell size of the device can be effectively reduced, and the characteristic on-resistance of the device can be effectively reduced. Further, the invention considers that a region with smaller space exists between the P-type well region and the gate oxide layer, if the doping concentration in the N-type region is smaller, the limiting current path comprises two factors, namely, the formation of an inversion layer in a channel due to the depletion between the P-type well region and the N-type region, the depletion of part of the N-type region on a current transmission path is the main influencing factor of threshold voltage, therefore, the doping concentration of the first current transmission layer is larger than that of the second current transmission layer, the first current transmission layer adopts higher doping concentration, the limitation of the current path is readjusted to the formation of the inversion layer in the channel, the problem that the threshold voltage of the device is positively biased due to the depletion between the P-well and the trench gate of the protruding P-well UMOSFET device can be solved, and the second current transmission layer adopts lower doping concentration for opening the conductive path of N-type doping and simultaneously preventing the reliability problem of the gate oxide layer due to higher doping concentration of the current transmission layer.
The present invention will be described in further detail with reference to the accompanying drawings and examples.
Drawings
FIG. 1 is a schematic diagram of a UMOSFET device with a protruding P-well provided in an embodiment of the present invention;
FIG. 2 is a schematic diagram of a UMOSFET device of the prior art;
FIG. 3 is a schematic diagram of a UMOSFET device with a protruding P-well provided in accordance with an embodiment of the present invention;
FIG. 4 is a flow chart of a method of fabricating a UMOSFET device with protruding P-wells provided in an embodiment of the present invention;
Fig. 5 (a) - (5 (j)) are schematic diagrams of a method for manufacturing a UMOSFET device with protruding P-wells according to an embodiment of the present invention.
Detailed Description
The present invention will be described in further detail with reference to specific examples, but embodiments of the present invention are not limited thereto.
The invention solves the problem that the reliability and the service life of an oxide layer are reduced due to the fact that an electric field is easy to gather at the corner of the gate oxide layer of an ordinary UMOSFET device by utilizing the special prominent P well morphology, and specifically comprises the following steps:
The first current transmission layer 6 and the second current transmission layer 8 are arranged below the trench gate, the problem that the P-well and the trench gate of the prominent P-well UMOSFET device are depleted due to the fact that the P-well and the trench gate are depleted is solved by the aid of the high doping concentration of the first current transmission layer 6, the threshold voltage forward bias of the device is affected, and the second current transmission layer 8 is low in doping concentration and used for opening an N-type doped conductive path and simultaneously preventing the reliability problem of a gate oxide layer caused by the fact that the doping concentration of the current transmission layer is high.
Referring to fig. 1, fig. 1 is a schematic diagram of a UMOSFET device with protruding P-wells according to an embodiment of the present invention, where the UMOSFET device with protruding P-wells includes:
A drift region 2;
The semiconductor device comprises a drift region 2, a channel region 3, a first current transmission layer 6, a corner accumulation region 7, a second current transmission layer 8, a gate dielectric layer 9 and a gate electrode 10, wherein the channel region 3 is arranged above the drift region 2 and is overlapped with the drift region 2, the channel region 3 comprises a groove, a first current transmission layer 6 and corner accumulation regions 7 are arranged at the bottom of the groove, the corner accumulation regions 7 are arranged at the two sides of the first current transmission layer 6, the second current transmission layer 8 is arranged below the first current transmission layer 6 and is overlapped with the first current transmission layer 6, the second current transmission layer 8 extends from the lower surface of the first current transmission layer 6 to the drift region 2, the orthographic projection of the second current transmission layer 8 is positioned in the middle of the orthographic projection of the first current transmission layer 6 along the direction perpendicular to the drift region, the doping concentration of the second current transmission layer 8 is smaller than that of the first current transmission layer 6, the gate dielectric layer 9 is arranged above the first current transmission layer 6 and the corner accumulation regions 7, the gate dielectric layer 9 is of a U-shaped structure, and the gate electrode 10 is arranged in the gate dielectric layer 9.
Specifically, please continue to refer to fig. 1, in the UMOSFET device with protruding P-well provided in this embodiment, a trench gate is provided in the channel region 3, the trench gate is provided on the gate dielectric layer 9, the gate dielectric layer 9 is provided in the trench in the channel region 3, in the prior art, the UMOSFET device easily gathers electric fields at corners of the gate dielectric layer 9, so that defects on the gate dielectric layer 9 are more, the reliability of the device is affected, please refer to the position indicated by circle 15 in fig. 2, namely, an electric field gathering area, fig. 2 is a schematic diagram of the UMOSFET device in the prior art, in the present invention, a first current transmission layer 6 and a second current transmission layer 8 are provided below the gate dielectric layer 9 of the trench, the electric field originally gathered at corners of the gate dielectric layer 9 is pushed into the semiconductor, it can be understood that, because the depth of the protruding P-well region is greater than the depth of the gate oxide layer, the electric field gathered at corners of the gate oxide layer can be pushed into the silicon carbide, meanwhile, the P-well region is epitaxial growth, and the P-well region is a reliable region of the P-well can not be pushed into the semiconductor region, and the size of the field can be reduced by the semiconductor device in the field region in the channel region 3, and the field region in the field region is further required to be reduced, the size of the field-conducting region is reduced, and the field-effect is further to be reduced by the field-doped region in the semiconductor device, and the field-cell device is shown in the schematic diagram, and the invention has the size is in the field-figure has the field-effect, and the effect has the effect.
In this embodiment, considering that there is a region with a smaller distance between the P-type well region and the gate oxide layer, if the doping concentration in the N-type region is smaller here, the limiting current path includes two factors, namely, the formation of the inversion layer in the channel due to the depletion between the P-type well region and the N-type region, and the depletion of a part of the N-type region on the current transmission path is the main influencing factor of the threshold voltage, therefore, the doping concentration of the first current transmission layer 6 is greater than the doping concentration of the second current transmission layer 8 in this embodiment, the first current transmission layer 6 adopts a higher doping concentration, and the limitation of the current path is readjusted to the formation of the inversion layer in the channel, so that the problem that the threshold voltage of the device is positively biased due to the depletion between the P-well region and the trench gate existing in the protruding P-well UMOSFET device can be solved, and the second current transmission layer 8 adopts a lower doping concentration for opening the N-type doped conductive path while preventing the reliability problem of the gate oxide layer due to the higher doping concentration of the current transmission layer.
It should be noted that, the embodiment shown in fig. 1 only schematically illustrates the positional relationship of each film layer and does not represent the actual dimension thereof, the embodiment shown in fig. 2 only schematically illustrates the position where the electric field is concentrated in the prior art, and the embodiment shown in fig. 3 only schematically illustrates the position where the electric field is pushed into the semiconductor according to the present invention.
In an alternative embodiment of the present invention, the doping concentration of the first current transport layer 6 is 9E16cm -3~1E18cm-3, the doping concentration of the corner stack 7 is 9E16cm -3~1E18cm-3, and the first current transport layer 6 is prepared simultaneously with the corner stack 7.
Specifically, referring to fig. 1, in the present embodiment, the doping ions of the first current transmission layer 6 may be N (nitrogen), P (phosphorus), etc. to form an N-type semiconductor, and compared with the doping concentration of the second current transmission layer 8, the threshold voltage caused by depletion at the ring 14 in fig. 1 is affected by the doping concentration of the channel region 3, the thickness of the oxide layer, various defects and charges in the oxide layer, defects and charges at the interface between the oxide layer and the semiconductor, and the depletion between PN, and the higher doping concentration can solve the problem. In addition, during the process of forming the first current transport layer 6, a deposition of dopant ions is generated at the bottom corners of the trench, and a deposition of dopant ions is also generated at the sidewalls of the trench, the doping concentration of which fluctuates in the vicinity of the doping concentration of the first current transport layer 6, the doping impurities are the same as those of the first current transport layer 6, and the corner deposition region 7 has the same function as the first current transport layer 6.
In an alternative embodiment of the invention, the doping concentration of the second current transport layer 8 is 3E16cm -3~5E17cm-3.
Specifically, referring to fig. 1, in the present embodiment, the doping ions of the second current transmission layer 8 may be N (nitrogen), P (phosphorus), etc. to form an N-type semiconductor, the first current transmission layer 6 and the second current transmission layer 8 combine to open a current path as shown in fig. 1, as indicated by a dotted line in fig. 1, so as to prevent the doping concentration of the first current transmission layer 6 from being too high compared with the doping concentration of the first current transmission layer 6, and to cause an electric field to gather toward the middle of the bottom of the gate oxide, thereby affecting the reliability of the gate oxide.
In an alternative embodiment of the present invention, further comprising:
A substrate 1 positioned below the drift region 2 and stacked with the drift region 2;
the drain electrode 13 is positioned below the substrate 1 and is stacked with the substrate 1.
Specifically, referring to fig. 1, in this embodiment, the substrate 1 is an N-type substrate, the doping concentration of the N-type drift region is 5E15cm -3~1E16cm-3, the doping ions may be N (nitrogen), P (phosphorus) or other impurity ions capable of forming an N-type semiconductor, the channel region 3 is a P-type channel region, the doping concentration is 8E16cm -3~2E17cm-3, and the doping ions may be B (boron), AL (aluminum) or other impurity ions capable of forming a P-type semiconductor.
In an alternative embodiment of the present invention, further comprising:
an N+ source region 4, which displaces both sides of the trench;
The P+ source region 5 is positioned at one side of the N+ source region 4 away from the groove;
The dielectric layer 11 is arranged above the gate electrode 10, the gate dielectric layer 9 and part of the N+ source region 4 in a laminated manner, and it is understood that the dielectric layer 11 is arranged in a laminated manner with the gate electrode 10, the dielectric layer 11 is arranged in a laminated manner with the gate dielectric layer 9, and the dielectric layer 11 is arranged in a laminated manner with part of the N+ source region 4;
The source electrode 12 is located above the dielectric layer 11, part of the n+ source region 4 and the p+ source region 5 and is stacked, the source electrode 12 and the n+ source region 4 form ohmic contact, it is understood that the source electrode 12 is stacked with the dielectric layer 11, the source electrode 12 and part of the n+ source region 4 are stacked, and the source electrode 12 and the p+ source region 5 are stacked.
Specifically, referring to fig. 1, in the embodiment, the doping concentration of the n+ Source region 4 is 1E19cm -3~5E20cm-3, the doping ions may be N (nitrogen), P (phosphorus) and other impurity ions capable of forming an N-type semiconductor, ohmic contact is formed with the Source electrode (Source) 12, the doping concentration of the p+ Source region 5 is 8E16cm -3~2E17cm-3, the doping ions may be B (boron), AL (aluminum) and other impurity ions capable of forming a P-type semiconductor, and the dielectric layer 11 may be spin-on glass.
In an alternative embodiment of the present invention, the gate dielectric layer 9 may be made of different materials according to different processes, silicon dioxide is used as the dielectric material in the case of an oxidation process, silicon dioxide (SiO 2), aluminum oxide (Al 2O3), gallium oxide (Ga 2O3), hafnium oxide (HfO 2), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO 2), zirconium oxynitride (ZrON) or the like, a combination of two processes or a combination of several materials, or the gate dielectric layer 9 may be made by an ALD (atomic layer deposition) process.
In an alternative embodiment of the present invention, the gate electrode 10 is polysilicon.
Based on the same inventive concept, please refer to fig. 4, fig. 4 is a flowchart of a method for manufacturing a UMOSFET device with protruding P-wells according to an embodiment of the present invention, and a method for manufacturing a UMOSFET device with protruding P-wells according to an embodiment of the present invention, where reference is made to the above embodiments of the device, and the method for manufacturing the UMOSFET device with protruding P-wells is not described herein:
S101, providing a drift region 2.
S102, growing a channel region 3 on a drift region 2, etching the channel region 3 to form a groove by an etching method, carrying out ion implantation at the bottom of the groove to form a first current transmission layer 6 at the bottom of the groove, an ion implantation layer on the side wall of the groove and a corner stacking region 7 at the corner of the groove respectively, depositing shielding layers on the upper surfaces of the first current transmission layer 6, the ion implantation layer and the corner stacking region 7, etching away part of the shielding layers above the first current transmission layer 6 to expose the first current transmission layer 6, carrying out ion implantation on the exposed first current transmission layer 6 to form a second current transmission layer, wherein the second current transmission layer 8 extends to the drift region 2 from the lower surface of the first current transmission layer 6, etching away the rest of the shielding layers, oxidizing part of the first current transmission layer 6, the ion implantation layer and part of the corner stacking region 7 to form a silicon dioxide sacrificial oxide layer, etching the silicon dioxide sacrificial oxide layer to remove the ion implantation layer, depositing a gate dielectric layer 9 in the processed groove in a U-shaped structure, and depositing a gate electrode 10 on the gate electrode 9.
In summary, in the preparation method of the UMOSFET device with the protruding P-well, the trench gate is arranged in the channel region 3, the trench gate is arranged on the gate dielectric layer 9, the gate dielectric layer 9 is arranged in the trench in the channel region 3, in the prior art, the UMOSFET device easily gathers electric fields at corners of the gate dielectric layer 9, so that defects on the gate dielectric layer 9 are more, the reliability of the device is affected, and in the preparation method, referring to fig. 2, the first current transmission layer 6 and the second current transmission layer 8 are arranged below the gate dielectric layer 9 of the trench, the electric fields gathered at the corners of the gate dielectric layer 9 are pushed into a semiconductor, and the fact that the depth of the protruding P-type well region is larger than the depth of the gate oxide layer can be understood that the electric fields gathered at the corners of the gate oxide layer are pushed into silicon carbide, meanwhile, the P-type well region is epitaxially grown, the reliability problem of the gate oxide layer can be solved, other high-doped P-type regions are not needed, the cell size can be effectively reduced, and the on-resistance of the device can be effectively reduced.
In this embodiment, considering that there is a region with a smaller distance between the P-type well region and the gate oxide layer, if the doping concentration in the N-type region is smaller here, the limiting current path includes two factors, namely, the formation of the inversion layer in the channel due to the depletion between the P-type well region and the N-type region, and the depletion of a part of the N-type region on the current transmission path is the main influencing factor of the threshold voltage, therefore, the doping concentration of the first current transmission layer 6 is greater than the doping concentration of the second current transmission layer 8 in this embodiment, the first current transmission layer 6 adopts a higher doping concentration, and the limitation of the current path is readjusted to the formation of the inversion layer in the channel, so that the problem that the threshold voltage of the device is positively biased due to the depletion between the P-well region and the trench gate existing in the protruding P-well UMOSFET device can be solved, and the second current transmission layer 8 adopts a lower doping concentration for opening the N-type doped conductive path while preventing the reliability problem of the gate oxide layer due to the higher doping concentration of the current transmission layer.
In an alternative embodiment of the present invention, further comprising:
Providing a substrate 1;
growing a drift region 2 over a substrate 1;
A drain electrode 13 is prepared below the substrate 1.
In an alternative embodiment of the present invention, further comprising:
A first mask layer grows above the channel region 3, then the first mask layer in the middle of the upper part of the channel region 3 is glued, exposed, developed and etched, photoresist is removed, N-type ions are implanted to form an N+ source region 4, and the first mask layer remained on two sides above the channel region 3 is corroded;
and growing a second mask layer above the channel region 3, gluing, exposing, developing, etching the second mask layers on two sides above the channel region 3, photoresist removing, and P-type ion implantation to form a P+ source region 5, and etching the second mask layer remained in the middle above the channel region 3.
In an alternative embodiment of the present invention, further comprising:
a dielectric layer 11 is deposited above the N+ source region 4, the gate dielectric layer 9 and the gate electrode 10;
A source electrode 12 is prepared above the dielectric layer 11 and the P + source region 5.
In an alternative embodiment of the present invention, please refer to fig. 5 (a) to 5 (j), and fig. 5 (a) to 5 (j) are schematic diagrams of a method for manufacturing a UMOSFET device with protruding P-wells according to an embodiment of the present invention, in which the UMOSFET device with protruding P-wells is manufactured by:
S1, epitaxially growing an N-type drift region and a P-type channel region on a substrate 1, wherein the thickness of the N-type drift region is determined by the voltage withstand class of the device, the doping concentration and the thickness of the N-type drift region of a general 1200V-level device are respectively 8E15cm -3 and 9 mu m, the thickness of the P-type channel region is larger than the thickness of a gate oxide layer, and particularly, when the depth of a groove is 1 mu m, the thickness of the P-type channel region is 1.0-3.0 mu m, as shown in fig. 5 (a).
S2, growing a first mask layer on the P-type channel region by CVD, then gluing, exposing and developing, etching the first mask layer, removing photoresist, performing N-type ion implantation to form an N+ source region 4, wherein the depth is 0.15-0.3 mu m, and etching the first mask layer remained above the P-type channel region, as shown in fig. 5 (b).
S3, growing a second mask layer above the P-type channel region, gluing, exposing, developing, etching the second mask layer above the P-type channel region, photoresist removing, and P-type ion implantation to form a P+ source region 5, wherein the P+ depth is 0.3-1.0 mu m, and etching away the second mask layer remained above the channel region 3, as shown in fig. 5 (c).
S4, etching a groove in the P-type channel region, wherein the width of the groove is 0.4-2.0 mu m, the depth of the groove is 0.4-2.0 mu m, but the depth of the gate electrode 10 is always smaller than the thickness of the P-type channel region 3, and the etching mask layer can be silicon dioxide, nickel metal and the like, as shown in fig. 5 (d).
S5, directly performing N-type ion implantation without removing the etching mask layer, forming a first current transmission layer 6 at the bottom of the groove, forming a first current transmission layer 6, generating accumulation at the corners of the groove according to the different doses and energy of the ion implantation, and generating non-ideal ion implantation at the side wall of the groove, wherein if the ion implantation energy is not large, the non-ideal ion implantation of the side wall is not obvious, and the depth of the first current transmission layer 6 does not exceed the bottom surface of the P-type channel region, as shown in fig. 5 (e).
S6, depositing an ion implantation shielding layer on the basis of the process S5, as shown in fig. 5 (f), etching the semiconductor at the bottom of the exposed groove, and performing ion implantation to form a second current transmission layer 8, wherein the bottom of the second current transmission layer 8 exceeds the P-type channel region, as shown in fig. 5 (g).
S7, after removing all mask layers, oxidizing 1-2 hours at 900-1600 ℃, wherein the oxidation time is different according to the oxidation temperature, the oxidation method comprises dry oxidation, wet oxidation and the like, a silicon dioxide sacrificial oxide layer is formed on the side wall of the groove and the upper surface and the lower surface of the wafer after oxidation, as shown in fig. 5 (h), and then the sacrificial oxide layer is corroded, wherein the sacrificial oxide layer is used for removing non-ideal ions possibly existing in the process, as shown in fig. 5 (i).
S8, preparing a gate dielectric layer 9 in the groove, wherein the method for preparing the gate dielectric layer 9 can be dry oxidation, wet oxidation, plasma oxidation, chemical vapor deposition (PECVD/LPCVD), atomic layer deposition and the like, dielectric materials can be silicon dioxide (SiO 2), aluminum oxide (Al 2O3), gallium oxide (Ga 2O3), hafnium oxide (HfO 2), hafnium silicon oxynitride (HfSiON), zirconium oxide (ZrO 2), zirconium oxynitride (ZrON) and the like, or can be a combination of two processes or a combination of a plurality of materials, and after the gate dielectric layer 9 is completed, polysilicon gate electrode deposition, polysilicon back etching, ILD (interlayer dielectric) formation and source electrode preparation are carried out, as shown in fig. 5 (j).
It should be noted that in this document relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed. Without further limitation, an element defined by the phrase "comprising one does not exclude the presence of other like elements in an article or apparatus that comprises the element. The terms "connected" or "connected," and the like, are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect. The orientation or positional relationship indicated by "upper", "lower", "left", "right", etc. is based on the orientation or positional relationship shown in the drawings, and is merely for convenience of description and to simplify the description, and is not indicative or implying that the apparatus or elements referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as limiting the invention.
In the description of the present specification, a description referring to terms "one embodiment," "some embodiments," "examples," "specific examples," or "some examples," etc., means that a particular feature or characteristic described in connection with the embodiment or example is included in at least one embodiment or example of the present invention. In this specification, schematic representations of the above terms are not necessarily directed to the same embodiment or example. Furthermore, the particular features or characteristics described may be combined in any suitable manner in any one or more embodiments or examples. Furthermore, one skilled in the art can combine and combine the different embodiments or examples described in this specification.
The foregoing is a further detailed description of the invention in connection with the preferred embodiments, and it is not intended that the invention be limited to the specific embodiments described. It will be apparent to those skilled in the art that several simple deductions or substitutions may be made without departing from the spirit of the invention, and these should be considered to be within the scope of the invention.
Claims (10)
1. A method of fabricating a UMOSFET device with protruding P-wells, comprising:
Providing a drift region;
Forming a channel region on the drift region, etching the channel region to form a groove by an etching method, carrying out ion implantation at the bottom of the groove, generating accumulation at the corners of the groove according to different doses and energy of the ion implantation to form a corner accumulation region, generating non-ideal ion implantation at the side wall of the groove to form an ion implantation layer at the side wall of the groove, forming a first current transmission layer at the bottom of the groove, wherein the depth of the first current transmission layer is not more than the bottom surface of a P-type channel region, depositing shielding layers at the upper surfaces of the first current transmission layer, the ion implantation layer and the corner accumulation region, etching away part of the shielding layers above the first current transmission layer to expose the first current transmission layer, forming a second current transmission layer extending from the lower surface of the first current transmission layer to the drift region, the bottom of the second current transmission layer exceeds the P-type channel region, etching away the second current transmission layer at the bottom of the second current transmission layer is less than the bottom surface of the P-type channel region, etching away from the silicon dioxide layer at the side wall of the first current transmission layer, etching away from the silicon dioxide layer, removing the silicon dioxide layer in the side wall of the groove, forming a silicon dioxide layer, etching away from the silicon oxide layer, removing the silicon dioxide layer in the groove, etching the silicon oxide layer, removing the silicon oxide layer, removing the oxide layer, and removing the oxide layer, and depositing a gate electrode on the gate dielectric layer.
2. The method of fabricating a UMOSFET device with protruding P-wells of claim 1, further comprising:
Providing a substrate;
Growing a drift region over the substrate;
a drain electrode is prepared below the substrate.
3. The method of fabricating a UMOSFET device with protruding P-wells of claim 1, further comprising:
A first mask layer grows above the channel region, then the first mask layer in the middle of the upper part of the channel region is glued, exposed, developed and etched, photoresist is removed, N-type ions are implanted to form an N+ source region, and the first mask layer remained on two sides above the channel region is corroded;
and growing a second mask layer above the channel region, gluing, exposing, developing, etching the second mask layer on two sides above the channel region, photoresist removing, and P-type ion implantation to form a P+ source region, and etching the second mask layer remained in the middle above the channel region.
4. The method of fabricating a UMOSFET device with protruding P-wells of claim 3, further comprising:
Depositing a dielectric layer above the N+ source region, the gate dielectric layer and the gate electrode;
and preparing a source electrode above the dielectric layer and the P+ source region.
5. The method of fabricating a UMOSFET device with protruding P-wells of claim 1, wherein the etching to form trenches in the channel region by etching comprises:
and growing a third mask layer above the drift region, etching the third mask layer in the middle above the channel region, and etching the middle region of the channel region to form a groove.
6. A UMOSFET device with protruding P-wells, prepared using the method of preparing a UMOSFET device with protruding P-wells as claimed in any one of claims 1-5, comprising:
A drift region;
The semiconductor device comprises a drift region, a channel region, a grid dielectric layer and a grid electrode, wherein the channel region is arranged above the drift region and is overlapped with the drift region, the channel region comprises a groove, a first current transmission layer and corner accumulation regions arranged at two sides of the first current transmission layer are arranged at the bottom of the groove, a second current transmission layer is arranged below the first current transmission layer and is overlapped with the first current transmission layer, the second current transmission layer extends from the lower surface of the first current transmission layer to the drift region, the orthographic projection of the second current transmission layer is positioned in the middle of the orthographic projection of the first current transmission layer along the direction perpendicular to the drift region, the doping concentration of the second current transmission layer is smaller than that of the first current transmission layer, the grid dielectric layer is arranged above the first current transmission layer and the corner accumulation regions, and the grid dielectric layer is of a U-shaped structure, and the grid electrode is arranged in the grid dielectric layer.
7. The UMOSFET device with protruding P-wells of claim 6 wherein the first current transport layer has a doping concentration of 9E16cm "3 to 1E18 cm" 3, the corner stack region has a doping concentration of 9E16cm "3 to 1E18 cm" 3, and the first current transport layer is fabricated simultaneously with the corner stack region.
8. The UMOSFET device with protruding P-wells of claim 6, wherein the second current transport layer has a doping concentration of 3E16cm "3 to 5E17 cm" 3.
9. The UMOSFET device with protruding P-wells as recited in claim 6, further comprising:
a substrate positioned below the drift region and stacked with the drift region;
and the drain electrode is positioned below the substrate and is laminated with the substrate.
10. The UMOSFET device with protruding P-wells as recited in claim 6, further comprising:
the N+ source regions are positioned at two sides of the groove;
the P+ source region is positioned at one side of the N+ source region, which is away from the groove;
the dielectric layer is positioned above the gate electrode, the gate dielectric layer and part of the N+ source region and is arranged in a stacked manner;
And the source electrode is positioned above the dielectric layer, part of the N+ source region and the P+ source region, and is stacked, and the source electrode and the N+ source region form ohmic contact.
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