CN118796342A - Instruction processing method, device and virtual machine - Google Patents

Abstract

The invention provides an instruction processing method, an instruction processing device and a virtual machine, and relates to the technical field of communication. The method comprises the following steps: acquiring a virtual Instruction Set (ISA) carried in an application program; according to virtual ISA execution task arrangement management, determining a virtual ISA sequence corresponding to a task to be executed; and converting the virtual ISA codes in the virtual ISA sequences into target ISA codes corresponding to different types of accelerators respectively. The invention can solve the problems that the computational system realizing isomerization and parallelization based on the traditional mode needs to carry out complicated scheduling according to the change of hardware, the system load is higher and the scheduling model is complex.

Description

Instruction processing method, device and virtual machine

Technical Field

The present invention relates to the field of communication technology, and in particular to an instruction processing method, device and virtual machine.

Background Art

With the rapid development of applications such as artificial intelligence and big data, higher requirements are brought about for the computing power and timeliness of diversified massive data, and greater computing power is needed for computing support. Limited by technical processes such as hardware architecture and communication bus, the computing power of traditional general-purpose central processing units (CPUs) tends to be saturated. Therefore, in order to improve computing performance, increase system flexibility and adaptability, and thus meet the needs of different computing tasks, computing systems are developing towards heterogeneity and parallelization. Heterogeneity refers to the use of processors and accelerators that are different from the CPU architecture in computing systems to optimize the execution of specific computing tasks, such as graphics processing units (GPUs), digital signal processors (DSPs), and tensor processing units (TPUs). These accelerators have higher performance and efficiency in specific tasks. By assigning tasks to processors and accelerators suitable for execution, heterogeneous computing systems can better utilize hardware resources and improve overall computing performance. Parallelization refers to decomposing computing tasks into multiple subtasks, and simultaneously interconnecting multiple processor nodes or accelerator nodes to form a distributed parallel system on which these subtasks are executed. By distributing tasks to multiple computing nodes, multiple subtasks can be processed simultaneously, thus accelerating the entire computing process. However, since each manufacturer's hardware can only recognize and run applications that conform to its own instruction set architecture, the traditional way of implementing heterogeneous and parallel computing systems requires the use of tools from different manufacturers to generate different instruction set (Instruction Set Architecture) codes corresponding to each manufacturer's accelerator, which will lead to complicated scheduling according to hardware changes, high system load and complex scheduling model.

Summary of the invention

The purpose of the present invention is to provide an instruction processing method, device and virtual machine to solve the problem that a heterogeneous and parallel computing system implemented in a traditional way requires complicated scheduling according to hardware changes, the system load is high and the scheduling model is also complex.

To achieve the above object, an embodiment of the present invention provides an instruction processing method, comprising:

Get the virtual ISA hosted in the application;

Perform task scheduling management according to the virtual ISA and determine the virtual ISA sequence corresponding to the task to be executed;

The virtual ISA code in the virtual ISA sequence is converted into target ISA codes corresponding to different types of accelerators.

Optionally, performing task scheduling management according to the virtual ISA to determine a virtual ISA sequence corresponding to the task to be executed includes:

Performing task scheduling management according to the virtual ISA to determine at least one virtual task cluster; wherein each of the virtual task clusters includes at least one virtual thread;

The virtual threads in each virtual task cluster run the same program to obtain a virtual ISA sequence corresponding to the task to be executed.

Optionally, performing task scheduling management according to the virtual ISA to determine at least one virtual task cluster includes:

Performing task identification according to the virtual ISA to determine the task to be performed;

According to the tasks to be executed, the virtual ISA is optimized and arranged to determine at least one virtual task cluster.

Optionally, the method further comprises:

Generate virtual task cluster related information;

Storing the virtual task cluster related information;

The virtual task cluster related information includes at least one of the following:

Identification information of a virtual task cluster, used to indicate a reading position of input data used by the virtual task cluster, and/or a writing position of output data generated by the virtual task cluster;

Dimension information of a virtual task cluster, used to indicate the number of virtual threads included in the virtual task cluster;

The identification information of the virtual thread is used to indicate a reading position of input data used by the virtual thread and/or a writing position of output data generated by the virtual thread.

Optionally, performing task scheduling management according to the virtual ISA to determine at least one virtual task cluster includes:

Performing task identification according to the virtual ISA to determine the task to be performed;

According to the task to be executed, the virtual ISA is task-decomposed to obtain at least one task partition; wherein different task partitions correspond to different parts of the task to be executed;

At least one virtual task cluster is determined according to each of the task partitions; wherein different virtual task clusters in each task partition are independent of each other, and the virtual task clusters in each task partition run the same program.

Optionally, the method further comprises:

Generate task partition related information;

Storing the task partition related information;

The task partition related information includes at least one of the following:

The identification information of the task partition is used to indicate the reading position of the input data used by the task partition and/or the writing position of the output data generated by the task partition;

The dimension information of the task partition is used to indicate the number of virtual task clusters contained in the task partition.

Optionally, after converting the virtual ISA code in the virtual ISA sequence into target ISA codes corresponding to different types of accelerators, the method further includes:

The target ISA code is cached in a data buffer corresponding to each accelerator.

The present application also provides an instruction processing device, including:

An acquisition module, used to acquire the virtual ISA carried in the application;

A determination module, used for performing task scheduling management according to the virtual ISA, and determining the virtual ISA sequence corresponding to the task to be executed;

The conversion module is used to convert the virtual ISA code in the virtual ISA sequence into target ISA codes corresponding to different types of accelerators.

The embodiment of the present application also provides a virtual machine, including: a virtual instruction loader, a virtual accelerator execution engine, and a virtual instruction model converter; wherein,

The virtual instruction loader is used to load the virtual ISA carried in the application program;

The virtual accelerator execution engine performs task arrangement management on the virtual ISA loaded by the virtual instruction loader, and determines the virtual ISA sequence corresponding to the task to be executed;

The virtual instruction model converter converts the virtual ISA code in the virtual ISA sequence obtained by the virtual accelerator execution engine performing task arrangement management into target ISA codes corresponding to different types of accelerators.

Optionally, the virtual machine further includes: a data buffer; wherein,

The virtual instruction model converter caches the target ISA code to the data buffer; wherein the virtual instruction model converter shares memory with the accelerator.

An embodiment of the present application also provides a virtual machine, including: a transceiver, a processor, a memory, and a program or instruction stored in the memory and executable on the processor; when the processor executes the program or instruction, the steps of the instruction processing method described above are implemented.

An embodiment of the present application also provides a readable storage medium on which a program or instruction is stored. When the program or instruction is executed by a processor, the steps of the instruction processing method as described above are implemented.

An embodiment of the present application also provides a computer program product, including computer instructions, which implement the steps of the instruction processing method described above when executed by a processor.

The beneficial effects of the above technical solution of the present invention are as follows:

In the embodiment of the present application, a virtual ISA compatible with multiple heterogeneous instructions is set, and a unified task scheduling management is performed for the virtual ISA compatible with multiple heterogeneous instructions to obtain a virtual ISA sequence corresponding to the task to be executed, and the virtual ISA sequence obtained by performing unified task scheduling management on the virtual ISA is converted to obtain target ISA codes corresponding to each type of accelerator. In this way, for multiple heterogeneous accelerators with the same function, a unified scheduling management can be performed using the virtual ISA to obtain target ISA codes corresponding to each type of accelerator, which will greatly improve the collaborative use efficiency of the hybrid heterogeneous system and solve the problem that the computing system based on the traditional method of heterogeneity and parallelization needs to be complicatedly scheduled according to the changes in the hardware, the system load is high, and the scheduling model is also relatively complex.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a schematic diagram of a computing system that implements heterogeneity and parallelization based on a traditional approach;

FIG2 is a flow chart of an instruction processing method according to an embodiment of the present application;

FIG3 is a block diagram of an instruction processing device according to an embodiment of the present application;

FIG4 is a block diagram of a virtual machine according to an embodiment of the present application;

FIG5 is a second block diagram of a virtual machine according to an embodiment of the present application;

FIG6 is a third block diagram of the virtual machine according to an embodiment of the present application.

DETAILED DESCRIPTION

In order to make the technical problems, technical solutions and advantages to be solved by the present invention more clear, a detailed description will be given below with reference to the accompanying drawings and specific embodiments.

It should be understood that the references to "one embodiment" or "an embodiment" throughout the specification mean that the specific features, structures, or characteristics associated with the embodiment are included in at least one embodiment of the present invention. Therefore, the references to "in one embodiment" or "in an embodiment" appearing throughout the specification do not necessarily refer to the same embodiment. In addition, these specific features, structures, or characteristics may be combined in any suitable manner in one or more embodiments.

In various embodiments of the present invention, it should be understood that the size of the serial numbers of the following processes does not mean the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of the present invention.

Additionally, the terms "system" and "network" are often used interchangeably herein.

In the embodiments provided in the present application, it should be understood that "B corresponding to A" means that B is associated with A, and B can be determined according to A. However, it should also be understood that determining B according to A does not mean determining B only according to A, and B can also be determined according to A and/or other information.

The instruction architecture of high-performance heterogeneous accelerated computing systems is mainly divided into two types of instruction forms: Single Instruction Multiple Data (SIMD) and Single Instruction Multiple Threads (SIMT). Different manufacturers have derived their own hardware instruction sets within the framework of the instruction form.

As shown in Figure 1, hardware from each manufacturer can only recognize and run applications that conform to its own instruction set architecture. Applications cannot recognize each other and cannot run across instruction architectures. At the same time, to generate applications, it is necessary to use the compiler and other tools of each manufacturer to generate them. Therefore, in the current clusters that are mixed with multiple types of heterogeneous computing systems, developers need to use tools from different manufacturers to develop and package applications for a certain function, and generate multiple binary files of different ISA versions of the same functional application. If business applications that integrate these binary files need to run in parallel in the cluster, they need to be complicatedly scheduled according to hardware changes, and the system load is extremely high and the scheduling model is extremely complex.

As mentioned above, it is very difficult to develop a program that can run in parallel for a mixed heterogeneous system according to the technical solution shown in Figure 1. It is usually required that the programmer knows the number of available processing units and their capabilities (instruction sets, number of data registers, interconnects, etc.) in order to create code that can actually be executed by the processing units. Although machine-specific compilers can provide considerable help in this regard, it is still necessary to recompile the code every time the code is ported to a different processor.

In addition, various aspects of parallel processing architectures are evolving rapidly. For example, new platform architectures, instruction sets, and programming models are being developed. As various aspects of the parallel architecture (e.g., programming models or instruction sets) change from one generation to the next, applications, software libraries, compilers, and other software and tools need to change accordingly. This instability can add considerable overhead to the development and maintenance of parallel processing code.

When coordination between threads is required, parallel programming becomes more difficult. The programmer needs to determine that there are mechanisms available to support (or emulate) inter-thread communication on a particular processor or computer system, and needs to write code that takes advantage of the available mechanisms. Because the available and/or optimal mechanisms are generally different on different computer systems, this type of parallel code is generally not portable; the parallel code needs to be rewritten for each hardware platform on which it runs.

In addition to providing executable code for the processor, programmers also need to provide control code for the CPU processor, which coordinates the operations of various heterogeneous hardware, for example, instructing each processing unit which program to execute and which input data to process, etc. The above control code is usually dedicated to a specific host processor and the communication protocol between processors, and if a different host processor is to be replaced, the control code usually needs to be rewritten.

The difficulty in compiling and recompiling parallel processing codes may make users reluctant to upgrade their systems as computing technology develops, and it also makes system design extremely difficult. The system structure and scheduling model are extremely complex, making it difficult to exert the overall performance of the system cluster. Therefore, it will be necessary to separate the compiled parallel processing code from a specific hardware platform and provide a stable parallel processing structure and instruction set as the target of parallel applications and tools.

In order to overcome the deficiencies in the prior art, the purpose of the present invention is to provide an instruction processing method, device and virtual machine for the current heterogeneous SIMD and SIMT instruction types with different parameter lengths and different single instructions, so as to solve the problem that a computing system that realizes heterogeneity and parallelization based on traditional methods needs to perform complicated scheduling according to hardware changes, the system load is high and the scheduling model is also complex.

As shown in FIG2 , the embodiment of the present application provides an instruction processing method, comprising the following steps:

Step 21: Get the virtual ISA hosted within the application.

Optionally, the virtual ISA is compatible with multiple heterogeneous instructions, such as SIMD, SIMT, etc. Specifically, the virtual ISA can be used to define a set of virtual instructions for computing task processing behaviors, including but not limited to at least one of the following: basic instructions such as access instructions, arithmetic operation instructions, logical operation instructions, shift instructions, selection instructions, comparison instructions, sorting instructions, and vector processing instructions.

Step 22: Perform task scheduling management according to the virtual ISA and determine the virtual ISA sequence corresponding to the task to be executed.

In this embodiment, a unified task scheduling management is performed for a virtual ISA compatible with multiple heterogeneous instructions to obtain a virtual ISA sequence corresponding to the task to be executed. Optionally, the virtual ISA sequence is composed of a virtual ISA code, which is a unified ISA code obtained by performing unified task scheduling management for a virtual ISA compatible with multiple heterogeneous instructions and can be applied to different types of accelerators.

Step 23: Convert the virtual ISA code in the virtual ISA sequence into target ISA codes corresponding to different types of accelerators.

Optionally, since different types of accelerators use different compilation methods, etc., the virtual ISA sequence obtained by performing unified task orchestration management on the virtual ISA is converted to obtain target ISA codes corresponding to each type of accelerator, so that each type of accelerator can recognize the corresponding ISA code and execute the corresponding function.

In the above scheme, a virtual ISA compatible with multiple heterogeneous instructions is set up, and unified task scheduling management is performed for the virtual ISA compatible with multiple heterogeneous instructions to obtain a virtual ISA sequence corresponding to the task to be executed, and the virtual ISA sequence obtained by performing unified task scheduling management on the virtual ISA is converted to obtain target ISA codes corresponding to each type of accelerator. In this way, for multiple heterogeneous accelerators with the same function, a unified scheduling management can be performed using the virtual ISA to obtain target ISA codes corresponding to each type of accelerator, which will greatly improve the collaborative efficiency of the hybrid heterogeneous system and solve the problem that the computing system based on traditional methods to achieve heterogeneity and parallelization needs to be complicatedly scheduled according to hardware changes, the system load is high, and the scheduling model is also relatively complex.

Optionally, obtain the virtual ISA hosted in the application, including:

Based on the virtual mapping model, the virtual instructions carried in the application are loaded.

For example, an application may define a data processing application that may be processed in a manner including virtual task clusters or VTCs and/or in a manner including task partitions. Optionally, the application may define at least one of the following:

Applications define behaviors using virtual task clusters or VTCs;

The application defines the dimensions of the virtual task cluster or VTC (e.g., the number of virtual threads contained), and if task partitioning is to be used, the dimensions of the task partition (e.g., the number of virtual task clusters or VTCs contained);

The application defines the input data sets to be processed by the virtual task cluster or VTC (or task partition) and the locations where the output data sets will be stored;

The application defines the overall processing behavior, such as when to start each virtual task cluster or VTC (or task partition). The application may include additional code that dynamically determines the dimensions of virtual task clusters or VTCs (or the dimensions of task partitions), whether to continuously start new virtual task clusters or VTC dimensions (or task partitions), etc.

For example, an application may be written in a high-level programming language such as C/C++, FORTRAN, etc. In one example, a C/C++ application directly specifies the behavior of a virtual thread. An application is written in a data parallel language (e.g., FORTRAN, C#, or openCL, etc.), and the application specifies data parallel operations on arrays and aggregate data structures; this application may be compiled into a virtual ISA program code that specifies the behavior of a VTC thread. In order to allow the behavior of a virtual thread to be defined, a language extension or function library may be provided in some embodiments, through which a programmer may specify the behavior of a parallel virtual thread. For example, special symbols or variables may be defined to correspond to thread IDs, VTC IDs, and task partition IDs, and functions may be provided through which a programmer may indicate when a virtual thread should synchronize with other virtual threads.

Optionally, performing task scheduling management according to the virtual ISA to determine a virtual ISA sequence corresponding to the task to be executed includes:

Performing task scheduling management according to the virtual ISA to determine at least one virtual task cluster; wherein each of the virtual task clusters includes at least one virtual thread;

The virtual threads in each virtual task cluster run the same program to obtain a virtual ISA sequence corresponding to the task to be executed.

Optionally, the virtual task cluster is an array group composed of a plurality of virtual threads that concurrently execute the same virtual instruction on an input data set to generate an output data set, or is called a group of multiple virtual threads that concurrently execute the same program on an input data set to generate an output data set. A virtual task cluster includes at least one virtual thread, so a virtual task cluster may also be called a virtual thread cluster (Virtual Thread Cluster, VTC), and the program may be called a VTC program.

For example, in a virtual task cluster or VTC, data can be generated by one virtual thread and consumed by another virtual thread. In certain embodiments, synchronization instructions can be inserted into the VTC program code at the point where the data will be shared to ensure that the virtual thread that generates the data actually generates the data before the virtual thread that consumes the data attempts to access the data. Optionally, if the virtual threads in the virtual task cluster or VTC support data sharing, the degree of data sharing can be determined by the VTC program. Of course, it should be noted that in the specific application using the virtual task cluster or VTC, the virtual threads in the virtual task cluster or VTC may or may not actually share data with each other, which may specifically depend on the VTC program, and the embodiments of the present application are not specifically limited.

Optionally, performing task scheduling management according to the virtual ISA to determine at least one virtual task cluster includes:

Performing task identification according to the virtual ISA to determine the task to be performed;

According to the tasks to be executed, the virtual ISA is optimized and arranged to determine at least one virtual task cluster.

In this embodiment, at least one virtual task cluster is determined according to the task scheduling management of the virtual ISA, that is, unified virtual computing is performed on the computing tasks corresponding to the virtual ISA. The virtual computing includes but is not limited to task identification, optimization scheduling, etc.

Optionally, the method further includes:

Generate virtual task cluster related information;

Storing the virtual task cluster related information;

The virtual task cluster related information includes at least one of the following:

Identification information of a virtual task cluster, used to indicate a reading position of input data used by the virtual task cluster, and/or a writing position of output data generated by the virtual task cluster;

Dimension information of a virtual task cluster, used to indicate the number of virtual threads included in the virtual task cluster;

The identification information of the virtual thread is used to indicate a reading position of input data used by the virtual thread and/or a writing position of output data generated by the virtual thread.

Optionally, identification information, such as a unique thread identifier or thread ID, is configured for each virtual thread in a virtual task cluster, which can be accessed by the virtual thread during its execution. The thread ID, which can be defined as a one-dimensional or multi-dimensional numerical value, controls various aspects of the processing behavior of the thread. For example, the identification information of the virtual thread can be used to determine which part of the input data set the virtual thread will process, and/or, determine which part of the output data set the virtual thread will generate or write. In a virtual task cluster or VTC, virtual threads can collaborate by sharing data with each other in a manner that depends on identification information (such as a unique thread identifier or thread ID).

Optionally, each virtual task cluster determined for a certain task to be executed is configured with identification information, such as a virtual task cluster identifier or a VTC identifier (VTC ID). Similar to the identification information of a virtual thread, any unique identifier (including but not limited to a numerical identifier, etc.) can be used as a VTC ID. For each virtual thread in a virtual task cluster, a combination of the identification information of the virtual task cluster (such as a virtual task cluster identifier or a VTC ID) and the identification information of the virtual thread (such as a unique thread identifier or a thread ID) can be used to determine the location for reading input data and writing output data, so that each virtual task cluster or VTC operates on the correct portion of the input data set and writes its output data set portion to the correct location.

Optionally, a virtual thread in a virtual task cluster or VTC shares input data or intermediate results with other virtual threads in the same virtual task cluster or VTC. For example, a VTC program may include instructions for calculating the address to which specific data in a shared memory will be written, wherein the address may be a function of a thread ID. Each virtual thread uses its own thread ID to calculate the function and writes it to the corresponding location. An address function may be defined so that different threads write to different locations; as long as the function is deterministic, the location to which any virtual thread writes may be predicted. For another example, a VTC program may also include instructions for calculating the address in a shared memory from which data will be read, wherein the address is a function of a thread ID. By defining appropriate functions and providing synchronization techniques, data can be written to a given location in a shared memory by a virtual thread of a virtual task cluster or VTC in a predictable manner, and read from the location by different virtual threads of the same virtual task cluster or VTC. In this way, the virtual task cluster or VTC in the embodiment of the present application can support any required data sharing mode between virtual threads, and can support any virtual thread in the virtual task cluster or VTC to share data with any other virtual thread in the same virtual task cluster or VTC.

Optionally, performing task scheduling management according to the virtual ISA to determine at least one virtual task cluster includes:

Performing task identification according to the virtual ISA to determine the task to be performed;

According to the task to be executed, the virtual ISA is task-decomposed to obtain at least one task partition; wherein different task partitions correspond to different parts of the task to be executed;

At least one virtual task cluster is determined according to each of the task partitions; wherein different virtual task clusters in each task partition are independent of each other, and the virtual task clusters in each task partition run the same program.

In this embodiment, at least one virtual task cluster is determined according to the task scheduling management performed by the virtual ISA, that is, unified virtual computing is performed on the computing tasks corresponding to the virtual ISA, and the virtual computing includes but is not limited to task identification, decomposition, and optimized scheduling, etc. For example: optimizing and scheduling is performed according to each of the task partitions to determine at least one virtual task cluster.

Optionally, task decomposition or data parallel decomposition may include any situation in which the same algorithm is executed multiple times in parallel on the input data to generate output data to solve the computational problem. For example, data parallel decomposition involves applying the same processing algorithm to different parts of the input data set in order to generate different parts of the output data set. Examples of problems suitable for data parallel decomposition include matrix algebra, linear and/or nonlinear transformations of any number of dimensions (e.g., fast Fourier transforms), or various filtering algorithms such as convolution filtering of any number of dimensions, separable filtering of multiple dimensions. In some embodiments, the processing algorithm to be applied to each part of the input data set may be specified in a VTC program, and each virtual thread in a virtual task cluster or VTC executes the same VTC program on a part of the input data set. Optionally, the VTC program may support the use of a wide range of mathematical and logical operations to implement the algorithm, and/or, the VTC program may include conditional or branch execution paths and direct and/or indirect memory access.

Based on task decomposition or data parallel decomposition, at least one task partition can be obtained. Each task partition can be formed by a number of virtual task clusters or VTCs, and all virtual task clusters or VTCs in each task partition execute the same program. Each virtual task cluster or VTC can be constructed by a number of virtual threads, and all virtual thread blocks in each virtual task cluster or VTC can be of the same size and execute the same VTC program. For example, for a large image data input, this large processing task can be managed by dividing the image between multiple VTCs so that each VTC generates a different part of the output pixel (for example: 32x32 small pieces).

Optionally, several virtual task clusters or VTCs within a task partition may be independent of each other, meaning that the execution of any virtual task cluster or VTC in each task partition is not affected by the execution of other virtual task clusters or VTCs, which can significantly improve flexibility when allocating tasks among available processing cores.

Optionally, the method further comprises:

Generate task partition related information;

Storing the task partition related information;

The task partition related information includes at least one of the following:

The identification information of the task partition is used to indicate the reading position of the input data used by the task partition and/or the writing position of the output data generated by the task partition;

The dimension information of the task partition is used to indicate the number of virtual task clusters contained in the task partition.

Optionally, each task partition determined by decomposing a task to be executed is configured with identification information, such as a task partition identifier. In some embodiments, in order to distinguish different virtual task clusters or VTCs within a task partition, the task partition related information may further include identification information of each virtual task cluster or VTC of the task partition.

Optionally, the virtual threads in each virtual task cluster run the same program to obtain a virtual ISA sequence corresponding to the task to be executed, including:

In each virtual task cluster or task partition, multiple virtual threads run the same program in parallel to obtain a virtual ISA sequence corresponding to the task to be executed. For example, in each virtual task cluster or task partition, multiple virtual threads are supported to achieve mutual cooperation at the required time (for example, a representation of a parallel processor and associated memory space of a large number of concurrent virtual threads that share data and synchronize). The multiple virtual threads running the same program in parallel can be mapped to a variety of actual processors and/or processing systems, such as different types of GPUs, neural network processors (Neural network Processing Unit, NPU) or deep learning accelerators (Deep learning accelerator, DLA), etc.

Optionally, when the virtual threads in each virtual task cluster run the same program, several virtual memory spaces with different levels of data sharing and access types may be supported, as well as identifying a virtual ISA that supports all functions executed.

Specifically, the virtual ISA code in the virtual ISA sequence is converted into target ISA code corresponding to different types of accelerators, that is, the compiler generates virtual ISA code for the part of the application that defines the virtual thread behavior, and translates the virtual ISA code into target ISA code to be executed by the accelerator.

In certain embodiments, virtual ISA code is program code, but is not limited to the form code that can be executed on a specific target platform, such as virtual ISA code can be stored and/or distributed as any other program code. In other embodiments, application program can be designated as virtual ISA code wholly or in part, and can avoid using compiler wholly or in part. In certain embodiments, target ISA code is the code that can be directly executed by target platform, and target ISA code can be received and correctly decoded, depending on the particularity of target platform. Virtual ISA code can be translated into program code to be executed respectively by n0 threads on target platform. Or, virtual ISA code also can be translated into program code that will be less than n0 threads and executed respectively, wherein each thread comprises the processing task relevant with at least one virtual thread in virtual task cluster or VTC.

Optionally, after converting the virtual ISA code in the virtual ISA sequence into target ISA codes corresponding to different types of accelerators, the method further includes:

The target ISA code is cached in a data buffer corresponding to each accelerator.

In this embodiment, the target ISA code is cached in the data buffer corresponding to each accelerator, so that different types of accelerators can each obtain the corresponding target ISA code. That is, by sharing content with different types of accelerators, different types of accelerators can each obtain the corresponding target ISA code.

As shown in FIG3 , the embodiment of the present application provides an instruction processing device 300, including:

An acquisition module 310 is used to acquire a virtual instruction set ISA carried in an application program;

A determination module 320 is used to determine a virtual ISA sequence corresponding to a task to be executed according to the virtual ISA execution task arrangement management;

The conversion module 330 is used to convert the virtual ISA code in the virtual ISA sequence into target ISA codes corresponding to different types of accelerators.

Optionally, the determining module 320 includes:

A determination unit, configured to perform task scheduling management according to the virtual ISA and determine at least one virtual task cluster; wherein each of the virtual task clusters includes at least one virtual thread;

The processing unit is used to run the same program in the virtual threads in each virtual task cluster to obtain the virtual ISA sequence corresponding to the task to be executed.

Optionally, the determining unit is further configured to:

Performing task identification according to the virtual ISA to determine the task to be performed;

According to the tasks to be executed, the virtual ISA is optimized and arranged to determine at least one virtual task cluster.

Optionally, the determining module 320 further includes:

A first generating unit, used to generate virtual task cluster related information;

A first storage unit, used for storing information related to the virtual task cluster;

The virtual task cluster related information includes at least one of the following:

Identification information of a virtual task cluster, used to indicate a reading position of input data used by the virtual task cluster, and/or a writing position of output data generated by the virtual task cluster;

Dimension information of a virtual task cluster, used to indicate the number of virtual threads included in the virtual task cluster;

The identification information of the virtual thread is used to indicate a reading position of input data used by the virtual thread and/or a writing position of output data generated by the virtual thread.

Optionally, the determining unit is further configured to:

Performing task identification according to the virtual ISA to determine the task to be performed;

According to the task to be executed, the virtual ISA is task-decomposed to obtain at least one task partition; wherein different task partitions correspond to different parts of the task to be executed;

At least one virtual task cluster is determined according to each of the task partitions; wherein different virtual task clusters in each task partition are independent of each other, and the virtual task clusters in each task partition run the same program.

Optionally, the determining module 320 further includes:

The second generating unit is used to generate task partition related information;

A second storage unit, used for storing the task partition related information;

The task partition related information includes at least one of the following:

The identification information of the task partition is used to indicate the reading position of the input data used by the task partition and/or the writing position of the output data generated by the task partition;

The dimension information of the task partition is used to indicate the number of virtual task clusters contained in the task partition.

Optionally, the instruction processing device 300 further includes:

The cache module is used to cache the target ISA code into a data buffer corresponding to each accelerator.

It should be noted that the above-mentioned device and the above-mentioned instruction processing method of the embodiment of the present application are based on the same inventive concept, and the embodiments of the two can refer to each other, that is, the above-mentioned device can implement the various embodiments of the above-mentioned instruction processing method and can achieve the same technical effect. To avoid repetition, they will not be repeated here.

As shown in Figure 4, an embodiment of the present invention provides a virtual machine, which can support a virtual accelerator model with concurrent execution of multiple threads with multi-layer data sharing and computing task scheduling between different threads, and a virtual execution driver for controlling the virtual accelerator model. For example, multiple compilers with the same function uniformly configure a set of virtual instruction sets (vISA), and the virtual machine performs task scheduling management for the vISA, issues an executed virtual accelerator model and translates it into actual ISA code available for accelerators of various manufacturers. Among them, the virtual instruction set (vISA) is used to define a set of virtual instructions for computing task processing behavior in the virtual accelerator model, including but not limited to basic instructions such as access instructions, arithmetic operation instructions, logical operation instructions, shift instructions, selection instructions, comparison instructions, sorting instructions and vector processing instructions. Based on the virtual machine of the embodiment of the present application, it can provide programmers with an application program in which concurrent and cooperative threads are executed to process data. The hardware-specific virtual instruction translator and execution driver adapt the application code to the specific hardware on which it is executed. Therefore, the application program is more portable and easier to develop because the development process is independent of the specific processing hardware.

Specifically, as shown in FIG5 , the virtual machine includes: a virtual instruction loader, a virtual accelerator execution engine, and a virtual instruction model converter; wherein,

The virtual instruction loader is used to load the virtual instruction set ISA carried in the application program;

The virtual accelerator execution engine performs task arrangement management on the virtual ISA loaded by the virtual instruction loader, and determines the virtual ISA sequence corresponding to the task to be executed;

The virtual instruction model converter converts the virtual ISA code in the virtual ISA sequence obtained by the virtual accelerator execution engine performing task arrangement management into target ISA codes corresponding to different types of accelerators.

Optionally, the virtual machine is compatible with virtual ISAs including SIMD and SIMT, and the virtual accelerator execution engine and virtual instruction model converter can parse the virtual ISA and complete conversion to target ISA code that can be used by SIMD and SIMT type vendor-level accelerators.

The following example illustrates the processing flow of a virtual machine:

Step 1: The virtual machine loads the virtual instructions carried by the application through its internal virtual instruction loader. This process relies on the virtual mapping model to define the method and operate the conceptual model of the target processor or platform through the virtual device mapping model. The application can define a data processing application, which can be processed in a manner including virtual task clusters or VTCs, and/or in a manner including task partitions. Optionally, the application can define at least one of the following:

Applications define behaviors using virtual task clusters or VTCs;

The application defines the dimensions of the virtual task cluster or VTC (e.g., the number of virtual threads contained), and if task partitioning is to be used, the dimensions of the task partition (e.g., the number of virtual task clusters or VTCs contained);

The application defines the input data sets to be processed by the virtual task cluster or VTC (or task partition) and the locations where the output data sets will be stored;

The application defines the overall processing behavior, such as when to start each virtual task cluster or VTC (or task partition). The application may include additional code that dynamically determines the dimensions of virtual task clusters or VTCs (or the dimensions of task partitions), whether to continuously start new virtual task clusters or VTC dimensions (or task partitions), etc.

For example, an application may be written in a high-level programming language such as C/C++, FORTRAN, etc. In one example, a C/C++ application directly specifies the behavior of a virtual thread. An application is written in a data parallel language (e.g., FORTRAN, C#, or openCL, etc.), and the application specifies data parallel operations on arrays and aggregate data structures; this application may be compiled into a virtual ISA program code that specifies the behavior of a VTC thread. In order to allow the behavior of a virtual thread to be defined, a language extension or function library may be provided in some embodiments, through which a programmer may specify the behavior of a parallel virtual thread. For example, special symbols or variables may be defined to correspond to thread IDs, VTC IDs, and task partition IDs, and functions may be provided through which a programmer may indicate when a virtual thread should synchronize with other virtual threads.

When compiling an application, the compiler generates virtual ISA code for the portion of the application that defines the behavior of virtual threads, and translates the virtual ISA code into target ISA code to be executed by the accelerator.

In certain embodiments, virtual ISA code is program code, but is not limited to the form code that can be executed on a specific target platform, such as virtual ISA code can be stored and/or distributed as any other program code. In other embodiments, application program can be designated as virtual ISA code wholly or in part, and can avoid using compiler wholly or in part. In certain embodiments, target ISA code is the code that can be directly executed by target platform, and target ISA code can be received and correctly decoded, depending on the particularity of target platform. Virtual ISA code can be translated into program code to be executed respectively by n0 threads on target platform. Or, virtual ISA code also can be translated into program code that will be less than n0 threads and executed respectively, wherein each thread comprises the processing task relevant with at least one virtual thread in virtual task cluster or VTC.

Step 2: The virtual accelerator execution engine relies on the virtual execution model and virtual data model to complete the interaction with the virtual instruction loader and complete tasks such as instruction fetching and data buffering;

Step 3: The virtual accelerator execution engine implements the identification, arrangement, and optimization of computing tasks. This process is independent of the characteristics and instruction set of the specific manufacturer's hardware. The specific virtual accelerator execution engine performs general virtual calculations on the computing task threads corresponding to vISA based on the virtual data model through the virtual execution model, completes the identification, decomposition, and optimization arrangement of a series of computing tasks, and runs to obtain the virtual ISA code.

Among them, the virtual data model can use a virtual task cluster or VTC to perform task scheduling management, or it can use a task partition to perform task scheduling management. For details, please refer to the above embodiment, which will not be repeated here. The virtual parallel execution model is used to execute virtual threads in a virtual task cluster or VTC (or task partition). The virtual parallel execution model supports the representation of parallel processors and associated memory spaces for executing a large number of concurrent virtual threads that can achieve each other's cooperative behavior (for example: sharing data and synchronization) at the required time. The virtual parallel execution model can be mapped to a variety of actual processors and/or processing systems, such as GPGPU, NPU or DLA of different manufacturers. The virtual execution model can define several virtual memory spaces that support different levels of data sharing and access types, and identify virtual ISAs of all functions that can be executed by a virtual accelerator execution engine. In this way, the virtual machine defines a virtual accelerator execution engine that can be used to control the execution of virtual threads by defining and starting a virtual task cluster or VTC (or task partition).

The virtual accelerator execution engine includes receiving and interpreting virtual instructions or virtual instruction sequences from the virtual instruction loader, and an execution core capable of concurrently executing all threads of a single VTC. The virtual accelerator can run concurrently according to the number of execution cores, and each virtual processing engine executes one virtual thread. The virtual processing engines concurrently execute their respective virtual threads. The virtual accelerator execution engine maintains instruction pointers for their respective virtual threads, wherein the instructions mentioned are defined by the virtual ISA as part of the virtual machine.

For a virtual ISA, Table 1 gives an example of special variables defined by a virtual ISA (e.g., a prefix "%" is used to indicate a special variable). Special variables are related to a programming model, where each virtual thread is identified by its location within a VTC, and the VTC is located in a specific one of a number of task partitions. In some embodiments, the special variables of Table 1 are mapped to virtual registers in a virtual machine device.

Table 1

In Table 1, VTC and task partitions are each defined using a three-dimensional space, and different task partitions are numbered sequentially in the one-dimensional space. Virtual ISA special variables will be initialized when starting the VTC, and the virtual ISA code can simply use these variables without initialization.

As shown in Table 1, the first three-dimensional vector of special variables %vtid=(%vtid.x, %vtid.y, %vtid.z) defines the dimensions of the VTC (in terms of the number of virtual threads). All virtual threads in the VTC will share the same %vtid vector. In the virtual machine, it is expected that the value of the %vtid vector will be provided to the virtual accelerator execution engine via a virtual API function call, which establishes the dimensions of the VTC.

As shown in Table 1, the second three-dimensional vector of special variables %vtcid=(%vtcid.x, %vtcid.y, %vtcid.z) refers to the task ID of a given computing task within the VTC. In the virtual machine, it is expected that the virtual accelerator execution engine will dispatch a unique %vtid vector that satisfies the constraints 0≤%vtid.x＜%vtcid.x, 0≤%vtid.y＜%vtcid.y and 0≤%vtid.z＜%vtcid.z when launching each virtual thread of the VTC.

As shown in Table 1, the third 3-vector of special variables %nvTCid=(%nvTCid.x, %nvTCid.y, %nvTCid.z) defines the dimensions of the task partition (in terms of the number of VTCs). In the virtual machine shown in Figure 5, it is expected that the values of the %nvTCid vector will be provided to the virtual accelerator execution engine via a virtual API function call, by which the dimensions of the task partition of the VTC are established.

The virtual ISA allows the programmer (or compiler) to define any number of variables to represent the data items being processed, and to define the variables by type and a virtual state space that indicates how the variables are used and to what extent they are shared. Variables are implemented using registers or other memory structures available in the target platform; in many target platforms, the state space may affect the choice of memory structure used to implement a particular variable.

As shown in Table 2, an example of variable types supported in a virtual ISA embodiment is given, for example: supported variable types include: bit, signed, unsigned, and precision types of void type.

Table 2

name illustrate N value enumeration .vb<n> Void Type 1,8,16,32,64 .vs<n> Signed Types 1,8,16,32,64 .vu<n> Unsigned Types 1,8,16,32,64 .vx<n> Precision Type 1,8,16,32,64

A variable of type void is a single bit or a group of bits of a specified length; signed integer and unsigned integer formats and floating point formats can be defined according to the conventional format. Optionally, multiple widths are supported for each type, where the width is specified using the parameter <n>. For example, .vs16 indicates a 16-bit signed number, .vx32 indicates a 32-bit precision number, etc.

As shown in Table 2, some variable types are restricted to specific widths, for example: precision variables must be at least 16 bits; and integer types must be at least 8 bits. In the design, the implementation of the virtual ISA supports all specified widths, and if the processor's data path and/or registers are narrower than the widest width, multiple registers and processor cycles can be used to handle wider types.

Table 3 shows an example of virtual state spaces supported in a virtual ISA. For example, the following nine state spaces are defined, which correspond to different sharing levels and possible storage locations in a virtual machine device.

Table 3

name illustrate Mapping location .vreg Threads register .vsreg Threads register .vlocal Threads Memory .vshare Task Cluster Memory .vparam Task Cluster Memory .vconst Mission Area Memory .vglobal Context Memory .vtex Context Memory .vsurf Context Memory

The first three state spaces are shared at the thread level, which means that each virtual thread will have a separate instance of a variable, and no virtual thread will have access to the instance of any other virtual thread. For example, the virtual register (.reg) state space is used to define operands, temporary values, and/or results of calculations to be performed by each virtual thread. A program can define any number of virtual registers. Virtual registers can be addressed by static compile-time names rather than calculated addresses. This state space corresponds to the virtual registers in the virtual machine device.

The special register (.sreg) state space corresponds to the predefined special variables of Table 1, which are stored in special registers in the virtual machine. In some embodiments, the virtual ISA code may not define any other variables in the .sreg space, but may use special variables as inputs to calculations. All virtual threads can read any variable in the .sreg state space. For %tid (or its components), each virtual thread will read its unique thread identifier; for other variables in the .sreg state space, all virtual threads in the same VTC will read the same value.

Each virtual thread's local memory (.local) variables correspond to an area of global memory that is allocated and addressed on a per-virtual thread basis. In other words, when a virtual thread accesses a .local variable, it accesses its own instance of the variable, and changes made to a .local variable in one virtual thread do not affect other virtual threads. Unlike the .reg and .sreg state spaces, each virtual thread's local memory can be addressed using calculated addresses.

The virtual machine supports register-to-register arithmetic, and all arithmetic operations manipulate one or more virtual register operands (denoted as a, b, c in Table 4) to produce results written to virtual registers (denoted as d in Table 4). The operands and destinations of such arithmetic operations are always in the virtual register state space .vreg, except that the special registers of Table 1 (in the special register state space .vsreg) can be used as operands.

Table 4

name illustrate vadd.<TYPE>d,a,b d＝a+b vsub.<TYPE>d,a,b d＝a-b vmul.<TYPE>d,a,b d＝a*b vdiv.<TYPE>d,a,b,c d＝a/b+c vmad.<TYPE>d,a,b,c d＝a+b vfma.<TYPE>d,a,b,c d＝a+b vsad.<TYPE>d,a,b d＝a+b vrem.<TYPE>d,a,b d＝a+b

Virtual registers may provide a register file for each processing core, providing a set of globally readable registers to store VTC IDs, task partition IDs, and VTC and task partition dimensions.

The instruction buffer may logically represent a physical accelerator local register file with P lanes, each with a certain number of entries. One lane is dispatched to P execution engines, and corresponding entries in different lanes may be filled with data that facilitates different threads executing the same program.

Step 4: After the arrangement and optimization, the task level and virtual instruction sequence are sent to the virtual instruction model converter, and the conversion is realized to the actual ISA of hardware of various manufacturers;

Step 5: The converted ISA (SIMD or SIMT type) is fed into a data buffer aligned with the accelerator’s shared memory to implement the actual computation execution within the hardware.

The data buffer can be used as a shared register file or a virtual cache memory, which has an operation that allows any execution engine to read or write to any location in the shared memory. Specifically, the virtual instruction model converter caches the target ISA code to the data buffer; wherein the virtual instruction model converter shares memory with the accelerator.

In the embodiment of the present application, a set of virtual instruction sets compatible with SIMD and SIMT is proposed for the current heterogeneous SIMD and SIMT instruction types with different parameter lengths and different single instructions, and a virtual machine that can parse the virtual instruction set and complete the conversion to the vendor-level ISA of SIMD and SIMT types is proposed. The use of the embodiment of the present application allows developers to use any compiler that supports the virtual instruction set to generate an application that can be executed in a virtual machine device. The virtual machine device can complete the conversion of the virtual instruction set to the SIMD or SIMT type ISA of different manufacturers, complete the actual computing action, and realize the one-time compilation of the same functional application and run it anywhere on different heterogeneous hardware. It will greatly improve the collaborative application efficiency of hybrid heterogeneous systems.

A virtual machine according to another embodiment of the present invention, as shown in FIG6 , includes a transceiver 610, a processor 600, a memory 620, and a program or instruction stored in the memory 620 and executable on the processor 600; when the processor 600 executes the program or instruction, the steps applied to the instruction processing method are implemented, and the same technical effect can be achieved, which will not be described again here to avoid repetition.

The transceiver 610 is used to receive and send data under the control of the processor 600 .

Wherein, in FIG6, the bus architecture may include any number of interconnected buses and bridges, specifically one or more processors represented by processor 600 and various circuits of memory represented by memory 620 are linked together. The bus architecture may also link together various other circuits such as peripherals, voltage regulators, and power management circuits, which are well known in the art and are therefore not further described herein. The bus interface provides an interface. The transceiver 610 may be a plurality of components, i.e., including a transmitter and a receiver, providing a unit for communicating with various other devices on a transmission medium. The processor 600 is responsible for managing the bus architecture and general processing, and the memory 620 may store data used by the processor 600 when performing operations.

A readable storage medium according to an embodiment of the present invention stores a program or instruction thereon. When the program or instruction is executed by a processor, the steps in the instruction processing method as described above are implemented and the same technical effect can be achieved. To avoid repetition, it will not be described here.

The processor is a processor in the virtual machine described in the above embodiment. The readable storage medium includes a computer readable storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

The embodiment of the present application also provides a computer program product, including computer instructions. When the computer instructions are executed by a processor, the various processes of the above-mentioned instruction processing method embodiment are implemented, and the same technical effect can be achieved. To avoid repetition, they are not repeated here.

It should be further explained that the terminals described in this specification include but are not limited to smart phones, tablet computers, etc., and many of the functional components described are called modules in order to more particularly emphasize the independence of their implementation methods.

In the embodiment of the present invention, module can be implemented with software so that it can be executed by various types of processors. For example, an executable code module of an identification can include one or more physical or logical blocks of computer instructions, for example, it can be constructed as an object, process or function. Nevertheless, the executable code of the identified module does not need to be physically located together, but can include different instructions stored in different positions, and when these instructions are logically combined together, it constitutes a module and realizes the specified purpose of the module.

In fact, executable code module can be a single instruction or many instructions, and can even be distributed on a plurality of different code segments, distributed among different programs, and distributed across a plurality of memory devices. Similarly, operating data can be identified in the module, and can be implemented and organized in the data structure of any appropriate type according to any appropriate form. The operating data can be collected as a single data set, or can be distributed in different locations (including on different storage devices), and can only be present on a system or network as an electronic signal at least in part.

When a module can be implemented by software, considering the level of existing hardware technology, a person skilled in the art can build a corresponding hardware circuit to implement the corresponding function of the module that can be implemented by software without considering the cost. The hardware circuit includes a conventional very large scale integration (VLSI) circuit or gate array and existing semiconductors such as logic chips, transistors, or other discrete components. The module can also be implemented by a programmable hardware device, such as a field programmable gate array, a programmable array logic, a programmable logic device, etc.

The above exemplary embodiments are described with reference to the accompanying drawings, and many different forms and embodiments are feasible without departing from the spirit and teachings of the present invention. Therefore, the present invention should not be constructed as a limitation of the exemplary embodiments proposed herein. More specifically, these exemplary embodiments are provided so that the present invention will be perfect and complete, and the scope of the present invention will be conveyed to those who are familiar with the technology. In these figures, the component sizes and relative sizes may be exaggerated for clarity. The terms used here are only based on the purpose of describing specific exemplary embodiments and are not intended to be limiting. As used herein, unless the text clearly indicates otherwise, the singular forms "one", "an" and "the" are intended to include these multiple forms. It will be further understood that the terms "including" and/or "comprising" when used in this specification indicate the presence of the features, integers, steps, operations, components and/or components, but do not exclude the presence or increase of one or more other features, integers, steps, operations, components, components and/or their groups. Unless otherwise indicated, when stated, a range of values includes the upper and lower limits of that range and any subranges therebetween.

The above is a preferred embodiment of the present invention. It should be pointed out that for ordinary technicians in this technical field, several improvements and modifications can be made without departing from the principles of the present invention. These improvements and modifications should also be regarded as the scope of protection of the present invention.

Claims (13)

1. A command processing method, comprising: Get the virtual instruction set ISA carried by the application; Perform task scheduling management according to the virtual ISA and determine the virtual ISA sequence corresponding to the task to be executed; The virtual ISA code in the virtual ISA sequence is converted into target ISA codes corresponding to different types of accelerators. 2. The method according to claim 1, wherein the step of performing task scheduling management according to the virtual ISA and determining the virtual ISA sequence corresponding to the task to be executed comprises: Performing task scheduling management according to the virtual ISA to determine at least one virtual task cluster; wherein each of the virtual task clusters includes at least one virtual thread; The virtual threads in each virtual task cluster run the same program to obtain a virtual ISA sequence corresponding to the task to be executed. 3. The method according to claim 2, wherein the performing task scheduling management according to the virtual ISA to determine at least one virtual task cluster comprises: Performing task identification according to the virtual ISA to determine the task to be performed; According to the tasks to be executed, the virtual ISA is optimized and arranged to determine at least one virtual task cluster. 4. The method according to claim 2, further comprising: Generate virtual task cluster related information; Storing the virtual task cluster related information; The virtual task cluster related information includes at least one of the following: Identification information of a virtual task cluster, used to indicate a reading position of input data used by the virtual task cluster, and/or a writing position of output data generated by the virtual task cluster; Dimension information of a virtual task cluster, used to indicate the number of virtual threads included in the virtual task cluster; The identification information of the virtual thread is used to indicate a reading position of input data used by the virtual thread and/or a writing position of output data generated by the virtual thread. 5. The method according to claim 2, wherein the performing task scheduling management according to the virtual ISA to determine at least one virtual task cluster comprises: Performing task identification according to the virtual ISA to determine the task to be performed; According to the task to be executed, the virtual ISA is task-decomposed to obtain at least one task partition; wherein different task partitions correspond to different parts of the task to be executed; At least one virtual task cluster is determined according to each of the task partitions; wherein different virtual task clusters in each task partition are independent of each other, and the virtual task clusters in each task partition run the same program. 6. The method according to claim 4, further comprising: Generate task partition related information; Storing the task partition related information; The task partition related information includes at least one of the following: The identification information of the task partition is used to indicate the reading position of the input data used by the task partition and/or the writing position of the output data generated by the task partition; The dimension information of the task partition is used to indicate the number of virtual task clusters contained in the task partition. 7. The method according to any one of claims 1 to 5, characterized in that after converting the virtual ISA code in the virtual ISA sequence into target ISA codes corresponding to different types of accelerators, the method further comprises: The target ISA code is cached in a data buffer corresponding to each accelerator. 8. An instruction processing device, comprising: An acquisition module, used to acquire a virtual instruction set ISA carried in an application program; A determination module, used for performing task scheduling management according to the virtual ISA, and determining the virtual ISA sequence corresponding to the task to be executed; The conversion module is used to convert the virtual ISA code in the virtual ISA sequence into target ISA codes corresponding to different types of accelerators. 9. A virtual machine, comprising: a virtual instruction loader, a virtual accelerator execution engine, and a virtual instruction model converter; wherein: The virtual instruction loader is used to load the virtual instruction set ISA carried in the application program; The virtual accelerator execution engine performs task arrangement management on the virtual ISA loaded by the virtual instruction loader, and determines the virtual ISA sequence corresponding to the task to be executed; The virtual instruction model converter converts the virtual ISA code in the virtual ISA sequence obtained by the virtual accelerator execution engine performing task arrangement management into target ISA codes corresponding to different types of accelerators. 10. The virtual machine according to claim 9, further comprising: a data buffer; wherein The virtual instruction model converter caches the target ISA code to the data buffer; wherein the virtual instruction model converter shares memory with the accelerator. 11. A virtual machine, comprising: a transceiver, a processor, a memory, and a program or instruction stored in the memory and executable on the processor; characterized in that when the processor executes the program or instruction, the steps of the instruction processing method as described in any one of claims 1 to 7 are implemented. 12. A readable storage medium having a program or instruction stored thereon, wherein when the program or instruction is executed by a processor, the steps of the instruction processing method according to any one of claims 1 to 7 are implemented. 13. A computer program product, characterized in that it comprises computer instructions, and when the computer instructions are executed by a processor, the steps of the instruction processing method according to any one of claims 1 to 7 are implemented.