CN1187835C - Semiconductor memory - Google Patents

Abstract

A semiconductor storage device with high soft-error immunity is obtained. A semiconductor storage device has SRAM memory cells. NMOS transistors (Q1, Q4) are driver transistors, NMOS transistors (Q3, Q6) are access transistors, and PMOS transistors (Q2, Q5) are load transistors. An NMOS transistor (Q7) is a transistor for adding a resistance. The NMOS transistor (Q7) has its gate connected to a power supply (1). The NMOS transistor (Q7) has one of its source and drain connected to a storage node (ND1) and the other connected to the gates of the NMOS transistor (Q4) and the PMOS transistor (Q5). The resistance between the source and drain of the NMOS transistor (Q7) can be adjusted with the gate length, the gate width, the source/drain impurity concentration, etc., which is, for example, about several tens of kilohms (kOmega).

Description

semiconductor memory

[Detailed description of the invention]

[Technical field to which the invention belongs]

The present invention relates to semiconductor memories, and more particularly to the structure of semiconductor memories provided with SRAM (Static Random Access Memory) memory cells.

[Description of background technology]

Fig. 24 is a circuit diagram showing the structure of a conventional SRAM memory cell. NMOS transistors Q1 and Q4 are drive transistors (also called “drive transistors”), NMOS transistors Q3 and Q6 are transfer transistors (also called “access transistors”), and PMOS transistors Q2 and Q5 are load transistors. Resistive elements are sometimes formed instead of the PMOS transistors Q2 and Q5.

The respective sources of the NMOS transistors Q1 and Q4 are connected to a power supply 2 which provides a GND potential. The respective sources of the PMOS transistors Q2 and Q5 are connected to a power supply 1 that provides a predetermined power supply potential (Vdd). Drains of NMOS transistor Q1 and PMOS transistor Q2 are connected to storage node ND1. The drains of NMOS transistor Q4 and PMOS transistor Q5 are connected to storage node ND2. The storage node ND1 is connected to the respective gates of the NMOS transistor Q4 and the PMOS transistor Q5. The storage node ND2 is connected to the respective gates of the NMOS transistor Q1 and the PMOS transistor Q2. The NMOS transistor Q3 has a gate connected to the word line WL, a source connected to the storage node ND1, and a drain connected to the bit line BL0. The gate of the NMOS transistor Q6 is connected to the word line WL, the source is connected to the storage node ND2, and the drain is connected to the bit line BL1.

FIG. 25 schematically shows a top view of a conventional SRAM memory cell structure. An element isolation insulating film 4 is partially formed on a silicon substrate, and an element formation region is defined by the element isolation insulating film 4 . The NMOS transistor Q1 shown in FIG. 24 has n ⁺ -type source region 5 and drain region 6 . Moreover, the PMOS transistors Q2 both have p ⁺ -type source regions 8 and drain regions 9 . Likewise, the NMOS transistor Q4 has n ⁺ -type source region 10 and drain region 11 . Furthermore, the PMOS transistor Q5 has a source region 13 and a drain region 14 of p ⁺ type. In addition, the NMOS transistor Q3 has an n ⁺ -type source region 6 and drain region 15 , and the NMOS transistor Q6 has an n ⁺ -type source region 11 and drain region 16 .

The NMOS transistor Q1 and the PMOS transistor Q2 have a common gate structure 7, and the gate structure 7 is connected to respective drain regions 11, 14 of the NMOS transistor Q4 and the PMOS transistor Q5. Similarly, the NMOS transistor Q4 and the PMOS transistor Q5 have a common gate structure 12, and the gate structure 12 is connected to the respective drain regions 6, 9 of the NMOS transistor Q1 and the PMOS transistor Q2. In addition, the NMOS transistors Q3 and Q6 have a common gate structure 17, and the gate structure 17 functions as a word line WL.

[Problems to be Solved by the Invention]

However, there is also a problem that, if it is related to such a conventional semiconductor memory, ionizing radiation such as α rays emitted from the packaging material etc. enters the memory cell and destroys the stored information (soft error). .

For example, referring to FIG. 24 , it is assumed that the potential of the storage node ND1 is at a high level and the potential of the storage node ND2 is at a low level. In this state, when α-rays are incident on the drain region of NMOS transistor Q1, a large number of electron-hole pairs are generated due to the irradiation of α-rays. The generated electrons are collected by the drain of the NMOS transistor Q1, so that the potential of the storage node ND1 changes from high level to low level. Then, the potential change of storage node ND1 is transmitted to NMOS transistor Q4 and PMOS transistor Q5, and the potential of storage node ND2 changes from low level to high level. Furthermore, the potential change of the storage node ND2 is transmitted to the NMOS transistor Q1 and the PMOS transistor Q2. As a result of the above, the stored information of the semiconductor memory is destroyed.

The present invention has been made to solve such problems, and an object of the present invention is to obtain a semiconductor memory having high resistance to soft errors.

[method to solve the problem]

The memory according to the first aspect of the present invention is a semiconductor memory provided with SRAM cells. The static random access memory cell has a first driving transistor, a first load element, and a first transfer transistor connected to each other through a first storage node; and a second driving transistor, a second transistor connected to each other through a second storage node The load element and the second transfer transistor, the first gate electrode of the first driving transistor is connected to the second storage node, the second gate electrode of the second driving transistor is connected to the first storage node, and the The semiconductor memory is characterized in that it further includes a first protective film formed to cover a part of the first gate electrode, and the first gate electrode not covered by the first protective film is sequentially laminated with a first semiconductor film on the first gate insulating film. layer and the structure of the first metal-semiconductor compound layer, the first gate electrode covered by the first protective film has a first semiconductor layer formed on the first gate insulating film, and the first metal-semiconductor compound layer is not formed on the first semiconductor layer. The structure of the semiconducting compound layer.

In addition, the semiconductor memory according to the second aspect of the present invention is the semiconductor memory according to the first aspect, and is characterized in that: a second protective film formed to cover a part of the second gate electrode is provided, and the second protective film is not protected by the second gate electrode. The second gate electrode of the film-covered part has a structure in which the second semiconductor layer and the second metal-semiconductor compound layer are sequentially stacked on the second gate insulating film, and the second gate electrode of the part covered by the second protective film has a A second semiconductor layer is formed on the insulating film, and a second metal-semiconductor compound layer is not formed on the second semiconductor layer.

Furthermore, the semiconductor memory according to the third aspect of the present invention is a semiconductor memory provided with a static random access memory cell having a first driving transistor, a first the load element and the first transfer transistor; and the second drive transistor connected to each other through the second storage node, the second load element and the second transfer transistor, the first gate electrode of the first drive transistor is connected to the On the second storage node, the second gate electrode of the second driving transistor is connected to the first storage node, and the semiconductor memory is characterized in that it further includes a first impurity introduction region connected to the first gate electrode and connected to the second gate electrode. The first transistor for adding resistance in the second impurity introduction region connected to the two storage nodes, and the first gate electrode is connected to the second storage node through the first transistor for adding resistance.

In addition, the semiconductor memory according to the fourth aspect of the present invention is the semiconductor memory according to the third aspect, and is characterized in that: a power supply connected to the first and second load elements to provide a predetermined power supply potential is also provided, The first resistor adding transistor is an NMOS transistor, and the gate electrode of the first resistor adding transistor is connected to a power source.

In addition, the semiconductor memory according to the fifth aspect of the present invention is the semiconductor memory according to the third aspect, which is characterized in that: it is also equipped with a power supply connected to the first and second driving transistors to give a GND potential. The first resistance adding transistor is a PMOS transistor, and the gate electrode of the first resistance adding transistor is connected to the power supply.

Furthermore, the semiconductor memory according to the seventh aspect of the present invention is the semiconductor memory according to the third aspect, characterized in that the first transistor for adding resistance also has the same conductivity type as that of the first and second impurity introduction regions. The channel region of the first resistance addition transistor is connected to the first or second impurity introduction region.

Furthermore, the semiconductor memory according to the ninth aspect of the present invention is the semiconductor memory according to the third aspect, wherein the threshold voltage of the first transistor for adding resistance is lower than the threshold voltages of the first and second transistors for driving, A gate electrode of the first transistor for adding resistance is connected to the first or second impurity introduction region.

In addition, the semiconductor memory according to the eleventh aspect of the present invention is the semiconductor memory according to the third aspect, further comprising a word line connected to each gate electrode of the first and second transfer transistors, and the second One resistance adding transistor is an NMOS transistor, and the gate electrode of the first resistance adding transistor is connected to the word line.

In addition, the semiconductor memory described in the twelfth aspect of the present invention is the semiconductor memory described in any one of the third to eleventh aspects, and is characterized in that it further includes a third impurity introduction gate connected to the second gate electrode. region and the second transistor for adding resistance in the fourth impurity introducing region connected to the first storage node, and the second gate electrode is connected to the first storage node through the second transistor for adding resistance.

Moreover, the semiconductor memory described in the thirteenth aspect of the present invention is the semiconductor memory described in any one of the third to twelfth aspects, characterized in that: a semiconductor substrate is also provided; The interlayer insulating film formed on the surface, the first gate electrode is formed on the main surface of the semiconductor substrate through the gate insulating film, the second storage node is formed on the main surface of the semiconductor substrate, and the first transistor for adding resistance is formed on the main surface of the semiconductor substrate. A thin film transistor formed on an interlayer insulating film.

[Brief explanation of attached drawings]

FIG. 1 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 1 of the present invention.

FIG. 2 is a plan view schematically showing the structure of the SRAM memory cell according to Embodiment 1 of the present invention.

FIG. 3 is a cross-sectional view showing a cross-sectional structure at a position along a line segment X1-X1 shown in FIG. 2 .

FIG. 4 is a cross-sectional view showing a cross-sectional structure at a position along a line segment X2-X2 shown in FIG. 2 .

5 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 2 of the present invention.

6 is a plan view schematically showing the structure of an SRAM memory cell according to Embodiment 2 of the present invention.

Fig. 7 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 3 of the present invention.

8 is a circuit diagram showing the structure of an SRAM memory cell according to a first modification of Embodiment 3 of the present invention.

9 is a circuit diagram showing the structure of an SRAM memory cell according to a second modification of the third embodiment of the present invention.

Fig. 10 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 4 of the present invention.

11 is a circuit diagram showing the structure of an SRAM memory cell according to a first modification of Embodiment 4 of the present invention.

Fig. 12 is a circuit diagram showing the structure of an SRAM memory cell according to a second modification of the fourth embodiment of the present invention.

Fig. 13 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 5 of the present invention.

Fig. 14 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 6 of the present invention.

Fig. 15 is a plan view schematically showing the structure of an SRAM memory cell according to Embodiment 7 of the present invention.

Fig. 16 is a cross-sectional view showing a cross-sectional structure at a position along line X3-X3 shown in Fig. 15 .

Fig. 17 is a cross-sectional view showing a cross-sectional structure at a position along line X4-X4 shown in Fig. 15 .

18 is a plan view schematically showing the structure of an SRAM memory cell according to a first modification of Embodiment 7 of the present invention.

Fig. 19 is a cross-sectional view showing a cross-sectional structure at a position along line X5-X5 shown in Fig. 18 .

Fig. 20 is a cross-sectional view showing a cross-sectional structure at a position along line X6-X6 shown in Fig. 18 .

21 is a plan view schematically showing the structure of an SRAM memory cell according to a second modification of the seventh embodiment of the present invention.

Fig. 22 is a cross-sectional view showing a cross-sectional structure at a position along line X7-X7 shown in Fig. 21 .

Fig. 23 is a cross-sectional view showing a cross-sectional structure at a position along line X8-X8 shown in Fig. 21 .

Fig. 24 is a circuit diagram showing the structure of a conventional SRAM memory cell.

Fig. 25 is a plan view schematically showing the structure of a conventional SRAM memory cell.

[Example of the invention]

Example 1

FIG. 1 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 1 of the present invention. NMOS transistors Q1 and Q4 are driving transistors (also called “drive transistors”), and NMOS transistors Q3 and Q6 are transfer transistors (also called “access transistors”). The PMOS transistors Q2 and Q5 are load transistors, and sometimes resistive elements are formed instead of the PMOS transistors Q2 and Q5.

The respective sources of the NMOS transistors Q1 and Q4 are connected to a power supply 2 which provides a GND potential. The sources of the PMOS transistors Q2 and Q5 are connected to a power supply 1 that provides a predetermined power supply potential Vdd (about 0.5 to 5.0V). Drains of NMOS transistor Q1 and PMOS transistor Q2 are connected to storage node ND1. The drains of NMOS transistor Q4 and PMOS transistor Q5 are connected to storage node ND2. Storage node ND1 is connected to respective gates of NMOS transistor Q4 and PMOS transistor Q5 via resistor 3 . Storage node ND2 is connected to respective gates of NMOS transistor Q1 and PMOS transistor Q2. NMOS transistor Q3 has its gate connected to word line WL, its source connected to storage node ND1, and its drain connected to bit line BL0. NMOS transistor Q6 has a gate connected to word line WL, a source connected to storage node ND2, and a drain connected to bit line BL1.

FIG. 2 is a top view schematically showing the structure of the SRAM memory cell of the first embodiment. An element isolation insulating film 4 is partially formed on a silicon substrate, and an element formation region is defined by the element isolation insulating film 4 . The NMOS transistor Q1 shown in FIG. 1 has n ⁺ -type source region 5 and drain region 6 . Moreover, the PMOS transistors Q2 both have p ⁺ -type source regions 8 and drain regions 9 . Likewise, the NMOS transistor Q4 has n ⁺ -type source region 10 and drain region 11 . In addition, the PMOS transistor Q5 has p ⁺ -type source region 13 and drain region 14 . In addition, the NMOS transistor Q3 has an n ⁺ -type source region 6 and drain region 15 , and the NMOS transistor Q6 has an n ⁺ -type source region 11 and drain region 16 .

The NMOS transistor Q1 and the PMOS transistor Q2 have a common gate structure 7, and the gate structure 7 is connected to respective drain regions 11, 14 of the NMOS transistor Q4 and the PMOS transistor Q5. Similarly, the NMOS transistor Q4 and the PMOS transistor Q5 have a common gate structure 12, and the gate structure 12 is connected to the respective drain regions 6, 9 of the NMOS transistor Q1 and the PMOS transistor Q2. Part of the gate structure 12 is covered with a silicide protection film 18 made of a silicon oxide film. The portion of the gate structure 12 covered by the protective silicide film 18 has a higher resistance value than the portion of the gate structure 12 not covered by the protective silicide film 18 , and is defined as a high-resistance portion 19 . In addition, the NMOS transistors Q3 and Q6 have a common gate structure 17, and the gate structure 17 functions as a word line WL.

FIG. 3 is a cross-sectional view showing a cross-sectional structure at a position along a line segment X1-X1 shown in FIG. 2 . An element isolation insulating film 4 made of a silicon oxide film is formed on a silicon substrate 24 , and a gate structure 12 is formed on the element isolation insulating film 4 . The gate structure 12 has a structure in which a polysilicon layer 21 and a cobalt silicide layer 22 are sequentially stacked on a gate insulating film 20 made of a silicon oxide film, and side walls 23 made of a silicon oxide film are formed on side surfaces of the stacked structure. The impurity concentration introduced into the polysilicon layer 21 is about 1×10 ¹⁷ to 1×10 ²¹ cm ⁻³ , and the sheet resistance of the gate structure 12 is about several 10 Ω/□.

FIG. 4 shows a cross-sectional view of the cross-sectional structure along the line X2-X2 shown in FIG. 2 . The high resistance portion 19 of the gate structure 12 is formed on the element isolation insulating film 4 . This high resistance portion 19 corresponds to the resistor 3 shown in FIG. 1 . The high resistance portion 19 has a structure in which a polysilicon layer 21 is formed on a gate insulating film 20 and side walls 23 are formed on side surfaces of the structure. In the high-resistance portion 19, the cobalt silicide layer 22 is not formed on the polysilicon layer 21, and the sheet resistance of the high-resistance portion 19 is in the range of several kΩ/□ to several 100 Ω/□, which is higher than that of the gate structure 12 other than the high-resistance portion 19. High sheet resistance.

The structures shown in Fig. 3 and Fig. 4 can be formed in the following order: (A) the process of forming the gate structure of the polysilicon layer 21 on the gate insulating film 20; (B) forming sidewalls on the sides of the gate structure 23; (C) a process of forming a silicide protective film 18 on the region to be the high resistance portion 19; (D) forming a cobalt silicide layer by silicided the polysilicon layer 21 not covered with the silicide protective film 18 22 processes.

Thus, according to the semiconductor memory device of the first embodiment, as shown in FIG. Therefore, the soft error resistance of the semiconductor memory can be improved.

The reason for this will be described in detail below. Referring to FIG. 1 , it is assumed that the potential of the storage node ND1 is at a high level and the potential of the storage node ND2 is at a low level. In this state, when α-rays are incident on the drain of the NMOS transistor Q1, a large number of electron-hole pairs are generated due to the irradiation of the α-rays. The generated electrons are collected by the drain of the NMOS transistor Q1, so that the potential of the storage node ND1 changes from high level to low level. Then, the potential change of storage node ND1 is gradually transmitted to NMOS transistor Q4 and PMOS transistor Q5 according to the time constant determined by the resistance value of resistor 3 and the respective gate capacitances of NMOS transistor Q4 and PMOS transistor Q5. That is, the time required for the potential change of the storage node ND1 to be transmitted to the NMOS transistor Q4 and the PMOS transistor Q5 is delayed by the resistor 3, so the potential of the storage node ND2 does not change immediately.

In contrast, before the potential of storage node ND2 changes, the potential (low level) of storage node ND2 continues to be applied to the gates of NMOS transistor Q1 and PMOS transistor Q2. Therefore, after the potential of the storage node ND1 changes from a high level to a low level due to irradiation of α rays, the potential of the storage node ND1 returns to a high level again. As a result, the potential of the storage node ND2 is kept at low level. For the above reasons, the soft error resistance of the semiconductor memory can be improved.

Furthermore, the high-resistance portion 19 of the gate structure 12 can be formed only by adding a simple process of forming the silicide protective film 18, so that neither complicating the manufacturing process nor increasing the chip area is required.

Example 2

Fig. 5 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 2 of the present invention. Storage node ND2 is connected to respective gates of NMOS transistor Q1 and PMOS transistor Q2 via resistor 25 . Other structures of the SRAM storage unit of the second embodiment are the same as those of the SRAM storage unit of the first embodiment shown in FIG. 1 .

FIG. 6 schematically shows a top view of the structure of the SRAM memory cell in the second embodiment. A part of the gate structure 7 is covered by a silicide protection film 26 formed of a silicon oxide film, and the gate structure 7 covered with the silicide protection film 26 has a higher resistance value than the gate structure 7 without a portion covered with the silicide protection film 26, It is defined as the high resistance portion 27 . High resistance portion 27 corresponds to resistor 25 shown in FIG. 5 . Like the high resistance portion 19 shown in FIG. 4 , the high resistance portion 27 has a structure in which a polysilicon layer 21 is formed on the gate insulating film 20 and side walls 23 are formed on side surfaces of the structure. In the high-resistance portion 27, the cobalt silicide layer 22 is not formed on the polysilicon layer 21, and the sheet resistance of the high-resistance portion 27 is on the order of several kΩ/□ to several 100 Ω/□, which is higher than that of the gate structure 7 other than the high-resistance portion 27. The sheet resistance (several 10Ω/□) is high. Other structures of the SRAM storage unit of the second embodiment are the same as those of the SRAM storage unit of the first embodiment shown in FIG. 2 .

Thus, according to the semiconductor memory device of the second embodiment, as shown in FIG. 5 , the storage node ND1 is connected to the respective gates of the NMOS transistor Q4 and the PMOS transistor Q5 through the resistor 3 . Furthermore, the storage node ND2 is connected to the respective gates of the NMOS transistor Q1 and the PMOS transistor Q2 through a resistor 25 . Therefore, compared with the semiconductor memory device of the first embodiment described above, the resistance to soft errors can also be improved.

Example 3

FIG. 7 is a circuit diagram of the SRAM memory cell structure of Embodiment 3 of the present invention. An NMOS transistor Q7 is formed instead of the resistor 3 shown in FIG. 1 . The gate of the NMOS transistor Q7 is connected to the power source 1 . In addition, one of the source and the drain of the NMOS transistor Q7 is connected to the storage node ND1, and the other is connected to the respective gates of the NMOS transistor Q4 and the PMOS transistor Q5. Other structures of the SRAM storage unit of the third embodiment are the same as those of the SRAM storage unit of the first embodiment shown in FIG. 1 . The source-drain resistance of the NMOS transistor Q7 can be adjusted by the gate length and gate width, and the impurity concentrations of the source and drain, for example, in the range of several kΩ to several 100Ω.

Thus, according to the semiconductor memory device of the third embodiment, the source-drain resistance of the NMOS transistor Q7 is added between the storage node 1 and the gates of the NMOS transistor Q4 and the PMOS transistor Q5. In particular, the on-resistance of the NMOS transistor Q7 can be added to the semiconductor memory device of the third embodiment. Therefore, for the same reason as in the first embodiment described above, the soft error resistance of the semiconductor memory can be improved.

Furthermore, since the source-drain resistance of the NMOS transistor Q7 can be adjusted by the gate length and gate width, and the impurity concentrations of the source and drain, it is possible to add a resistance having a desired resistance value.

8 is a circuit diagram showing the structure of an SRAM memory cell according to a first modification of Embodiment 3 of the present invention. A PMOS transistor Q8 is formed instead of the NMOS transistor Q7 in FIG. 7 . The gate of PMOS transistor Q8 is connected to power supply 2 . In addition, one of the source and the drain of the PMOS transistor Q8 is connected to the storage node ND1, and the other is connected to the respective gates of the NMOS transistor Q4 and the PMOS transistor Q5.

9 is a circuit diagram showing the structure of an SRAM memory cell according to a second modification of the third embodiment of the present invention. It is formed by both the NMOS transistor Q7 shown in FIG. 7 and the PMOS transistor Q8 shown in FIG. 8 .

The same effect as that of the semiconductor memory shown in FIG. 7 can also be obtained in the semiconductor memories according to the first and second modifications of the third embodiment.

Example 4

Fig. 10 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 4 of the present invention. An NMOS transistor Q9 is formed instead of the resistor 3 shown in FIG. 1 . One of the source and the drain of the NMOS transistor Q9 is connected to the storage node ND1, and the other is connected to the respective gates of the NMOS transistor Q4 and the PMOS transistor Q5. In addition, the gate of the NMOS transistor Q9 is connected to any one of its own source and drain.

In order to electrically conduct the source-drain of the NMOS transistor Q9, the NMOS transistor Q9 is a transistor whose source-channel-drain conductivity type is n ⁺ -nn ⁺ . Alternatively, the absolute value of the threshold voltage of the NMOS transistor Q9 is set to be lower than the absolute values of the threshold voltages of the other NMOS transistors Q1 and Q4. For example, a current as low as several μA to several mA is set to flow when a voltage of 0 volts is applied to the gate. Other structures of the SRAM storage unit of the fourth embodiment are the same as those of the SRAM storage unit of the first embodiment shown in FIG. 1 .

In this way, according to the semiconductor memory device of the fourth embodiment, the source-drain resistance of the NMOS transistor Q9 can be added between the storage node ND1 and the gates of the NMOS transistor Q4 and the PMOS transistor Q5. Effect.

In addition, since the gate capacitance of the NMOS transistor Q9 is added to the respective gate capacitances of the NMOS transistor Q4 and the PMOS transistor Q5, changes in the potentials of the storage nodes ND1 and ND2 due to irradiation of α-rays can be apparently reduced. quantity. As a result, compared with the semiconductor memory device of the third embodiment described above, the resistance to soft errors can be further improved.

11 is a circuit diagram showing the structure of an SRAM memory cell according to a first modification of Embodiment 4 of the present invention. A PMOS transistor Q10 is formed instead of the NMOS transistor Q9 shown in FIG. 10 . One of the source and drain regions of the PMOS transistor Q10 is connected to the storage node ND1, and the other is connected to the respective gates of the NMOS transistor Q4 and the PMOS transistor Q5. In addition, the gate of the PMOS transistor Q10 is connected to either one of its source and drain.

In order to electrically conduct the source-drain of the PMOS transistor Q10, the PMOS transistor Q10 is a transistor whose source-channel-drain conductivity type is p ⁺ -pp ⁺ . Alternatively, the absolute value of the threshold voltage of the PMOS transistor Q10 is set lower than the absolute values of the threshold voltages of the other PMOS transistors Q2 and Q5.

Fig. 12 is a circuit diagram showing the structure of an SRAM memory cell according to a second modification of the fourth embodiment of the present invention. It is formed by both the NMOS transistor Q9 shown in FIG. 10 and the PMOS transistor Q10 shown in FIG. 11 .

The same effect as that of the semiconductor memory shown in FIG. 10 can also be obtained by the semiconductor memories of the first and second modifications of the fourth embodiment.

Example 5

FIG. 13 is a circuit diagram showing the structure of a SRAM memory cell according to Embodiment 5 of the present invention, and is formed by replacing the resistor 3 shown in FIG. 1 with an NMOS transistor Q11. One of the source and the drain of the NMOS transistor Q11 is connected to the storage node ND1, and the other is connected to the respective gates of the NMOS transistor Q4 and the PMOS transistor Q5. Furthermore, the gate of the NMOS transistor Q11 is connected to the word line WL.

In order to electrically conduct the source-drain of the NMOS transistor Q11, the NMOS transistor Q11 is a transistor whose source-channel-drain conductivity type is n ⁺ -nn ⁺ . Alternatively, the absolute value of the threshold voltage of the NMOS transistor Q11 is set to be lower than the absolute values of the threshold voltages of the other NMOS transistors Q1 and Q4. For example, a current as low as several μA to several mA is set to flow when a voltage of 0 volts is applied to the gate. Other structures of the SRAM storage unit of the fifth embodiment are the same as those of the SRAM storage unit of the first embodiment shown in FIG. 1 .

In this way, according to the semiconductor memory device of the fifth embodiment, the source-drain resistance of the NMOS transistor Q11 can be added between the storage node ND1 and the gates of the NMOS transistor Q4 and the PMOS transistor Q5. Effect.

In addition, since the gate of the NMOS transistor Q11 is connected to the word line WL, when the data line WL is activated during data writing and reading, the voltage applied to the word line WL is also applied to the NMOS transistor Q11. , driving the NMOS transistor Q11. As a result, the source-drain resistance of the NMOS transistor Q11 becomes low, so that operation delays in writing and reading data can be suppressed.

Example 6

Fig. 14 is a circuit diagram showing the structure of an SRAM memory cell according to Embodiment 6 of the present invention. Storage node ND2 is connected to respective gates of NMOS transistor Q1 and PPMOS transistor Q2 via NMOS transistor Q12. One of the source and the drain of the NMOS transistor Q12 is connected to the storage node ND2, and the other is connected to the respective gates of the NMOS transistor Q1 and the PMOS transistor Q2. In addition, the gate of the NMOS transistor Q12 is connected to the power supply 1 as in the third embodiment described above. However, the gate of the NMOS transistor Q12 may be connected to its own source or drain as in the fourth embodiment, or may be connected to the word line WL as in the fifth embodiment. The same applies to the gate of the NMOS transistor Q7. Other structures of the SRAM storage unit of the sixth embodiment are the same as those of the SRAM storage unit of the first embodiment shown in FIG. 1 .

Thus, according to the semiconductor memory device of the sixth embodiment, as shown in FIG. 14, the storage node ND1 is connected to the respective gates of the NMOS transistor Q4 and the PMOS transistor Q5 through the NMOS transistor Q7. Furthermore, storage node ND2 is connected to respective gates of NMOS transistor Q1 and PMOS transistor Q2 via NMOS transistor Q12. Therefore, compared with the semiconductor memories of the third to fifth embodiments described above, the resistance to soft errors can be further improved.

Example 7

In this seventh embodiment, the structure of an additional MOS transistor (hereinafter referred to as "transistor for adding resistance") will be described. Hereinafter, as a representative example, an example of the structure of the NMOS transistor Q12 shown in FIG. 14 will be described.

Fig. 15 is a plan view schematically showing the structure of an SRAM memory cell according to Embodiment 7 of the present invention. 16 is a cross-sectional view showing a cross-sectional structure along line X3-X3 shown in FIG. 15, and FIG. 17 is a cross-sectional view showing a cross-sectional structure along line X4-X4 shown in FIG. As shown in FIGS. 16 and 17, an interlayer insulating film 40 made of a silicon oxide film is formed on the silicon substrate 24 and the element isolation insulating film 4, and the NMOS transistor Q12 is a thin film transistor formed on the interlayer insulating film 40 ( TFT).

Referring to FIGS. 15 to 17 , each NMOS transistor Q12 has a channel region 38 formed on an interlayer insulating film 40 , and a pair of source and drain regions 31 and 32 sandwiching the channel region 38 . Also, the NMOS transistor Q12 has the gate electrode 30 formed on the channel region 38 with the gate insulating film 39 interposed therebetween. The conductivity type of the source and drain regions 31 and 32 is n ⁺ type, and the conductivity type of the channel region 38 is p type. However, in the NMOS transistor Q9 shown in FIG. 10 and FIG. 12 and the NMOS transistor Q11 shown in FIG. 13 , the conductivity type of the channel region 38 is n-type.

Referring to FIG. 15 , the source and drain regions 31 are connected to the gate structure 7 through contact plugs 33 . Furthermore, the source and drain regions 32 are connected to the drain regions 11 and 14 through contact plugs 34 and 35, respectively. Referring to FIG. 16 , the contact plug 33 has a contact hole 36 formed in the interlayer insulating film 40 between the bottom surface of the source and drain region 31 and the top surface of the gate structure 7 and a metal plug 37 filled in the contact hole 36 . Referring to FIG. 17 , the contact plug 34 has a contact hole 41 formed in the interlayer insulating film 40 between the bottom surface of the source/drain region 32 and the top surface of the drain region 11 and a metal plug 42 filled in the contact hole 41 . Furthermore, the contact plug 35 has a contact hole 43 formed in the interlayer insulating film 40 between the bottom surface of the source/drain region 32 and the top surface of the drain region 14 and a metal plug 44 filled in the contact hole 43 .

In this way, according to the semiconductor memory device of the seventh embodiment, since the transistor for additional resistance is formed on the insulating film 40, the transistor for additional resistance can be compared with the case where the transistor for additional resistance is formed on the silicon substrate 24 together with other NMOS transistors Q1 to Q6. An increase in chip area is suppressed.

18 is a plan view schematically showing the structure of an SRAM memory cell according to a first modification of Embodiment 7 of the present invention. 19 is a cross-sectional view showing the cross-sectional structure along the line X5-X5 shown in FIG. 18, and FIG. 20 is a cross-sectional view showing the cross-sectional structure along the line X6-X6 shown in FIG. As shown in FIGS. 19 and 20, an interlayer insulating film 60 made of a silicon oxide film is formed on the silicon substrate 24 and the element isolation insulating film 4, and an interlayer insulating film made of a silicon oxide film is formed on the interlayer insulating film 60. insulating film 63 . The NMOS transistor Q12 is a thin film transistor formed on the interlayer insulating film 60 .

Referring to FIGS. 18 to 20 , each NMOS transistor Q12 has a channel region 61 formed on an interlayer insulating film 60 , and a pair of source and drain regions 51 and 52 sandwiching the channel region 61 . Also, the NMOS transistor Q12 has a gate electrode 50 formed on the channel region 61 with the gate insulating film 62 interposed therebetween. The conductivity type of the source and drain regions 51 and 52 is n ⁺ type, and the conductivity type of the channel region 61 is p type. However, in the NMOS transistor Q9 shown in FIG. 10 and FIG. 12 and the NMOS transistor Q11 shown in FIG. 13 , the conductivity type of the channel region 61 is n-type.

Referring to FIG. 18 , source and drain regions 51 are connected to gate structure 7 through contact plugs 54 and 55 and metal wiring 53 made of aluminum. Furthermore, the source and drain regions 52 are connected to the drain region 11 through contact plugs 57 and 58 and metal wiring 56 . Similarly, source and drain regions 52 are connected to drain region 14 through contact plugs 57 and 59 and metal wiring 56 .

Referring to FIG. 19 , the contact plug 55 has a contact hole 64 formed in the interlayer insulating film 63 between the top surface of the source/drain region 51 and the bottom surface of the metal wiring 53 and a metal plug 65 filled in the contact hole 64 . Further, the contact plug 57 has a contact hole 66 formed in the interlayer insulating film 63 between the top surface of the source/drain region 52 and the bottom surface of the metal wiring 56 , and a metal plug 67 filled in the contact hole 66 . Also, the contact plug 54 has a contact hole 68 formed in the interlayer insulating films 60 , 63 between the top surface of the gate structure 7 and the bottom surface of the metal wiring 53 and a metal plug 69 filled in the contact hole 68 .

Referring to FIG. 20 , the contact plug 57 has a contact hole 70 formed in the interlayer insulating film 63 between the top surface of the source/drain region 52 and the bottom surface of the metal wiring 56 and a metal plug 71 filled in the contact hole 70 . Also, the contact plug 58 has a contact hole 72 formed in the interlayer insulating films 60 , 63 between the bottom surface of the metal wiring 56 and the top surface of the drain region 11 and a metal plug 73 filled in the contact hole 72 . Likewise, the contact plug 59 has a contact hole 74 formed in the interlayer insulating films 60 , 63 between the bottom surface of the metal wiring 56 and the top surface of the drain region 14 and a metal plug 75 filled in the contact hole 74 .

21 is a plan view schematically showing the structure of an SRAM memory cell according to a second modification of the seventh embodiment of the present invention. 22 is a cross-sectional view showing a cross-sectional structure along line X7-X7 shown in FIG. 21, and FIG. 23 is a cross-sectional view showing a cross-sectional structure along line X8-X8 shown in FIG. As shown in FIGS. 22 and 23, an interlayer insulating film 85 made of a silicon oxide film is formed on the silicon substrate 24 and the element isolation insulating film 4, and an interlayer insulating film made of a silicon oxide film is formed on the interlayer insulating film 85. insulating film 88 . The NMOS transistor Q12 is a thin film transistor formed on the interlayer insulating film 85 .

Referring to FIGS. 21 to 23 , each NMOS transistor Q12 has a channel region 86 formed on an interlayer insulating film 85 , and a pair of source and drain regions 80 and 81 formed with the channel region 86 therebetween. Also, the NMOS transistor Q12 has a gate electrode 50 formed on the channel region 86 with the gate insulating film 87 interposed therebetween. The conductivity type of the source and drain regions 80 and 81 is n ⁺ type, and the conductivity type of the channel region 86 is p type. However, in the NMOS transistor Q9 shown in FIG. 10 and FIG. 12 and the NMOS transistor Q11 shown in FIG. 13 , the conductivity type of the channel region 86 is n-type.

Referring to FIG. 21 , the source and drain regions 80 are connected to the gate structure 7 through contact plugs 82 . Furthermore, the source and drain regions 81 are connected to the drain regions 11 and 14 through contact plugs 83 and 84, respectively.

Referring to FIG. 22, the contact plug 82 exposes the end of the source and drain regions 80 on the opposite side to the channel region 86, and has an interlayer insulating film 85 between the top surface of the gate structure 7 and the bottom surface of the metal wiring 91. , 88 formed in the contact hole 89 and the metal plug 90 filled in the contact hole 89 .

23, the contact plug 83 exposes one end of the source and drain regions 81, and has a contact hole 92 formed in the interlayer insulating films 85, 88 between the top surface of the drain region 11 and the bottom surface of the metal wiring 94 and a filling. Metal plug 93 within contact hole 92 . Similarly, the contact plug 84 exposes the other end of the source and drain region 81, and has a contact hole 95 formed in the interlayer insulating films 85, 88 between the top surface of the drain region 14 and the bottom surface of the metal wiring 97 and filled in the contact hole 95. Metal plug 96 inside contact hole 95 .

The semiconductor memories according to the first and second modifications of the seventh embodiment can also obtain the same effects as those of the semiconductor memories shown in FIGS. 15 to 17 .

[Effect of the invention]

According to the semiconductor memory device according to the first aspect of the present invention, the second storage node is covered with the first protection film, the first metal-semiconductor compound layer is not formed, and is connected to the first driving transistor through the high resistance portion of the first gate electrode. . Therefore, the soft error resistance of the semiconductor memory can be improved.

And, according to the semiconductor memory device of the second aspect of the present invention, the first storage node is covered by the second protective film, the second metal-semiconductor compound layer is not formed, and the high resistance part of the second gate electrode is connected to the second driving electrode. on the transistor. Therefore, the soft error resistance of the semiconductor memory can also be improved.

Also, according to the semiconductor memory of the third aspect of the present invention, since the first gate electrode is connected to the second storage node through the first transistor for adding resistance, soft error resistance of the semiconductor memory can be improved.

Also, according to the semiconductor memory device according to the fourth aspect of the present invention, the on-resistance of the first resistance adding transistor as an NMOS transistor can be added between the first gate electrode and the second storage node.

Also, according to the semiconductor memory device according to the fifth aspect of the present invention, the on-resistance of the first resistance adding transistor as a PMOS transistor can be added between the first gate electrode and the second storage node.

Likewise, according to the semiconductor memory device of the seventh aspect of the present invention, the gate capacitance of the transistor for adding the first resistance can be added to the gate capacitance of the transistor for driving the second. Therefore, the first resistance caused by the irradiation of α rays can be reduced apparently. The change amount of the potential of the first and second storage nodes. As a result, soft error resistance can also be improved.

Likewise, according to the semiconductor memory device according to the ninth aspect of the present invention, the gate capacitance of the transistor for adding the first resistance can be added to the gate capacitance of the transistor for driving the second. Therefore, it is possible to reduce the first-order capacitance caused by α-ray irradiation apparently. The change amount of the potential of the first and second storage nodes. As a result, soft error resistance can also be improved.

Likewise, according to the semiconductor memory device of the eleventh aspect of the present invention, when the word line is activated during data writing and reading, the voltage applied to the word line is also applied to the gate electrode of the first resistance adding transistor. above, the first resistor addition transistor is driven. This can reduce the source-drain resistance of the first resistance adding transistor, so that operation delays during data writing and reading can be suppressed.

Also, according to the semiconductor memory of the twelfth aspect of the present invention, since the second gate electrode is connected to the first storage node through the transistor functioning as the second additional resistance, the resistance to soft errors of the semiconductor memory can also be improved.

Also, according to the semiconductor memory device of the thirteenth aspect of the present invention, the first resistor adding transistor as the thin film transistor is formed on the interlayer insulating film, so the first resistor adding transistor is formed on the semiconductor substrate together with other transistors. Compared with other types of semiconductor memories, an increase in chip area can be suppressed.

Claims (13)

1. semiconductor memory, it has static random access memory (sram) cell, and this static random access memory (sram) cell has by first memory node interconnective first and drives with transistor, first load elements and the first transmission transistor; And by the interconnective second driving transistor of second memory node, second load elements and the second transmission transistor, above-mentioned first drives the first grid electrode that has with transistor is connected on above-mentioned second memory node, above-mentioned second drives second gate electrode that has with transistor is connected on above-mentioned first memory node, and this semiconductor memory is characterised in that:

Also have a part that covers above-mentioned first grid electrode and first diaphragm that forms,

The structure that stacks gradually first semiconductor layer and the first metal-semiconductor compound layer on first grid dielectric film is not arranged by the above-mentioned first grid electrode of the above-mentioned first diaphragm cover part,

By the above-mentioned first grid electrode of the above-mentioned first diaphragm cover part above-mentioned first semiconductor layer of formation on above-mentioned first grid dielectric film is arranged, on above-mentioned first semiconductor layer, do not form the structure of the above-mentioned first metal-semiconductor compound layer.

2. semiconductor memory as claimed in claim 1 is characterized in that:

Also have a part that covers above-mentioned second gate electrode and second diaphragm that forms,

The structure that stacks gradually second semiconductor layer and the second metal-semiconductor compound layer on second gate insulating film is not arranged by above-mentioned second gate electrode of the above-mentioned second diaphragm cover part,

By above-mentioned second gate electrode of the above-mentioned second diaphragm cover part above-mentioned second semiconductor layer of formation on above-mentioned second gate insulating film is arranged, on above-mentioned second semiconductor layer, do not form the structure of the above-mentioned second metal-semiconductor compound layer.

3. semiconductor memory, it has static random access memory (sram) cell, and this static random access memory (sram) cell has by first memory node interconnective first and drives with transistor, first load elements and the first transmission transistor; And by the interconnective second driving transistor of second memory node, second load elements and the second transmission transistor, above-mentioned first drives the first grid electrode that has with transistor is connected on above-mentioned second memory node, above-mentioned second drives second gate electrode that has with transistor is connected on above-mentioned first memory node, and this semiconductor memory is characterised in that:

Also comprise the additional transistor of using of first resistance with the first impurity Lead-In Area that is connected with above-mentioned first grid electrode and the second impurity Lead-In Area that is connected with above-mentioned second memory node,

Above-mentioned first grid electrode connects with above-mentioned second memory node of transistor AND gate by above-mentioned first resistance is additional.

4. semiconductor memory as claimed in claim 3 is characterized in that:

Also have the power supply with above-mentioned first and second load elements power supply potential that be connected, that provide prescribed limit,

The additional transistor with transistor one additional resistance effect of above-mentioned first resistance is a nmos pass transistor,

Above-mentioned first resistance is additional to be connected with above-mentioned power supply with transistorized gate electrode.

5. semiconductor memory as claimed in claim 3 is characterized in that:

Also have with above-mentioned first and second and drive power supply that be connected with transistor, that provide the GND current potential,

Above-mentioned first resistance is additional to be the PMOS transistor with transistor,

Above-mentioned first resistance is additional to be connected with above-mentioned power supply with transistorized gate electrode.

6. semiconductor memory as claimed in claim 3 is characterized in that:

Also have first power supply with above-mentioned first and second load elements power supply potential that be connected, that provide prescribed limit; And

Drive second source that be connected with transistor, that provide the GND current potential with above-mentioned first and second,

Above-mentioned first resistance is additional to be comprised with transistor:

Has the nmos pass transistor that is connected the gate electrode on above-mentioned first power supply; And

PMOS transistor with the gate electrode that is connected on the above-mentioned second source.

7. semiconductor memory as claimed in claim 3 is characterized in that:

Above-mentioned first resistance is additional also to have channel region with the conduction type identical conduction type of above-mentioned first and second impurity Lead-In Area with transistor,

Above-mentioned first resistance is additional to be connected with the above-mentioned first or second impurity Lead-In Area with transistorized gate electrode.

8. semiconductor memory as claimed in claim 7 is characterized in that:

Above-mentioned first resistance is additional be configured to transistor a plurality of.

9. semiconductor memory as claimed in claim 3 is characterized in that:

Above-mentioned first resistance is additional lower with the absolute value of transistorized threshold voltage than above-mentioned first and second driving with the absolute value of transistorized threshold voltage,

Above-mentioned first resistance is additional to be connected with the above-mentioned first or second impurity Lead-In Area with transistorized gate electrode.

10. semiconductor memory as claimed in claim 9 is characterized in that:

Above-mentioned first resistance is additional be configured to transistor a plurality of.

11. semiconductor memory as claimed in claim 3 is characterized in that:

Also have the word line that is connected with transistorized each gate electrode with above-mentioned first and second transmission,

Above-mentioned first resistance is additional to be nmos pass transistor with transistor,

Above-mentioned first resistance is additional to be connected with above-mentioned word line with transistorized gate electrode.

12. semiconductor memory as claimed in claim 3 is characterized in that:

Comprise the additional transistor of using of second resistance with the 3rd impurity Lead-In Area that is connected with above-mentioned second gate electrode and the 4th impurity Lead-In Area that is connected with above-mentioned first memory node,

Above-mentioned second gate electrode connects with above-mentioned first memory node of transistor AND gate by above-mentioned second resistance is additional.

13., it is characterized in that as any described semiconductor memory in the claim 3～12:

Also have Semiconductor substrate; And

The interlayer dielectric that on the interarea of above-mentioned Semiconductor substrate, forms,

Above-mentioned first grid electrode forms on the above-mentioned interarea of above-mentioned Semiconductor substrate by gate insulating film,

Above-mentioned second memory node forms in the above-mentioned interarea of above-mentioned Semiconductor substrate,

Above-mentioned first resistance is additional to be the thin-film transistor that forms on above-mentioned interlayer dielectric with transistor.

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