CN118782129B - Signal generation circuit, test circuit and memory - Google Patents
Signal generation circuit, test circuit and memoryInfo
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- CN118782129B CN118782129B CN202310352108.6A CN202310352108A CN118782129B CN 118782129 B CN118782129 B CN 118782129B CN 202310352108 A CN202310352108 A CN 202310352108A CN 118782129 B CN118782129 B CN 118782129B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
- G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
- G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
- G11C29/20—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits using counters or linear-feedback shift registers [LFSR]
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Abstract
本公开提供了一种信号生成电路、测试电路及存储器，涉及半导体技术领域，信号生成电路包括计数电路和选择电路；计数电路包括n个计数信号输出端；选择电路包括选择信号输入端、与二进制位对应的n个第一接收端与n个第二接收端；每个第一接收端与位于相同二进制位的计数信号输出端连接；按照从低位到高位的顺序，前m个第二接收端与后m个计数信号输出端连接，剩余每个第二接收端与低于其自身m位的计数信号输出端连接，m＜n；选择电路被配置为：基于选择信号输入端接收到的选择信号，选择输出目标信号，该目标信号可以用于地址升序寻址、地址降序寻址、地址跳跃升序寻址、地址跳跃降序寻址等多种寻址方式，能更好的满足存储器的测试需求。
The present disclosure provides a signal generating circuit, a test circuit and a memory, and relates to the field of semiconductor technology. The signal generating circuit includes a counting circuit and a selection circuit; the counting circuit includes n counting signal output terminals; the selection circuit includes a selection signal input terminal, n first receiving terminals corresponding to binary bits, and n second receiving terminals; each first receiving terminal is connected to the counting signal output terminal located at the same binary bit; in order from low to high bits, the first m second receiving terminals are connected to the last m counting signal output terminals, and each remaining second receiving terminal is connected to the counting signal output terminal m bits lower than itself, m＜n; the selection circuit is configured to: based on the selection signal received by the selection signal input terminal, select and output a target signal, and the target signal can be used for multiple addressing modes such as address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing, etc., which can better meet the testing requirements of the memory.
Description
Technical Field
The present disclosure relates to the field of semiconductor technologies, and in particular, to a signal generating circuit, a test circuit, and a memory.
Background
A Memory built-in self-test (Memory Build IN SELF TEST, MBIST) is a test circuit built in the Memory, and can generate information such as commands, addresses, data and the like to test the Memory.
In MBIST, the address generation circuit typically counts up from 0 according to the requirements of the controller. However, with the rise of test requirements, the types of test vectors are increasingly required, and the existing test circuits cannot meet the current test requirements.
Disclosure of Invention
The disclosure provides a signal generating circuit, a test circuit and a memory, which can solve the technical problem that the signal generating circuit in the existing test circuit cannot meet the test requirement.
In a first aspect, embodiments of the present disclosure provide a signal generating circuit including a counting circuit and a selecting circuit;
the counting circuit comprises n counting signal output ends and is used for outputting n-bit binary counting signals, wherein n is a positive integer;
The selection circuit comprises a selection signal input end, n first receiving ends corresponding to binary bits and n second receiving ends corresponding to the binary bits;
The first receiving ends are connected with the counting signal output ends positioned in the same binary bit, the first m second receiving ends are connected with the last m counting signal output ends in the sequence from the lower bit to the higher bit, the rest of the second receiving ends are connected with the counting signal output ends lower than the m bit of the second receiving ends, m is a positive integer, and m is less than n;
The selection circuit is configured to select and output any one of the target signals of the n first receiving ends, the n second receiving ends, the reverse signals of the n first receiving ends and the reverse signals of the n second receiving ends based on the selection signal received by the selection signal input end.
In some embodiments, when i is less than or equal to m, the ith second receiving end is connected with the m-i+1 count signal output ends, and when i is greater than m, the ith second receiving end is connected with the i-m count signal output ends, wherein i is {1, 2,3,.
In some embodiments, m=1, the second receiving terminal of the lowest order is connected to the signal output terminal of the highest order in order from the lower order to the higher order, and the remaining second receiving terminals are each connected to the signal output terminal of 1 bit below.
In some embodiments, m=2, the 1 st second receiving terminal is connected to the n-1 st counting signal output terminal, the 2 nd second receiving terminal is connected to the n-th counting signal output terminal, and each of the remaining second receiving terminals is connected to the counting signal output terminal lower than its own 2 bits in order from the lower position to the higher position.
In some embodiments, the selection circuit comprises n signal selection circuits corresponding to binary bits, wherein each signal selection circuit comprises a first selector, a second selector and a first inverter;
each first selector comprises a first receiving end, a second receiving end, a first selection signal input end and a first output end;
each second selector comprises a third receiving end, a fourth receiving end, a second selection signal input end and a second output end;
The first output end is respectively connected with the third receiving end and the input end of the first inverter, and the output end of the first inverter is connected with the fourth receiving end.
In some embodiments, the first output outputs a signal received by the first receiving end when the first selection signal input end receives a non-skip selection signal, and outputs a signal received by the second receiving end when the first selection signal input end receives a skip selection signal;
When the second selection signal input end receives the ascending selection signal, the second output end outputs the signal received by the third receiving end, when the second selection signal input end receives the descending selection signal, the second output end outputs the signal received by the fourth receiving end.
In some embodiments, the signal generation circuit is applied to a memory;
The selection circuit is configured to select and output either one of the target signals as a row address addressing signal or a column address addressing signal of the memory based on a selection signal received by the selection signal input terminal.
In some embodiments, the counting circuit comprises n cascaded counting units, and the output end of each counting unit is connected with the counting signal output end positioned in the same binary bit;
the n cascaded counting units are configured to output the n-bit binary counting signal based on a clock signal.
In a second aspect, embodiments of the present disclosure provide a test circuit for use in a memory built-in self-test, the test circuit including a counting circuit and a selection circuit;
the counting circuit comprises n counting signal output ends and is used for outputting n-bit binary counting signals, wherein n is a positive integer;
The selection circuit comprises a selection signal input end and n receiving ends corresponding to binary bits;
The first m receiving ends are connected with the last m counting signal output ends in the order from the lower position to the higher position, each remaining receiving end is connected with the counting signal output end lower than the m bit of the receiving end, m is a positive integer, and m is smaller than n;
The selection circuit is configured to select and output any one of a target signal, which is a reverse signal of the signal received by the n receivers, as an address signal of the built-in self test of the memory based on a selection signal received by the selection signal input terminal.
In some embodiments, when i is less than or equal to m, the ith receiving end is connected with the m-i+1 count signal output end, and when i is greater than m, the ith receiving end is connected with the i-m count signal output end, wherein i is {1, 2, 3.
In some embodiments, m=1, the receiving terminal of the lowest order is connected to the signal output terminal of the highest order in order from the lower order to the higher order, and the remaining receiving terminals are each connected to the signal output terminal of 1 bit below.
In a third aspect, embodiments of the present disclosure provide a memory comprising the signal generating circuit provided in the first aspect or the test circuit provided in the second aspect.
The signal generating circuit, the test circuit and the memory provided by the embodiment of the disclosure can realize various counting time sequence control modes, such as various addressing modes of address ascending addressing, address descending addressing, address jump ascending addressing, address jump descending addressing and the like, so that more test vectors can be supported, the scheme is simple and easy to implement, the influence on circuit area, power consumption and time sequence is small, and the test requirement of the current memory can be better met.
Drawings
Fig. 1 is a schematic diagram of a signal generating circuit provided in an embodiment of the disclosure;
FIG. 2 is a schematic diagram of a signal selection circuit according to an embodiment of the disclosure;
FIG. 3 is a schematic diagram of a counting circuit according to an embodiment of the disclosure;
fig. 4 is a timing diagram of a signal generating circuit and a test circuit according to an embodiment of the disclosure.
Detailed Description
For the purposes of making the objects, technical solutions and advantages of the embodiments of the present disclosure more apparent, the technical solutions of the embodiments of the present disclosure will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present disclosure, and it is apparent that the described embodiments are some embodiments of the present disclosure, but not all embodiments. Based on the embodiments in this disclosure, all other embodiments that a person of ordinary skill in the art would obtain without making any inventive effort are within the scope of protection of this disclosure. Furthermore, while the disclosure has been presented by way of example only, it should be appreciated that various aspects of the disclosure may be separately implemented in a complete embodiment.
It should be noted that the brief description of the terms in the present disclosure is only for convenience in understanding the embodiments described below, and is not intended to limit the embodiments of the present disclosure. Unless otherwise indicated, these terms should be construed in their ordinary and customary meaning.
The terms first, second and the like in the description and in the claims and in the above-described figures are used for distinguishing between similar or similar objects or entities and not necessarily for describing a particular sequential or chronological order, unless otherwise indicated. It is to be understood that the terms so used are interchangeable under appropriate circumstances such that the embodiments of the disclosure are, for example, capable of operation in sequences other than those illustrated or otherwise described herein.
Furthermore, the terms "comprise" and "have," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a product or apparatus that comprises a list of elements is not necessarily limited to those elements expressly listed, but may include other elements not expressly listed or inherent to such product or apparatus.
The term "module" as used in the embodiments of the present disclosure refers to any known or later developed hardware, software, firmware, artificial intelligence, fuzzy logic, or combination of hardware or/and software code that is capable of performing the function associated with that element.
The embodiment of the disclosure can be applied to the field of semiconductor technology, for example, can be applied to the design of a test circuit of a memory in an integrated circuit design, including the design of an address generator in the memory test to generate address information required by the memory test, but can also be not limited to the scope, and other command planning and generating circuits and counting time sequence control circuits can all adopt the technical scheme provided by the embodiment of the disclosure.
With the rapid development of integrated circuits, the scale of the integrated circuits is larger and larger, the requirements on the quality and the reliability of the circuits are further improved, and the testing method of the integrated circuits is also more and more difficult, so that automatic testing equipment (Automated Test Equipment, ATE) provides strong support for the rapid testing and screening of the integrated circuits. The ATE uses the integrated circuit design simulation file to be used as the input excitation of the integrated circuit, provides the test environment of the integrated circuit through the ATE test platform, and compares the output of the integrated circuit with the test result so as to judge the quality of the integrated circuit.
In the integrated circuit testing industry, test vectors represent the timing characteristics of the integrated circuits that need to be tested. In brief, during testing of an integrated circuit, the ATE sends a series of timing signals to the input pins of the integrated circuit under test, and then compares the output timing signals at the output pins of the integrated circuit, thereby testing whether the integrated circuit is functioning. A test vector in a narrow sense is a truth table for an integrated circuit.
MBIST is a test circuit built in the memory, which can generate information such as command, address, data and the like to test the memory. Where "built-in" means that the test vectors for the pointer to memory are not generated by external ATE, but rather are automatically generated by built-in memory test logic, and a comparison of the results is made. In the MBIST test, a test result can be obtained from the TDO interface only by issuing a test instruction from the machine through the JTAG standard interface.
It is understood that a memory generally includes a plurality of Bit Lines (BL), a plurality of Word Lines (WL), and a plurality of memory cells, wherein each memory cell is connected to a corresponding one of the WL and BL. In practical applications, a certain memory cell may be activated by a row address and a column address to achieve access to the memory cell.
Address generation (address generation, AG for short) is an addressing technique that facilitates the addressing of mass memory and the implementation of dynamic program floating. In MBIST, the address generation circuit typically counts up from 0 according to the requirements of the controller. However, with the rise of test requirements, the types of test vectors are increasingly demanded, and the address generation circuit with only the ascending addressing function cannot meet the current test requirements.
In view of the above technical problems, embodiments of the present disclosure provide a signal generating circuit that may generate an ascending count, a descending count, a jumping ascending count, and a jumping descending count, and implement various count timing control. The test circuit has simple structure, has little influence on circuit area, power consumption and time sequence, and can realize a plurality of addressing modes such as address ascending addressing, address descending addressing, address jump ascending addressing, address jump descending addressing and the like, thereby supporting more test vectors and better meeting the test requirement of a memory. It should be noted that the functions of the test circuit are not limited to the test circuit and MBIST, and other command planning and generating circuits and counting timing control circuits can be used. For details, reference is made to the following examples.
Referring to fig. 1, fig. 1 is a schematic diagram of a signal generating circuit according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the signal generation circuit 300 includes a counting circuit 310 and a selection circuit 320.
Wherein the counter circuit 310 includes n counter signal outputs RA < n-1>, RA <3>, RA <2>, RA <1>, RA <0>, respectively, for outputting n-bit binary count signals RA < n-1:0>. Where n is a positive integer, n may be, for example, 4, 8, 10, 14, 15, 16, 32, etc., and may be specifically determined according to the number of address lines of the memory.
The selection circuit 320 includes a selection signal input terminal S, n first receiving terminals corresponding to binary bits, n second receiving terminals corresponding to binary bits, and n output terminals corresponding to binary bits.
The n first receiving ends are CA <0>, CA <1>, CA <2>, and CA < n-1>, respectively, and in this embodiment, CA < n-1> -CA <0> is shown in fig. 1. The n second receiving ends are CB <0>, CB <1>, CB <2>, and CB < n-1>, respectively, and in this embodiment, CB < n-1> -CB <0> is shown in fig. 1. The n outputs are respectively RB <0>, RB <1>, RB <2>, RB < n-1>, and the embodiment is shown as RB < n-1> -RB <0> in FIG. 1.
In some embodiments, each first receiving terminal is connected to a count signal output terminal located at the same binary bit. Taking n=16 as an example, CA <0> is connected to RA <0>, CA <1> is connected to RA <1>, CA <2> is connected to RA <2>, CA <15> is connected to RA <15 >.
Each second receiving end is connected with the counting signal output end according to a preset mode, wherein the preset mode comprises that the first m second receiving ends are connected with the last m counting signal output ends according to the sequence from the lower position to the higher position, and the rest second receiving ends are connected with the counting signal output ends lower than the first m. Wherein m is a positive integer and m < n.
Taking n=16, m=1 as an example, CB <0> is connected to RA <15>, CB <1> is connected to RA <0>, CB <2> is connected to RA <1>, and CB <15> is connected to RA <14 >.
The selection circuit 320 is configured to selectively output any one of the signals received by the n first receiving terminals, the signals received by the n second receiving terminals, the reverse signals of the signals received by the n first receiving terminals, and the reverse signals of the signals received by the n second receiving terminals, based on the selection signal received by the selection signal input terminal S.
It will be appreciated that since each first receiving terminal is connected to the count signal output terminal located at the same binary bit, the signals received by the n first receiving terminals output by the selection circuit 320 are consistent with the n-bit binary count signals RA < n-1:0> output by the n count signal output terminals.
Since each second receiving terminal is connected to the count signal output terminal in the preset manner, the n signals received by the n second receiving terminals and the n binary count signals RA < n-1:0> output by the n count signal output terminals output by the selection circuit 320 may have a difference, specifically, the count result corresponding to the n binary count signals RA < n-1:0> is continuously incremented, and the count result corresponding to the n signals received by the n second receiving terminals is incrementally incremented.
For example, when n=4 and m=1, the n second receiving ends receive 0010 when the n binary count signal RA <3:0> is 0001, 0100 when the n binary count signal RA <3:0> is 0010, and 0110 when the n binary count signal RA <3:0> is 0011.
In some embodiments, the selection circuit 320 may selectively output any one of the n first receiving signals, the n second receiving signals, the inverse of the n first receiving signals, and the inverse of the n second receiving signals based on the selection signal received by the selection signal input terminal S.
It can be understood that, since the signals received by the first receiving end and the second receiving end are not 0, i.e. 1, the signals received by the n first receiving ends are inverted, so that the descending order signals with count values gradually changing from large to small can be obtained. Similarly, the signals received by the n second receivers are reversed, so that the jump descending order signals with count values gradually changing from large to small can be obtained.
In some embodiments, the signals received by the n first receivers may be addressed in ascending order as ascending order addresses, the signals received by the n second receivers may be addressed in ascending order as ascending order jump addresses, the inverted signals of the signals received by the n first receivers may be addressed in descending order as descending order addresses, and the inverted signals of the signals received by the n second receivers may be addressed in descending order as descending order jump addresses.
It will be appreciated that as the density of memory increases, the data lines in its memory cells become physically closer, resulting in a gradual increase in capacitive coupling between adjacent data lines. In the process of testing the memory, when a certain data line is read and written, the adjacent data line can be influenced, including but not limited to electric leakage, so that faults among the data lines are caused. By jump addressing, each data line can be written with different data, thereby facilitating fault triggering and facilitating problem detection. For example, the leakage condition of the data lines of rows 2 and 4 is tested by writing data to the data lines of rows 1,3 and 5.
In addition, faults between the memory cells can also be detected by a jump addressing mode, for example, different data are written into different data lines to excite the electric leakage influence of surrounding memory cells on a target memory cell, so that problems are eliminated.
The embodiment of the disclosure provides a signal generating circuit, which can realize various counting time sequence control modes, such as various addressing modes of address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing and the like, so that more test vectors can be supported, the scheme is simple and easy to implement, the influence on circuit area, power consumption and time sequence is small, and the test requirement of a current memory can be better met.
Based on the descriptions in the above embodiments, in some embodiments, the i-th second receiving end may be connected to the m-th count signal output end when i is less than or equal to m, and the i-th second receiving end may be connected to the i-th signal output end when i is greater than m, in order from the lower position to the higher position, where i∈ {1, 2, 3, &.
For example, in some embodiments, taking m=1 as an example, the 1 st (lowest) second receiving terminal is connected to the count signal output terminal of the 1 st (highest) last, and each remaining second receiving terminal is connected to the count signal output terminal of the 1 st (highest) last, so that the count value of the signals received by the n second receiving terminals may be increased by 2 each time a trigger edge of the clock signal arrives.
In other embodiments, taking m=2 as an example, the 1 st second receiving terminal is connected to the count signal output terminal of the 2 nd second receiving terminal, the 2 nd second receiving terminal is connected to the count signal output terminal of the 1 st second receiving terminal, and each remaining second receiving terminal is connected to the count signal output terminal of 2 bits lower than itself in order from the lower position to the higher position. Taking n=16 and m=2 as an example, CB <0> is connected to RA <14>, CB <1> is connected to RA <15>, CB <2> is connected to RA <0>, CB <3> is connected to RA <1>, CB <15> is connected to RA <13 >. This makes it possible to increment the count value of the signals received by the n second receivers by 4 each time a trigger edge of the clock signal arrives.
It is understood that the values of m may also be 3, 4, 5. The embodiments of the present disclosure are not described in detail.
Referring to fig. 2, fig. 2 is a schematic diagram of a signal selection circuit according to an embodiment of the disclosure. In some embodiments, the selection circuits include n signal selection circuits 410 corresponding to binary bits, each signal selection circuit 410 includes a first selector 411, a second selector 412, and a first inverter 413, and the selection signal input terminal S includes a first selection signal input terminal S1 and a second selection signal input terminal S2.
Each first selector 411 includes a first receiving terminal CA, a second receiving terminal CB, a first selection signal input terminal S1, and a first output terminal Z. Each of the second selectors 412 includes a third receiving terminal EA, a fourth receiving terminal EB, a second selection signal input terminal S2, and a second output terminal RB. The first output terminal Z is connected to the third receiving terminal EA and the input terminal of the first inverter 413, respectively, and the output terminal of the first inverter 413 is connected to the fourth receiving terminal EB.
In some embodiments, the first output terminal Z outputs the signal received by the first receiving terminal CA when the first selection signal input terminal S1 receives the non-skip selection signal, and outputs the signal received by the second receiving terminal CB when the first selection signal input terminal S1 receives the skip selection signal.
When the second selection signal input terminal S2 receives the ascending selection signal, the second output terminal RB outputs the signal received by the third receiving terminal EA, and when the second selection signal input terminal S2 receives the descending selection signal, the second output terminal RB outputs the signal received by the fourth receiving terminal EB.
Alternatively, the non-skip select signal and the up select signal may be low level signal 0, and the skip select signal and the down select signal may be high level signal 1. Or the non-jump selection signal and the ascending selection signal are high level signal 1, and the jump selection signal and the descending selection signal are low level signal 0.
In some embodiments, the selection circuit may be further configured to select any one of the target signals to be outputted as the address signal of the memory based on the selection signal received by the selection signal input terminal.
For example, in some embodiments, the memory includes n row address lines and n column address lines, and the second output terminal of each of the second selectors is connected to one of the row address lines or the column address lines. The above-mentioned several target signals can be used as row address addressing signals of the memory for row addressing.
Or the above-mentioned several target signals may be used as column address addressing signals of the memory for column addressing.
Based on what has been described in the above embodiments, in some embodiments, the disclosed embodiments also provide a test circuit applied to a memory built-in self-test, the test circuit including a counting circuit and a selecting circuit;
the counting circuit comprises n counting signal output ends and is used for outputting n-bit binary counting signals, wherein n is a positive integer.
The selection circuit comprises a selection signal input end and n receiving ends corresponding to binary bits, wherein the first m receiving ends are connected with the last m counting signal output ends in the sequence from low bits to high bits, each remaining receiving end is connected with the counting signal output end lower than the m bit of the receiving end, m is a positive integer, and m is less than n;
The selection circuit is configured to select, as the address signal of the memory, any one of the n-number of reception signals and the n-number of reception signals, which are inverse signals of the signal received by the n-number of reception signals, based on the selection signal received by the selection signal input terminal.
In some embodiments, the ith receiving end is connected to the m-th to m+1 th count signal output ends in order from lower to higher, when i is less than or equal to m, and the ith receiving end is connected to the i-th to m-th count signal output ends, when i is greater than m, wherein i e {1, 2, 3.
For example, in some embodiments, taking m=1 as an example, the 1 st (lowest) receiving terminal is connected to the count signal output terminal of the 1 st (highest) count, and each remaining receiving terminal is connected to the count signal output terminal of 1 st (highest) count, so that the count value of the signals received by the n receiving terminals may be increased by 2 when each trigger edge of the clock signal arrives.
Optionally, the values of m may be 1, 2, 3, 4, 5, etc., and specific reference may be made to the description of the foregoing embodiments, which is not repeated herein.
It can be understood that, since the signals received by the receiving ends are not 0, i.e. 1, the signals received by the n receiving ends are inverted, so that the skip descending signal with the count value gradually changing from large to small can be obtained.
In some embodiments, the signals received by the n receivers may be addressed in ascending order as a jump ascending address, and the signals received by the n receivers may be addressed in descending order as a jump descending address.
The test circuit provided by the embodiment of the disclosure can be applied to built-in self-test of the memory, can detect faults between data lines or between memory cells through address jump ascending order addressing or address jump descending order addressing, is simple and easy to implement, has little influence on circuit area, power consumption and time sequence, and better meets the test requirement of the current memory.
In some embodiments, the counting circuit 310 includes n cascaded counting units, and an output terminal of each counting unit is connected to a counting signal output terminal located in the same binary bit. The n cascaded counting units are configured to output n-bit binary counting signals based on clock signals, wherein the difference between the counting results of the n-bit binary counting signals output twice before and after is 1.
Alternatively, the above-mentioned counting unit may be an asynchronous counter composed of D-type Flip-Flop (Data Flip-Flop or DELAY FLIP-Flop, DFF). The D-type trigger is an information storage device with a memory function and two stable states, is the most basic logic unit for forming various time sequence circuits, and is also an important unit circuit in a digital logic circuit. The D-type flip-flop has two stable states, namely "0" and "1", which can be flipped from one stable state to the other under the action of a signal received at the clock terminal of the flip-flop.
In the embodiment of the present disclosure, the flip-flop may include an input terminal D, a clock terminal Clk, an output terminal Q, and a reset terminal RST. The output end Q of each stage of flip-flop is used for outputting the corresponding bit in the counting signal, and the reset end RST of each stage of flip-flop is used for receiving the reset signal, so that reset and zero clearing operation of the counting circuit can be realized, and further counting is restarted.
In some embodiments of the present disclosure, the first counting unit may include a first flip-flop, an inverter is connected between an input terminal D and an output terminal Q of the first flip-flop, a clock terminal of the first flip-flop is configured to receive the first clock signal, and an output terminal Q of the first flip-flop is configured to output the first count signal, and the first count signal is a 0 th bit in the count signal, the second counting unit may include a second flip-flop and a second exclusive-or gate, a first input terminal of the second exclusive-or gate is connected to the output terminal Q of the first flip-flop, a second input terminal of the second exclusive-or gate is connected to the output terminal Q of the second flip-flop, an output terminal Q of the second flip-flop is configured to receive the first clock signal, and the second count signal is a1 st bit in the count signal.
And the ith counting submodule comprises an ith trigger, an ith NAND gate, an ith NOT gate and an ith XOR gate, wherein the first input end of the ith NAND gate is connected with the output end Q of the ith trigger, the second input end of the ith NAND gate is connected with the first input end of the ith XOR gate, the output end of the ith NAND gate is connected with the input end of the ith NOT gate, the output end of the ith NOT gate is connected with the first input end of the ith XOR gate, the second input end of the ith XOR gate is connected with the output end Q of the ith trigger, the output end of the ith XOR gate is connected with the input end D of the ith trigger, the clock end of the ith trigger is used for receiving a first clock signal, the output end Q of the ith trigger is used for outputting an ith counting signal, and the ith counting signal is an ith-1 bit in the counting signal, wherein i is an integer which is more than or equal to 3 and less than or equal to n.
In some embodiments, the D input terminal of the D flip-flop in the above counting unit may also directly use the signal of the Q inverting output terminal of the D flip-flop as the input signal, without introducing the nor gate structure through the Q output terminal.
Referring to fig. 3, fig. 3 is a schematic structural diagram of a counting circuit according to an embodiment of the disclosure. In some embodiments of the present disclosure, taking n=8 as an example, the counting circuit 310 includes a clock source CLK, and 8 cascaded counting units, each including a flip-flop.
The flip-flops in the above 8 cascaded counting units are denoted as D0, D1, D2, &..4, and D7, respectively, and the count signal output terminals connected to the output terminals Q of the flip-flops in the above 8 cascaded counting units are denoted as RA <0>, RA <1>, RA <2>, RA <7>, respectively.
The clock source CLK is coupled to the clock input terminals of the 8 flip-flops, respectively, and is used for providing the clock signal CLK.
The first counting unit comprises a D0 and an inverter, wherein an output end Q of the D0 is connected with an input end of the inverter, and an input end D of the D0 is connected with an output end of the inverter.
The second counting unit comprises a D1 and an exclusive-OR gate, wherein the output end Q of the D1 is connected with the first input end of the exclusive-OR gate, the output end Q of the D0 is connected with the second input end of the exclusive-OR gate, and the input end D of the D1 is connected with the output end of the exclusive-OR gate.
The third counting unit comprises a D2, an AND gate and an exclusive OR gate, wherein the output end Q of the D2 is connected with the first input end of the exclusive OR gate, the output end of the AND gate is connected with the second input end of the exclusive OR gate, the input end D of the D2 is connected with the output end of the exclusive OR gate, and the two input ends of the AND gate are respectively connected with the output end Q of the output end Q, D1 of the D0.
The structures of the fourth to seventh counting units are similar to those of the third counting unit, and are not described in detail in the embodiment of the present disclosure.
Taking D0, D1, D2, and D7 as rising edge triggers as examples, the above-mentioned counting circuit 310 operates as follows:
In the initial state, D0, D1, D2, and D7 are reset by the reset signal RST, so that the output terminals Q of D0, D1, D2, and D7 output low level 0, and the initial binary count signal RA <7:0> output by the count circuit 310 is 00000000.
Before the first rising edge occurs in the clock signal received by the counter circuit 310, since the input terminals D except D0 are at the high level 1 (because an inverter is connected between the output terminal Q and the input terminal D of D0), the remaining input terminals D1, D2, D7 are all at the low level 0, and therefore, when the first rising edge occurs in the clock signal, the output terminal Q of D0 is inverted from the low level 0 to the high level 1, and the output terminals Q of the remaining D1, D2, D4, D7 are all kept at the low level 0, and the binary count signal RA <7:0> output by the counter circuit 310 is 00000001.
Before the second rising edge occurs in the clock signal received by the counter circuit 310, the input terminal D of D0 is at low level 0 (because an inverter is connected between the output terminal Q and the input terminal D of D0), the input terminal D of D1 is at high level 1 (because the input terminal D of D1 is connected to the output terminal of an exclusive or gate, because the first input terminal of the exclusive or gate connected to the output terminal Q of D0 is at high level 1, the second input terminal connected to the output terminal Q of D1 is at low level 0, so that the output terminal of the exclusive or gate is at high level 1), and the remaining D2,.
Before the third rising edge occurs in the clock signal received by the counter circuit 310, the input terminal D of D0 is at high level 1 (because an inverter is connected between the output terminal Q and the input terminal D of D0), the input terminal D of D1 is at high level 1 (because the input terminal D of D1 is connected to the output terminal of an exclusive or gate, because the first input terminal of the exclusive or gate connected to the output terminal Q of D0 is at low level 0, the second input terminal of the exclusive or gate connected to the output terminal Q of D1 is at high level 1, so that the output terminal of the exclusive or gate is at high level 1), and the input terminals D of the remaining D2, &.
Similarly, when the 4 th rising edge occurs in the clock signal, the binary count signal RA <7:0> output by the count circuit 310 is 00000100, the count circuit 310 outputs a binary count signal RA <7:0> of 11111111 when the 255 th rising edge of the clock signal occurs.
In some embodiments, the above-described counting circuit may be implemented by other structures, that is, a counting circuit capable of outputting an n-bit binary counting signal may be used as the counting circuit described in the above-described embodiments.
For a better understanding of the embodiments of the present disclosure, in some embodiments of the present disclosure, if n=16 is taken as an example, the above-mentioned counting circuit may include 16 cascaded counting units. When the initial output value of each counting unit is 0, each counting unit generates one jump at each clock rising edge of the clock signal Clk output by the clock source, and the signal generating circuit and the test circuit output 16-bit binary counting signals RB <15:0>.
Referring to fig. 4, fig. 4 is a timing diagram of a signal generating circuit and a testing circuit according to an embodiment of the disclosure.
It should be noted that, for convenience of reading, the 16-bit binary count signal RB <15:0> is shown after being converted into hexadecimal in fig. 4.
The selection circuit may selectively output the signals received by the n first receiving ends or the signals received by the n second receiving ends by using the signals received by the first selection signal input end S1, and selectively output the reverse signals of the signals received by the n first receiving ends or the reverse signals of the signals received by the n second receiving ends by using the signals received by the second selection signal input end S2.
Exemplary, as shown in fig. 4, when the first selection signal input terminal S1 and the second selection signal input terminal S2 are both at low level 0, the count value of RB <15:0> increases by 1 along with the rising edge of the clock signal, when RB <15:0> can be used as an ascending addressing signal, when the first selection signal input terminal S1 is at low level 0 and the second selection signal input terminal S2 is at high level 1, the count value of RB <15:0> decreases by 1 along with the rising edge of the clock signal, when RB <15:0> can be used as an descending addressing signal, when the first selection signal input terminal S1 is at high level 1 and the second selection signal input terminal S2 is at low level 0, the count value of RB <15:0> increases by 2 along with the rising edge of the clock signal, when RB <15:0> can be used as a jumping ascending addressing signal, when the first selection signal input terminal S1 and the second selection signal input terminal S2 are both at high level 1, the count value of RB <15:0> can be used as a jumping addressing signal.
The signal generating circuit and the test circuit provided by the embodiment of the disclosure can realize multiple addressing modes such as address ascending addressing, address descending addressing, address jumping ascending addressing, address jumping descending addressing and the like by designing the selection circuit on the basis of the counting circuit, so that more test vectors can be supported, the scheme is simple and easy to implement, the influence on circuit area, power consumption and time sequence is small, and the test requirement of a current memory can be better met.
Based on the descriptions in the foregoing embodiments, a memory is further provided in the embodiments of the present disclosure, where the memory includes the signal generating circuit or the test circuit described in the foregoing embodiments, which is not described herein again.
The foregoing embodiments are merely for illustrating the technical solutions of the present disclosure, and not for limiting the same, and although the present disclosure has been described in detail with reference to the foregoing embodiments, it will be understood by those skilled in the art that the technical solutions described in the foregoing embodiments may be modified or some or all of the technical features may be equivalently replaced, and these modifications or replacements do not deviate from the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present disclosure.
Claims (11)
1. A signal generating circuit, comprising a counting circuit and a selecting circuit;
the counting circuit comprises n counting signal output ends and is used for outputting n-bit binary counting signals, wherein n is a positive integer;
The selection circuit comprises a selection signal input end, n first receiving ends corresponding to binary bits and n second receiving ends corresponding to the binary bits;
The first receiving ends are connected with the counting signal output ends positioned in the same binary bit, the first m second receiving ends are connected with the last m counting signal output ends in the sequence from the lower bit to the higher bit, the rest of the second receiving ends are connected with the counting signal output ends lower than the m bit of the second receiving ends, m is a positive integer, and m is less than n;
The selection circuit is configured to select and output any one of the target signals of the signals received by the n first receiving ends, the signals received by the n second receiving ends, the reverse signals of the signals received by the n first receiving ends and the reverse signals of the signals received by the n second receiving ends based on the selection signals received by the selection signal input end;
the selection circuit comprises n signal selection circuits corresponding to binary bits, wherein each signal selection circuit comprises a first selector, a second selector and a first inverter, and the selection signal input end comprises a first selection signal input end and a second selection signal input end;
each first selector comprises a first receiving end, a second receiving end, a first selection signal input end and a first output end;
each second selector comprises a third receiving end, a fourth receiving end, a second selection signal input end and a second output end;
The first output end is respectively connected with the third receiving end and the input end of the first inverter, and the output end of the first inverter is connected with the fourth receiving end.
2. The signal generating circuit according to claim 1, wherein when i is less than or equal to m, the ith second receiving terminal is connected to the m-i+1 th count signal output terminal, and when i is greater than m, the ith second receiving terminal is connected to the i-m th count signal output terminal, in order from low to high, where i e {1, 2, 3,.
3. The signal generating circuit according to claim 1 or 2, wherein said m=1, in order from the lower order to the higher order, said second receiving terminal of the lowest order is connected to said signal output terminal of the highest order, and each of the remaining second receiving terminals is connected to said signal output terminal of less than 1bit itself.
4. The signal generating circuit according to claim 1 or 2, wherein said m = 2, in order from lower order to higher order, a1 st said second receiving terminal is connected to an n-1 st said count signal output terminal, a2 nd said second receiving terminal is connected to an n-th said count signal output terminal, and the remaining ones of said second receiving terminals are each connected to said count signal output terminal lower than its own 2 bits.
5. The signal generating circuit according to claim 1, wherein,
When the first selection signal input end receives a non-jump selection signal, the first output end outputs a signal received by the first receiving end, and when the first selection signal input end receives a jump selection signal, the first output end outputs a signal received by the second receiving end;
When the second selection signal input end receives the ascending selection signal, the second output end outputs the signal received by the third receiving end, when the second selection signal input end receives the descending selection signal, the second output end outputs the signal received by the fourth receiving end.
6. The signal generation circuit of claim 5, wherein the signal generation circuit is applied to a memory;
The selection circuit is configured to select and output either one of the target signals as a row address addressing signal or a column address addressing signal of the memory based on a selection signal received by the selection signal input terminal.
7. The signal generating circuit according to claim 1, wherein the counting circuit comprises n cascaded counting units, an output terminal of each of the counting units being connected to the counting signal output terminal located in the same binary bit;
the n cascaded counting units are configured to output the n-bit binary counting signal based on a clock signal.
8. A test circuit, which is characterized by being applied to a built-in self test of a memory, wherein the test circuit comprises a counting circuit and a selecting circuit;
the counting circuit comprises n counting signal output ends and is used for outputting n-bit binary counting signals, wherein n is a positive integer;
The selection circuit comprises a selection signal input end and n receiving ends corresponding to binary bits;
The first m receiving ends are connected with the last m counting signal output ends in the order from the lower position to the higher position, each remaining receiving end is connected with the counting signal output end lower than the m bit of the receiving end, m is a positive integer, and m is smaller than n;
The selection circuit is configured to select and output any one of a target signal, which is a reverse signal of the signal received by the n receivers, as an address signal of the built-in self test of the memory based on a selection signal received by the selection signal input terminal;
the selection circuit comprises n signal selection circuits corresponding to binary bits, wherein each signal selection circuit comprises a first selector, a second selector and a first inverter, and the selection signal input end comprises a first selection signal input end and a second selection signal input end;
Each first selector comprises a first receiving end, a second receiving end, a first selection signal input end and a first output end;
each second selector comprises a third receiving end, a fourth receiving end, a second selection signal input end and a second output end;
The first output end is respectively connected with the third receiving end and the input end of the first inverter, and the output end of the first inverter is connected with the fourth receiving end.
9. The test circuit of claim 8, wherein the ith said receiving terminal is connected to the m-i+1 th count signal output terminal in order from lower to higher, when i is less than or equal to m, and the ith said receiving terminal is connected to the i-m th count signal output terminal when i is greater than m, wherein i e {1, 2,3, &.
10. Test circuit according to claim 8 or 9, characterized in that m = 1, the receiving terminal of the lowest order being connected to the signal output terminal of the highest order, in order from the lower order to the higher order, the remaining receiving terminals each being connected to the signal output terminal of less than 1 bit per se.
11. A memory comprising a signal generating circuit according to any one of claims 1 to 7 or comprising a test circuit according to any one of claims 8 to 10.
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| KR20070064848A (en) * | 2005-12-19 | 2007-06-22 | 삼성전자주식회사 | Semiconductor memory test apparatus and method for setting logical address for each mode |
| CN114649023A (en) * | 2022-03-23 | 2022-06-21 | 长鑫存储技术有限公司 | Address selection circuit, control method thereof and memory |
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| JP3246449B2 (en) * | 1998-08-27 | 2002-01-15 | 日本電気株式会社 | ROM test circuit for microcomputer with built-in ROM |
| JP2001236797A (en) * | 1999-12-17 | 2001-08-31 | Fujitsu Ltd | Self-test circuit and memory device incorporating the same |
| US10957376B1 (en) * | 2019-12-18 | 2021-03-23 | Winbond Electronics Corp. | Refresh testing circuit and method |
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| Publication number | Priority date | Publication date | Assignee | Title |
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| KR20070064848A (en) * | 2005-12-19 | 2007-06-22 | 삼성전자주식회사 | Semiconductor memory test apparatus and method for setting logical address for each mode |
| CN114649023A (en) * | 2022-03-23 | 2022-06-21 | 长鑫存储技术有限公司 | Address selection circuit, control method thereof and memory |
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