CN118747085A - Register allocation method, processor, chip and electronic device - Google Patents

Abstract

The embodiment of the present application provides a register allocation method, a processor, a chip and an electronic device, wherein the register allocation method comprises: obtaining an instruction, wherein the instruction is related to a mask operation; decoding the instruction to obtain a micro-operation; allocating a mask physical register for the micro-operation from a mask physical register set according to the operand bit width of the instruction to meet the mask requirement of the instruction; wherein the mask physical register set comprises a plurality of mask physical registers, and the register bit width of each mask physical register is fixed to the first bit width; wherein the first bit width is less than the second bit width, and the value of the second bit width corresponds to the number of elements of a SIMD instruction whose operand bit width is the third bit width under the minimum data type, and the third bit width is the maximum operand bit width of the SIMD instruction. The embodiment of the present application can reduce the idle resources in the mask physical register and reduce the waste of power consumption.

Description

Register allocation method, processor, chip and electronic device

Technical Field

The embodiments of the present application relate to the field of computer technology, and specifically to a register allocation method, a processor, a chip, and an electronic device.

Background Art

In the processing of SIMD (Streaming SIMD Extensions) instructions, there is an optional source operand, called a mask; the mask is used to adjust the calculation result of the SIMD instruction. When the mask data is small, a large amount of empty data will be read each time the instruction is processed, resulting in power consumption waste. Therefore, how to provide a technical solution to reduce power consumption waste has become a problem that needs to be solved urgently by those skilled in the art.

Summary of the invention

In view of this, embodiments of the present application provide a register allocation method, a processor, a chip, and an electronic device to reduce power consumption during the processing of SIMD instructions.

To achieve the above objectives, the embodiments of the present invention provide the following technical solutions:

The present application embodiment provides a register allocation method, including:

fetching instructions, the instructions being associated with mask operations;

Decoding the instruction to obtain micro-operations;

According to the operand bit width of the instruction, a mask physical register is allocated to the micro-operation from a mask physical register set to meet the mask requirement of the instruction; wherein the mask physical register set includes a plurality of mask physical registers, and the register bit width of each mask physical register is fixed to the first bit width;

The first bit width is smaller than the second bit width, the value of the second bit width corresponds to the number of elements of a SIMD instruction whose operand bit width is a third bit width under the minimum data type, and the third bit width is the maximum operand bit width of the SIMD instruction.

Optionally, the instruction is a mask calculation instruction; and the mask physical register allocated to the micro-operation includes:

A mask physical register with a first bit width and an indicator bit, wherein the indicator bit is used to indicate whether the high bit of the data is valid, and the high bit range of the data is between the first bit width and the second bit width;

Alternatively, two first-bit wide mask physical registers.

Optionally, allocating a mask physical register from a mask physical register set for the micro-operation according to the operand bit width of the instruction to meet the mask requirement of the instruction includes:

If the operand bit width of the mask calculation instruction is less than or equal to the first bit width, a mask physical register with the first bit width and an indicator bit are allocated to each operand of the mask calculation instruction, and the indicator bit is set to invalidate the high bit of the data.

Optionally, allocating a mask physical register from a mask physical register set for the micro-operation according to the operand bit width of the instruction to meet the mask requirement of the instruction includes:

If the operand bit width of the mask calculation instruction is equal to the second bit width, two mask physical registers with the first bit width are allocated to each operand of the mask calculation instruction, or one mask physical register with the first bit width and an indicator bit, and the indicator bit is set to invalidate the high bit of the data; wherein the second bit width is twice the first bit width.

Optionally, it also includes: allocating two sets of mask arithmetic logic units with the first bit width to the mask calculation instruction to complete the mask calculation instruction with the second bit width in the same cycle.

Optionally, the instruction is a SIMD instruction, wherein the mask is used to adjust the calculation result of the SIMD instruction; the second bit width is twice the first bit width; and the mask physical register allocated to the micro-operation includes:

A first-bit-wide mask physical register;

Alternatively, two first-bit wide mask physical registers.

Optionally, allocating a mask physical register from a mask physical register set for the micro-operation according to the operand bit width of the instruction to meet the mask requirement of the instruction includes:

If the operand bit width of the SIMD instruction is the fourth bit width or the fifth bit width, a mask physical register with the first bit width is allocated to the micro-operation to meet the mask requirement of the SIMD instruction not exceeding the first bit width;

The fourth bit width and the fifth bit width are between the second bit width and the third bit width, and the fourth bit width is smaller than the fifth bit width; the SIMD instruction of the fourth bit width or the fifth bit width uses the mask of the first bit width to adjust the calculation result.

Optionally, decoding the instruction to obtain a micro-operation includes:

If the operand bit width of the SIMD instruction is the third bit width and the data type is not the minimum data type, the SIMD instruction is decoded to obtain two micro-operations; wherein the operand bit width of one micro-operation obtained by decoding is the fifth bit width, and the fifth bit width is the second largest operand bit width of the SIMD instruction;

The allocating a mask physical register from a mask physical register set for the micro-operation according to the operand bit width of the instruction to meet the mask requirement of the instruction includes:

Allocating a mask physical register with a first bit width for the two micro-operations to meet the mask requirement of the SIMD instruction not exceeding the first bit width;

If the target operand of the SIMD instruction is a mask, the method further comprises:

The operation results of the two micro-operations are fused, and the fused result is written into the allocated mask physical register.

Optionally, decoding the instruction to obtain a micro-operation includes:

If the operand bit width of the SIMD instruction is the third bit width and the data type is the minimum data type, the SIMD instruction is decoded to obtain two micro-operations; wherein the operand bit width of one micro-operation obtained by decoding is the fifth bit width, and the fifth bit width is the second largest operand bit width of the SIMD instruction;

The allocating a mask physical register from a mask physical register set for the micro-operation according to the operand bit width of the instruction to meet the mask requirement of the instruction includes:

A mask physical register with a first bit width is allocated to each micro-operation to meet the mask requirement of a second bit width of the SIMD instruction.

Optionally, the two micro-operations include a first micro-operation and a second micro-operation; and the step of allocating a first-bit-width mask physical register to each micro-operation includes:

If the high bit of the mask of the SIMD instruction is invalid, a mask physical register with the first bit width and an indicator bit are allocated to the first micro-operation, and the indicator bit is set to invalidate the high bit of the data;

A mask physical register with a first-bit width is allocated to the second micro-operation, and the encoding of the allocated mask physical register is invalid.

Optionally, the first bit width is 32 bits; the second bit width is 64 bits; the third bit width is 512 bits; and the minimum data type is 8 bits.

Optionally, the fifth bit width is 256 bits, and the fourth bit width between the second bit width and the fifth bit width is 128 bits.

The present application also provides a processor, including:

An instruction acquisition module, used for acquiring instructions, wherein the instructions are related to mask operations;

An instruction decoding module, used for decoding the instruction to obtain a micro-operation;

an allocation unit, configured to allocate a mask physical register from a mask physical register set for the micro-operation according to the operand bit width of the instruction; wherein the mask physical register set includes a plurality of mask physical registers, and the register bit width of each mask physical register is fixed to the first bit width;

The first bit width is smaller than the second bit width, the value of the second bit width corresponds to the number of elements of a SIMD instruction whose operand bit width is a third bit width under the minimum data type, and the third bit width is the maximum operand bit width of the SIMD instruction.

An embodiment of the present application further provides a storage medium, wherein the storage medium stores a design program of a chip, and when the design program is executed, the power supply design method as described above is implemented.

An embodiment of the present application also provides a computer device, comprising the chip as described above.

The register allocation method provided in the embodiment of the present application fixes the register bit width of each masked physical register in the masked physical register set to the first bit width, and the first bit width is smaller than the second bit width, and the value of the second bit width corresponds to the number of elements of the SIMD instruction whose operand bit width is the third bit width under the minimum data type, and the third bit width is the maximum operand bit width of the SIMD instruction; that is, the second bit width is the mask bit width required by the SIMD instruction whose operand bit width is the maximum operand bit width under the minimum data type. The embodiment of the present application fixes the register bit width of each masked physical register to the first bit width smaller than the second bit width, so that the masked physical register has a fixed smaller first bit width, so that the bit width of the masked physical register is closer to the actual demand, and reduces the situation where the masked physical register has unused bits due to setting a larger second bit width. Furthermore, after decoding the instructions related to the mask operation, the embodiments of the present application can allocate mask physical registers that can meet the mask requirements for the micro-operations obtained by decoding the instructions according to the operand bit width of the instructions, and the allocated mask physical registers are based on the first bit width; that is, when the mask physical registers are allocated based on the fixed smaller first bit width, the embodiments of the present application can dynamically allocate mask physical registers that can meet the mask requirements for the micro-operations of the instructions according to the mask requirements of the instructions, thereby optimizing the resource utilization and allocation of the mask physical registers.

Therefore, the embodiment of the present application fixes the register bit width of the mask physical register to a smaller first bit width, and dynamically allocates mask physical registers that can meet the mask requirements, which can effectively reduce the situation where unused bits appear in the mask physical register, reduce the idle resources in the mask physical register, and optimize the resource utilization and allocation of the mask physical register, thereby reducing power consumption waste.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

FIG1 is a schematic diagram of a first flow chart of a register allocation method provided in an embodiment of the present application;

FIG2 is a schematic diagram of a second flow chart of the register allocation method provided in an embodiment of the present application;

FIG3 is a schematic diagram of a third flow chart of the register allocation method provided in an embodiment of the present application;

FIG4 is a schematic diagram of a fourth flow chart of the register allocation method provided in an embodiment of the present application;

FIG5 is a schematic diagram of a fifth flow chart of the register allocation method provided in an embodiment of the present application;

FIG6 is a schematic diagram of the structure of a processor provided in an embodiment of the present application;

FIG7 is another schematic diagram of the structure of a processor provided in an embodiment of the present application;

FIG8 is another schematic diagram of the structure of the processor provided in an embodiment of the present application.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

As technology advances, computing devices are increasingly demanding computing power from SIMD processors, which requires SIMD processors to process more vectors in parallel and accurately control every data change in the vectors.

In SIMD instructions, there is an optional source operand called a mask. When a mask exists, the calculation result of the SIMD instruction needs to be processed according to the value of each bit of the mask. Specifically, the value of each bit of the mask can be 1 or 0. If a bit of the mask is 1, the data of the element bit field corresponding to the SIMD instruction calculation result and the bit will be output normally; if a bit of the mask is 0, the data of the element bit field corresponding to the SIMD instruction calculation result and the bit will be replaced by the data of the element bit field in the target operand, which is also called retaining the original data.

For example, in a SMID instruction, the mask (mask) is: 0010_1110_1000_0011, the source operand (vec0) is: 0x0123_4567_89AB_CDEF, the source operand (vec1) is: 0x1358_1050_3011_0210, and the original value of the destination operand (vec2) is: 0xAAAA_AAAA_AAAA_AAAA.

If the SMID instruction is an addition instruction, the source operand (vec0) and the source operand (vec1) need to be added, and stored in the destination operand (vec2) after masking. Then the intermediate result after adding the source operand (vec0) and the source operand (vec1) is: 0x147B_55B7_B9BC_CFFF. The final result after storing the intermediate result in the destination operand (vec2) after masking is: 0xAA7A_55BA_BAAA_AAFF.

In addition, the mask as an optional operand can also be used as the calculation result of the instruction, that is, as the target operand, for example, the mask can be calculated by a mask instruction. The SIMD processor may include a mask arithmetic logic unit for performing mask calculations, and some operations can be performed between multiple masks through the mask arithmetic logic unit. When there is no mask, the instruction is executed normally.

The vector bit width of SIMD instructions supported by the mask is usually 128bit, 256bit, and 512bit. The vector bit width is the number of bits of the total amount of data that can be processed simultaneously by a single instruction. Taking a SIMD instruction with a vector bit width of 512bit as an example, at this time, the maximum bit width of the operand that the instruction can process is 512bit, and the data types of the operands that the instruction can process are 8bit, 16bit, 32bit, and 64bit, a total of 4 types. When the bit width of an operand is the maximum bit width of 512bit and the data type is the minimum data type of 8bit, an operand will contain 64 elements, and 1bit in the mask is used to process 1 element, so the mask of the operand is 64bit; accordingly, the mask physical register that stores the mask requires 64bit. Therefore, for a SIMD instruction with a vector bit width of 512bit, the required bit width of the mask physical register is up to 64bit.

Furthermore, since the bit width of the mask physical register is related to the processor architecture, the bit width of the mask physical register is usually immutable. Therefore, for any SIMD instruction, the bit width of the mask physical register allocated by the SIMD instruction is equal to the bit width of the maximum required mask physical register, both of which are 64 bits. This ensures that the mask physical register can adapt to more types of SIMID instructions.

In addition, the mask can also be used as the calculation result of the SIMD instruction. If the calculation result of the SIMD instruction is a mask, then an idle mask physical register will be allocated to the SIMD instruction as the target register for storing the mask. The bit width of the mask arithmetic logic unit is consistent with that of the mask register, both of which are 64 bits.

However, the 64 bits of the mask physical register will only be fully used when the vector bit width of the SMID instruction is 512 bits and the data type of the operand is 8 bits. For other cases, the maximum mask bit width is only 32 bits, so only the lower 32 bits of the mask physical register are used in other cases. Every time the mask physical register is read, all 64 bits of data in the mask physical register are read. Even if there is idle data, all data needs to be read. When data is written to the data in the mask physical register, all 64 bits of data in the mask physical register are also refreshed. Even if there is idle high 32 bits of data, all data needs to be refreshed at the same time. Since the mask is 64 bits only in some cases, for other cases, the mask physical register will be over-read and written, resulting in a waste of power consumption.

Based on this, the embodiments of the present application consider reducing the bit width allocated to a single mask physical register for each SMID instruction, reducing the idle resources in the mask physical register, reducing excessive reading and writing of the mask physical register, and reducing power consumption.

Based on the above ideas, in order to solve the above problems, the embodiment of the present application provides a register allocation method to reduce the waste of power consumption. As an optional implementation, Figure 1 shows a flow chart of the register allocation method provided by the embodiment of the present application. As shown in Figure 1, the register allocation method provided by the embodiment of the present application includes the following steps.

Step S10: Get instructions, where the instructions are related to the mask operation.

Specifically, the instruction may be a mask calculation instruction that uses a mask as a source operand or a target operand, or may be a SIMD instruction that requires the use of a mask to process a calculation result.

Step S20: Decode the instruction to obtain at least one micro-operation.

Step S30: allocating a mask physical register from a mask physical register set for the micro-operation according to the operand bit width of the instruction to meet the mask requirement of the instruction.

The mask physical register set includes a plurality of mask physical registers, and the register bit width of each mask physical register is fixed to the first bit width. The first bit width is smaller than the second bit width, and the value of the second bit width corresponds to the number of elements of a SIMD instruction whose operand bit width is the third bit width under the minimum data type, and the third bit width is the maximum operand bit width of the SIMD instruction.

It should be noted that, from the foregoing content, it can be seen that the maximum operand bit width is equal to the maximum vector bit width of the instruction, that is, 512 bits. Therefore, in an optional implementation, the value of the third bit width is 512 bits.

Furthermore, the 1-bit data of the mask is used to process an element of the calculation result of the instruction. Therefore, when the maximum bit width of the mask is 64 bits, the number of elements corresponding to the mask is equal to the number of elements when the bit width of the operand is the maximum operand bit width and the data type is the minimum data type, that is, the second bit width. As can be seen from the foregoing, in an optional implementation, the minimum data type of the SIMD instruction is 8 bits. At this time, the number of elements of the instruction of the third bit width under the minimum data type is 64, and the value of the second bit width is 64 bits.

Furthermore, since the first bit width is smaller than the second bit width, that is, the first bit width is smaller than 64 bits. As can be seen from the foregoing, the vector bit width of SIMD instructions is usually 128 bits, 256 bits, and 512 bits, that is, the bit width of the operand of SIMD instructions can be 128 bits, 256 bits, and 512 bits, and the data types of the operands of SIMD instructions are 8 bits, 16 bits, 32 bits, and 64 bits. Therefore, the selectable values of the first bit width include 8 bits, 16 bits, and 32 bits.

Furthermore, it can be seen from the above content that when the size of the mask physical register is 64 bits, it is easy to waste more resources. If the size of the mask physical register is too small, too many mask physical registers will be required when processing a single instruction. The increase in the number of mask physical registers will cause the bit width of the instruction scheduling queue to increase significantly, thereby causing the problem of resource explosion. Therefore, optionally, the value of the first bit width is 32 bits.

It should be noted that, since the bit width of the mask physical register is related to the architecture of the processor, in a processor, the bit width of any mask physical register is equal, that is, the bit width of all mask physical registers is the first bit width of 32 bits.

In particular, when allocating mask physical registers from the mask physical register set for the micro-operation, the allocated mask physical registers are all idle mask physical registers, which can reduce data conflicts and delays of the mask physical registers.

It can be seen that the register bit width of each masked physical register in the masked physical register set is fixed to the first bit width, and the first bit width is smaller than the second bit width, the value of the second bit width corresponds to the number of elements of the SIMD instruction with the operand bit width of the third bit width under the minimum data type, and the third bit width is the maximum operand bit width of the SIMD instruction; that is, the second bit width is the mask bit width required by the SIMD instruction with the maximum operand bit width under the minimum data type. The embodiment of the present application fixes the register bit width of each masked physical register to a first bit width smaller than the second bit width, so that the masked physical register has a fixed smaller first bit width, so that the bit width of the masked physical register is closer to the actual demand, and reduces the situation where unused bits of the masked physical register are caused by setting a larger second bit width. Furthermore, after decoding the instructions related to the mask operation, the embodiments of the present application can allocate mask physical registers that can meet the mask requirements for the micro-operations obtained by decoding the instructions according to the operand bit width of the instructions, and the allocated mask physical registers are based on the first bit width; that is, when the mask physical registers are allocated based on the fixed smaller first bit width, the embodiments of the present application can dynamically allocate mask physical registers that can meet the mask requirements for the micro-operations of the instructions according to the mask requirements of the instructions, thereby optimizing the resource utilization and allocation of the mask physical registers.

Therefore, the embodiment of the present application fixes the register bit width of the mask physical register to a smaller first bit width, and dynamically allocates mask physical registers that can meet the mask requirements, which can effectively reduce the situation where unused bits appear in the mask physical register, reduce the idle resources in the mask physical register, and optimize the resource utilization and allocation of the mask physical register, thereby reducing power consumption waste.

As a special operand, mask can be used not only to process the calculation results of SIMD instructions, but also as the source operand or target operand of instructions. For example, the mask required by SIMD instructions is not pre-stored data, but the result value calculated by specific data. Such instructions that use mask as source operand or target operand are called mask calculation instructions.

For SIMD instructions other than mask calculation instructions, the bit width of the operand can be 128 bits, 256 bits, or 512 bits. However, the maximum size of the mask is only 64 bits, and the modules that process mask calculation instructions and general SIMD instructions in the processor are also different. Therefore, different types of instructions need to be processed differently.

Further, for an instruction type of mask calculation instruction, in an optional implementation, the instruction is a mask calculation instruction, and the mask physical register allocated to the micro-operation in step S30 includes any of the following:

A mask physical register with a first bit width and an indicator bit, wherein the indicator bit is used to indicate whether the high bit of the data is valid, wherein the high bit range of the data is between the first bit width and the second bit width.

Two first-bit wide mask physical registers.

It should be noted that the "high bit of data" is the digit with the largest value in a binary number, located at the leftmost end of the number. Specifically, the "high bit of data" is the leftmost part of the mask when the mask size is 64 bits, and the high bit range of the data is the high 32 bits of the data. The "indicating whether the high bit of data or data is valid" indicates whether the value of the high bit of the data or data is all 0.

Since the maximum bit width of the mask can be 64 bits, and in the embodiment of the present application, the size of the first bit width mask physical register, that is, the first bit width, is only 32 bits. Therefore, when the mask is larger than 32 bits, one first bit width mask physical register cannot be fully stored, so two different methods are required, respectively for storing a mask with a bit width less than or equal to 32 bits or a mask with a bit width greater than 32 bits.

Specifically, as shown in Figure 2, in an optional implementation, if the operand bit width of the mask calculation instruction is less than or equal to the first bit width, the step S30 includes step S31: a mask physical register with the first bit width and an indicator bit are allocated to each operand of the mask calculation instruction, and the indicator bit is set to invalidate the high bit of the data.

Since the maximum size of the mask is 64 bits, and in the embodiment of the present application, the size of the first bit width mask physical register, i.e., the first bit width is 32 bits, if the mask size is less than the first bit width 32 bits, only one first bit width mask physical register and an indicator bit are needed to store the complete mask.

In particular, in an optional implementation, when the size of the mask is less than or equal to 32 bits, a mask physical register with the first bit width can store the mask. Therefore, there is no "high bit of data" at this time, and the indicator bit can be omitted, that is, only one mask physical register with the first bit width is allocated.

Further, as shown in Figure 2, in an optional implementation, if the operand bit width of the mask calculation instruction is equal to the second bit width, the step S30 includes step S32: allocating two mask physical registers with the first bit width to each operand of the mask calculation instruction, or, one mask physical register with the first bit width and an indicator bit, and the indicator bit is set to invalidate the high bit of the data.

The second bit width is twice the first bit width.

It should be noted that the second bit width is the maximum possible size of the mask, i.e. 64 bits. For a mask greater than 32 bits and less than or equal to 64 bits, one mask physical register with the first bit width cannot store the entire mask, so two mask physical registers with the first bit width are required to store the entire mask.

In addition, when a mask with a value of 0 is used to process the calculation result of an instruction, the calculation result of the instruction will not be changed. At this time, in order to save physical register resources, the mask can be stored in a mask physical register with a first bit width combined with an indicator bit structure. The value of the indicator bit includes 1 or 0, 1 indicates that the value of the high bit of the data is 0, and 0 indicates that the value of the high bit of the data is not 0. In this way, the indicator bit can indicate whether the high-order part of the mask is 0, so that a mask greater than 32 bits can still be stored using only a mask physical register with a first bit width. When reading the mask physical register, the amount of data read from the mask physical register can be reduced to reduce resource consumption.

In particular, in some special cases, the values of the mask may all be 0. For example, when the instruction is a mask calculation instruction, the source operands are two source operands with the same value, and the calculation performed is an XOR calculation. According to the calculation rules of the XOR calculation, before completing the mask calculation instruction, it can be foreseen that the values of the calculation results are all 0. At this time, instead of allocating 2 mask physical registers with the first bit width for the result value that is all 0, a mask physical register with the first bit width and an indicator bit can be allocated to avoid wasting resources.

Furthermore, since the bit width of the mask arithmetic logic unit is equal to the bit width of the mask physical register, which is only the first bit width, for example, 32 bits, when the instruction is a mask calculation instruction and the source operand is the second bit width, for example, 64 bits, it takes 2 cycles to complete the mask calculation instruction using only one mask arithmetic logic unit with the first bit width.

In order to improve the instruction processing speed, when the instruction is a mask calculation instruction and the source operand is the second bit width, in an optional implementation, two sets of mask arithmetic logic units with the first bit width can be allocated to the mask calculation instruction to complete the mask calculation instruction with the second bit width in the same cycle. In this way, each mask arithmetic logic unit with the first bit width processes a 32-bit source operand, and two sets of mask arithmetic logic units with the first bit width can process a total of 64 bits of source operands, thereby completing the mask calculation instruction with the source operand being the second bit width in one cycle.

Further, for SIMD instructions other than the above-mentioned mask calculation instructions, the mask is used to adjust the calculation result of the SIMD instruction; at this time, for the SIMD instruction, the first bit width may be half of the second bit width, and the mask physical register allocated to the micro-operation of the SIMD instruction may include any of the following:

A first-bit-wide mask physical register;

Two first-bit wide mask physical registers.

Since the maximum bit width of the mask can be 64 bits, and in the embodiment of the present application, the size of the first bit width mask physical register, that is, the first bit width, is only 32 bits. Therefore, if the mask of the SIMD instruction is larger than 32 bits, one first bit width mask physical register cannot be fully stored, so two different methods are required, one for storing a mask with a bit width less than or equal to 32 bits or a mask with a bit width greater than 32 bits.

Further, as shown in FIG3 , in an optional implementation, if the operand bit width of the SIMD instruction is the fourth bit width or the fifth bit width, the step S30 includes a step S33: allocating a mask physical register of the first bit width to the micro-operation to meet the mask requirement of the SIMD instruction not exceeding the first bit width. The fourth bit width and the fifth bit width are between the second bit width and the third bit width, and the fourth bit width is smaller than the fifth bit width; the SIMD instruction of the fourth bit width or the fifth bit width uses the mask of the first bit width to adjust the calculation result.

It should be noted that the fourth bit width is the bit width of the SIMD instruction operand in the above content, 128 bits. For SIMD instructions, the minimum data type is 8 bits, so for the fourth bit width of the operand 128 bits, the number of elements included in the operand of the SIMD instruction is at most 16. The maximum bit width of the mask of the corresponding SIMD instruction with the fourth bit width of 128 bits is 16 bits.

The fifth bit width is the bit width of the operand of the SIMD instruction in the above content, 256 bits. For SIMD instructions, the minimum data type is 8 bits, so for the fifth bit width of the operand of 256 bits, the number of elements included in the operand of the SIMD instruction is at most 32. The maximum bit width of the mask of the corresponding SIMD instruction with the fifth bit width of 256 bits is 32 bits.

It can be seen that when the operand bit width of the SIMD instruction is the fourth bit width of 128 bits or the fifth bit width of 256 bits, the mask bit width of the SIMD instruction must be smaller than the first bit width of 32 bits. Therefore, when the operand bit width of the SIMD instruction is the fourth bit width of 128 bits and the fifth bit width of 256 bits, only one mask physical register with the first bit width is allocated to the micro-operation to completely store the mask.

Further, as shown in Fig. 4, in an optional implementation, if the operand bit width of the SIMD instruction is the third bit width and the data type is not the minimum data type, the step S20 includes a step S21: decoding the SIMD instruction to obtain two micro-operations. The operand bit width of one micro-operation obtained by decoding is the fifth bit width, and the fifth bit width is the second largest operand bit width of the SIMD instruction.

It should be noted that the third bit width is 521 bits, and the fifth bit width is 256 bits. Since in the embodiment of the present application, the bit width of a mask physical register is the first bit width of 32 bits, the maximum bit width of the operand of the SIMD instruction corresponding to a mask physical register is the bit width of the operand when the data type of the operand is the minimum data type of 8 bits. At this time, the bit width of the operand of the SIMD instruction is 256 bits, that is, the fifth bit width. Therefore, the size of the vector arithmetic logic unit that can be used to process operations between operands and masks is the fifth bit width of 256 bits, which can process most operations between operands and masks.

However, there are still a small number of SIMD instructions whose operands have a bit width of 512 bits. At this time, only one vector arithmetic logic unit cannot process 512-bit operands. If an additional 512-bit vector arithmetic logic unit is implemented in the system, the system architecture will be too complicated, resulting in a large waste of resources. Therefore, it is chosen to decompose the 512-bit operand into two 256-bit micro-operations when decoding and obtaining micro-operations, so that two fifth-bit-wide vector arithmetic logic units can be used to process a 512-bit operand. In this way, it can be ensured that the processing of 512-bit operands is achieved without changing the system architecture.

Furthermore, when the operand bit width of the SIMD instruction is the third bit width and the data type is not the minimum data type, after obtaining two micro-operations of the fifth bit width, in an optional implementation, the step S30 includes step S34: allocating a mask physical register of the first bit width to the two micro-operations to meet the mask requirement of the SIMD instruction not exceeding the first bit width.

It should be noted that when the operand bit width of the SMID instruction is 512 bits and the data type of the operand is not 8 bits, the minimum data type of the operand is 16 bits, the maximum mask bit width of the SMID instruction is 32 bits, and the mask bit width of the SMID instruction is less than or equal to 32 bits. Therefore, when the SMID instruction vector bit width is the third bit width and the data type is not the minimum data type 8 bits, only one mask physical register with the first bit width needs to be allocated to completely store the mask.

In an optional implementation, after step S34, the method further includes step S341: if the target operand of the SIMD instruction is a mask, fusing the operation results of the two micro-operations, and writing the fusion result into the allocated mask physical register.

It should be noted that when the data type is not the minimum data type of 8 bits, each micro-operation with a fifth bit width of 256 bits requires a 16-bit mask. If two 16-bit masks are stored in the first bit width mask physical register, the two 16-bit masks may overwrite each other. Therefore, in order to avoid storage errors, the two 16-bit masks can be merged into a complete 32-bit mask before storage.

Further, as shown in FIG4 , if the operand bit width of the SIMD instruction is the third bit width and the data type is the minimum data type, similar to the above content, in an optional implementation, the step S20 includes step S21: decoding the SIMD instruction to obtain two micro-operations. The operand bit width of one micro-operation obtained by decoding is the fifth bit width, and the fifth bit width is the second largest operand bit width of the SIMD instruction.

As shown in FIG4 , when the operand bit width of the SIMD instruction is the third bit width and the data type is the minimum data type, after obtaining two micro-operations of the fifth bit width, in an optional implementation, the step S30 includes a step S35: allocating a mask physical register of the first bit width to each micro-operation to meet the mask requirement of the second bit width of the SIMD instruction, wherein the second bit width is twice the first bit width.

It should be noted that when the bit width of the operand of the SMID instruction is 512 bits and the data type of the operand is the minimum data type of 8 bits, the mask size of the SMID instruction is 64 bits. At this time, only one mask physical register with a first bit width of 32 bits cannot fully store the 64-bit mask. The bit width of each micro-operation is 256 bits, and the bit width of the mask required for each micro-operation is 32 bits. Therefore, one mask physical register can be allocated to each micro-operation to store 32-bit masks in two mask physical registers with a first bit width of 32 bits respectively, so as to completely store the above 64-bit mask. Using two mask physical registers instead of a single mask physical register can also avoid the delay introduced when first fusing two 32-bit masks into 64 bits and then writing them into the mask physical register.

In particular, as shown in Figure 5, when the operand bit width of the SIMD instruction is the third bit width and the data type is the minimum data type, and the high bit of the mask of the SIMD instruction is invalid, that is, when the values of the high 32 bits of the 64-bit mask of the above SIMD instruction are all 0, in an optional implementation, the step S35 includes step S351: allocating a mask physical register with the first bit width and an indicator bit to the first micro-operation, and the indicator bit is set to invalidate the high bit of the data; allocating a mask physical register with the first bit width to the second micro-operation, and the encoding of the allocated mask physical register is invalid.

At this time, for the first micro-operation corresponding to the lower 32 bits of the mask, it can be normally allocated to a 32-bit mask physical register and an indicator bit, and the indicator bit is set to invalidate the high bit of the data, and store the lower 32 bits of the mask. When the second micro-operation corresponding to the upper 32 bits of the mask is allocated a mask physical register with the first bit width, the encoding of the mask physical register is invalid; at this time, the upper 32 bits of the mask do not exist in the mask physical memory, and 32 bits of 0 value data will be directly obtained when reading the upper 32 bits of the mask. In this way, when the mask bit width is 64 bits and the values of the upper 32 bits of the mask are all 0, the use of the mask physical register can be reduced, the resource consumption in the system can be reduced, and the overhead required to read the mask can be shortened.

Furthermore, the register allocation method provided in the embodiment of the present application can also reduce the waiting time of the program and improve the operation efficiency. For example, for an instruction A1 with an operand bit width of the third bit width (512 bits), the instruction A1 needs to first use the source operands vec1 and vec2 with a bit width of 512 bits, and cooperate with mask mask1 to calculate mask mask2 and store it. After that, it is necessary to add the source operands vec2 and vec3, and then calculate the result with mask mask2, and the result is stored as the source operand vec1.

If a 256-bit data path and a 64-bit mask physical register are used, the above instruction needs to be divided into four micro-operations, namely:

Micro-operation U1: According to the high bits of source operand vec1 and source operand vec2, the high bits of mask mask2 are calculated with mask mask1 and stored in the cache.

Micro-operation U2: According to the low bits of source operand vec1 and source operand vec2, the low bits of mask mask2 are calculated in conjunction with mask mask1. The low bits of mask mask2 and the high bits of mask mask2 in the cache are stored as mask mask2 and stored in the mask physical register.

Micro-operation U3: The high bits of source operand vec2 are added to the high bits of source operand vec3, the result is calculated with mask mask2, and stored as the high bits of source operand vec1.

Micro-operation U4: Add the low bits of source operand vec2 and source operand vec3, calculate the result with mask mask2, and store it as the low bits of source operand vec1.

In the above case, the micro-operation U2 can be scheduled for execution only after the calculation process of the micro-operation U1 starts. The micro-operations U3 and U4 can be scheduled for execution only after the calculation process of the micro-operation U2 starts. When other operands are prepared by default, it takes a total of 7 cycles to complete the above micro-operations U1 to U4.

If the register allocation method provided in the embodiment of the present application is used, the above instruction is divided into 4 micro-operations:

Micro-operation U5: According to the high bits of source operand vec1 and source operand vec2, the high bits of mask mask2 are calculated with mask mask1 and stored in the mask physical register.

Micro-operation U6: According to the low bits of source operand vec1 and source operand vec2, the low bits of mask mask2 are calculated with mask mask1 and stored in the mask physical register.

Micro-operation U7: Add the high bits of source operand vec2 and source operand vec3, calculate the result with mask mask2, and store it as the high bits of source operand vec1.

Micro-operation U8: Add the low bits of source operand vec2 and source operand vec3, calculate the result with mask mask2, and store it as the low bits of source operand vec1.

Under the register allocation method provided in the embodiment of the present application, the high and low bits of the mask related to the above instruction are allocated and stored in 2 mask physical registers. Therefore, the micro-operation U1 and micro-operation U2 can start scheduling operation at the same time, and the micro-operation U7 and micro-operation U8 can be respectively scheduled and operated after the calculation process of the micro-operation U1 and micro-operation U2 starts. In the case where other operands are all prepared by default, it only takes 6 cycles to complete the above micro-operations U5 to U8. The running time of 2 cycles can be shortened, and the operating efficiency of the instruction is improved.

The register allocation method provided in the embodiment of the present application reduces the register bit width of each mask physical register in the mask physical register set from 64 bits to 32 bits, which can reduce the bit width of the mask physical register, so that the bit width of the mask physical register is closer to the actual demand, and reduce the situation where too many unused bits of the mask physical register appear due to setting a larger bit width. Furthermore, after decoding the instructions related to the mask operation, the embodiment of the present application can allocate mask physical registers that can meet the mask requirements for the micro-operations obtained by decoding the instructions according to the operand bit width of the instructions; that is, in the case where the mask physical register is allocated based on a smaller bit width, the embodiment of the present application can dynamically allocate mask physical registers that can meet the mask requirements for the micro-operations of the instructions according to the mask requirements of the instructions, thereby optimizing the resource utilization and allocation of the mask physical registers.

Based on the above method, the embodiment of the present application considers reducing the bit width allocated to a single mask physical register for each SMID instruction, reducing the idle resources in the mask physical register, reducing excessive reading and writing of the mask physical register, and reducing the waste of power consumption. The embodiment of the present application also provides a processor to reduce the waste of power consumption. As an optional implementation, FIG6 shows a schematic diagram of the structure of the processor provided by the embodiment of the present application. As shown in FIG6, the processor provided by the embodiment of the present application includes:

The instruction acquisition module 100 is used to acquire instructions, where the instructions are related to mask operations.

The instruction decoding module 200 is used to decode the instruction to obtain a micro-operation.

The allocation unit 300 is used to allocate a mask physical register 400 for the micro-operation from a mask physical register set according to the operand bit width of the instruction. The mask physical register set includes a plurality of mask physical registers 400 .

The mask physical register 400 is used to store a mask, and has a bit width of the first bit.

Among them, the first bit width is smaller than the second bit width, the value of the second bit width corresponds to the number of elements under the minimum data type of an instruction whose operand bit width is a third bit width, and the third bit width is the maximum operand bit width among multiple operand bit widths.

Further, as shown in FIG6 , in an optional implementation, the instruction is a mask calculation instruction; the mask physical register 400 allocated to the micro-operation includes:

A mask physical register with the first bit width and an indicator bit, wherein the indicator bit is used to indicate whether the high bit of the data is valid, and the high bit range of the data is between the first bit width and the second bit width; or, two mask physical registers with the first bit width.

Furthermore, in an optional implementation, the allocation unit 300 is used to allocate a mask physical register with the first bit width and an indicator bit to each operand of the mask calculation instruction if the operand bit width of the mask calculation instruction is less than or equal to the first bit width, and the indicator bit is set to invalidate the high bit of the data.

Further, in an optional implementation, the allocation unit 300 is used to allocate two mask physical registers with the first bit width to each operand of the mask calculation instruction if the operand bit width of the mask calculation instruction is equal to the second bit width, or, a mask physical register with the first bit width and an indicator bit, and the indicator bit is set to invalidate the high bit of the data; wherein the second bit width is twice the first bit width; wherein the mask calculation instruction uses two sets of mask arithmetic logic units with the first bit width to complete the mask calculation instruction with the second bit width in the same cycle.

Further, in an optional implementation, the instruction is a SIMD instruction, wherein the mask is used to adjust the calculation result of the SIMD instruction; the second bit width is twice the first bit width; the mask physical register 400 allocated to the micro-operation includes: a mask physical register with the first bit width; or, two mask physical registers with the first bit width.

Further, in an optional implementation, the allocation unit 300 is used to allocate a mask physical register with a first bit width to the micro-operation if the operand bit width of the SIMD instruction is a fourth bit width or a fifth bit width, so as to meet the mask requirement of the SIMD instruction not exceeding the first bit width; wherein the fourth bit width and the fifth bit width are between the second bit width and the third bit width, and the fourth bit width is smaller than the fifth bit width; and the SIMD instruction with a fourth bit width or a fifth bit width uses a mask with a first bit width to adjust the calculation result.

Further, in an optional implementation, the instruction decoding module 200 is used to decode the SIMD instruction to obtain two micro-operations if the operand bit width of the SIMD instruction is the third bit width and the data type is not the minimum data type; wherein the operand bit width of one micro-operation obtained by decoding is the fifth bit width, and the fifth bit width is the second largest operand bit width of the SIMD instruction.

Furthermore, in an optional implementation, the allocation module 300 is used to allocate a mask physical register with a first bit width for the two micro-operations to meet the mask requirement of the SIMD instruction not exceeding the first bit width; wherein, the fusion result after the operation results of the two micro-operations are fused is written into the allocated mask physical register.

Furthermore, as shown in FIG. 7 , in an optional implementation, the processor further includes a result fusion module 301 for fusing the operation results of the two micro-operations, and writing the fusion result into the allocated mask physical register 400 .

Further, in an optional implementation, the instruction decoding module 200 decodes the SIMD instruction to obtain two micro-operations if the operand bit width of the SIMD instruction is the third bit width and the data type is the minimum data type; wherein the operand bit width of one micro-operation obtained by decoding is the fifth bit width, and the fifth bit width is the second largest operand bit width of the SIMD instruction.

The allocation unit 300 allocates a mask physical register of the first bit width to each micro-operation to meet the mask requirement of the second bit width of the SIMD instruction.

Further, in an optional implementation, the allocation unit 300 is used to allocate a mask physical register with a first bit width and an indicator bit to the first micro-operation if the high bit of the mask of the SIMD instruction is invalid, and the indicator bit is set to invalid high bit of the data; allocate a mask physical register with a first bit width to the second micro-operation, and the encoding of the allocated mask physical register is invalid.

Further, from the foregoing content, it can be seen that in an optional implementation, the first bit width is 32 bits, the second bit width is 64 bits, the third bit width is 64 bits, the minimum data type is 8 bits, the fourth bit width is 128 bits, and the fifth bit width is 256 bits.

Furthermore, in an optional implementation, the processor includes a plurality of peripheral modules in addition to the above modules related to the register allocation process. Specifically, as shown in FIG8 , the processor also includes: an instruction issuing module 600, which is used to send the instruction and the allocation requirement of the mask physical register 400 to other subsequent modules.

The floating point operation unit 700 is used to schedule the operands and masks and process numerical calculations of the operands or masks.

Furthermore, the floating point operation unit 700 further includes: a scheduling unit 710, which is used to schedule signal transmission between other units in the floating point operation unit 700. A mask arithmetic logic unit 501, which is used to process the numerical calculation of the mask. It should be noted that in order to improve the calculation efficiency of the mask, the number of the mask arithmetic logic units 501 is multiple. A vector arithmetic logic unit 720, which is used to process the numerical calculation of the operand.

The processor further includes a vector physical register 810 for storing the operands. A fixed-point module 910 is a processor for performing fixed-point operations, and is used to process operations on numbers without decimal points or with fixed decimal points. A loading module 920 is used to process data transmitted between the floating-point operation unit 700 and the fixed-point module 910 and a memory or register.

An embodiment of the present application also provides a chip, which includes the processor as described above.

An embodiment of the present application also provides an electronic device, including the processor as described above or the chip as described above.

Although the embodiments of the present application are disclosed above, the present application is not limited thereto. Any person skilled in the art may make various changes and modifications without departing from the spirit and scope of the present application. Therefore, the scope of protection of the present application shall be subject to the scope defined by the claims.

Claims (27)

1. A register allocation method, comprising:

Fetching an instruction, the instruction associated with a masking operation;

Decoding the instruction to obtain micro-operation;

According to the operation digital width of the instruction, a mask physical register is allocated for the micro operation from a mask physical register set so as to meet the mask requirement of the instruction; wherein the set of mask physical registers includes a plurality of mask physical registers, a register bit width of each mask physical register being fixed to a first bit width;

The first bit width is smaller than the second bit width, the value of the second bit width corresponds to the element number of the SIMD instruction with the third bit width under the minimum data type, and the third bit width is the maximum operation bit width of the SIMD instruction.

2. The register allocation method according to claim 1, wherein the instruction is a mask calculation instruction; the masked physical registers allocated for the micro-operations include:

A first bit wide mask physical register and an indication bit, wherein the indication bit is used for indicating whether the high order bits of the data are valid, and the high order bit range of the data is between the first bit wide and the second bit wide;

Or two first bit wide masked physical registers.

3. The register allocation method according to claim 2, wherein said allocating a mask physical register from a mask physical register set for said micro-operation according to an operand bit width of said instruction to satisfy a mask requirement of said instruction comprises:

If the operand bit width of the mask calculation instruction is less than or equal to the first bit width, each operand of the mask calculation instruction is allocated a mask physical register of the first bit width and an indication bit, and the indication bit is set to be invalid in the high order of the data.

4. The register allocation method according to claim 2, wherein said allocating a mask physical register from a mask physical register set for said micro-operation according to an operand bit width of said instruction to satisfy a mask requirement of said instruction comprises:

If the operation digital width of the mask calculation instruction is equal to the second digital width, two mask physical registers with the first digital width or one mask physical register with the first digital width and an indication bit are allocated to each operand of the mask calculation instruction, and the indication bit is set to be invalid in the high order of the data; wherein the second bit width is twice the first bit width.

5. The register allocation method according to claim 4, further comprising: two sets of mask arithmetic logic units of a first bit width are allocated for the mask calculation instruction to complete the mask calculation instruction of a second bit width in the same period.

6. The register allocation method of claim 1, wherein the instruction is a SIMD instruction, wherein a mask is used to adjust a calculation result of the SIMD instruction; the second bit width is twice the first bit width; the masked physical registers allocated for the micro-operations include:

A first bit wide mask physical register;

Or two first bit wide masked physical registers.

7. The register allocation method according to claim 6, wherein said allocating a mask physical register from a mask physical register set for said micro-operation according to an operand bit width of said instruction to satisfy a mask requirement of said instruction comprises:

If the operating digital width of the SIMD instruction is the fourth bit width or the fifth bit width, a mask physical register with a first bit width is allocated for the micro-operation so as to meet the mask requirement that the SIMD instruction does not exceed the first bit width;

wherein the fourth bit width and the fifth bit width are between the second bit width and the third bit width, and the fourth bit width is smaller than the fifth bit width; the fourth bit wide or fifth bit wide SIMD instruction adjusts the result of the calculation using the mask of the first bit wide.

8. The method of register allocation according to claim 6, wherein said decoding said instruction resulting in a micro-operation comprises:

If the operation digital width of the SIMD instruction is the third bit width and the data type is not the minimum data type, decoding the SIMD instruction to obtain two micro-operations; the operation digital width of one micro-operation obtained by decoding is a fifth bit width, and the fifth bit width is a second large operation digital width of the SIMD instruction;

The allocating a mask physical register from a mask physical register set for the micro-operation according to the operation digital width of the instruction to meet the mask requirement of the instruction comprises:

allocating a first bit wide mask physical register for said two micro-operations to meet the mask requirement that said SIMD instruction not exceed the first bit wide;

If the target operand of the SIMD instruction is a mask, the method further includes:

And fusing the operation results of the two micro-operations, and writing the fused results into the allocated mask physical register.

9. The method of register allocation according to claim 6, wherein said decoding said instruction resulting in a micro-operation comprises:

If the operation digital width of the SIMD instruction is the third bit width and the data type is the minimum data type, decoding the SIMD instruction to obtain two micro-operations; the operation digital width of one micro-operation obtained by decoding is a fifth bit width, and the fifth bit width is a second large operation digital width of the SIMD instruction;

The allocating a mask physical register from a mask physical register set for the micro-operation according to the operation digital width of the instruction to meet the mask requirement of the instruction comprises:

Each micro-operation is respectively allocated a first bit wide mask physical register to meet the mask requirement of the second bit wide of the SIMD instruction.

10. The register allocation method according to claim 9, wherein the two micro-operations comprise a first micro-operation and a second micro-operation; the allocating a mask physical register with a first bit width for each micro-operation includes:

If the upper bits of the mask of the SIMD instruction are invalid, allocating a mask physical register with a first bit width and an indication bit for the first micro-operation, wherein the indication bit is set to be invalid in the upper bits of the data;

a first bit wide mask physical register is allocated for the second micro-operation and the encoding of the allocated mask physical register is not valid.

11. The register allocation method according to any one of claims 1 to 10, wherein the first bit width has a size of 32 bits; the second bit width is 64 bits; the size of the third bit width is 512 bits; the minimum data type is 8 bits.

12. The register allocation method according to any one of claims 7-10, wherein the fifth bit width is 256 bits, and the fourth bit width between the second bit width and the fifth bit width is 128 bits.

13. A processor comprising a processor, a memory, and a control unit, characterized by comprising the following steps:

An instruction acquisition module for acquiring an instruction, the instruction being associated with a masking operation;

the instruction decoding module is used for decoding the instruction to obtain micro-operation;

An allocation unit, configured to allocate a mask physical register from a mask physical register set for the micro-operation according to an operation digital width of the instruction; wherein the set of mask physical registers includes a plurality of mask physical registers, a register bit width of each mask physical register being fixed to a first bit width;

The first bit width is smaller than the second bit width, the value of the second bit width corresponds to the element number of the SIMD instruction with the third bit width under the minimum data type, and the third bit width is the maximum operation bit width of the SIMD instruction.

14. The processor of claim 13, wherein the instruction is a mask calculation instruction; the masked physical registers allocated for the micro-operations include:

A first bit wide mask physical register and an indication bit, wherein the indication bit is used for indicating whether the high order bits of the data are valid, and the high order bit range of the data is between the first bit wide and the second bit wide;

Or two first bit wide masked physical registers.

15. The processor of claim 14, wherein the allocation unit to allocate the masked physical registers for the micro-operations from a set of masked physical registers according to an operand bit width of the instruction comprises:

And if the operation digital width of the mask calculation instruction is smaller than or equal to the first bit width, allocating a mask physical register with the first bit width and an indication bit for each operand of the mask calculation instruction, wherein the indication bit is set to be invalid in the high order of data.

16. The processor of claim 14, wherein the allocation unit to allocate the masked physical registers for the micro-operations from a set of masked physical registers according to an operand bit width of the instruction comprises:

For allocating two mask physical registers of a first bit width, or one mask physical register of a first bit width and an indication bit for each operand of the mask calculation instruction if the operand bit width of the mask calculation instruction is equal to the second bit width, and the indication bit is set to be high order invalid of data; wherein the second bit width is twice the first bit width;

The mask calculation instruction adopts two sets of mask arithmetic logic units with first bit width to complete the mask calculation instruction with second bit width in the same period.

17. The processor of claim 13, wherein the instruction is a SIMD instruction, and wherein the mask is used to adjust the computation result of the SIMD instruction; the second bit width is twice the first bit width; the masked physical registers allocated for the micro-operations include:

A first bit wide mask physical register;

Or two first bit wide masked physical registers.

18. The processor of claim 17, wherein the allocation unit to allocate the masked physical registers for the micro-operations from a set of masked physical registers according to an operand bit width of the instruction comprises:

for allocating a first bit wide mask physical register for said micro-operation if the operand bit width of said SIMD instruction is either a fourth bit wide or a fifth bit wide to meet the mask requirement that said SIMD instruction does not exceed the first bit wide;

wherein the fourth bit width and the fifth bit width are between the second bit width and the third bit width, and the fourth bit width is smaller than the fifth bit width; the fourth bit wide or fifth bit wide SIMD instruction adjusts the result of the calculation using the mask of the first bit wide.

19. The processor of claim 17, wherein the instruction decode module to decode the instruction to obtain the micro-operation comprises:

If the operation digital width of the SIMD instruction is the third bit width and the data type is not the minimum data type, decoding the SIMD instruction to obtain two micro-operations; the operation digital width of one micro-operation obtained by decoding is a fifth bit width, and the fifth bit width is a second large operation digital width of the SIMD instruction;

The allocation module is configured to allocate, according to the operation digital width of the instruction, a mask physical register from a mask physical register set for the micro-operation, where the allocation module includes:

A mask physical register for allocating a first bit width for said two micro-operations to meet a mask requirement that said SIMD instruction not exceed the first bit width;

And if the target operand of the SIMD instruction is a mask, writing the fused result after the fused operation results of the two micro-operations into an allocated mask physical register.

20. The processor of claim 17, wherein the instruction decode module to decode the instruction to obtain the micro-operation comprises:

The method comprises the steps of decoding the SIMD instruction to obtain two micro-operations if the operation digital width of the SIMD instruction is a third bit width and the data type is the minimum data type; the operation digital width of one micro-operation obtained by decoding is a fifth bit width, and the fifth bit width is a second large operation digital width of the SIMD instruction;

The allocation unit, configured to allocate, according to the operation digital width of the instruction, a mask physical register from a mask physical register set for the micro-operation, where the mask physical register includes:

a first bit wide mask physical register is allocated for each micro-operation to meet the second bit wide mask requirement of the SIMD instruction.

21. A processor according to claim 20, wherein the two micro-operations comprise a first micro-operation and a second micro-operation; the allocation unit, configured to allocate a mask physical register with a first bit width for each micro-operation, includes:

for allocating a first bit wide mask physical register and indication bits for a first micro-operation if the upper bits of the mask of the SIMD instruction are invalid and the indication bits are set to the upper bits of the data are invalid;

a first bit wide mask physical register is allocated for the second micro-operation and the encoding of the allocated mask physical register is not valid.

22. A processor according to any of claims 13-21, wherein the first bit width is 32 bits in size; the second bit width is 64 bits; the third bit width is 64 bits in size, and the minimum data type is 8 bits.

23. A processor according to any of claims 18-21, wherein the fifth bit width is 256 bits and the fourth bit width between the second bit width and the fifth bit width is 128 bits.

24. A processor according to any one of claims 13-23, further comprising:

the instruction issuing module is used for issuing the micro-operation obtained by decoding by the instruction decoding module to the execution unit;

and the execution unit is used for executing the micro-operation.

25. The processor of claim 24, wherein the execution unit comprises a floating point arithmetic unit; the floating point arithmetic unit includes:

the scheduling unit is used for scheduling the micro-operation to an operation unit in the floating point operation unit;

a mask arithmetic logic unit for processing a mask operation of the micro-operation; the data bit width of the mask arithmetic logic unit is the first bit width;

Vector arithmetic logic unit for processing the vector operation of micro-operation; the mask arithmetic logic unit and the vector arithmetic logic unit belong to an arithmetic unit inside a floating point arithmetic unit;

The processor further includes:

A mask physical register for storing mask data of a mask operation; the bit width of the read-write data of the mask physical register is the first bit width;

and the vector physical register is used for storing a source operand and a destination operand of the vector operation.

26. A chip comprising the processor of any one of claims 13-25.

27. An electronic device comprising a processor according to any of claims 13-25, or a chip according to claim 26.