CN118737007A - Display Panel - Google Patents

Abstract

The present application provides a display panel, including a cascaded multi-stage gate driving unit, wherein the Nth stage gate driving unit in the multi-stage gate driving unit includes: a scan signal output terminal; a stage transmission signal output terminal; a first control signal input terminal; a first transistor, one of the source and drain of the first transistor is electrically connected to the stage transmission signal output terminal, and the other is electrically connected to the first clock signal input terminal of the gate driving unit; a second transistor, one of the source and drain of the second transistor is electrically connected to the scan signal output terminal, and the other is electrically connected to the first clock signal input terminal; a third transistor, one of the source and drain of the third transistor is electrically connected to the gate of the first transistor, and the other is electrically connected to the gate of the second transistor, and the gate of the third transistor is electrically connected to the first control signal input terminal; wherein N is a positive integer. The present application can realize differentiated scan control of different display areas in the display panel.

Description

Display Panel

Technical Field

The present application relates to the field of display technology, and in particular to a display panel.

Background Art

In the prior art, a display panel generally uses a gate driving circuit to control a scanning signal of each row of pixels.

Traditional gate drive circuits often use fixed frequency scanning. Although this method is simple, it will cause unnecessary power consumption in some application scenarios. In addition, the gate drive solution with fixed scanning frequency is difficult to meet complex display requirements. For example, it may be necessary to display dynamic content with a high refresh rate and static content with a low refresh rate on the same display panel at the same time, but the existing technology is difficult to achieve such differentiated scanning control on the same panel.

Therefore, there is an urgent need for a new display panel that can achieve differentiated scanning control of different areas, thereby effectively reducing power consumption while ensuring display quality.

Summary of the invention

An embodiment of the present application provides a display panel, aiming to achieve differentiated scanning control of different display areas in the display panel.

An embodiment of the present application provides a display panel, which includes a cascaded multi-stage gate driving unit, and the Nth stage of the multi-stage gate driving unit includes: a scan signal output terminal; a stage transmission signal output terminal; a first control signal input terminal; a first transistor, one of the source and the drain of the first transistor is electrically connected to the stage transmission signal output terminal, and the other of the source and the drain of the first transistor is electrically connected to the first clock signal input terminal of the gate driving unit; a second transistor, one of the source and the drain of the second transistor is electrically connected to the scan signal output terminal, and the other of the source and the drain of the second transistor is electrically connected to the first clock signal input terminal; and a third transistor, one of the source and the drain of the third transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the third transistor is electrically connected to the gate of the second transistor, and the gate of the third transistor is electrically connected to the first control signal input terminal; wherein N is a positive integer.

In the above-mentioned display panel, when the first control signal is a high-level signal, the level transmission signal output terminal is used to output the level transmission signal, and the scanning signal output terminal is used to output the scanning signal; when the first control signal is a low-level signal, the level transmission signal output terminal is used to output the level transmission signal, and the scanning signal output terminal is used not to output the scanning signal.

In the above-mentioned display panel, the multiple frames of images displayed by the display panel include a first frame and a second frame that are continuous in time; during the driving cycle of the first frame, the first control signal is a high-level signal; the driving cycle of the second frame includes a first stage and a second stage located after the first stage, during the first stage, the first control signal is a high-level signal, and during the second stage, the first control signal is a low-level signal, or, during the first stage, the first control signal is a low-level signal, and during the second stage, the first control signal is a high-level signal.

In the above display panel, the starting time of the falling edge of the first control signal is consistent with the starting time of the falling edge of the Kth first clock signal in the driving cycle of the second picture; wherein K is a positive integer.

In the above-mentioned display panel, the display panel includes multiple display areas, the multiple display areas include a first display area and a second display area, the first display area and the second display area are arranged in the same direction as the arrangement direction of the multiple gate driving units; wherein the first control signal is used to control the scanning signal output ends of the multiple gate driving units electrically connected to the pixels in the first display area to output the scanning signal at a first frequency, and to control the scanning signal output ends of the multiple gate driving units electrically connected to the pixels in the second display area to output the scanning signal at a second frequency, and the first frequency is greater than the second frequency.

In the above-mentioned display panel, the gate driving unit also includes: a second control signal input terminal; and a fourth transistor, one of the source and the drain of the fourth transistor is electrically connected to the gate of the second transistor, the other of the source and the drain of the fourth transistor is electrically connected to the low potential signal input terminal of the gate driving unit, and the gate of the fourth transistor is electrically connected to the second control signal input terminal; wherein, when the first control signal input to the first control signal input terminal is a high level signal, the second control signal input to the second control signal input terminal is a low level signal, and when the first control signal is a low level signal, the second control signal is a high level signal.

In the above display panel, the display panel further comprises a control signal generating circuit, and a control signal output terminal of the control signal generating circuit is electrically connected to the first control signal input terminal of each stage of the gate driving unit.

In the above display panel, the gate driving unit further includes: an inverter, the inverter is electrically connected to the first control signal input terminal and the second control signal input terminal, and the inverter is used to generate the second control signal according to the first control signal transmitted by the first control signal input terminal.

In the above-mentioned display panel, the inverter includes a fifth transistor and a sixth transistor, the gate of the fifth transistor is electrically connected to the high potential signal input terminal of the gate driving unit, one of the source and the drain of the fifth transistor is electrically connected to the gate of the fifth transistor, the other of the source and the drain of the fifth transistor is electrically connected to the second control signal input terminal, one of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor, the other of the source and the drain of the sixth transistor is electrically connected to the low potential signal input terminal, and the gate of the sixth transistor is electrically connected to the first control signal input terminal.

In the above-mentioned display panel, the gate driving unit also includes: a seventh transistor, one of the source and the drain of the seventh transistor is electrically connected to the stage transfer signal output terminal, and the other of the source and the drain of the seventh transistor is electrically connected to the low potential signal input terminal; and an eighth transistor, one of the source and the drain of the eighth transistor is electrically connected to the scanning signal output terminal, and the other of the source and the drain of the eighth transistor is electrically connected to the low potential signal input terminal.

The present application realizes independent control of the scan signal output terminal and the level transmission signal output terminal by introducing the first transistor, the second transistor and the third transistor in the gate drive unit, and connecting the gate of the third transistor to the first control signal input terminal, so that the output of the level transmission signal can be separated from the output of the scan signal. This design enables the gate drive unit to selectively output or not output the scan signal according to the level state of the first control signal, thereby realizing differentiated scan control. Even when the scan signal is not output, the level transmission signal can still be output normally, ensuring the continuity and stability of the gate drive circuit. In addition, the present application can maintain a high refresh rate in some areas of the display panel and a low refresh rate in other areas by selectively controlling the gate drive unit to output or not output the scan signal, thereby realizing differentiated refresh rate control of different areas on the same display panel. This differentiated refresh rate control can not only maintain a high refresh rate in the area displaying dynamic content to ensure display quality, but also use a low refresh rate in the area displaying static content to save power consumption.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic diagram of a display device provided in an embodiment of the present application.

FIG. 2 is a schematic diagram of a gate driving unit of a display device provided in an embodiment of the present application.

FIG. 3 is a timing diagram of a gate driving unit of a display device provided in an embodiment of the present application.

FIG. 4 is a schematic diagram of a display method of an image at different refresh frequencies provided by a display device according to an embodiment of the present application.

DETAILED DESCRIPTION

The specific implementation methods of the present application are described in detail below with reference to the accompanying drawings.

The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise clearly defined.

The display device provided by the embodiment of the present application includes an LCD display device, an OLED display device, etc. As shown in FIG1 , the display device includes a display panel, a timing controller TCON, a source driving circuit DataDriver, and a power management chip (not shown in the figure). The power management chip can be integrated with the timing controller TCON into the same chip). The display panel includes a plurality of pixels P, a plurality of scan lines (GL1 to GLn), a plurality of data lines (DL1 to DLm), a gate driving circuit GOA, etc., the plurality of pixels P are arranged in rows and columns, the gate driving circuit GOA is electrically connected to the plurality of scan lines (GL1 to GLn), the source driving circuit DataDriver is electrically connected to the plurality of data lines (DL1 to DLm), the scan lines (GL1 to GLn) and the data lines (DL1 to DLm) are electrically connected to the pixels P, and the timing controller TCON is electrically connected to the gate driving circuit GOA and the source driving circuit DataDriver.

In the case where the display panel is an LCD display panel, the display panel includes a thin film transistor array substrate, an opposing substrate, and a liquid crystal material arranged between the thin film transistor array substrate and the opposing substrate. The thin film transistor array substrate includes a substrate, a gate drive circuit GOA, pixels P, scan lines (GL1~GLn), data lines (DL1~DLm), color resistance, etc. The pixel P includes a thin film transistor, a pixel electrode, etc. The thin film transistor is electrically connected to the pixel electrode, the scan line (GL1~GLn) and the data line (DL1~DLm).

In the case where the display panel is an OLED display panel, the display panel includes a substrate, a pixel P, a gate drive circuit GOA, an organic light-emitting device, an encapsulation layer, a polarizer, a color filter, etc. The substrate may be, for example, a glass substrate, a flexible substrate (for example, a polyimide substrate), etc. The pixel P includes an organic light-emitting device (OLED) and a drive circuit. The drive circuit includes a plurality of thin-film transistors. The organic light-emitting device is electrically connected to the drive circuit. The organic light-emitting device includes a light-emitting layer, an electron transport layer, a hole transport layer, a cathode and an anode, etc. The encapsulation layer includes an organic/inorganic alternating multilayer structure.

The gate driving circuit GOA includes a plurality of cascaded gate driving units. Each gate driving unit is electrically connected to a row of pixels P. The gate driving unit is used to provide a scanning signal to the pixels P.

The source driving circuit DataDriver is used to provide data signals to the pixels P.

The timing controller TCON is used to receive externally input image data, and control the gate driving circuit GOA to output a scanning signal, and control the source driving circuit DataDriver to output a data signal.

The power management chip is used to provide the required operating voltage for each part of the display device.

As shown in FIG. 2 , the display panel in the display device provided in the embodiment of the present application includes a cascaded multi-stage gate driving unit, and the Nth stage gate driving unit in the multi-stage gate driving unit includes:

The scanning signal output terminal OUT is used to output the scanning signal;

The level transmission signal output terminal Carry is used to output the level transmission signal;

A first control signal input terminal SW0, used for receiving a first control signal;

A first clock signal input terminal CK[n], used for receiving a first clock signal;

A first transistor NT15, one of a source or a drain of which is electrically connected to the stage transfer signal output terminal Carry, and the other of which is electrically connected to the first clock signal input terminal CK[n];

A second transistor NT9, one of a source or a drain of which is electrically connected to the scan signal output terminal OUT, and the other of which is electrically connected to the first clock signal input terminal CK[n];

The third transistor NT18 has one of its source or drain electrically connected to the gate of the first transistor NT15, and the other electrically connected to the gate of the second transistor NT9, and its gate is electrically connected to the first control signal input terminal SW0. In other words, one of the source and drain of the third transistor NT18 is electrically connected to the first node Q of the gate driving unit.

Wherein, N is a positive integer.

The first transistor NT15 and the second transistor NT9 are used to control the output of the stage transfer signal and the scan signal respectively. The third transistor NT18 is used as a control switch to control the conduction state of the second transistor NT9 through the control signal received by the first control signal input terminal SW0.

For example, when the first control signal is at a high level, the third transistor NT18 is turned on, so that the gate potential of the second transistor NT9 is increased, thereby allowing the output of the scan signal. Conversely, when the first control signal is at a low level, the third transistor NT18 is turned off, so that the gate potential of the second transistor NT9 is reduced, thereby inhibiting the output of the scan signal.

It should be noted that whether the level transmission signal is output is not controlled by the first control signal, and the output of the level transmission signal is controlled by the potential of the Q point of the gate driving unit.

Through the above technical solution, each level of the gate driving unit can flexibly control the output of the scanning signal according to the state of the first control signal, thereby realizing differentiated scanning control of different areas or different contents of the display panel.

The gate driving unit in the display device provided in the embodiment of the present application presents two different working modes according to the level state of the first control signal:

When the first control signal is a high level signal, the third transistor NT18 is turned on. Since the source and drain of the third transistor NT18 are respectively connected to the gates of the first transistor NT15 and the second transistor NT9, when the potential of the Q point of the gate drive unit is a high potential, the first transistor NT15 and the second transistor NT9 are turned on at the same time. At this time, the level transfer signal output terminal Carry outputs the level transfer signal, and the scan signal output terminal OUT outputs the scan signal. The level transfer signal is transmitted from the first clock signal input terminal CK[n] to the level transfer signal output terminal Carry through the turned-on first transistor NT15. The scan signal is transmitted from the first clock signal input terminal CK[n] to the scan signal output terminal OUT through the turned-on second transistor NT9.

When the first control signal is a low level signal, the third transistor NT18 is turned off. Since the third transistor NT18 is disconnected, the potential of the gate of the second transistor NT9 is no longer consistent with the potential of the Q point of the gate driving unit (approximately equal), causing the second transistor NT9 to be turned off. At this time, the level transfer signal output terminal Carry can still output the level transfer signal, because the output of the level transfer signal is controlled by the potential of the Q point of the gate driving unit, and the scan signal output terminal OUT does not output the scan signal. Since the second transistor NT9 is turned off, the first clock signal cannot be transmitted to the scan signal output terminal OUT, so the scan signal is suppressed from output.

Through the above technical solution, the display panel of the present application can flexibly control the output of the scanning signal according to the state of the first control signal without affecting the normal transmission of the level transfer signal, which is conducive to realizing the differentiated scanning control and low-power operation of the display panel. For example, in an area or time period where the display content does not need to be updated, the output of the scanning signal can be suspended by setting the first control signal to a low level, thereby reducing unnecessary power consumption.

As shown in FIG. 3 , the multiple frames of images displayed by the display panel include a first frame of image and a second frame of image that are continuous in time.

During the driving cycle of the first picture, the first control signal remains a high level signal. At this time, the level transfer signal output terminal Carry outputs the level transfer signal, and the scanning signal output terminal OUT outputs the scanning signal. This means that during the display process of the entire first picture, the display panel maintains normal scanning and driving to ensure the complete display of the picture.

The driving cycle of the second picture includes a first stage and a second stage located after the first stage, in which the first control signal is a high level signal, and in the second stage, the first control signal is a low level signal. Alternatively, in the first stage, the first control signal is a low level signal, and in the second stage, the first control signal is a high level signal.

For example, the driving cycle of the second screen is divided into two stages:

The first stage: the first control signal is a high-level signal. The working state of this stage is the same as the driving cycle of the first screen. The level transfer signal and the scanning signal are output normally. This stage is used to update the changed part of the second screen.

The second stage: the first control signal is converted to a low level signal. At this time, the level transmission signal output terminal Carry still outputs the level transmission signal, but the scanning signal output terminal OUT does not output the scanning signal. This stage is used to maintain the unchanged part of the second picture without continuing the scanning drive.

The above technical solution can dynamically adjust the driving strategy based on the actual display content requirements. When the content of two frames is similar or some areas have not changed, the scanning of these unchanged areas can be stopped in a part of the second frame, thereby achieving the purpose of reducing power consumption.

For example, if only a local area of the second screen changes, then after the update of these changed areas is completed in the first stage, the remaining second stage can stop the output of the scanning signal by lowering the level of the first control signal, which not only ensures the timeliness of the screen update, but also avoids unnecessary refresh of static content, thereby achieving low power consumption operation of the display panel.

The duration of the first stage and the second stage in the second picture driving cycle can be flexibly adjusted according to the degree of change of the actual display content. Specifically, it can be adjusted by controlling the signal generating circuit to further optimize power consumption.

The embodiment of the present application further optimizes the switching timing of the first control signal so that it is precisely synchronized with the first clock signal CK, thereby achieving more accurate drive control. Specifically:

The falling edge start time of the first control signal is consistent with the falling edge start time of the Kth first clock signal CK in the second picture driving cycle. Here K is a positive integer representing the number of first clock signals counted from the second picture driving cycle.

Through the above-mentioned synchronization design, it can be ensured that the state switching of the first control signal occurs at the falling edge of the first clock signal CK, which is usually the most stable moment in the digital circuit. It can effectively avoid glitches or abnormalities caused by asynchronous signal switching, and by selecting an appropriate K value, the duration of the first stage and the second stage in the second screen drive cycle can be accurately controlled, thereby achieving fine adjustment of scanning control (refresh frequency control) and power consumption control.

In specific implementation, the K value can be set according to the actual requirements of the display panel:

If the K value is small, it means that the first control signal switches to a low level earlier, which will result in a shorter first stage of the second picture driving cycle, which is suitable for the case where only a small amount of content needs to be updated on the picture.

If the K value is larger, the first control signal switches to a low level later, so that the first stage of the second picture driving cycle is longer, which is suitable for the situation where the picture needs more content update.

For example: Assume that the driving cycle of a display panel includes 100 clock cycles. If K=30 is set, it means that: in the first 30 clock cycles of the second picture driving cycle, the first control signal maintains a high level, and the gate driving unit outputs the scanning signal normally. Starting from the falling edge of the 30th first clock signal, the first control signal SW0 switches to a low level, and the gate driving unit stops outputting the scanning signal and enters a low power consumption mode.

By dynamically adjusting the K value, the display panel can find the optimal balance between display quality and power consumption according to the needs of different scenarios.

In practical applications, the optimal K value can be dynamically calculated through image analysis algorithms to achieve adaptive scanning control.

The display panel in the display device provided in the embodiment of the present application includes a plurality of display areas, and these display areas include at least a first display area and a second display area. The first display area and the second display area are arranged in sequence along the arrangement direction of the gate drive unit. Among them, the first display area adopts high-frequency refresh, and the second display area adopts low-frequency refresh, and the frequency of the high-frequency refresh is higher than the frequency of the low-frequency refresh, and vice versa. The first display area is used to display content that requires a high refresh rate, and the second display area is used to display content that allows a low refresh rate, thereby achieving the purpose of reducing overall power consumption.

The first display area is used to display dynamic content (such as videos, animations, etc.), so a higher refresh rate is required to ensure smooth images; while the second display area is used to display static content (such as text, icons, etc.), and a lower refresh rate is required to meet display requirements. This design enables the display panel to achieve differentiated driving of different areas, thereby meeting the needs of different application scenarios.

Each display area has a corresponding gate drive unit group, and each of these gate drive units includes a scan signal output terminal OUT, a level transfer signal output terminal Carry, and the like.

The first control signal is used to realize differentiated scanning control of different display areas of the display panel:

For the first display area, the first control signal controls the gate drive unit electrically connected to the pixels in the first display area, so that its scan signal output terminal OUT outputs a scan signal at a first frequency f1. For the second display area, the first control signal controls the gate drive unit electrically connected to the pixels in the second display area, so that its scan signal output terminal OUT outputs a scan signal at a second frequency f2. The first frequency f1 is greater than the second frequency f2. The specific values of the first frequency f1 and the second frequency f2 can be optimized and set according to the actual application scenario of the display panel. For example, as shown in Figure 4, in some applications, f1 can be set to 60Hz and f2 can be set to 30Hz, or f1 can be set to 120Hz and f2 can be set to 60Hz.

Through the above technical solution, the most suitable refresh frequency can be implemented in areas with different content types, thereby improving the overall display effect, and a lower refresh frequency can be used for areas that do not require high-frequency refresh, thereby significantly reducing power consumption.

The gate driving unit of this embodiment further includes a second control signal input terminal SW1 and a fourth transistor NT19. The second control signal input terminal SW1 is used to input a second control signal.

One of the sources or drains of the fourth transistor NT19 is electrically connected to the gate of the second transistor NT9, the other of the sources or drains of the fourth transistor NT19 is electrically connected to the low potential signal input terminal VGL of the gate driving unit, and the gate of the fourth transistor NT19 is electrically connected to the second control signal input terminal SW1.

The second control signal is used to pull down the voltage of the gate of the second transistor through the fourth transistor when the third transistor NT18 is turned off, so that the second transistor remains turned off, preventing the gate of the second transistor from being stretched due to the coupling effect of the first clock signal input terminal, thereby preventing the scanning signal output terminal from outputting a scanning signal when it should not output a scanning signal.

That is, the second control signal is used to control the conduction state of the fourth transistor NT19 to prevent the scan signal output terminal OUT from being in a floating state.

The gate potential of the second transistor NT9 is controlled by the switching state of the fourth transistor NT19, thereby achieving precise control of the output of the scanning signal.

In this embodiment, when the first control signal is at a high level, the second control signal is at a low level; when the first control signal is at a low level, the second control signal is at a high level.

Specifically, when the scan signal needs to be output, the first control signal is high level, the second control signal is low level, the third transistor NT18 is turned on, and the fourth transistor NT19 is turned off, and the gate of the second transistor NT9 is pulled high, allowing the scan signal to be output.

When the scan signal does not need to be output, the first control signal is low level, the second control signal is high level, the third transistor NT18 is turned off, and the fourth transistor NT19 is turned on, and the gate of the second transistor NT9 is pulled down to the VGL potential to ensure that the scan signal is not output.

In the above technical solution, the dual control mechanism effectively prevents erroneous operation caused by abnormal single control signal. The anti-interference ability of the circuit is enhanced. Even if the gate of the second transistor NT9 is coupled by the first clock signal inputted by the first clock signal input terminal, it can ensure that when the scanning signal does not need to be outputted, the potential of the gate of the second transistor NT9 is low potential, further reducing the leakage current, thereby reducing static power consumption.

The display device of this embodiment further comprises a control signal generating circuit, wherein the control signal generating circuit is provided with a control signal output terminal, and the control signal output terminal is electrically connected to the first control signal input terminal of each stage of the gate driving unit in the display panel.

The control signal generating circuit is used to generate and output a first control signal, and the first control signal is used to uniformly control whether all gate driving units output scanning signals. Specifically, the control signal generating circuit is used to simultaneously transmit the first control signal to the first control signal input terminal of each level of gate driving unit through the control signal output terminal. After receiving the first control signal, the gate driving units at each level control the scanning signal output terminal to output or not output the scanning signal according to the high and low level states of the first control signal.

Since all gate driving units receive the same control signal, it is possible to ensure that the working states of the gate driving units are highly synchronized, thereby reducing potential timing deviations.

The control signal generating circuit may be, for example, a digital logic circuit, a microcontroller or an application specific integrated circuit (ASIC), etc. The control signal generating circuit may be, for example, a timing control circuit, and the control signal generating circuit may also be integrated in the timing control circuit.

The gate driving unit of this embodiment further includes an inverter. The inverter is electrically connected to the first control signal input terminal and the second control signal input terminal SW1. The inverter is used to generate a second control signal inverted to the first control signal according to the first control signal transmitted by the first control signal input terminal.

When the first control signal is at a high level, the inverter outputs a second control signal at a low level. When the first control signal is at a low level, the inverter outputs a second control signal at a high level.

With the built-in inverter, the gate drive unit can generate the required complementary control signal without external circuits, reducing the complexity of the overall circuit. In addition, since the second control signal is directly generated from the first control signal, the timing relationship between the two is more precise, reducing possible signal delays or asynchronous problems. The inverter can ensure that the first control signal and the second control signal always remain complementary, which helps to accurately control the working state of the gate drive unit and further optimize power consumption.

The inverter of this embodiment includes a fifth transistor NT22 and a sixth transistor NT23.

The gate of the fifth transistor NT22 is electrically connected to the high potential signal input terminal VGH of the gate driving unit, and one of the source or drain of the fifth transistor NT22 is electrically connected to the gate of the fifth transistor NT22.

The other of the source and the drain of the fifth transistor NT22 is electrically connected to the second control signal input terminal SW1 for outputting the second control signal SW1.

One of the source or drain of the sixth transistor NT23 is electrically connected to the other of the source or drain of the fifth transistor NT22 (i.e., the second control signal input terminal SW1), the other of the source or drain of the sixth transistor NT23 is electrically connected to the low potential signal input terminal VGL, and the gate of the sixth transistor NT23 is electrically connected to the first control signal input terminal for receiving the first control signal.

The working principle of the inverter is as follows:

When the first control signal is at a high level, the sixth transistor NT23 is turned on, and the second control signal input terminal SW1 is pulled down to the VGL level. At this time, the second control signal is at a low level. When the first control signal is at a low level, the sixth transistor NT23 is turned off, and the fifth transistor NT22 is turned on under the action of the high potential signal of the high potential signal input terminal VGH, and the second control signal input terminal SW1 is pulled up to a high level. At this time, the second control signal SW1 is at a high level.

Through the combination of two transistors, a fast and reliable signal inversion function is achieved.

The gate driving unit of this embodiment further includes a seventh transistor NT16 and an eighth transistor NT10.

One of the source or drain of the seventh transistor NT16 is electrically connected to the level transfer signal output terminal Carry, and the other of the source or drain of the seventh transistor NT16 is electrically connected to the low potential signal input terminal VGL. The seventh transistor NT16 is used to control the output of the level transfer signal. When the seventh transistor NT16 is turned on, the level transfer signal output Carry terminal can be pulled down to a low level, effectively suppressing the unnecessary level transfer signal output.

One of the source or drain of the eighth transistor NT10 is electrically connected to the scan signal output terminal OUT, and the other of the source or drain of the eighth transistor NT10 is electrically connected to the low potential signal input terminal VGL. The eighth transistor NT10 is used to control the output of the scan signal. When the eighth transistor NT10 is turned on, the scan signal output terminal OUT can be pulled down to a low level to ensure that the scan signal remains at a low level during the non-scanning period.

Through the functions of the seventh transistor NT16 and the eighth transistor NT10, the level transfer signal and the scan signal can be effectively prevented from being in a floating state during a non-working period.

The gate driving unit in the display panel of this embodiment also includes a ninth transistor NT11, a tenth transistor NT12, an eleventh transistor NT17, a twelfth transistor NT20, a thirteenth transistor NT13, a fourteenth transistor NT1, a fifteenth transistor NT7, a sixteenth transistor NT3, a seventeenth transistor NT4, an eighteenth transistor NT14, a nineteenth transistor NT8, a twentieth transistor NT2, a twenty-first transistor NT6, a twenty-second transistor NT21, a twenty-third transistor NT5, a first capacitor C1, a second capacitor C2 and a third capacitor C3.

The gate of the ninth transistor NT11 is electrically connected to one of the source and drain of the ninth transistor NT11, the other of the source and drain of the ninth transistor NT11 is electrically connected to the stage transfer signal output terminal Carry, and the gate of the ninth transistor NT11 is electrically connected to the first all-row switching signal (Gate All Switch) input terminal GAS1.

The gate of the tenth transistor NT12 is electrically connected to the gate of the ninth transistor NT11, one of the source and the drain of the tenth transistor NT12 is electrically connected to the low potential signal input terminal VGL, and the other of the source and the drain of the tenth transistor NT12 is electrically connected to the gate of the seventh transistor NT16.

The gate of the eleventh transistor NT17 is electrically connected to one of the source and the drain of the eleventh transistor NT17 , and the other of the source and the drain of the eleventh transistor NT17 is electrically connected to the scan signal output terminal OUT.

The gate of the twelfth transistor NT20 is electrically connected to the gate of the eleventh transistor NT17, one of the source and the drain of the twelfth transistor NT20 is electrically connected to the low potential signal input terminal VGL, one of the source and the drain of the twelfth transistor NT20 is electrically connected to the gate of the eighth transistor NT10, and one of the source and the drain of the twelfth transistor NT20 is electrically connected to the gate of the seventh transistor NT16.

One of the source and drain of the thirteenth transistor NT13 is electrically connected to the low potential signal input terminal VGL, the other of the source and drain of the thirteenth transistor NT13 is electrically connected to the scan signal output terminal OUT, and the gate of the thirteenth transistor NT13 is electrically connected to the second all-row switching signal (Gate All Switch) input terminal GAS2.

The gate of the fourteenth transistor NT1 is electrically connected to the start signal input terminal STV of the gate driving unit, one of the source and the drain of the fourteenth transistor NT1 is electrically connected to the forward scanning control signal input terminal U2D, and the other of the source and the drain of the fourteenth transistor NT1 is electrically connected to the first node Q of the gate driving unit.

The gate of the fifteenth transistor NT7 is electrically connected to the high level signal input terminal VGH of the gate driving unit, one of the source and drain of the fifteenth transistor NT7 is electrically connected to the first node Q, and the other of the source and drain of the fifteenth transistor NT7 is electrically connected to the gate of the first transistor NT15. The fifteenth transistor NT7 is used to ensure that each first clock signal can be given to the stage transmission signal output terminal Carry when the first node Q is at a high potential.

The gate of the sixteenth transistor NT3 is electrically connected to the forward scanning control signal input terminal U2D, and one of the source and the drain of the sixteenth transistor NT3 is electrically connected to the second clock signal input terminal CK[n+2].

The gate of the seventeenth transistor NT4 is electrically connected to the reverse scan control signal input terminal D2U, one of the source and the drain of the seventeenth transistor NT4 is electrically connected to the third clock signal input terminal CK[n-2], and the other of the source and the drain of the seventeenth transistor NT4 is electrically connected to the other of the source and the drain of the sixteenth transistor NT3.

The gate of the eighteenth transistor NT14 is electrically connected to the first all-row switching signal input terminal GAS1.

One of the source and the drain of the eighteenth transistor NT14 is electrically connected to the other of the source and the drain of the sixteenth transistor NT3 .

A first plate of the first capacitor C1 is electrically connected to the first node Q, and a second plate of the first capacitor is electrically connected to the other of the source and the drain of the eighteenth transistor NT14.

The gate of the nineteenth transistor NT8 is electrically connected to the other of the source and drain of the sixteenth transistor NT3, one of the source and drain of the nineteenth transistor NT8 is electrically connected to the high potential signal input terminal VGH, and the other of the source and drain of the nineteenth transistor NT8 is electrically connected to the gate of the seventh transistor NT16.

The gate of the twentieth transistor NT2 is electrically connected to the scan signal output terminal G[N+2] of the N+2th gate driving unit, and one of the source and the drain of the twentieth transistor NT2 is electrically connected to the reverse scan control signal input terminal D2U.

The gate of the twenty-first transistor NT6 is electrically connected to the other of the source and drain of the twentieth transistor NT2, one of the source and drain of the twenty-first transistor NT6 is electrically connected to the low potential signal input terminal VGL, and the other of the source and drain of the twenty-first transistor NT6 is electrically connected to the gate of the seventh transistor NT16.

The gate of the twenty-second transistor NT21 is electrically connected to the reset signal input terminal Reset of the gate driving unit, one of the source and the drain of the twenty-second transistor NT21 is electrically connected to the gate of the twenty-second transistor NT21, and the other of the source and the drain of the twenty-second transistor NT21 is electrically connected to the gate of the seventh transistor NT16.

The gate of the twenty-third transistor NT5 is electrically connected to the gate of the seventh transistor NT16, one of the source and the drain of the twenty-third transistor NT5 is electrically connected to the low potential signal input terminal VGL, and the other of the source and the drain of the twenty-third transistor NT5 is electrically connected to the first node Q.

The first plate of the second capacitor C2 is electrically connected to the low potential signal input terminal VGL, and the second plate of the second capacitor C2 is electrically connected to the gate of the seventh transistor NT16.

A first plate of the third capacitor C3 is electrically connected to the gate of the first transistor NT15, and a second plate of the third capacitor C3 is electrically connected to the stage transfer signal output terminal Carry.

The transistors in this embodiment are all N-type thin film transistors (TFTs). Of course, these transistors can also be P-type thin film transistors.

The present application realizes independent control of the scan signal output terminal and the level transmission signal output terminal by introducing the first transistor, the second transistor and the third transistor in the gate drive unit, and connecting the gate of the third transistor to the first control signal input terminal, so that the output of the level transmission signal can be separated from the output of the scan signal. This design enables the gate drive unit to selectively output or not output the scan signal according to the level state of the first control signal, thereby realizing differentiated scan control. Even when the scan signal is not output, the level transmission signal can still be output normally, ensuring the continuity and stability of the gate drive circuit. In addition, the present application can maintain a high refresh rate in some areas of the display panel and a low refresh rate in other areas by selectively controlling the gate drive unit to output or not output the scan signal, thereby realizing differentiated refresh rate control of different areas on the same display panel. This differentiated refresh rate control can not only maintain a high refresh rate in the area displaying dynamic content to ensure display quality, but also use a low refresh rate in the area displaying static content to save power consumption.

The embodiment of the present application provides a technical solution for realizing the zoned frequency display of the display panel. The gate drive unit of the display panel adopts a design in which the scanning signal output terminal is separated from the level transmission signal output terminal, so that the scanning signal can be output or not output by a switch while the level transmission signal is normally output. The transistors NT15 and NT16 newly added to the gate drive unit of the present application serve as replicas of NT9 and NT10, and can generate a level transmission signal with the same potential as the scanning signal, thereby realizing the separation of the scanning signal from the level transmission signal. Whether the scanning signal is output is controlled by controlling the transistors NT18 and NT19 of the present application, so as to achieve the purpose of outputting a multi-frequency signal, and effectively reduce the overall power consumption of the display panel.

The gate drive unit of the display panel of the present application uses an inverter to generate an inverted second control signal from a first control signal. As shown in Figure 2, the gate drive unit controls whether the transistor NT9 outputs a scan signal through the first control signal. When the first control signal is a low-potential signal, the potential of point N is susceptible to the influence of the first clock signal CK, etc. At this time, the gate potential of the transistor NT19 is a high potential, which can pull the potential of point N down to VGL, thereby eliminating the influence of point N on the output of the scan signal by the transistor NT9. Since the inverted signal generated according to the first control signal, that is, the second control signal, has a higher time accuracy and a smaller reverse delay, it can accurately control whether the specified row in each frame is output, so it can not only prevent the transistor NT9 from erroneously outputting the scan signal, but also accurately control the multi-frequency drive output, while reducing an external signal input port.

As shown in FIG3 , in the first frame, the first control signal maintains a high potential to ensure that each row can be output normally. In the second frame, the first control signal is consistent with the falling edge of the first clock signal CK1, thereby controlling all rows after row G[2] not to be output. This design achieves the characteristic that the refresh frequency of the first two rows within two frames is higher than that of the following rows, and has a higher time accuracy while realizing multi-frequency drive, reducing the error of the output scanning signal.

The above is a detailed introduction to the embodiments of the present application. The contents of this specification should not be construed as limiting the scope of protection of the present application.

Claims (10)

1. A display panel comprising cascaded multi-stage gate driving units, an nth stage of the multi-stage gate driving units comprising:

A scanning signal output terminal;

A stage signaling output;

a first control signal input;

A first transistor, one of a source and a drain of the first transistor being electrically connected to the stage signal output terminal, the other of the source and the drain of the first transistor being electrically connected to a first clock signal input terminal of the gate driving unit;

A second transistor having one of a source and a drain electrically connected to the scan signal output terminal, and the other of the source and the drain electrically connected to the first clock signal input terminal; and

A third transistor, one of a source and a drain of the third transistor is electrically connected to the gate of the first transistor, the other of the source and the drain of the third transistor is electrically connected to the gate of the second transistor, and the gate of the third transistor is electrically connected to the first control signal input terminal;

wherein N is a positive integer.

2. The display panel according to claim 1, wherein the stage signal output terminal is configured to output a stage signal and the scan signal output terminal is configured to output a scan signal when the first control signal is a high level signal;

When the first control signal is a low level signal, the stage signal output end is used for outputting a stage signal, and the scanning signal output end is used for not outputting a scanning signal.

3. The display panel according to claim 2, wherein the multi-frame pictures displayed by the display panel include a first frame and a second frame that are consecutive in time;

in the driving period of the first picture, the first control signal is a high level signal;

The driving period of the second picture includes a first phase in which the first control signal is a high level signal, and a second phase after the first phase in which the first control signal is a low level signal, or in which the first control signal is a low level signal, and in which the first control signal is a high level signal.

4. A display panel according to claim 3, wherein the start time of the falling edge of the first control signal coincides with the start time of the falling edge of the kth first clock signal in the drive cycle of the second picture;

Wherein K is a positive integer.

5. The display panel according to claim 1, wherein the display panel includes a plurality of display regions including a first display region and a second display region, the first display region and the second display region being arranged in the same direction as an arrangement direction of the plurality of gate driving units;

the first control signal is used for controlling the scanning signal output ends of the plurality of gate driving units electrically connected to the pixels in the first display area to output the scanning signal at a first frequency, and controlling the scanning signal output ends of the plurality of gate driving units electrically connected to the pixels in the second display area to output the scanning signal at a second frequency, wherein the first frequency is larger than the second frequency.

6. The display panel according to claim 1, wherein the gate driving unit further comprises:

a second control signal input; and

A fourth transistor, one of a source and a drain of which is electrically connected to the gate of the second transistor, the other of the source and the drain of which is electrically connected to the low potential signal input terminal of the gate driving unit, and the gate of which is electrically connected to the second control signal input terminal;

When the first control signal input by the first control signal input end is a high-level signal, the second control signal input by the second control signal input end is a low-level signal, and when the first control signal is a low-level signal, the second control signal is a high-level signal.

7. The display panel according to claim 6, further comprising a control signal generation circuit, a control signal output of the control signal generation circuit being electrically connected to the first control signal input of the gate driving unit of each stage.

8. The display panel of claim 7, wherein the gate driving unit further comprises:

The inverter is electrically connected with the first control signal input end and the second control signal input end, and the inverter is used for generating the second control signal according to the first control signal transmitted by the first control signal input end.

9. The display panel according to claim 8, wherein the inverter includes a fifth transistor and a sixth transistor, wherein a gate of the fifth transistor is electrically connected to the high potential signal input terminal of the gate driving unit, one of a source and a drain of the fifth transistor is electrically connected to the gate of the fifth transistor, the other of the source and the drain of the fifth transistor is electrically connected to the second control signal input terminal, one of the source and the drain of the sixth transistor is electrically connected to the other of the source and the drain of the fifth transistor, the other of the source and the drain of the sixth transistor is electrically connected to the low potential signal input terminal, and the gate of the sixth transistor is electrically connected to the first control signal input terminal.

10. The display panel according to claim 1, wherein the gate driving unit further comprises:

A seventh transistor having one of a source and a drain electrically connected to the stage signal output terminal, and the other of the source and the drain electrically connected to the low potential signal input terminal; and

And an eighth transistor having one of a source and a drain electrically connected to the scan signal output terminal and the other of the source and the drain electrically connected to the low potential signal input terminal.