CN118660246B - Oversampling method, device, electronic device and computer-readable storage medium - Google Patents
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Abstract
本发明公开了一种过采样方法、装置、电子设备及计算机可读存储介质，应用于光网络测试技术领域，过采样方法包括：根据对应于当前时钟周期的目标相位偏移参数，对对应于当前时钟周期的实时并行过采样数据组进行滑动框选获得实时框选数据组；对实时框选数据组进行数据抽取获得对应于当前时钟周期的有效采样数据组；目标相位偏移参数基于对应于第一滤波周期的第一目标相位与对应于第二滤波周期的第二目标相位对比获得，第一滤波周期与第二滤波周期连续且不重合，任一滤波周期包括预设数量个时钟周期。本发明中的过采样方法能实现有效地滤除数据抖动并持续跟踪相位偏移，使待提取的并行数据相位对齐，保证采样数据提取的正确性。
The present invention discloses an oversampling method, device, electronic device and computer-readable storage medium, which are applied to the field of optical network testing technology. The oversampling method includes: according to the target phase offset parameter corresponding to the current clock cycle, sliding frame selection is performed on the real-time parallel oversampling data group corresponding to the current clock cycle to obtain the real-time frame selection data group; data extraction is performed on the real-time frame selection data group to obtain the effective sampling data group corresponding to the current clock cycle; the target phase offset parameter is obtained based on the first target phase corresponding to the first filtering cycle and the second target phase corresponding to the second filtering cycle. The first filtering cycle and the second filtering cycle are continuous and do not overlap, and any filtering cycle includes a preset number of clock cycles. The oversampling method in the present invention can effectively filter out data jitter and continuously track phase offset, so that the phases of the parallel data to be extracted are aligned, and the correctness of the sampling data extraction is ensured.
Description
Technical Field
The present invention relates to the field of optical network testing technologies, and in particular, to an oversampling method, an oversampling device, an electronic device, and a computer readable storage medium.
Background
The passive optical network (Passive Optical Network, PON) is a pure medium network, which avoids electromagnetic interference and lightning influence of external devices, reduces failure rate of lines and external devices, improves system reliability, and saves maintenance cost.
The error code analysis technology, especially the burst error code analysis technology, is a very useful technical means, and through the error code analysis, we can effectively understand various errors occurring in data transmission, and is generally used in the field of PON module error code testing. One of the most challenging components in a PON environment is BCDR (fast clock extraction) operating on burst signals of 2.48832Gb/s and 1.24416 Gb/s. Likewise, BCDR of burst data of 2.48832Gb/s and 1.24416Gb/s is a difficult problem in the field of PON module error code test instrument. The high-speed transceiver (10 Gb/s) is adopted to oversample low-rate data (such as 2.48832Gb/s and 1.24416 Gb/s), the received data can have multiple bit numbers, and jitter and phase shift can occur to the received data along with the change of optical power, so that the oversampled data have errors.
Therefore, the over-sampling method in the error code test of the current PON module has the technical problem that jitter and phase offset cannot be handled, so that the over-sampling result is inaccurate.
Disclosure of Invention
Accordingly, an object of the present invention is to provide an oversampling method, an apparatus, an electronic device, and a computer readable storage medium, which solve the technical problem of inaccurate oversampling in the prior art.
In order to solve the above technical problems, the present invention provides an oversampling method, including:
acquiring a real-time parallel oversampling data set based on the oversampling data set acquired in the current clock cycle;
Performing sliding frame selection on the real-time parallel oversampling data set corresponding to the current clock cycle according to a pre-obtained target phase offset parameter corresponding to the current clock cycle to obtain a real-time frame selection data set;
performing data extraction on the real-time frame selection data set to obtain an effective sampling data set corresponding to the current clock period;
The target phase offset parameter is obtained based on a comparison of a first target phase corresponding to a first filtering period and a second target phase corresponding to a second filtering period, wherein the first filtering period is continuous and not coincident with the second filtering period, and any filtering period comprises a preset number of clock periods.
Optionally, the first filtering period is a filtering period before the current filtering period, and the second filtering period is a filtering period before the first filtering period; before the obtaining the target phase offset parameter corresponding to the current clock cycle according to the pre-obtained target phase offset parameter, the method further comprises obtaining the target phase offset parameter based on the first target phase and the second target phase contrast, including:
performing signal edge variation detection on any data block group included in any clock cycle in the first filtering cycle to obtain a corresponding edge variation detection result, and obtaining a clock cycle phase corresponding to a corresponding clock cycle based on all the edge variation detection results in any clock cycle;
Taking the clock cycle phase with the largest number in the first filtering cycle as the first target phase;
and comparing the first target phase with the second target phase which is determined in advance to determine the target phase offset parameter.
Optionally, performing signal edge variation detection on any data block group included in any clock cycle in the first filtering cycle to obtain a corresponding edge variation detection result, and obtaining a clock cycle phase corresponding to the corresponding clock cycle based on all edge variation detection results in any clock cycle, where the signal edge variation detection includes:
Judging whether rising edge phases exist in all edge change detection results of any clock period or not;
If yes, the rising edge phase is taken as the corresponding clock cycle phase.
Optionally, performing signal edge variation detection on any one of the data block groups included in any one of the clock cycles in the first filtering cycle to obtain a corresponding edge variation detection result, and obtaining a clock cycle phase corresponding to the corresponding clock cycle based on all the edge variation detection results in any one of the clock cycles, further including:
If not, judging whether falling edge phases exist in all edge change detection results of any clock period;
If yes, taking the phase of the last clock cycle as the phase of the clock cycle;
if not, taking the preset phase as the clock cycle phase.
Optionally, the step of taking the rising edge phase as the corresponding clock cycle phase includes:
The first non-0 rising edge phase of all the data block groups arranged from the upper bits to the lower bits is taken as the clock cycle phase of the corresponding clock cycle.
Optionally, the target phase offset parameter includes a slip offset direction and a slip offset amount;
The comparing the first target phase with the second target phase determined in advance to determine the target phase offset parameter includes:
Acquiring the second target phase;
comparing the first target phase with the second target phase, and determining the sliding offset direction according to a comparison result;
an absolute value of a difference between the first target phase and the second target phase is determined as the slip offset.
Optionally, the comparing the magnitudes of the first target phase and the second target phase, and determining the sliding offset direction according to the comparison result includes:
When the first target phase is equal to the second target phase, the first target phase is not shifted from the second target phase;
When the first target phase is greater than the second target phase, determining that the sliding offset direction is right-shifted; wherein the first target phase is not a phase maximum and the second target phase is not a phase minimum; or, the first target phase is not the phase minimum and the second target phase is not the phase maximum;
When the first target phase is smaller than the second target phase, determining that the sliding offset direction is left-shifted; wherein the first target phase is not a phase maximum and the second target phase is not a phase minimum; or, the first target phase is not the phase minimum and the second target phase is not the phase maximum;
When the first target phase is the maximum phase value and the second target phase is the minimum phase value, determining that the sliding offset direction is left-shifted;
and when the first target phase is the phase minimum value and the second target phase is the phase maximum value, determining that the sliding offset direction is right-shifted.
Optionally, before the obtaining, according to the target phase offset parameter corresponding to the current clock cycle, the method further includes obtaining a sliding frame selection start signal corresponding to the first filtering cycle, and performing sliding frame selection on the real-time parallel oversampled data set corresponding to the current clock cycle to obtain a real-time frame selection data set, including:
Judging whether the sliding frame selection starting signal is a target signal value or not;
If yes, acquiring an initial frame selection position;
Sliding according to the target phase shift parameter based on the initial frame selection position to obtain a target frame selection position;
And framing in the parallel oversampled data according to the target framing position to obtain the real-time framing data set.
Optionally, before obtaining the real-time parallel oversampled data set based on the oversampled data set acquired in the current clock cycle, the method further comprises:
and when the first filtering period is formed by a preset number of clock periods, updating the sliding frame selection starting signal corresponding to the first filtering period to the target signal value.
The invention also provides an oversampling apparatus comprising:
The data set determining module is used for obtaining real-time parallel oversampling data sets based on the oversampling data sets acquired in the current clock cycle;
the real-time frame selection data set determining module is used for carrying out sliding frame selection on the real-time parallel oversampling data set corresponding to the current clock cycle according to a pre-obtained target phase offset parameter corresponding to the current clock cycle to obtain a real-time frame selection data set;
The effective sampling data set determining module is used for extracting data from the real-time frame selection data set to obtain an effective sampling data set corresponding to the current clock period;
The target phase offset parameter is obtained based on a comparison of a first target phase corresponding to a first filtering period and a second target phase corresponding to a second filtering period, wherein the first filtering period is continuous and not coincident with the second filtering period, and any filtering period comprises a preset number of clock periods.
The invention also provides an electronic device, comprising:
A memory for storing a computer program;
a processor for implementing the steps of the oversampling method as described above when executing the computer program.
The invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor implements the steps of the oversampling method as described above.
It can be seen that the present invention obtains a real-time parallel oversampled data set by the oversampled data set acquired based on the current clock cycle; according to a target phase offset parameter corresponding to the current clock cycle, sliding frame selection is carried out on a real-time parallel oversampling data set corresponding to the current clock cycle to obtain a real-time frame selection data set; performing data extraction on the real-time frame selection data set to obtain an effective sampling data set corresponding to the current clock cycle; the target phase offset parameter is obtained based on a comparison of a first target phase corresponding to a first filtering period and a second target phase corresponding to a second filtering period, wherein the first filtering period is continuous and not coincident with the second filtering period, and any filtering period comprises a preset number of clock periods. The beneficial effects of the invention are as follows: according to the invention, the target phase shift parameter is obtained by comparing the first target phase corresponding to the first filtering period with the second target phase corresponding to the second filtering period, so that the phase shift is tracked in real time, the response speed of data phase tracking is improved, and the accuracy of sampling data extraction is improved.
In addition, the invention also provides an oversampling device, electronic equipment and a computer readable storage medium, which also have the beneficial effects.
Drawings
In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are required to be used in the embodiments or the description of the prior art will be briefly described below, and it is obvious that the drawings in the following description are only embodiments of the present invention, and that other drawings can be obtained according to the provided drawings without inventive effort for a person skilled in the art.
FIG. 1 is a flow chart of an oversampling method according to an embodiment of the present invention;
FIG. 2 is a flowchart illustrating an oversampling method according to an embodiment of the present invention;
FIG. 3 is a diagram illustrating an exemplary architecture of an oversampling method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of jitter and phase offset according to an embodiment of the present invention;
fig. 5 is a schematic structural diagram of an oversampling apparatus according to an embodiment of the present invention;
fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention.
Detailed Description
For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.
Referring to fig. 1, fig. 1 is a flowchart of an oversampling method according to an embodiment of the present invention. The method may include:
s101, acquiring a real-time parallel oversampling data set based on the oversampling data set acquired in the current clock cycle.
The execution body of this embodiment is an electronic device, which may be a test device, such as an error analyzer, in particular, such as a burst error analyzer. Obtaining the real-time parallel oversampled data set based on the oversampled data set acquired in the current clock cycle in this embodiment may refer to combining the sampled data based on the current clock cycle and the sampled data of the preset number of clock cycles closest to the current clock cycle into the real-time parallel oversampled data set. The embodiment is not limited to a specific number of data bits of the real-time parallel oversampled data set, and may be, for example, 64 bits, 96 bits, etc.
It should be further noted that, in order to improve accuracy of sliding frame timing, before the acquiring the real-time parallel oversampled data set based on the oversampled data set acquired in the current clock cycle, the method may further include: when a preset number of clock cycles form a first filtering cycle, updating the sliding frame selection starting signal corresponding to the first filtering cycle to a target signal value. The embodiment updates the sliding frame selection start signal once every preset number of clock cycles, so that sliding frame selection and data extraction can be performed in time every filtering cycle.
S102, sliding frame selection is carried out on the real-time parallel oversampling data set corresponding to the current clock cycle according to a target phase offset parameter corresponding to the current clock cycle, which is obtained in advance, so as to obtain a real-time frame selection data set.
The target phase shift parameter in this embodiment may include a slip shift direction and a slip shift amount. This embodiment does not limit the method of sliding framing. For example, this embodiment may recombine two beats of parallel 32-bit data received into 64-bit data, and slide-frame the 64-bit data to obtain 32-bit parallel data for subsequent data extraction. Or the embodiment can also recombine the parallel 32bit data received with three beats into 96bit data, and slide frame selection is carried out from the 96bit data to obtain the parallel data of 32 bit.
It should be further noted that, the first filtering period is a previous filtering period of the current filtering period, and the second filtering period is a previous filtering period of the first filtering period; the method may further include obtaining a target phase offset parameter based on a comparison of the first target phase and the second target phase, before obtaining the target phase offset parameter corresponding to the current clock cycle in accordance with the pre-obtained target phase offset parameter, and may include: performing signal edge change detection on any data block group included in any clock cycle in the first filtering cycle to obtain a corresponding edge change detection result, and obtaining a clock cycle phase corresponding to the corresponding clock cycle based on all edge change detection results in any clock cycle; taking the clock cycle phase with the largest number in the first filtering cycle as a first target phase; and comparing the first target phase with a second target phase which is determined in advance to determine a target phase offset parameter. The second target phase may be a set value, or may be a target phase value that has been validated corresponding to any filtering period preceding the first filtering period. The embodiment realizes the filtering processing of the phases by taking the clock cycle phase with the largest number in the first filtering period as the first target phase of the first filtering period.
It should be noted that, any over-sampled data is sequentially divided into a plurality of data block groups according to the sampling multiple, and each data block group includes the same bit data of the sampling multiple, for example, when the sampling multiple is 4, the data block group may be b1111, b0111, b0011, b0001 or b0000. The edge change detection result in this embodiment is a phase value. For example, the phase value of the edge change detection result in this embodiment may be 1, such as a data block b0111 (rising edge position is 1); or the phase value of the edge variation detection result in this embodiment may be 2 as well, such as the data block b0011 (rising edge position is 2); or the phase value of the edge change detection result in this embodiment may also be 3, such as the data block group b0001 (rising edge position is 3).
It will be appreciated that the presence of jitter in the received data will result in occasional phase jitter and bit width inconsistencies in the received oversampled data when oversampled. Phase jitter, e.g. two adjacent data blocks b0011, b1100. When phase jitter occurs, the two data blocks may become b0111, b1000 or b0001, b1110. Bit width inconsistencies, such as two adjacent data blocks b0011 and b1100, may become b0001, b1100 or b0111, b1000 when bit width inconsistencies occur. For the above case, the erroneous phase due to jitter must be filtered out. And counting the clock cycle phases corresponding to each clock cycle in the first filtering cycle, and assigning the clock cycle phase with the largest clock cycle phase number to the current phase register. The embodiment is not limited to a specific number of clock cycles of the preset number in the first filtering period. For example, the preset number in this embodiment may be 1000; or the preset number in this embodiment may also be 1500. The embodiment does not limit the determination method of the phase that occurs most frequently. For example, this embodiment may perform statistical processing to determine the phase that occurs most frequently; alternatively, the embodiment may also use registers to store each obtained different Phase (each register corresponds to a different Phase), so that the clock cycle Phase with the largest occurrence in the first filtering cycle is determined by the count number of the registers, that is, by counting the number of clock cycle phases corresponding to the clock cycle of the first filtering cycle, and stored in phase_count_regIn the (phase count) register, i ranges from 0 to 3, and phase_count_reg <0> stores the number of phases of 0; phase_count_reg <1> stores the number of phases 1; phase_count_reg <2> stores the number of phases of 2; phase_count_reg <3> stores the number of phases 3; by comparing the values of the several registers, the phase with the largest value is taken as the most numerous clock cycle phase. This embodiment gives a specific procedure for determining the first target phase, thereby improving the accuracy of determining the target phase offset parameter from the first target phase and the second target phase.
It should be further noted that, in order to improve accuracy of determining the clock cycle phase, the detecting the signal edge change of any one of the data block groups included in any one of the clock cycles in the first filtering cycle to obtain a corresponding edge change detection result, and obtaining the clock cycle phase corresponding to the corresponding clock cycle based on all edge change detection results in any one of the clock cycles may include:
S1, judging whether rising edge phases exist in all edge change detection results of any clock period;
and S2, if so, taking the rising edge phase as the corresponding clock cycle phase.
S3, if not, judging whether falling edge phases exist in all edge change detection results of any clock period;
S4, if so, taking the phase of the last clock cycle as the phase of the clock cycle;
S5, if not, taking the preset phase as the clock period phase.
This embodiment is not limited to a specific method of taking the rising edge phase as the corresponding clock period phase. For example, the first occurring non-0 rising edge phase may be taken as the corresponding clock cycle phase in this embodiment; or the embodiment may also take the second occurring non-0 rising edge phase as the corresponding clock cycle phase. If there is no rising edge phase, it is determined whether there is a falling edge phase. If there is a falling edge phase, the phase of the last clock cycle is taken as the clock cycle phase. If there is no falling edge phase, the preset phase is taken as the clock period phase. The embodiment is not limited to a specific preset phase. For example, the preset phase in this embodiment may be 0. The purpose is to eliminate the phase misjudgment which can be caused when the phase is 0. According to the embodiment, the clock cycle phases corresponding to the data block groups under different conditions are determined, so that phase misjudgment possibly caused when the phase is 0 is eliminated, and the accuracy of phase determination is further improved.
It should be further noted that the target phase offset parameter is obtained based on a comparison of a first target phase corresponding to the first filtering period and a second target phase corresponding to the second filtering period.
In a preferred embodiment, the first filtering period is continuous and non-coincident with the second filtering period, any filtering period comprising a predetermined number of clock cycles. Specifically, the first target phase is the most number of clock cycle phases determined by the first filtering cycle. The second target phase is the most number of clock cycle phases determined by the second filter period and is also the target phase that has been validated. The second filtering period, the first filtering period and the current filtering period are acquired sequentially in sequence, and the number of clock periods in the current filtering period does not reach the preset number yet.
It should be further noted that, in order to improve the accuracy of determining the target phase offset parameter, the target phase offset parameter includes a sliding offset direction and a sliding offset amount; the comparing the first target phase with the predetermined second target phase to determine the target phase offset parameter may include: acquiring a second target phase; comparing the first target phase with the second target phase, and determining a sliding offset direction according to a comparison result; an absolute value of a difference between the first target phase and the second target phase is determined as a slip offset.
The target phase shift parameter in this embodiment may include the slip shift direction and the slip shift amount, and a method of determining the slip shift direction and the slip shift amount is given, so that the accuracy of the target phase shift parameter determination may be improved.
It should be further noted that comparing the magnitudes of the first target phase and the second target phase, determining the sliding offset direction according to the comparison result may include:
s1021, when the first target phase is equal to the second target phase, the first target phase is not shifted from the second target phase.
S1022, when the first target phase is greater than the second target phase, determining that the sliding offset direction is right-shifted; wherein the first target phase is not the phase maximum and the second target phase is not the phase minimum; or, the first target phase is not the phase minimum and the second target phase is not the phase maximum.
In this embodiment, when the comparison result is that the first target phase is greater than the second target phase, the phase shift direction is determined to be shifted to the right. The embodiment is not limited to a specific phase maximum value, for example, the phase maximum value in the embodiment may be 3, and the embodiment is not limited to a phase minimum value, for example, the phase minimum value in the embodiment may be 0.
S1023, when the first target phase is smaller than the second target phase, determining that the sliding offset direction is left shift; wherein the first target phase is not the phase maximum and the second target phase is not the phase minimum; or, the first target phase is not the phase minimum and the second target phase is not the phase maximum.
S1024, when the first target phase is the maximum phase value and the second target phase is the minimum phase value, the sliding offset direction is determined to be shifted left.
S1025, when the first target phase is the phase minimum value and the second target phase is the phase maximum value, determining the sliding offset direction to be right-shifted.
The steps S1021-S1025 are alternatively executed.
The embodiment gives the corresponding sliding offset directions under various conditions of the first target phase and the second target phase, and improves the accuracy of determining the sliding offset direction.
It should be further noted that, in order to improve accuracy of sliding frame selection, before the step of obtaining the target phase offset parameter corresponding to the current clock cycle in advance, the method further includes obtaining a sliding frame selection start signal corresponding to the first filtering cycle, and performing sliding frame selection on the real-time parallel oversampled data set corresponding to the current clock cycle to obtain a real-time frame selection data set, which may include: judging whether the sliding frame selection starting signal is a target signal value or not; if yes, acquiring an initial frame selection position; sliding according to the target phase shift parameter based on the initial frame selection position to obtain a target frame selection position; and framing in the parallel oversampled data according to the target framing position to obtain a real-time framing data set. The embodiment is not limited to a specific slide frame select enable signal. For example, the slide frame select enable signal in this embodiment may be 1. The embodiment is not limited to a specific initial framing position, for example, the initial framing position in the embodiment may be 17; or the initial framing position in this embodiment may be 32. It will be appreciated that the initial framing position may be 17, and 32 data may be extracted from 96 bits of 3 clock cycles, and the sliding position may be larger, and the initial framing position may be 32, that is, may be generally an intermediate position (a position of the total number of bits minus the median of the number of extracted bits) of the total sliding position, or may be another position, and the accuracy of framing near the intermediate position may be relatively higher.
S103, data extraction is carried out on the real-time frame selection data set to obtain a valid sampling data set corresponding to the current clock cycle.
The embodiment is not limited to the particular manner in which the data extraction is performed. For example, the embodiment may extract the 2 nd bit of each real-time frame data set as the valid bit of the data set, and may obtain 1 data_8bit [7:0] after sampling, where the data_8bit [7:0] is valid data obtained by the oversampling technique of tracking phase offset; alternatively, the embodiment may extract the 3 rd bit of each real-time framing data set as the valid bit of that data set, it being understood that the middle bit may generally be selected as the valid bit of that data set. The first filter period and the second filter period in this embodiment are consecutive and non-overlapping filter periods. For example, the first 1000 clock cycles are taken as one filtering cycle, and the next filtering cycle is 1000 clock cycles corresponding to the 2000 th clock cycle.
The oversampling method provided by the embodiment of the invention can comprise the following steps: s101, acquiring a real-time parallel oversampling data set based on the oversampling data set acquired in the current clock cycle; s102, sliding frame selection is carried out on a real-time parallel oversampling data set corresponding to a current clock cycle according to a target phase offset parameter corresponding to the current clock cycle, which is obtained in advance, so as to obtain a real-time frame selection data set; s103, data extraction is carried out on the real-time frame selection data set to obtain an effective sampling data set corresponding to the current clock period; the target phase offset parameter is obtained based on a comparison of a first target phase corresponding to a first filtering period and a second target phase corresponding to a second filtering period, wherein the first filtering period is continuous and not coincident with the second filtering period, and any filtering period comprises a preset number of clock periods. According to the invention, the target phase shift parameter is obtained based on the comparison of the first target phase corresponding to the first filtering period and the second target phase corresponding to the second filtering period, the phase shift is tracked in real time, the response speed of data phase tracking is improved, and the accuracy of oversampling data extraction is improved. Moreover, the embodiment provides a specific process of determining the first target phase, so that the accuracy of determining the target phase offset parameter according to the first target phase and the second target phase is improved; in addition, according to the embodiment, the clock cycle phases corresponding to the data block groups under different conditions are determined, so that phase misjudgment possibly caused when the phase is 0 is eliminated, and the accuracy of phase determination is further improved; also, the target phase shift parameter in this embodiment may include the slip shift direction and the slip shift amount, and a method of determining the slip shift direction and the slip shift amount is given, so that the accuracy of the target phase shift parameter determination may be improved; in addition, the embodiment gives the corresponding sliding offset directions under various conditions of the first target phase and the second target phase, and improves the accuracy of determining the sliding offset directions.
For better understanding of the present invention, please refer to fig. 2, fig. 2 is a flowchart illustrating an oversampling method according to an embodiment of the present invention, which may include:
S201, parallel oversampling data corresponding to any clock period in a first filtering period are obtained, and the parallel oversampling data are divided to obtain a plurality of data block groups.
S202, signal edge change detection is carried out on any data block group included in any clock cycle in the first filtering cycle to obtain corresponding edge change detection results, and clock cycle phases corresponding to corresponding clock cycles are obtained based on all edge change detection results in any clock cycle.
S203, taking the clock cycle phase with the largest number in the first filtering cycle as a first target phase.
S204, comparing the first target phase with a second target phase determined in advance to determine a sliding offset direction; the first target phase is the most clock cycle phase determined by the first filtering period, and the second target phase is the most clock cycle phase determined by the second filtering period, and is also the effective target phase. The first filtering period and the second filtering period are continuous and do not coincide.
S205, the absolute value of the difference between the first target phase and the second target phase is determined as the slip offset amount.
S206, acquiring an initial frame selection position, and acquiring a target frame selection position according to the sliding offset and the sliding offset direction based on the initial frame selection position.
S207, performing frame selection in parallel oversampling data corresponding to the current clock cycle according to the target frame selection position to obtain a real-time frame selection data set, and grouping the real-time frame selection data set to obtain a plurality of grouping data.
S208, extracting preset bits of each packet data as valid bits of the packet data, and taking all valid bits as valid sampling data groups of the current clock cycle.
The embodiment of the invention can effectively filter the parallel data bit jitter caused by the phase jitter, continuously track the data phase offset, align the phase of the parallel data to be extracted and ensure the accuracy of data extraction.
For better understanding of the present invention, please refer to fig. 3, fig. 3 is a schematic diagram of an embodiment of an oversampling method according to the present invention, which may include: the device comprises a bit phase discriminator, a phase filtering module, a phase offset calculating module, a sliding frame selection module and a data extraction module. The embodiment of the invention provides a calculation method of an oversampling technology for tracking phase offset. The oversampling technique is to sample input data using a sampling rate N times that of the input rate, and sample one bit of the input data N times, so that parallel data of 1 group per N bits is obtained. The received data is passed through a bit phase discriminator to calculate the clock cycle phase of the current clock cycle. The phase filtering module performs statistical calculation on the calculated clock cycle phase for filtering, continuously calculates M times of phase positions with the largest number as the target phase of the current filtering cycle, and updates the current phase position once every M times. The phase offset calculation module is used for determining a sliding offset and a sliding offset direction, taking K+1th statistics as an example, taking a K-th phase result as feedback, comparing the K-th and K+1th phase positions, and determining the K+1th sliding offset and the sliding offset direction. The sliding frame selection module is used for carrying out sliding frame selection on the current oversampled data according to the sliding offset and the sliding offset direction, the data selected by the sliding frame through the algorithm can be directly used for data extraction, 4 bits are a group, and the 2 nd bit or the 3 rd bit is used as a tap position, so that the anti-shake effect can be achieved. It is important to receive and recover the jittered and phase shifted serial data. Especially when the phase continuously shifts due to the change of the optical power in the GPON module test, the technical scheme provides a very effective solution. Please refer to the following steps:
step 1, after passing through a receiver with N times of input rate, parallel oversampled data with 1 group of every N identical bits is obtained.
For ease of understanding, fig. 4 is a schematic diagram of jitter and phase offset provided by an embodiment of the present invention, where the receiving uses a 9.95328Gbps rate to oversample data for an OLT (optical line terminal) link for optical communications at a 2.48832Gbps rate. When the input optical power of the OLT module changes, jitter and phase shift of the flip edge occur in the electrical port data converted by the OLT. The parallel data represented at the receiver is that the boundary position of 0 and 1 has bit jitter and bit offset in the parallel data bits.
This embodiment, after passing through a receiver with N times the input rate, will result in 1 set of parallel data for every N identical bits. Taking 4 times oversampling as an example, namely using a 9.95328Gbps receiver to receive 2.48832Gbps input data, sampling each bit of input data to 4 identical bit data, taking the acquired actually 8bit sampled data as an example, and obtaining parallel data with 32bit width by oversampling, wherein the repeated 4bit phases in the 32bit data are not aligned due to the serial data delay and the working principle of the receiver. And also an overall positional shift may occur.
And 2, processing the parallel oversampled data by using a bit phase discriminator to obtain the phase of the current clock cycle.
The current clock cycle phase in this embodiment corresponds to the clock cycle phase above. The phase mode of the bit phase detector in this embodiment to obtain the current clock cycle is: parallel data with input 32 bits of bit width is named as in_data <31:0>, and is divided into 8 groups of data blocks (corresponding to the above data block groups) from high order to low order, and each 4 bits is taken as a data block and is named as data_ bitdiv<3:0>, I=0 to 7.data_4bitdiv <0> = in_data <31:28>, which is the 28 th bit to 31 th bit of the received data; data_4bitdiv <1> = in_data <27:24>, which is the 24 th to 27 th bits of the received data; .. data_4bitdiv <7> = in_data <3:0>, which is the 0 th to 3 rd bits of the received data; detecting the rising edge phase of each data block and judging whether a falling edge bit_ falledge is generated or not; b0111, the rising edge phase is 1, bit_roller=0; b0011, the rising edge phase of which is 2, bit_roller=0; b0001, its rising edge phase is 3, bit_roller=0; otherwise, the rising edge phase is 0, and bit_roller=1; and sequentially detecting rising edge phases of 8 groups of data blocks from high order to low order, wherein the first non-0 rising edge phase is taken as the clock cycle phase of the 8 groups of data blocks and is recorded as bit_current_position. If there is no rising edge, it is determined whether bit_ falledge is 0. If 0, the phase of the 8 groups of data blocks is 0; if bit falledge is 1, the phase of the 8-set data block remains consistent with bit current position for the last clock cycle. This is to eliminate phase misjudgment that may be caused when the phase is 0. By the method, the phase bit_current_position of the current clock period can be obtained.
And step 3, filtering the phase of the current clock cycle by using a phase filtering module to obtain a first target phase of the current filtering cycle.
The first target phase of the current filter period in this embodiment corresponds to the filtered phase position in the plot. The process of the phase filtering module obtaining the first target phase of the current filtering period in this embodiment includes: the existence of jitter in the received data will cause occasional phase jitter and bit width inconsistencies in the parallel data received during over-sampling. Phase jitter, e.g. two adjacent data blocks b0011, b1100. When phase jitter occurs, the two data blocks may become b0111, b1000 or b0001, b1110. The bit width is not uniform, e.g., two adjacent data blocks b0011, and b1100. When bit width inconsistencies occur, the two data blocks may become b0001, b1100 or b0111, b1000. For the above case, the erroneous phase due to jitter must be filtered out. Counting the number of phases of 1000 clock cycles, and storing in phase_count_regIn the (phase counting) register, the i range is 0-3, and the phase_count_reg <0> storage phase is 0 number; phase_count_reg <1> stores the number of phases 1; phase_count_reg <2> stores the number of phases of 2; phase_count_reg <3> stores the number of phases 3; the phase of the register with the largest value is assigned to the filtered current phase register bit_position_reg by comparing the data of the registers, the phase register bit_position_reg is updated once every 1000 clock cycles, and a sliding frame selection starting signal bit_draw_check_flag in the sliding frame selection module is updated to 1. Therefore, the phase filtering module takes 1000 clock cycles as a filtering cycle, and outputs the current phase register bit_position_reg and the sliding frame selection starting signal bit_draw_check_flag in the sliding frame selection module.
And 4, determining the sliding offset and the sliding offset direction by using the phase offset calculation module according to the first target phase of the current filtering period and the second target phase of the last filtering period.
The process of determining the slip offset and the slip offset direction by the phase offset calculation module in this embodiment is as follows: the phase offset calculation module and the sliding frame selection module below calculate once every filtering period, i.e. the sliding frame selection module will give the phase position (second target phase) bit_position_valid, where the last filtering period has been effective, as feedback to the phase offset calculation module. The calculation of the current phase (first target phase) bit_position_reg corresponding to the current phase register results in two data. One is an offset direction register bit_position_dir for determining the bit offset direction (sliding offset direction) of the sliding frame selection module; The other is a bit offset bit_position_offset for determining the sliding offset of the sliding framing module. And carrying out logic judgment on the current phase register bit_position_reg and the phase register bit_position_valid which is validated in the sliding frame selection module, calculating the absolute value of the difference value between the current phase register bit_position_reg and the phase register bit_position_valid, and assigning the absolute value to the bit_position_offset register. Comparing the current phase register bit_position_reg with the validated phase register bit_position_valid, there are several cases: when bit_position_valid=bit_position_reg, the phase of the current filtering period is unchanged compared with the phase of the last filtering period, and bit_position_dir=0 and bit_position_offset=0; When the bit_position_valid < bit_position_reg indicates that the phase of the current filtering period is shifted to the right compared with the phase of the previous filtering period, bit_position_dir=2, bit_position_offset=bit_position_reg-bit_position_valid; when bit_position_valid > bit_position_reg, the phase of the current filtering period is shifted to the left compared with the phase of the last filtering period, and bit_position_dir=1, bit_position_offset=bit_position_valid_bit_position_reg; When bit_position_valid=0 and bit_position_reg=3, the phase of the current filtering period is shifted to the left compared with the phase of the last filtering period, and bit_position_dir=1 and bit_position_offset=1; when bit_position_valid=3 and bit_position_reg=0, the phase of the current filtering period is shifted to the right compared with the phase of the last filtering period, and bit_position_dir=2 and bit_position_offset=1; Through the above logical judgment, the slip offset direction bit_position_dir and the slip offset amount bit_position_offset can be obtained.
And 5, determining the real-time frame selection data set by utilizing the sliding frame selection module according to the sliding offset and the sliding offset direction.
The process of determining the sliding frame selection phase using the sliding frame selection module in this embodiment includes: the module is used for selecting 32-bit parallel data from 64 bits according to a frame selection position frame (bit_draw_position) every clock cycle and is used for carrying out data extraction in a data extraction module, wherein the parallel data of the received two beats of parallel 32-bit data are recombined into 64-bit data and are denoted as s_data_64 bits. The location of the box selection is therefore important for the accuracy of the data extraction. The frame selection mode is as follows: s_data_32bit = s_data_64bit <64-bit_draw_position:32-bit_draw_position >; And extracting the 32-bit data according to the bit_draw_position from the 64-bit data formed by two beats of parallel 32-bit data. That is to say, when bit_draw \u when the position=16, the position is set, s_data_get32bit = s_data_64bit <48:17>; when bit_draw \u when the position=15, the position is calculated, s_data_get32bit = s_data_64bit <49:18>; when bit_draw_position=1, s_data_ge32bit=s_data_64bit <63:32>, bit_draw_position has an initial value of 17, s_data_get32bit=s_data_64bit <47:16>, and bit_position_valid initial value is 0; And calculating the value of the bit_draw_position according to the direction register bit_position_dir and the offset bit_position_offset output by the offset calculation module when the bit_draw_check_flag starting signal of the filtering module is temporary. The calculation method is as follows: when bit_position_dir=1, the bit_draw_position itself subtracts bit_position_offset, and the frame selection position shifts left the bit_position_offset by a number of bits; when bit position dir=2, bit_draw_position itself plus bit position offset, the frame selection position shifts right by bit_position_offset bits; when bit_position_dir=0, bit_draw_position is unchanged, and the frame selection position is also unchanged; and assigning the value of the bit_position_reg to the bit_position_valid while the above box selection position is effective, and participating in feedback of the next filtering period. The s_data_get32bit obtained by the frame selection mode is 32bit data with aligned phases, and along with the phase shift of a received signal, bit_position_dir and bit_position_offset change along with the phase shift, the frame selection position bit_draw_position also tracks the phase shift, so that the frame selection data is composed of 8 groups of data blocks with 4bit repeated occurrence, and the phase alignment is ensured.
And 6, extracting preset bits of each group of data to be used as valid bits of the group of data by using a data extraction module, and taking all valid bits as valid sampling data groups of the current clock cycle.
The process of obtaining valid data by using the data extraction module in this embodiment includes: the s_data_get32bit data obtained by the sliding frame selection module is divided into 8 groups of data blocks, the 8 groups of data blocks are recorded as data_4bit_in [ j ] [3:0], the value range of j is 0-7, the data_4bit_in[0][3:0]=s_data_get32bit[31:28];data_4bit_in[1][3:0]=s_data_get32bit[27:24];……data_4bit_in[7][3:0]=s_data_get32bit[3:0]; th bit of each data group is extracted as the valid bit of the data group, and 1 sampled data data_8bit [7:0] with the width of 8 bits can be obtained. The data_8bit [7:0] at this time is valid data obtained by the oversampling technique that tracks the phase offset.
The embodiment of the invention provides an oversampling technology for tracking phase deviation, and provides a method for phase identification and phase filtering, which can effectively filter phase errors generated by phase jitter. When the phase of the received signal is shifted, the data phase shift direction and the shift amount are calculated through feedback control, so that the phase tracking of the data is realized. And a method for extracting data by sliding frame selection is designed, and the frame selection position is adjusted by periodic sliding according to the phase shift direction and the shift amount of the data, so that parallel data with aligned phases is obtained, and data extraction is performed. The method can ensure that the data phase jitter and the data phase offset are effectively generated in the process of oversampling the low-speed data. Parallel data bit jitter caused by phase jitter can be effectively filtered, and data phase offset can be continuously tracked, so that the parallel data to be extracted are aligned in phase, and the accuracy of data extraction is ensured. The method can effectively solve the problem that the recovered data generate phase shift when the optical power is changed in the GPON optical module testing process, and can continuously follow the phase change to recover the correct data.
The following describes an oversampling apparatus provided in an embodiment of the present invention, and the oversampling apparatus described below and the oversampling method described above may be referred to correspondingly.
Referring to fig. 5, fig. 5 is a schematic structural diagram of an oversampling apparatus according to an embodiment of the present invention, which may include:
A data set determining module 100, configured to obtain a real-time parallel oversampled data set based on the oversampled data set acquired in the current clock cycle;
The real-time frame selection data set determining module 200 is configured to perform sliding frame selection on the real-time parallel oversampled data set corresponding to the current clock cycle according to a target phase offset parameter obtained in advance and corresponding to the current clock cycle to obtain a real-time frame selection data set;
An effective sampling data set determining module 300, configured to perform data extraction on the real-time frame selection data set to obtain an effective sampling data set corresponding to the current clock cycle;
The target phase offset parameter is obtained based on a comparison of a first target phase corresponding to a first filtering period and a second target phase corresponding to a second filtering period, wherein the first filtering period is continuous and not coincident with the second filtering period, and any filtering period comprises a preset number of clock periods.
Further, based on the above embodiment, the first filtering period is a filtering period before the current filtering period, and the second filtering period is a filtering period before the first filtering period; the above-mentioned oversampling apparatus may further include: a target phase offset parameter determination module, configured to obtain the target phase offset parameter based on a comparison of the first target phase and the second target phase, where the target phase offset parameter determination module may include:
The clock cycle phase determining unit is used for detecting signal edge variation of any data block group included in any clock cycle in the first filtering cycle to obtain corresponding edge variation detection results, and obtaining clock cycle phases corresponding to corresponding clock cycles based on all the edge variation detection results in any clock cycle;
A first target phase determining unit, configured to take, as the first target phase, the clock cycle phase with the largest number in the first filtering cycle;
And the target phase shift parameter determining unit is used for comparing the first target phase with the second target phase which is determined in advance to determine the target phase shift parameter.
Further, based on the above embodiment, the above clock cycle phase determining unit may include:
A rising edge phase judging subunit, configured to judge whether a rising edge phase exists in all edge change detection results of any clock cycle;
and the first clock cycle phase determining subunit is used for taking the rising edge phase as the corresponding clock cycle phase if the rising edge phase is the same as the rising edge phase.
Further, based on the above embodiment, the above clock cycle phase determining unit may include:
A falling edge phase determining subunit, configured to determine whether a falling edge phase exists in all edge change detection results of any clock cycle if not;
The second clock period determining subunit is configured to use, if yes, a phase of a previous clock period as the phase of the clock period;
and the third clock period determining subunit is used for taking the preset phase as the clock period phase if not.
Further, based on the above embodiment, the rising edge phase determining subunit may include:
And the non-0 rising edge phase judgment subunit is used for taking the first non-0 rising edge phase of all the data block groups arranged from the high order to the low order as the clock cycle phase of the corresponding clock cycle.
Further, based on any of the above embodiments, the target phase offset parameter includes a slip offset direction and a slip offset amount; the target phase shift parameter determining unit may include:
A second target phase acquisition subunit, configured to acquire the second target phase;
The sliding offset direction determining subunit is used for comparing the magnitudes of the first target phase and the second target phase and determining the sliding offset direction according to a comparison result;
a slip offset determination subunit configured to determine an absolute value of a difference between the first target phase and the second target phase as the slip offset.
Further, based on the above embodiment, the above sliding offset direction determining subunit may include:
A first offset direction determining subunit configured to, when the first target phase is equal to the second target phase, not offset from the second target phase by the first target phase;
A second shift direction determining sub-unit configured to determine that the sliding shift direction is shifted right when the first target phase is greater than the second target phase; wherein the first target phase is not a phase maximum and the second target phase is not a phase minimum; or, the first target phase is not the phase minimum and the second target phase is not the phase maximum;
A third shift direction determining subunit configured to determine that the sliding shift direction is shifted left when the first target phase is smaller than the second target phase; wherein the first target phase is not a phase maximum and the second target phase is not a phase minimum; or, the first target phase is not the phase minimum and the second target phase is not the phase maximum;
A fourth shift direction determining subunit configured to determine that the sliding shift direction is shifted left when the first target phase is the phase maximum value and the second target phase is the phase minimum value;
And a fifth offset direction determining subunit configured to determine that the sliding offset direction is shifted to the right when the first target phase is the phase minimum value and the second target phase is the phase maximum value.
Further, based on the above embodiment, the above oversampling apparatus may further include: the sliding frame selection start signal obtaining module, configured to obtain a sliding frame selection start signal corresponding to the first filtering period, and the real-time frame selection data set determining module 200 may include:
The target signal value judging unit is used for judging whether the sliding frame selection starting signal is a target signal value or not;
the initial frame selection position determining unit is used for acquiring an initial frame selection position if the initial frame selection position is determined to be the initial frame selection position;
The target frame selection position determining unit is used for obtaining a target frame selection position according to the initial frame selection position and the target phase shift parameter in a sliding mode;
and the real-time frame selection data set determining unit is used for frame selection in the parallel oversampled data according to the target frame selection position to obtain the real-time frame selection data set.
Further, based on the above embodiment, the above oversampling apparatus may further include:
And the target signal value updating module is used for updating the sliding frame selection starting signal corresponding to the first filtering period into the target signal value when the first filtering period is formed by a preset number of clock periods.
It should be noted that the modules and units in the over-sampling device can change the order of the modules and units before and after the modules and units do not affect the logic.
The oversampling apparatus provided by the embodiment of the invention may include: a data set determining module 100, configured to obtain a real-time parallel oversampled data set based on the oversampled data set acquired in the current clock cycle; the real-time frame selection data set determining module 200 is configured to perform sliding frame selection on the real-time parallel oversampled data set corresponding to the current clock cycle according to a target phase offset parameter obtained in advance and corresponding to the current clock cycle to obtain a real-time frame selection data set; an effective sampling data set determining module 300, configured to perform data extraction on the real-time frame selection data set to obtain an effective sampling data set corresponding to the current clock cycle; the target phase offset parameter is obtained based on a comparison of a first target phase corresponding to a first filtering period and a second target phase corresponding to a second filtering period, wherein the first filtering period is continuous and not coincident with the second filtering period, and any filtering period comprises a preset number of clock periods. According to the invention, the target phase shift parameter is obtained based on the comparison of the first target phase corresponding to the first filtering period and the second target phase corresponding to the second filtering period, the phase shift is tracked in real time, the response speed of data phase tracking is improved, and the accuracy of oversampling data extraction is improved. Moreover, the embodiment provides a specific process of determining the first target phase, so that the accuracy of determining the target phase offset parameter according to the first target phase and the second target phase is improved; in addition, according to the embodiment, the clock cycle phases corresponding to the data block groups under different conditions are determined, so that phase misjudgment possibly caused when the phase is 0 is eliminated, and the accuracy of phase determination is further improved; also, the target phase shift parameter in this embodiment may include the slip shift direction and the slip shift amount, and a method of determining the slip shift direction and the slip shift amount is given, so that the accuracy of the target phase shift parameter determination may be improved; in addition, the embodiment gives the corresponding sliding offset directions under various conditions of the first target phase and the second target phase, and improves the accuracy of determining the sliding offset directions.
The following describes an electronic device provided by an embodiment of the present invention, where the electronic device described below and the oversampling method described above may be referred to correspondingly. Specifically, the electronic device is a test device for testing a GPON optical module in the technical field of optical network testing, such as a general error code analyzer, a burst error code analyzer and the like, and is used for performing error rate testing, optical eye testing, receiving sensitivity testing and the like of the GPON optical module based on an effective sampling data set acquired by the over-sampling method.
Referring to fig. 6, fig. 6 is a schematic structural diagram of an electronic device according to an embodiment of the present invention, which may include:
a memory 10 for storing a computer program;
A processor 20 for executing a computer program to implement the above-described oversampling method.
The memory 10, the processor 20, and the communication interface 30 all communicate with each other via a communication bus 40.
In the embodiment of the present invention, the memory 10 is used to store one or more programs, and the programs may include program codes including computer operation instructions, and in the embodiment of the present invention, the memory 10 may store programs for implementing functions corresponding to the above-mentioned process methods.
In one possible implementation, the memory 10 may include a storage program area and a storage data area, wherein the storage program area may store an operating system, and at least one application program required for functions, etc.; the storage data area may store data created during use.
In addition, memory 10 may include read only memory and random access memory and provide instructions and data to the processor. A portion of the memory may also include NVRAM. The memory stores an operating system and operating instructions, executable modules or data structures, or a subset thereof, or an extended set thereof, where the operating instructions may include various operating instructions for performing various operations. The operating system may include various system programs for implementing various basic tasks as well as handling hardware-based tasks.
The processor 20 may be a central processing unit (Central Processing Unit, CPU), an asic, a dsp, a fpga or other programmable logic device, and the processor 20 may be a microprocessor or any conventional processor. The processor 20 may call a program stored in the memory 10.
The communication interface 30 may be an interface of a communication module for connecting with other devices or systems.
Of course, it should be noted that the structure shown in fig. 6 is not limited to the electronic device in the embodiment of the present invention, and the electronic device may include more or fewer components than those shown in fig. 6 or may be combined with some components in practical applications.
The following describes a computer readable storage medium provided in an embodiment of the present invention, where the computer readable storage medium described below and the oversampling method described above may be referred to correspondingly.
The present invention also provides a computer readable storage medium having stored thereon a computer program which when executed by a processor performs the steps of the above-described oversampling method.
The computer readable storage medium may include: a U-disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, or an optical disk, or other various media capable of storing program codes.
In this specification, each embodiment is described in a progressive manner, and each embodiment is mainly described in a different point from other embodiments, so that the same or similar parts between the embodiments are referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant points refer to the description of the method section.
Those of skill would further appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, computer software, or combinations of both, and that the various illustrative elements and steps are described above generally in terms of functionality in order to clearly illustrate the interchangeability of hardware and software. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the present invention.
Finally, it is further noted that, in this document, relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such process, method, article, or apparatus.
The above description of the oversampling method, apparatus, electronic device and computer readable storage medium provided by the present invention has been presented in detail, and specific examples are applied to illustrate the principles and embodiments of the present invention, and the above examples are only used to help understand the method and core idea of the present invention; meanwhile, as those skilled in the art will have variations in the specific embodiments and application scope in accordance with the ideas of the present invention, the present description should not be construed as limiting the present invention in view of the above.
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