CN118645144B - Flash memory test system and test method - Google Patents
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- CN118645144B CN118645144B CN202411124780.0A CN202411124780A CN118645144B CN 118645144 B CN118645144 B CN 118645144B CN 202411124780 A CN202411124780 A CN 202411124780A CN 118645144 B CN118645144 B CN 118645144B
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
- G11C29/50—Marginal testing, e.g. race, voltage or current testing
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- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
- G11C29/70—Masking faults in memories by using spares or by reconfiguring
- G11C29/78—Masking faults in memories by using spares or by reconfiguring using programmable devices
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Abstract
本发明提供一种闪存的测试系统及测试方法，测试系统包括温箱，温箱内设有闪存，温箱用以调节闪存周围的温度范围；控制器，在某组区块中，控制器对不同区块按照阶梯分布的编程/擦除次数进行数据处理；其中，在某组区块进行阶梯分布的编程与擦除次数数据处理后，控制器在第一温度区间下，首先对某组区块进行宽温测试和数据保持测试，其次将某组区块进行擦除处理，然后在第二温度区间下，对某组区块进行宽温测试和数据保持测试，第二温度区间包括第一温度区间。本发明可在闪存于不同温度区间，保持最佳使用性能的前提下，获取其最大的使用寿命。
The present invention provides a flash memory test system and test method, the test system includes a temperature box, a flash memory is arranged in the temperature box, and the temperature box is used to adjust the temperature range around the flash memory; a controller, in a certain group of blocks, the controller performs data processing on the programming/erasing times of different blocks according to the step distribution; wherein, after the step distribution programming and erasing times data processing is performed on a certain group of blocks, the controller first performs a wide temperature test and a data retention test on the certain group of blocks in a first temperature interval, and then performs an erasing process on the certain group of blocks, and then performs a wide temperature test and a data retention test on the certain group of blocks in a second temperature interval, and the second temperature interval includes the first temperature interval. The present invention can obtain the maximum service life of the flash memory under the premise of maintaining the best performance in different temperature intervals.
Description
Technical Field
The present invention relates to the field of static storage technologies, and in particular, to a flash memory testing system and a flash memory testing method.
Background
The flash memory is used as a storage medium, and can be divided into a consumption level, a construction level, a vehicle level and the like according to the application field, wherein the main difference is that the requirement on stability performance is gradually increased, and particularly the tolerance degree on temperature is improved. For most of middle and small-sized storage manufacturers in industry, only the functionality of the flash memory is verified without quality classification, and the flash memory is sold in an industrial standard flash memory after being simply classified according to parameter standards.
The quality of flash memory can be significantly degraded with wear consumption, particularly for high and low temperatures, and the durability of data retention in high temperature environments. Therefore, the performance of the standard class is tested only in the early life of the flash memory, and the whole life cycle of the flash memory cannot be considered. Therefore, there is a need for improvement.
Disclosure of Invention
The invention provides a flash memory test system and a test method, which are used for solving the technical problem that the whole life cycle of a flash memory cannot be considered in the prior art because the performance of an engineering standard is only tested in the early life of the flash memory.
The invention provides a flash memory test system, which comprises:
The temperature box is internally provided with a flash memory, the temperature box is used for adjusting the temperature range around the flash memory, and the flash memory comprises a plurality of groups of blocks;
The controller is used for carrying out data processing on different blocks according to the programming and erasing times distributed in steps in a certain group of blocks, wherein one programming and erasing time represents that the block is subjected to one-time writing and erasing processing;
After the data processing of the programming and erasing times of the step distribution is performed on the certain group of blocks, the controller firstly performs a wide temperature test and a data retention test on the certain group of blocks in a first temperature interval, secondly performs an erasing process on the certain group of blocks, and then performs a wide temperature test and a data retention test on the certain group of blocks in a second temperature interval, wherein the second temperature interval comprises the first temperature interval;
the controller generates first test data corresponding to the certain group of blocks in the first temperature interval and second test data corresponding to the certain group of blocks in the second temperature interval.
In one embodiment of the present invention, the controller counts the maximum programming and erasing times of the block without error data under the wide temperature test as the wide temperature times, and counts the maximum programming and erasing times of the block without error data under the data retention test as the data retention times;
and the controller records the minimum value of the wide temperature times and the data holding times as the maximum service life of the first test data or the second test data.
In one embodiment of the present invention, the controller performs a test of high temperature erasing, high Wen Douqu, or high temperature erasing, low temperature reading, or low temperature erasing, high Wen Douqu, or low temperature erasing, low temperature reading on the certain group of blocks in the first temperature interval or the second temperature interval;
the maximum programming and erasing times of the data without error in the test are respectively recorded as high-temperature writing and high-temperature reading times, high-temperature writing and low-temperature reading times, low-temperature writing and high-temperature reading times and low-temperature writing and low-temperature reading times;
And recording the minimum value of the high-temperature writing and high-temperature reading times, the high-temperature writing and low-temperature reading times, the low-temperature writing and high-temperature reading times and the low-temperature writing and low-temperature reading times as the wide-temperature times.
In one embodiment of the present invention, the controller performs high temperature erasure or low temperature erasure processing on the certain group of blocks in the first temperature interval or the second temperature interval, and performs high temperature reading verification and low temperature reading verification on the certain group of blocks under a preset data holding temperature and data holding time;
The maximum programming and erasing times of the data without error in the reading and checking are respectively recorded as high-temperature erasing and writing maintaining times and low-temperature erasing and writing maintaining times;
and recording the minimum value of the high-temperature erasing and writing maintaining times and the low-temperature erasing and writing maintaining times as the data maintaining times.
In one embodiment of the present invention, the certain group of blocks have different data retention times at different data retention temperatures, and the ratio between the different data retention times is the temperature acceleration coefficientThe method comprises the following steps:
;
;
Wherein, In order for the reaction rate constant to be constant,Is the Arrhenius constant of the Arrhenius,In order to react the activation energy of the reaction,Is a boltzmann constant,In the case of a thermodynamic temperature of the material,Is a bottom of natural logarithm;
At the first temperature of the material to be treated, At the temperature of the second temperature of the first temperature,In order to be a temperature acceleration coefficient,Is thatThe corresponding reaction rate constant is used to determine,Is thatA corresponding reaction rate constant.
In one embodiment of the present invention, in the step distribution of the program and erase times corresponding to the certain group of blocks, the step distribution includes a plurality of step segments;
In a certain step section, the controller performs data processing on two adjacent blocks according to the gradient step number which is a non-zero constant and is the difference value of corresponding programming and erasing times.
In one embodiment of the present invention, the controller selects chips at different positions on the surface of the wafer, or randomly selects chips of different batches and then divides the chips into a plurality of groups to be used as the flash memories for testing, and selects blocks of different segments on the flash memories for testing.
The invention also provides a method for testing the flash memory, which comprises the following steps:
Setting a flash memory in an incubator, and adjusting the temperature range around the flash memory through the incubator, wherein the flash memory comprises a plurality of groups of blocks;
In a certain group of blocks, performing data processing on different blocks according to the programming and erasing times distributed in a step manner, wherein one programming and erasing time indicates that the block is subjected to write-in and erasing processing once;
After the data processing of the programming and erasing times of the step distribution is carried out on a certain group of blocks, a wide temperature test and a data retention test are carried out on the certain group of blocks in a first temperature interval;
Performing erasure processing on the certain group of blocks, and performing wide temperature testing and data retention testing on the certain group of blocks in a second temperature interval, wherein the second temperature interval comprises the first temperature interval;
And generating first test data corresponding to the certain group of blocks in the first temperature interval and second test data corresponding to the certain group of blocks in the second temperature interval.
In one embodiment of the present invention, the step of performing a wide temperature test and a data retention test on the set of blocks at a first temperature interval includes:
The maximum programming and erasing times of the block without error data are recorded as the wide temperature times under the wide temperature test;
The maximum programming and erasing times of the block without error data are recorded as data retention times under the data retention test;
and recording the minimum value of the wide temperature times and the data retention times as the maximum service life of the first test data.
In one embodiment of the present invention, the step of counting the maximum programming and erasing times of the block without error data under the wide temperature test as the wide temperature times includes:
In the first temperature interval, respectively performing high-temperature erasing, high Wen Douqu, high-temperature erasing, low-temperature reading, low-temperature erasing, high Wen Douqu, or low-temperature erasing, low-temperature reading test on the certain group of blocks;
the maximum programming and erasing times of the data without error in the test are respectively recorded as high-temperature writing and high-temperature reading times, high-temperature writing and low-temperature reading times, low-temperature writing and high-temperature reading times and low-temperature writing and low-temperature reading times;
And recording the minimum value of the high-temperature writing and high-temperature reading times, the high-temperature writing and low-temperature reading times, the low-temperature writing and high-temperature reading times and the low-temperature writing and low-temperature reading times as the wide-temperature times.
The invention has the beneficial effects that the maximum service life of the flash memory can be obtained on the premise that the flash memory keeps the optimal service performance in different temperature ranges. The abrasion threshold analysis of the ' consumption level ' standard flash memory and the abrasion threshold analysis of the ' industry standard flash memory can be synchronously realized, so that the testing and labor cost of the flash memory are greatly saved.
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In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present application, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.
Fig. 1 is a schematic structural diagram of a flash memory testing system according to an embodiment of the invention.
Fig. 2 is a schematic diagram illustrating a location of a flash memory on a selected wafer according to an embodiment of the invention.
FIG. 3 is a schematic diagram illustrating a step-wise program/erase count data processing for multiple blocks according to an embodiment of the present invention.
Fig. 4 is a schematic diagram illustrating steps of a method for testing a flash memory according to an embodiment of the invention.
Fig. 5 is a schematic diagram illustrating a step S30 in fig. 4 according to an embodiment of the invention.
Fig. 6 is a schematic diagram illustrating a step of step S310 in fig. 5 according to an embodiment of the present invention.
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
In the following description, numerous details are set forth in order to provide a more thorough explanation of embodiments of the present invention, it will be apparent, however, to one skilled in the art that embodiments of the present invention may be practiced without these specific details, in other embodiments, well-known structures and devices are shown in block diagram form, rather than in detail, in order to avoid obscuring the embodiments of the present invention.
Referring to fig. 1 to 6, the present invention provides a system and a method for testing a flash memory, which can be applied to memory devices such as eMMC (Embedded Multi MEDIA CARD), SSD (Solid STATE DISK), UFS (Univeral Flash Storage, universal flash memory), and the like. The invention can obtain the maximum service life of the flash memory 30 on the premise of keeping the optimal service performance in different temperature ranges. For example, compliance with industry standard class standards throughout the life of the consumer class flash memory 30 may enable the consumer class flash memory 30 to make industry standard class products without affecting the yield of the industry standard class products. The following is a detailed description of specific embodiments.
Referring to fig. 1, in one embodiment of the present invention, a flash memory testing system is provided, which may include a controller 10 and an incubator 20, wherein the incubator 20 may have a flash memory 30 disposed therein, and the temperature range around the flash memory 30 may be adjusted by the incubator 20. The flash memory 30 is provided with a bus interface, and the flash memory 30 is electrically connected with the controller 10 through the bus interface. The controller 10 may write host data and send instructions to the flash memory 30, or the controller 10 may read host data and receive instructions from the flash memory 30, or the controller 10 may erase host data in the flash memory 30, which is application data written by the controller 10. The controller 10 may be a processor in a communication device such as a personal computer (PC, personal Computer), tablet (Pad), mobile Phone (Cell Phone), or the like.
Referring to fig. 1, in one embodiment of the present invention, a flash memory (flash memory) 30 is a non-volatile memory, which is typically used to store host data and system programs, and the flash memory 30 may be a NAND type flash memory. The flash memory 30 may include a plurality of blocks (blocks) 31, and the blocks 31 may be used to store host data written by the controller 10, and one Block 31 may further include a plurality of pages (pages). The block 31 is an erase unit of host data on the flash memory 30, and the page is a read unit of host data on the flash memory 30. The memory cells of block 31 may be Single-level memory cells (SLC, single-LEVEL CELL), double-level memory cells (MLC, multi-LEVEL CELL), triple-level memory cells (TLC, trinary-LEVEL CELL), quad-level memory cells (QLC, quad-LEVEL CELL), and the like.
Referring to fig. 1 and 2, in one embodiment of the present invention, chips at different locations on the wafer surface, such as chips at upper, lower, left, right, and middle locations on the wafer surface, may be selected as the flash memory 30 for testing. The flash memory 30 at different locations on the wafer is tested to improve the reliability of the test data. If it is impossible to distinguish the flash memories 30 from specific locations on the wafer, a plurality of flash memories 30 can be randomly selected from three wafer lots at a time according to the Jedec test standard, and the plurality of flash memories 30 are divided into a plurality of groups to be used as the tested flash memories 30.
Specifically, 77 flash memories 30 are randomly selected from three wafer lots at a time, and 231 flash memories 30 are tested in total. To more fully explore the performance of a batch of flash memory 30 on the industry standard, different segmented blocks 31 on the flash memory 30, such as front, middle and back blocks 31 on the flash memory 30, may be selected for testing.
Referring to fig. 1 and 3, in one embodiment of the present invention, in a certain group of blocks 31 of a flash memory 30, the controller 10 performs data processing on different blocks 31 according to a ladder distribution of Program and erase counts (PEC, program ERASE CYCLE), one Program and erase count indicating that the block 31 has undergone a write and erase process.
Referring to fig. 1 and 3, in one embodiment of the present invention, after a set of blocks 31 is subjected to a step-distributed Program and Erase Count (PEC) data process in a flash memory 30, the controller 10 first performs a wide temperature test and a data retention test on the set of blocks 31 at a first temperature interval, and then performs an erase process on the set of blocks 31. Then, the controller 10 performs a wide temperature test and a data retention test on the set of blocks 31 at a second temperature interval including the first temperature interval. The controller 10 generates first test data corresponding to the set of blocks 31 in the first temperature interval and second test data corresponding to the second temperature interval.
Specifically, the wide temperature test is a test that the block 31 can perform stable performance under a wide temperature operating environment between a minimum value and a maximum value of one temperature interval. For example, the wide temperature working environment corresponding to the consumption-level block 31 is 0-70 ℃, and the wide temperature working environment corresponding to the industrial-level block 31 is-40-85 ℃. The usability can be determined by reading the host data on the block 31, and when the host data on the block 31 is not in error, the usability of the block 31 is good, and when the host data on the block 31 is in error, the usability of the block 31 is reduced. The data retention test refers to a test of retention time corresponding to the host data on the block 31 without error data in a certain temperature environment of the block 31.
Specifically, as shown in fig. 1 and 3, after a group of blocks 31 undergoes a step-distributed Program and Erase Count (PEC) data process, the group of blocks 31 may be regarded as undergoing a step-distributed normal use process corresponding to the step-distributed Program and Erase Count (PEC). The embodiment is illustrated with flash memory 30 of consumer grade and industry standard grade, wherein the first temperature range may be 0-70 ℃ and the second temperature range may be-40-85 ℃. In other embodiments, the specific setting of the corresponding temperature interval may be performed according to the classification of the flash memory 30.
Referring to fig. 1 and 3, in one embodiment of the present invention, since the lowest temperature of the second temperature interval is-40 ℃ and the highest temperature is 85 ℃, the temperature conditions are more severe than those of the first temperature interval. After performing the step-distributed Program and Erase Count (PEC) data processing on a certain set of blocks 31, in order to "light and heavy" concept, if a block 31 cannot be used normally in the first temperature interval, the block 31 cannot be used normally in the second temperature interval. Conversely, if a block 31 is not normally used in the second temperature range, it is entirely possible that the block 31 is normally used in the first temperature range. Therefore, it is considered that the block 31 is first subjected to the wide temperature test and the data retention test in the first temperature interval, and then subjected to the wide temperature test and the data retention test in the second temperature interval.
Specifically, for a group of blocks 31, first, the group of blocks 31 may be set to perform a wide temperature test and a data retention test at a first temperature interval. Next, after the group of blocks 31 is subjected to the wide temperature test and the data retention test in the first temperature interval, the group of blocks 31 may be subjected to the erase process. Finally, the set of blocks 31 is subjected to a wide temperature test and a data retention test at a second temperature interval, the second temperature interval including the first temperature interval.
Specifically, the process of performing the wide temperature test and the data retention test on the set of blocks 31 at the first temperature interval and performing the erase process on the set of blocks 31 increases the number of times of Programming and Erasing (PEC) by only a small amount compared to the step distribution of 500, 1000, 2000, 3000. In the embodiment, only by adjusting the first temperature interval and the second temperature interval for a group of blocks 31, the wide temperature test and the data retention test of the group of blocks 31 in the first temperature interval can be obtained, and the wide temperature test and the data retention test of the group of blocks 31 in the second temperature interval can also be obtained. The controller 10 may generate first test data corresponding to the set of blocks 31 in the first temperature interval and second test data corresponding to the second temperature interval. The invention can obtain the maximum service life of the flash memory 30 on the premise of keeping the optimal service performance in different temperature ranges.
In addition, there are slight differences between the different blocks 31, and in this embodiment, there is no need to set up multiple groups of control blocks 31 for testing, i.e. there is no need to set up a first temperature interval for the first group of blocks 31 for testing, and there is no need to set up a second temperature interval for the second group of blocks 31 for testing.
Referring to fig. 1 and 3, in one embodiment of the present invention, in a certain group of blocks 31, the process of performing data processing on different blocks 31 according to the step distribution of programming and erasing times by the controller 10 may be as follows.
Specifically, as shown in fig. 3, the front, middle and rear three blocks 31 may be selected from one flash memory 30, and may be denoted as three sets of blocks 31. In a step distribution of a set of blocks 31 corresponding to the number of programming and erasing times, the step distribution includes a plurality of step segments. In a certain step, the controller 10 performs data processing on two adjacent blocks 31 according to the gradient step number which is a non-zero constant corresponding to the difference between the programming and erasing times.
Specifically, in the step of programming and erasing times (PEC) of 1 to 1000 in a certain group of blocks 31, the controller 10 performs data processing on the blocks 31 according to the programming and erasing times (PEC) of 500 steps. In the step of programming and erasing times (PEC) of 1000-2000 in a certain group of blocks 31, the controller 10 performs data processing on the blocks 31 according to the step number of 200. In the step of programming and erasing times (PEC) of 2000-3000 in a certain group of blocks 31, the controller 10 performs data processing on the blocks 31 according to the programming and erasing times (PEC) of 500 steps.
Specifically, in each group of blocks 31, the number of program and erase times (PEC) for the first block 31 wear may be 3000, the number of program and erase times (PEC) for the second block 31 wear may be 2500, and the number of program and erase times (PEC) for the third block 31 wear may be 2000. The fourth block 31 is worn out with a Program and Erase Count (PEC) of 1800, and the following blocks 31 are worn out with a gradient of 200 steps until the eighth block 31 is worn out with a Program and Erase Count (PEC) of 1000. The ninth block 31 is worn out by a Program and Erase Count (PEC) of 500, and the subsequent blocks 31 are worn out by a gradient of 500 steps until the tenth block 31 is worn out by a Program and Erase Count (PEC) of 1.
Referring to fig. 1, in one embodiment of the present invention, the controller 10 records the maximum Program and Erase Count (PEC) of a block 31 without error data under the wide temperature test as the wide temperature count in the first temperature interval or the second temperature interval. In the first temperature interval or the second temperature interval, the controller 10 records the maximum programming and erasing times (PEC) of the block 31 without error data as the data retention times under the data retention test. The controller 10 compares the number of times of the wide temperature and the number of times of the data holding, and records the minimum value of the number of times of the wide temperature and the number of times of the data holding as the maximum service life of the first test data or the second test data.
Referring to fig. 1, in an embodiment of the present invention, the controller 10 performs a test of high temperature erasing, high Wen Douqu, or high temperature erasing, low temperature reading, or low temperature erasing, high Wen Douqu, or low temperature erasing, low temperature reading on a certain group of blocks 31 in the first temperature interval or the second temperature interval, respectively. And respectively recording the maximum programming and erasing times of the data without errors in the test as high-temperature writing and high-temperature reading times, high-temperature writing and low-temperature reading times, low-temperature writing and high-temperature reading times and low-temperature writing and low-temperature reading times. And recording the minimum value of the high-temperature writing and high-temperature reading times, the high-temperature writing and low-temperature reading times, the low-temperature writing and high-temperature reading times and the low-temperature writing and low-temperature reading times as the wide-temperature times.
Specifically, the first temperature range is 0-70 ℃ and the second temperature range is-40-85 ℃. Since the processing procedures of the wide temperature test corresponding to the first temperature section and the second temperature section are the same, the difference is only that the highest temperature value and the lowest temperature value are different, and therefore, the wide temperature test of the second temperature section will be specifically described below as an example.
High temperature erasing, high Wen Douqu test after a set of blocks 31 is subjected to step-distributed Program and Erase Count (PEC) data processing, first, the set of blocks 31 is placed in an 85 ℃ incubator 20, and after 10min, high Wen Ca writing at 85 ℃ is performed, and the test data is 0x3CC35AA5. Next, the number of Error bits (Error Bit Count) occurring in the set of blocks 31 is read and detected, and it is determined whether the number of Error bits exceeds the Error correction threshold of the controller 10, and is recorded as an Error correction code (UECC, uncorrectable Error Correction Code) when the number of Error bits in the blocks 31 exceeds the Error correction threshold. If an error correction code is present in a block 31, it indicates that the corresponding program and erase times (PEC) of that block 31 cannot be subjected to the high temperature erase and write, high Wen Douqu test. In contrast, if no error correction code is present in a block 31, the corresponding program and erase times (PEC) of that block 31 are able to withstand the high temperature erase and write test, high Wen Douqu. In this test, the maximum program and erase times (PEC) without error correction code is the maximum lifetime in this scenario.
The low temperature erasing and writing, low Wen Douqu test, after a group of blocks 31 is processed by step-distributed programming and erasing times (PEC) data, firstly, the group of blocks 31 is put into a-40 ℃ incubator 20, and after 10min, the low temperature erasing and writing of-40 ℃ is performed, and the test data is 0x3CC35AA5. Next, the number of Error bits (Error Bit Count) occurring in the set of blocks 31 is read and detected, and it is determined whether the number of Error bits exceeds the Error correction threshold of the controller 10, and is recorded as an Error correction code (UECC, uncorrectable Error Correction Code) when the number of Error bits in the blocks 31 exceeds the Error correction threshold. If an error correction code is present in a block 31, it indicates that the corresponding program and erase times (PEC) of the block 31 cannot be subjected to the low temperature erase and write, low temperature read test. In contrast, if no error correction code is present in a block 31, the corresponding program and erase times (PEC) of that block 31 are capable of being subjected to low temperature erase and write, low temperature read tests. In this test, the maximum program and erase times (PEC) without error correction code is the maximum lifetime in this scenario.
High temperature erasing, low Wen Douqu test after a set of blocks 31 is subjected to step-distributed Program and Erase Count (PEC) data processing, first, the set of blocks 31 is placed in an 85 ℃ incubator 20, after 10min, high Wen Ca writing at 85 ℃ is performed, and the test data is 0x3CC35AA5. Next, the set of blocks 31 is placed in the incubator 20 at-40 ℃, the number of Error bits (Error Bit Count) occurring in the set of blocks 31 is read and detected, and it is determined whether the number of Error bits exceeds the Error correction threshold of the controller 10, and an Error correction code (UECC, uncorrectable Error Correction Code) is recorded when the number of Error bits in the block 31 exceeds the Error correction threshold. If an error correction code is present in a block 31, it indicates that the corresponding program and erase times (PEC) of that block 31 cannot be subjected to high temperature erase, low temperature read test. In contrast, if no error correction code is present in a block 31, the corresponding program and erase times (PEC) of that block 31 are subject to high temperature erase and write, low temperature read tests. In this test, the maximum program and erase times (PEC) without error correction code is the maximum lifetime in this scenario.
The low temperature erasing and writing, low Wen Douqu test, after a group of blocks 31 is processed by step-distributed programming and erasing times (PEC) data, firstly, the group of blocks 31 is put into a-40 ℃ incubator 20, and after 10min, the low temperature erasing and writing of-40 ℃ is performed, and the test data is 0x3CC35AA5. Next, the set of blocks 31 is placed in the 80 ℃ incubator 20, the number of Error bits (Error Bit Count) occurring in the set of blocks 31 is read and detected, and it is determined whether the number of Error bits exceeds the Error correction threshold of the controller 10, and an Error correction code (UECC, uncorrectable Error Correction Code) is recorded when the number of Error bits in the block 31 exceeds the Error correction threshold. If an error correction code is present in a block 31, it indicates that the corresponding program and erase times (PEC) of the block 31 cannot be subjected to the low temperature erase and write, high Wen Douqu test. In contrast, if no error correction code is present in a block 31, the corresponding program and erase times (PEC) of that block 31 are tested for low temperature erasure, high Wen Douqu. In this test, the maximum program and erase times (PEC) without error correction code is the maximum lifetime in this scenario.
And respectively performing the high-temperature erasing and writing, the high-Wen Douqu testing, the high-temperature erasing and writing, the low-temperature reading testing and the low-temperature erasing and writing, and selecting minimum programming and erasing times (PEC) without error correction codes in each scene, and respectively recording the minimum programming and erasing times, the high-temperature writing and high-temperature reading times, the high-temperature writing and low-temperature reading times, the low-temperature writing and high-temperature reading times and the low-temperature writing and low-temperature reading times. The controller 10 compares the high temperature writing and high temperature reading times, the high temperature writing and low temperature reading times, the low temperature writing and high temperature reading times and the low temperature writing and low temperature reading times, and marks the minimum value of the high temperature writing and high temperature reading times, the high temperature writing and low temperature reading times, the low temperature writing and high temperature reading times and the low temperature writing and low temperature reading times as the wide temperature times of the second temperature interval.
Referring to fig. 1, in an embodiment of the present invention, the controller 10 performs high temperature erasing or low temperature erasing processing on a certain group of blocks 31 in a first temperature interval or a second temperature interval, and performs high temperature reading verification and low temperature reading verification on a certain group of blocks 31 under a preset data holding temperature and data holding time. The maximum programming and erasing times (PEC) of the read-verify without error data are respectively recorded as high-temperature erasing and writing maintaining times and low-temperature erasing and writing maintaining times. And recording the minimum value of the high-temperature erasing and writing maintaining times and the low-temperature erasing and writing maintaining times as the data maintaining times.
Specifically, for high temperature erasing, the high temperature read check and the low temperature read check are performed at the data holding temperature and the data holding time as follows. After a set of blocks 31 is subjected to a stepwise distributed Program and Erase Count (PEC) data process, the set of blocks 31 is first placed in an 85 ℃ incubator 20, and after 10 minutes, subjected to a 85 ℃ high Wen Ca write, with test data of 0x3CC35AA5. Next, the set of blocks 31 is put into the incubator 20 at 125 ℃ for power-off baking, and the time period can be confirmed according to the time calculated by the temperature acceleration coefficient. After the accelerated baking is finished, the block 31 is put into an incubator 20 at 85 ℃ for 10min and then is read and checked, and whether error correction codes appear in the block 31. Finally, the set of blocks 31 is placed in the incubator 20 at-40 ℃ for 10min, and then read-checking is performed to detect whether the error correction code appears in the set of blocks 31. The read checks were performed in incubators 20 at-40 ℃ and 85 ℃ and the maximum program and erase times (PEC) of the error correction code were not present for both read checks, noted as the high temperature erase-write retention times.
Specifically, for the low-temperature erasing, the high-temperature read check and the low-temperature read check are performed at the data holding temperature and the data holding time as follows. After a set of blocks 31 is subjected to step-distributed Program and Erase Count (PEC) data processing, the set of blocks 31 is first placed in a-40 ℃ incubator 20, and after 10 minutes, subjected to-40 ℃ low temperature erasure, with test data of 0x3CC35AA5. Next, the set of blocks 31 is put into the incubator 20 at 125 ℃ for power-off baking, and the time period can be confirmed according to the time calculated by the temperature acceleration coefficient. After the accelerated baking is finished, the block is put into an incubator 20 at-40 ℃ for 10min, and then read and verification is carried out to detect whether error correction codes appear on the group of blocks 31. Finally, the set of blocks 31 is placed in the incubator 20 at 85 ℃ for 10min, and then read-checking is performed to detect whether the error correction code appears in the set of blocks 31. The read checks were performed in incubators 20 at-40 ℃ and 85 ℃ and the maximum program and erase times (PEC) of the error correction code were not present for both read checks, noted as the low temperature erase-write retention times.
Specifically, the controller 10 compares the high temperature erasing and writing maintaining times and the low temperature erasing and writing maintaining times, and records the minimum value of the high temperature erasing and writing maintaining times and the low temperature erasing and writing maintaining times as the data maintaining times, which is the maximum service life in the scene.
Referring to fig. 1, in one embodiment of the present invention, a group of blocks 31 has different data retention times at different data retention temperatures, and the ratio between the different data retention times is the temperature acceleration coefficientThe method comprises the following steps:
;
;
Wherein, In order for the reaction rate constant to be constant,Is the Arrhenius constant of the Arrhenius,In order to react the activation energy of the reaction,The numerical value of (2) is 1.1,Is a boltzmann constant,The numerical value of (2) is 8.62X10 -5 ,In the case of a thermodynamic temperature of the material,Is a natural logarithmic base.At the first temperature of the material to be treated,At the temperature of the second temperature of the first temperature,In order to be a temperature acceleration coefficient,Is thatThe corresponding reaction rate constant is used to determine,Is thatA corresponding reaction rate constant.
In particular, whenTable 1 can be calculated at 30 ℃.
TABLE 1 temperature acceleration coefficient table for data retention temperature and data retention time
As can be seen from table 1, the data retention time can be measured at high temperature, and then calculated at normal temperature by the above formula. Therefore, the corresponding data retention time at each temperature can be obtained rapidly, and the test in a normal temperature environment is not needed, so that the test time required by different data retention temperatures is shortened greatly. As can be seen from table 1, the corresponding data retention time at 30 ℃ is calculated to be one year, the oven 20 with a high temperature of 125 ℃ can be used for acceleration, and the time period required for the acceleration test can be specifically calculated according to the above formula.
After performing the above-mentioned wide temperature test and data retention test on a certain group of blocks 31 in the first temperature interval or the second temperature interval, the controller 10 compares the number of wide temperature times with the number of data retention times, and marks the minimum value of the number of wide temperature times and the number of data retention times as the maximum service life of the first test data or the second test data.
Therefore, the maximum difference between the consumer grade flash memory 30 and the industry standard grade flash memory 30 is that the range of working temperature is different, the consumer grade flash memory 30 is 0-70 ℃, and the industry standard grade flash memory 30 is-40-85 ℃. Secondly, the requirements for data retention time are different, the consumer grade flash memory 30 is mostly kept at 30 ℃ for one year, and the industry standard flash memory 30 is mostly kept at 55 ℃ for one year. The quality of the flash memory 30 is mainly affected by the number of programming and erasing times (PEC). The ability to store charge is greater when the program and erase times (PEC) are smaller, i.e., when the flash memory 30 is newer, which is why the consumer grade flash memory 30 is able to pass the wide temperature test early in its life. However, as the number of programming and erasing times (PEC) increases, the ability of flash memory 30 to store charge decreases, and this effect is irreversible and can severely impact endurance of the wide temperature test and the data retention test.
Therefore, the present invention can obtain the maximum service life of the flash memory 30 on the premise of maintaining the optimal service performance in different temperature ranges. The present embodiment can quickly determine the defect level flash memory 30 as the lifetime of the specification level flash memory 30. Therefore, the problem of reduced service performance of the consumer grade flash memory 30 caused by the fact that the consumer grade flash memory 30 is regarded as the industry standard grade flash memory 30 is solved, the service life of the consumer grade flash memory 30 is sacrificed, the requirements for supporting the industry standard grade flash memory 30 in the whole service period are replaced, and the yield of the flash memory 30 can be controlled. The embodiment can synchronously realize the abrasion threshold analysis of the 'consumption level' standard flash memory 30 and the abrasion threshold analysis of the 'engineering level' standard flash memory 30, thereby greatly saving the test and labor cost of the flash memory 30.
Referring to fig. 4, in an embodiment of the present invention, a method for testing a flash memory is provided, which may include the following steps.
Step S10, setting the flash memory in an incubator, and adjusting the temperature range around the flash memory by the incubator, wherein the flash memory comprises a plurality of groups of blocks.
In one embodiment of the present invention, a flash memory 30 may be provided within the incubator 20, and the temperature range around the flash memory 30 may be adjusted by the incubator 20. Flash memory 30 may be a flash memory pellet, which is a non-volatile memory that is typically used to store host data, system programs, and the like. The flash memory 30 may include a plurality of blocks (blocks) 31, and the blocks 31 may be used to store host data written by the controller 10, and one Block 31 may further include a plurality of pages (pages). The block 31 is an erase unit of host data on the flash memory 30, and the page is a read unit of host data on the flash memory 30.
In step S20, in a certain group of blocks, data processing is performed on different blocks according to the program and erase times distributed in steps, where one program and erase time indicates that a block is subjected to write-once and erase processing.
In one embodiment of the present invention, the controller 10 performs data processing on the partial blocks 31 according to the first gradient of the program and erase times (PEC) in the step distribution of 1 to 1000 of the program and erase times (PEC) in a certain group of the blocks 31. In a step distribution of 1000 to 2000 program and erase times (PEC) in a certain group of blocks 31, the controller 10 performs data processing on a part of the blocks 31 according to a second gradient of program and erase times (PEC). In a step distribution of 2000 to 3000 program and erase times (PEC) in a certain group of blocks 31, the controller 10 performs data processing on a portion of the blocks 31 according to a third gradient of program and erase times (PEC).
Step S30, after the step distribution programming and erasing times data processing is performed on a certain group of blocks, a wide temperature test and a data retention test are performed on a certain group of blocks in a first temperature interval.
In one embodiment of the present invention, since the minimum temperature of the second temperature interval is-40 ℃ and the maximum temperature is 85 ℃, the temperature conditions are more severe than those of the first temperature interval. After performing the step-distributed Program and Erase Count (PEC) data processing on a certain set of blocks 31, in order to "light and heavy" concept, if a block 31 cannot be used normally in the first temperature interval, the block 31 cannot be used normally in the second temperature interval. Conversely, if a block 31 is not normally used in the second temperature range, it is entirely possible that the block 31 is normally used in the first temperature range. Therefore, it is considered that the block 31 is first subjected to the wide temperature test and the data retention test in the first temperature interval, and then subjected to the wide temperature test and the data retention test in the second temperature interval.
Step S40, erasing a group of blocks, and performing a wide temperature test and a data retention test on a group of blocks in a second temperature interval, wherein the second temperature interval comprises the first temperature interval.
In one embodiment of the present invention, for a group of blocks 31, first, the group of blocks 31 may be set at a first temperature interval for a wide temperature test and a data retention test. Next, after the group of blocks 31 is subjected to the wide temperature test and the data retention test in the first temperature interval, the group of blocks 31 may be subjected to the erase process. Finally, the set of blocks 31 is subjected to a wide temperature test and a data retention test at a second temperature interval, the second temperature interval including the first temperature interval.
Step S50, generating first test data corresponding to a group of blocks in a first temperature interval and second test data corresponding to a group of blocks in a second temperature interval.
In one embodiment of the present invention, the process of performing the wide temperature test and the data retention test on the set of blocks 31 at the first temperature interval and performing the erase process on the set of blocks 31 increases the number of times of Programming and Erasing (PEC) by only a small amount compared to the step distribution of 500, 1000, 2000, 3000. In the embodiment, only by adjusting the first temperature interval and the second temperature interval for a group of blocks 31, the wide temperature test and the data retention test of the group of blocks 31 in the first temperature interval can be obtained, and the wide temperature test and the data retention test of the group of blocks 31 in the second temperature interval can also be obtained. The controller 10 may generate first test data corresponding to the set of blocks 31 in the first temperature interval and second test data corresponding to the second temperature interval.
In addition, there are slight differences between the different blocks 31, and in this embodiment, there is no need to set up multiple groups of control blocks 31 for testing, i.e. there is no need to set up a first temperature interval for the first group of blocks 31 for testing, and there is no need to set up a second temperature interval for the second group of blocks 31 for testing.
Referring to fig. 5, in one embodiment of the present invention, step S30 may include step S310, step S320 and step S330, and step S310 may be represented as counting the maximum number of programming and erasing times of a group of blocks 31 without error data under the wide temperature test as the wide temperature number. Step S320 may be expressed as recording the maximum number of times of programming and erasing that a certain group of blocks 31 has no error data under the data retention test as the number of times of data retention. Step S330 may represent the minimum value of the number of times of wide temperature and the number of times of data retention as the maximum service life in the first test data.
Referring to fig. 6, in one embodiment of the present invention, step S310 may include step S311, step S312, and step S313, where step S311 may be represented as a test of high temperature erasing, high Wen Douqu, or high temperature erasing, low temperature reading, or low temperature erasing, high Wen Douqu, or low temperature erasing, low temperature reading of a certain group of blocks 31 in the first temperature interval. Step S312 may be expressed as the maximum programming and erasing times of the data without error in the above test, which are respectively recorded as the high temperature writing and high temperature reading times, the high temperature writing and low temperature reading times, the low temperature writing and high temperature reading times, and the low temperature writing and low temperature reading times. Step S313 may be expressed as a minimum value of the high temperature write high temperature read number, the high temperature write low temperature read number, the low temperature write high temperature read number, and the low temperature write low temperature read number, which is denoted as a wide temperature number.
In summary, the present invention provides a testing system and a testing method for a flash memory, which can obtain the maximum service life of the flash memory under the premise that the flash memory maintains the optimal service performance in different temperature ranges. The embodiment can generate the first test data corresponding to the block in the first temperature interval and the second test data corresponding to the block in the second temperature interval. The first test data and the second test data are only increased by one time of programming and erasing, and the influence is very little. The invention can synchronously realize the abrasion threshold analysis of the 'consumption level' standard flash memory and the abrasion threshold analysis of the 'engineering standard' standard flash memory, thereby greatly saving the test and labor cost of the flash memory.
The flowcharts and block diagrams in the figures illustrate the architecture, functionality, and operation of possible implementations of methods and computer program products according to various embodiments of the present disclosure. In this regard, each block in the flowchart or block diagrams may represent a module, segment, or portion of code, which comprises one or more executable instructions for implementing the specified logical function(s). It should also be noted that, in some alternative implementations, the functions noted in the block may occur out of the order noted in the figures. For example, two blocks shown in succession may, in fact, be executed substantially concurrently, or the blocks may sometimes be executed in the reverse order, depending upon the functionality involved. It will also be noted that each block of the block diagrams and/or flowchart illustration, and combinations of blocks in the block diagrams and/or flowchart illustration, can be implemented by special purpose hardware-based systems which perform the specified functions or acts, or combinations of special purpose hardware and computer instructions.
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