CN118611810A - Synchronous processing method, device and electronic device based on data interface - Google Patents

Abstract

The present disclosure provides a synchronization processing method based on a data interface. A first device communicates with multiple second devices through a data interface, wherein the first device runs multiple master clock programs, and the method includes: sending first time information and second time information to at least one second device, wherein the first time information represents the moment when the master clock program sends a first data packet to the data interface, and the second time information represents the moment when the second device sends a first synchronization data packet to the data interface. Clock synchronization is performed on multiple second devices according to the first time information and the second time information. The data interface is used to identify a control field in a first data packet, or to add a control field to a first synchronization data packet to obtain a second data packet. The control field is used to control the data interface to timestamp the first data packet and the second data packet, and to record the port address of the second device.

Description

Synchronous processing method, device and electronic device based on data interface

Technical Field

The present disclosure relates to the technical field of clock synchronization, and in particular to a synchronization processing method, device and electronic device based on a data interface.

Background Art

In a digital communication network, data communication equipment places pulses in specific time slots when sending digital pulse signals through the signal transmitter, and the receiver must be able to extract the pulses in specific time slots to ensure normal communication between the transmitter and the receiver. Keeping the clocks of the signal transmitter and the receiver consistent is a prerequisite for normal and accurate communication between the two parties.

However, in the current clock synchronization process, the master clock device and the slave clock device are bound to independent network interfaces to work. In the scenario of message multicast, it is difficult to determine the target device when sharing a network interface.

Summary of the invention

One aspect of the present disclosure provides a synchronization processing method based on a data interface, wherein a first device communicates with multiple second devices via a data interface, wherein the first device runs multiple master clock programs, and the method comprises: sending first time information and second time information to at least one second device, wherein the first time information represents the moment when the master clock program sends a first data packet to the data interface, and the second time information represents the moment when the second device sends a first synchronization data packet to the data interface. Clock synchronization is performed on multiple second devices according to the first time information and the second time information. The data interface is used to identify a control field in a first data packet, or to add a control field to a first synchronization data packet to obtain a second data packet. The control field is used to control the data interface to timestamp the first data packet and the second data packet, and to record the port address of the second device.

Optionally, the data interface is a hardware interface for timestamping the data packet, and sending the first time information and the second time information to the at least one second device comprises: in response to identifying the first control field of the first data packet, inserting the first time stamp in a second synchronization data packet of the first data packet. According to the port address, sending the second synchronization data packet containing the first time stamp to at least one of the plurality of second devices. In response to adding the second control field to the first synchronization data packet, inserting the second time stamp in the second control field. And sending the second synchronization data packet containing the second time stamp to at least one of the plurality of second devices according to the port address.

Optionally, a precision time protocol is used to synchronize the clocks of the first device and the second device, and the first data packet includes an event message and a general message.

Optionally, the general message does not include a following message.

Optionally, the first control field includes a timestamp insertion bit, a timestamp operation bit, and a timestamp storage bit. In response to identifying the first control field of the first data packet, inserting the first timestamp in the second synchronization data packet of the first data packet includes: in the case where the general message does not include a follow-up message, in response to identifying the first control field of the event message, setting the timestamp insertion bit and the timestamp operation bit, and inserting the first timestamp into the second synchronization data packet of the event message. Or in the case where the general message includes a follow-up message, in response to identifying the first control field of the event message, setting the timestamp storage bit and the timestamp operation bit, and saving the first timestamp to a register. In response to sending the follow-up message, reading the first timestamp from the register, and inserting the first timestamp into the second synchronization data packet of the follow-up message.

Optionally, the second control field includes a timestamp reception bit, and in response to adding the second control field to the first synchronization data packet, inserting the second timestamp in the second control field includes: in response to adding the second control field to the first synchronization data packet, setting the timestamp reception bit and the timestamp operation bit, and inserting the second timestamp into the second control field.

Optionally, the control field includes a data direction bit, a channel ID bit, a data type bit, and a spare bit. The data direction bit is used to control the transmission direction of the first data packet and the second data packet. The channel ID bit is used to record the port address. The data type bit is used to limit the network type corresponding to the first data packet and the second data packet. And the spare bit is used for data expansion or data alignment.

Optionally, a first timestamp is inserted into the second synchronization data packet and a second timestamp is inserted into the second control field through the FPGA.

Another aspect of the present disclosure provides a synchronization processing device based on a data interface, wherein a first device communicates with multiple second devices through a data interface, wherein the first device runs multiple master clock programs, and the device includes: a sending module, used to send first time information and second time information to at least one second device, wherein the first time information represents the moment when the master clock program sends a first data packet to the data interface, and the second time information represents the moment when the second device sends a first synchronization data packet to the data interface. A calibration module, used to perform clock synchronization on multiple second devices according to the first time information and the second time information. The data interface is used to identify a control field in a first data packet, or to add a control field to a first synchronization data packet to obtain a second data packet. The control field is used to control the data interface to timestamp the first data packet and the second data packet, and to record the port address of the second device.

Another aspect of the present disclosure provides an electronic device, comprising: one or more processors; and a memory for storing one or more programs, wherein when the one or more programs are executed by the one or more processors, the one or more processors execute any one of the above-mentioned synchronization processing methods based on the data interface.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present disclosure will become more apparent through the following description of the embodiments of the present disclosure with reference to the accompanying drawings, in which:

FIG1 schematically shows an application scenario diagram of a synchronization processing method based on a data interface according to an embodiment of the present disclosure;

FIG2 schematically shows a flow chart of a synchronization processing method based on a data interface according to an embodiment of the present disclosure;

FIG3 schematically shows a flow chart of a method for sending time information to a second device according to an embodiment of the present disclosure;

FIG4 schematically shows a flow chart of a method for inserting a first timestamp according to an embodiment of the present disclosure;

FIG5 schematically shows a format diagram of a data packet in a sending direction according to an embodiment of the present disclosure;

FIG6 schematically shows a flow chart of a method for inserting a second timestamp according to an embodiment of the present disclosure;

FIG7 schematically shows a format diagram of a receiving direction data packet according to an embodiment of the present disclosure;

FIG8 schematically shows a flow chart of sending and receiving data packets according to an embodiment of the present disclosure;

FIG9 schematically shows a structural block diagram of a synchronization processing device based on a data interface according to an embodiment of the present disclosure;

FIG10 schematically shows a block diagram of an electronic device suitable for implementing a synchronization processing method based on a data interface according to an embodiment of the present disclosure.

DETAILED DESCRIPTION

Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are exemplary only and are not intended to limit the scope of the present disclosure. In addition, in the following description, descriptions of well-known structures and technologies are omitted to avoid unnecessary confusion of the concepts of the present disclosure.

The terms used herein are only for describing specific embodiments and are not intended to limit the present disclosure. The terms "include", "comprising", etc. used herein indicate the existence of the features, steps, operations and/or components, but do not exclude the existence or addition of one or more other features, steps, operations or components.

All terms (including technical and scientific terms) used herein have the meanings commonly understood by those skilled in the art unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

Some block diagrams and/or flow charts are shown in the accompanying drawings. It should be understood that some blocks or combinations thereof in the block diagrams and/or flow charts may be implemented by computer program instructions. These computer program instructions may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that these instructions, when executed by the processor, may create a device for implementing the functions/operations described in these block diagrams and/or flow charts.

Therefore, the technology of the present disclosure can be implemented in the form of hardware and/or software (including firmware, microcode, etc.). In addition, the technology of the present disclosure can take the form of a computer program product on a computer-readable medium storing instructions, which can be used by an instruction execution system or in combination with an instruction execution system. In the context of the present disclosure, a computer-readable medium can be any medium that can contain, store, transmit, propagate, or transmit instructions. For example, a computer-readable medium can include, but is not limited to, an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, device, device, or propagation medium. Specific examples of computer-readable media include: magnetic storage devices, such as magnetic tape or hard disk (HDD); optical storage devices, such as compact disk (CD-ROM); memory, such as random access memory (RAM) or flash memory; and/or wired/wireless communication links.

An embodiment of the present disclosure provides a data interface-based synchronization processing method for clock synchronization. The method includes sending first time information and second time information to at least one second device, wherein the first time information represents the moment when the master clock program sends a first data packet to the data interface, and the second time information represents the moment when the second device sends a first synchronization data packet to the data interface. Based on the first time information and the second time information, clock synchronization is performed on multiple second devices. By adding a control field recording the port address of the second device in front of the first synchronization data packet, the data packet can be accurately sent to the corresponding second device when multiple second devices share a network interface, which greatly simplifies the network connection relationship.

FIG1 schematically shows an application scenario diagram of a synchronization processing method based on a data interface according to an embodiment of the present disclosure.

As shown in Fig. 1, the application scenario 100 according to this embodiment may include a first device 101, a first network interface 102, second devices 103, 104, 105 and second network interfaces 106, 107, 108. The first device 101 is, for example, a master clock device, including multiple master clock programs 1011, 1012, 1013, each of which can independently serve as a clock source to synchronize the clocks of the second devices 103, 104, 105.

The master clock device can be, for example, a hardware clock server, a software clock server, and a distributed clock system. The master clock program can be, for example, a program that supports the NTP (Network Time Protocol) protocol and the PTP (Precision Time Protocol) protocol. Multiple NTP or PTP servers can be used to form a clock cluster, and a specific algorithm (such as the best master clock algorithm) can be used to select the most reliable and accurate time source. In addition, heartbeat detection and failover mechanisms can be implemented to ensure that when the master clock device fails, the backup device can quickly take over and provide time services.

The second devices 103, 104, 105 are, for example, slave clock devices, which may be network slave clocks (such as routers, switches, servers, etc.), device built-in slave clocks (such as computers, smart phones, tablet computers, etc.), dedicated slave clock devices (such as in industrial automation systems, it may be necessary to use slave clock devices with high-precision time synchronization functions to ensure time consistency between various sensors, actuators and other devices) and distributed slave clock systems composed of multiple slave clock devices.

The first network interface 102 and the second network interface 106, 107, 108 can, for example, use an FPGA to timestamp the data packets between the first device 101 and the second devices 103, 104, 105, or other devices such as a network interface card (NIC), a network monitor, a network analyzer, etc. can be used to timestamp the data packets between the first device 101 and the second devices 103, 104, 105. Among them, the relevant data packets between the first device 101 and the second devices 103, 104, 105, for example, include a target port address and a control field for controlling the timestamping operation. The FPGA or other device timestamps the passing data packets by identifying the control field and sends them to the target device.

First, the related terms of the embodiments of the present disclosure are explained as follows:

HPS (High Performance Switch) is a high-performance switch with the characteristics of high-speed data transmission, low latency, and high reliability. It is often used in large-scale data centers, cloud computing, high-performance computing and other fields.

SFP (Small Form-factor Pluggable) is a small pluggable optical module commonly used in fiber optic communication networks. The SFP module is an independent standard package that can be inserted into the fiber optic module slot of a switch or other device to achieve high-speed data transmission.

GMII (Gigabit Media Independent Interface) is an Ethernet physical layer interface specification used to connect Ethernet physical layer devices (such as network cards) and Ethernet controllers. GMII uses 8-bit parallel data transmission, with a data transmission rate of up to 1000Mbps, supports full-duplex mode, and can receive and send data at the same time. GMII defines specifications for both data interface and physical interface. The data interface includes data lines and control lines for transmitting data and control signals; the physical interface includes TX (transmit) and RX (receive) data lines, clock lines, and power lines. Through the GMII interface, the Ethernet controller can perform high-speed data transmission with the physical layer device to achieve network communication.

Netlink is a method for implementing communication between the kernel and user space in Linux. Data is transmitted between the two in the form of network packets. It is an asynchronous full-duplex communication method that supports active communication initiated by the kernel state. The kernel provides a set of special API interfaces for Netlink communication, and the user state is based on the socket API. The data sent by the kernel will be saved in the receiving process socket's receiving buffer and processed by the receiving process.

The Ethernet packet is a packet format used to transmit data in a local area network. It consists of a series of fields, including the destination address, source address, protocol type, data, etc. The destination address of the Ethernet packet is the destination MAC address of the data packet, the source address is the source MAC address of the data packet, the protocol type field indicates the type of the upper layer protocol, and the data field contains the data of the transport layer and the application layer.

FPGA is the abbreviation of Field Programmable Gate Array, which is a further development of programmable devices such as PAL, GAL, EPLD, etc. It appears as a semi-custom circuit in the field of application-specific integrated circuits (ASICs), which not only solves the shortcomings of custom circuits, but also overcomes the shortcomings of limited gate circuits of original programmable devices.

Based on the scenario described in FIG. 1 , the synchronization processing method based on the data interface of the disclosed embodiment will be described in detail below through FIGS. 2 to 8 .

FIG2 schematically shows a flow chart of a synchronization processing method based on a data interface according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, a first device communicates with multiple second devices via a data interface, wherein the first device runs multiple master clock programs, as shown in FIG. 2 . The synchronization processing method based on the data interface of this embodiment, for example, includes operations S210 to S220.

In operation S210, first time information and second time information are sent to at least one second device, wherein the first time information represents the moment when the master clock program sends a first data packet to the data interface, and the second time information represents the moment when the second device sends a first synchronization data packet to the data interface.

In operation S220, clock synchronization is performed on multiple second devices according to the first time information and the second time information. The data interface is used to identify a control field in the first data packet, or to add a control field to the first synchronization data packet to obtain a second data packet. The control field is used to control the data interface to timestamp the first data packet and the second data packet, and to record the port address of the second device.

In some embodiments, the synchronization process may be performed based on an Ethernet data interface.

For example, the first device is a main server in a data center, which runs two main clock programs: clock A and clock B. The main server is connected to multiple second devices (such as servers, storage devices, etc.) through an Ethernet interface.

Sending time information:

When sending a data packet to the Ethernet interface (ie, the first network interface), clock A records the current timestamp t ₁ (indicating the time when the master clock program sends the first data packet to the data interface).

At the same time, when a second device (such as server S1) responds to the request of clock A and sends a synchronization data packet back to the Ethernet interface, the interface recognizes that this is a synchronization data packet and records the current timestamp _t4 (indicating the time when the second device sends the first synchronization data packet to the data interface).

Timestamp and port number:

The Ethernet interface recognizes or adds a control field in the data packet, which is represented by a specific bit combination and is used to indicate that the interface needs to timestamp the data packet.

When a data packet passes through an Ethernet interface, the interface not only timestamps the data packet, but also records the MAC address or IP address of the second device that sends or receives the data packet. This information can be considered as a substitute for the port address.

Clock synchronization:

The second device collects synchronization data packets sent by the first device multiple times and their corresponding timestamp information.

Using these timestamp information, the second device can calculate the network delay and clock offset, and adjust the clock accordingly to achieve synchronization with the clock of the first device.

It should be noted that when the first device sends a data packet to the network interface of the second device (i.e., the second network interface), the second network interface will also timestamp the arriving data packet with t ₂ , and when the data packet sent by the second device to the first device arrives at the second network interface, the second network interface will also timestamp the arriving data packet with t ₃ . The second device can calculate the network delay and clock offset based on t ₁ , t ₂ , t ₃ , and t ₄ , and adjust the clock accordingly to achieve clock synchronization with the first device. Since t ₂ and t ₃ are recorded by the second device itself, they are not mentioned in the above operation.

The method disclosed in the present invention can also perform data synchronization based on a serial interface.

In another scenario, the first device is, for example, an industrial control device that is connected to a plurality of sensors and other devices using a serial interface (eg, RS-485).

Sending time information:

Similarly, the master clock program records a timestamp t ₁ when sending data to the serial interface, and the serial interface records a timestamp t ₄ when receiving a synchronization data packet from a second device (eg, sensor S2 ).

Timestamp and port number:

The serial interface identifies the synchronization data packet through specific control signals or protocol fields and timestamps the beginning or end of the data packet.

Since a serial interface usually has no direct concept of a port address, it may use the device's ID or serial number as identification.

Clock synchronization:

The second device collects the timestamp information and adjusts accordingly to synchronize with the clock of the first device.

The above two embodiments demonstrate synchronization processing methods based on different data interfaces. Whether it is an Ethernet interface or a serial interface, it includes sending time information, stamping timestamps and recording device identification at the data interface, and using this information to achieve clock synchronization. This method can ensure the consistency of time in a multi-device environment, which is particularly important for applications that require high-precision time synchronization (such as financial transactions, network communications, industrial automation, etc.).

In addition to operations S210 to S220 described above with reference to Fig. 2, the method of this embodiment also includes operations S311 to S314. For the sake of brevity, the description of operations S210 to S220 is omitted here, and the subsequent related method embodiments are similar and will not be repeated.

FIG3 schematically shows a flow chart of a method for sending time information to a second device according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, the data interface is a hardware interface for timestamping a data packet, as shown in FIG. 3 , for example, by operating S311 to S314 to send first time information and second time information to at least one second device.

In operation S311, in response to identifying a first control field of a first data packet, a first time stamp is inserted into a second synchronization data packet of the first data packet.

In operation S312, a second synchronization data packet including a first timestamp is sent to at least one of the plurality of second devices according to the port address.

In operation S313, in response to adding the second control field to the first synchronization data packet, inserting a second timestamp into the second control field.

In operation S314, a second synchronization data packet including a second timestamp is sent to at least one of the plurality of second devices according to the port address.

In some embodiments, for example, there is a master clock device (first device) that synchronizes time to multiple slave clock devices (second devices) via a network. The master clock device periodically sends data packets that contain information required for time synchronization.

The master clock device includes a specific control field in the data packet sent, which is used to identify that this is a time synchronization data packet. For example, in the first data packet, the control field may be a specific bit or byte sequence, such as 0x1234, indicating that this is a time synchronization request.

When the master-clock device recognizes the control field of the first packet, it inserts the current timestamp in the subsequent portion of the packet (e.g., the second synchronization packet). For example, if the first packet is a TCP or UDP packet, it may contain multiple segments or blocks of data. The master-clock device inserts a timestamp with microsecond or nanosecond accuracy in the second synchronization packet (which may be the payload portion of the packet).

The master clock device knows which slave clock devices need to receive time synchronization information, and sends data packets to the corresponding ports or addresses based on this information. For example, the master clock device has a list of slave clock devices and their respective IP addresses or MAC addresses. It uses the functions of the network layer (such as the IP layer) and the data link layer (such as the Ethernet layer) to send data packets containing timestamps to the specified ports of these devices.

In some cases, the master-clock device may need to send additional synchronization information or acknowledgments. It can do this by adding a new control field to the synchronization packet sent back from the slave-clock device and inserting a new timestamp in this field. For example, the master-clock device may decide to send a packet containing an acknowledgment or additional synchronization information after sending the packet containing the first timestamp. This new packet has a different control field (such as 0x5678) and a new timestamp inserted in it.

Similar to sending the first timestamp, the master-clock device sends a data packet containing the new timestamp to the slave-clock device that needs it. For example, the master-clock device sends an acknowledgment data packet containing the new timestamp to the slave-clock device using a network protocol and address information.

In this example, it is described in detail how a master-clock device sends time synchronization information to a slave-clock device over a network. This includes identifying the control field in the data packet, inserting a timestamp, and sending the data packet based on the device's address information. In this way, the master-clock device can ensure that the slave-clock device has accurate and synchronized time information.

According to an embodiment of the present disclosure, a precision time protocol is used to perform clock synchronization on a first device and a second device, and a first data packet includes an event message and a general message.

In some embodiments, when the Precision Time Protocol (PTP) is used to synchronize the clocks of a first device (master clock device) and a second device (slave clock device), the use of control fields and messages plays a key role in the synchronization process. The following is a specific embodiment of a synchronization method based on PTP.

In PTP, there are two main message types: Event Messages and General Messages. Event Messages are used for timestamp generation and transmission, while General Messages are used for management, configuration, and other communications during synchronization.

The master clock device sends a Sync message to the slave clock device. The Sync message is a key event message in PTP, which is used to trigger the timestamp recording in the slave clock device. The Sync message contains a specific control field, which is used to specify the target slave clock device and insert the timestamp in the Sync message. When the Sync message arrives at the slave clock device, the slave clock device records the timestamp t ₂ of receiving the Sync message at its data interface.

After sending the Sync message, the master clock device immediately sends a Follow_Up message, which contains the timestamp t ₁ when the Sync message was sent. This message is a general message used to transmit time information related to the event message. The Follow_Up message contains a control field for specifying the target slave clock device and inserting the timestamp t ₁ in the Follow_Up message. After receiving the Follow_Up message, the corresponding slave clock device can obtain the t ₁ timestamp.

After the slave clock device records the timestamp t ₂ , it sends a Delay_Req message to the master clock device and records the timestamp t ₃ when it is sent. This message is another event message used to trigger the timestamp recording on the master clock device. When the Delay_Req message arrives at the master clock device, a specific control field is added to the front of it to specify the target master clock program and insert the timestamp t ₄ in the Delay_Req message.

After receiving the Delay_Req message, the master clock device sends a Delay_Resp message, which contains the timestamp t ₄ when the Delay_Req message arrives. This message is a general message used to return the time information requested by the slave clock device. The Delay_Resp message contains a control field for specifying the target slave clock device and inserting the timestamp t ₄ in the Delay_Resp message. After receiving the Delay_Resp message, the slave clock device can obtain the t ₄ timestamp.

The slave clock device can calculate the time offset and network delay between the slave clock device and the master clock device according to the four timestamps t ₁ , t ₂ , t ₃ and t _4. According to the time offset and network delay, the slave clock device can adjust its local clock to synchronize with the master clock device.

By combining PTP's event messages and general messages, and using the data interface to operate the control field to determine the target slave clock device and transmit timestamp information, accurate clock synchronization can be achieved between the master clock device and the slave clock device. This method ensures that the slave clock device can accurately know when the Sync message is received and adjust its local clock accordingly to keep in sync with the master clock device.

According to an embodiment of the present disclosure, the general message does not include a follow-up message.

In some embodiments, when the Precision Time Protocol (PTP) is used to perform clock synchronization on a first device (master clock device) and a second device (slave clock device), a single-step method may also be used to perform time synchronization.

For example, the master clock device sends a Sync message to the slave clock device. The Sync message contains a specific control field for specifying the target slave clock device and inserting a timestamp in the Sync message. When the Sync message arrives at the slave clock device, the slave clock device records the timestamp t ₂ of receiving the Sync message at its data interface.

When sending a Sync message, the master clock device records the timestamp t ₁ it sends. This timestamp is necessary for the subsequent calculation of offset and delay, and it will be directly included in the Sync message and sent to the slave clock device.

After the slave clock device records the timestamp t ₂ , it sends a Delay_Req message to the master clock device and records the timestamp t ₃ when it is sent. This message is another event message that is used to trigger the timestamp recording on the master clock device. When the Delay_Req message arrives at the master clock device, a specific control field is added to the front of it to specify the target master clock program and insert the timestamp t ₄ in the Delay_Req message.

After receiving the Delay_Req message, the master clock device sends a Delay_Resp message to the slave clock device, which contains the timestamp t ₄ when the Delay_Req message arrives at the master clock device. This message is a general message used to return the time information requested by the slave clock device. The Delay_Resp message contains a control field for specifying the target slave clock device and inserting the timestamp t ₄ in the Delay_Resp message. After receiving the Delay_Resp message, the slave clock device can obtain the t ₄ timestamp.

The slave clock device can calculate the time offset and network delay between the slave clock device and the master clock device according to the four timestamps t ₁ , t ₂ , t ₃ and t _4. According to the time offset and network delay, the slave clock device can adjust its local clock to synchronize with the master clock device.

Although the general message does not contain a follow-up message, the master clock device and the slave clock device can still accurately calculate the time offset and network delay through the timestamps recorded by each, as well as the exchange of event messages and general messages, thereby achieving clock synchronization. This method makes full use of the design of the PTP protocol to ensure the accuracy and reliability of clock synchronization.

Fig. 4 schematically shows a flow chart of a method for inserting a first timestamp according to an embodiment of the present disclosure. Fig. 5 schematically shows a format diagram of a data packet in a sending direction according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, the first control field includes a timestamp insertion bit, a timestamp operation bit and a timestamp preservation bit, as shown in Figure 4. For example, through operations S4111~S4113, in response to identifying the first control field of the first data packet, the first timestamp is inserted into the second synchronization data packet of the first data packet.

In operation S4111, when the general message does not include a follow-up message, in response to identifying the first control field of the event message, the timestamp insertion bit and the timestamp operation bit are set, and the first timestamp is inserted into the second synchronization data packet of the event message.

In operation S4112, when the general message includes a follow-up message, in response to the first control field of the recognition event message, a timestamp preservation bit and a timestamp operation bit are set, and the first timestamp is saved in a register.

In operation S4113, in response to sending the follow-up message, the first timestamp is read from the register and the first timestamp is inserted into the second synchronization data packet of the follow-up message.

In some embodiments, there is a network device that processes data packets from different sources and needs to record the timestamp information of the data packets for performance analysis or troubleshooting. The data packets received by the device may include event packets (i.e., data packets that are important or require special processing) and general packets (i.e., regular traffic).

The timestamping hardware receives an Event Message when an Event Message is sent and no following Message is sent. Identify the first control field of the Event Message. Check if the Timestamp Insertion Bit and the Timestamp Action Bit are set. If not set, set the Timestamp Insertion Bit and the Timestamp Action Bit. Generate the first timestamp (for example, using the device's internal clock). Insert the timestamp into the second sync packet of the Event Message (this usually means in a specific field or header of the packet). Continue processing or forwarding the packet.

When an event message is sent and there is a following message, the timestamping hardware first receives the event message and generates a first timestamp. The first timestamp is not immediately inserted into the event message, but saved into a register. Then, the following message is received. The first control field of the following message is identified. Check whether the timestamp save bit and the timestamp operation bit are set. If not set, set the timestamp save bit and the timestamp operation bit. Read the previously saved timestamp from the register. Insert the timestamp into the second synchronization data packet of the following message. Continue to process or forward the following message.

The method of inserting the timestamp depends on the type of packet and whether there are following messages. For event messages (special packets without subsequent following messages), the timestamp is inserted directly into the synchronization packet of the packet. For event messages with subsequent following messages, the timestamp is first saved to a register and then inserted when the following message arrives. This method allows the device to handle timestamps more flexibly while ensuring that time information is accurately recorded even when there are multiple related packets in the packet stream.

For example, the data packet in the sending direction may be a Sync message, a Follow_up message, a Delay_Req message, and a Delay_Req message. As shown in FIG5 , the data packet in the sending direction may include a 16-byte control field and a 1588 data packet, wherein byte1:0x5a indicates the sending direction, byte2:channel id indicates the address of the target second device, byte3~4:reserve indicates a spare bit, byte5 (bit0:ts_insert_reg) indicates an insertion timestamp, (bit1:ts_flag) indicates an operation timestamp, (bit2:save_ts_reg) indicates a save timestamp, byte6:sequence id indicates a sequential address, byte7:tsoffset indicates a timestamp offset (i.e., a position inserted in the 1588 data packet), byte8~12:reserve indicates a spare bit, byte13~14:0x0600 indicates a data packet type (such as Ethernet 2), and byte15~16:reserve indicates a spare bit for data alignment.

The PTP master (master clock device) mainly sends sync messages, follow-up messages, and delay_resp messages.

In single-step mode, the master sends a sync message, the software sets ts_flag and ts_insert_flag when assembling the packet, embeds the timestamp _t1 into the message through the FPGA and sends it to the corresponding port. The subsequent steps are the same as the double-step mode.

In dual-step mode, the master sends a sync message, and the software sets save_ts_flag and ts_flag when assembling the packet. The sender FPGA saves the timestamp t ₁ to the register. When the software assembles the packet to send the follow-up message, it reads the FPGA register to obtain the timestamp t ₁ and assembles the packet to send to the FPGA, and then the FPGA sends it to the corresponding port according to the channel ID. And the Master receives the delay_req message. When the FPGA receives the delay_req message, it adds the t ₄ timestamp. The packetization module adds the timestamp to the private field of the packet header. After the software monitors the corresponding port data, it obtains the delay_req message and the t ₄ timestamp of the private field, and assembles the t ₄ timestamp into the delay_resp and replies to the slave.

Fig. 6 schematically shows a flow chart of a method for inserting a second timestamp according to an embodiment of the present disclosure. Fig. 7 schematically shows a format diagram of a receiving direction data packet according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, the second control field includes a timestamp reception bit, as shown in FIG. 6 , for example, in response to adding the second control field to the first synchronization data packet through operation S6131 , a second timestamp is inserted into the second control field.

In operation S6131, in response to adding a second control field to the first synchronization data packet, a timestamp reception bit and a timestamp operation bit are set, and a second timestamp is inserted into the second control field.

In some embodiments, for example, the timestamping hardware first receives a data packet (eg, a Sync message or a Delay_Resp message of the PTP protocol).

The timestamping hardware checks the packet type and field structure to determine that it is a packet that needs to be timestamped. If the packet itself does not contain a second control field or the field does not have enough space for timestamp insertion, the timestamping hardware will create a new second control field or extend the existing field to accommodate the timestamp information.

When adding or modifying the second control field, the timestamping hardware sets the "timestamp received bit" and the "timestamp operation bit". These bit flags tell the device to insert a timestamp in this field next. The timestamping hardware uses its internal high-precision clock to generate an accurate timestamp (the second timestamp). After setting the corresponding bit flags, the timestamping hardware inserts the generated second timestamp into the predefined position in the second control field. This may involve rearranging or replacing specific parts of the data packet to accommodate the timestamp. Once the timestamp is successfully inserted into the second control field, the data packet can be further processed by the timestamping hardware or forwarded to the next network node.

This method provides a flexible and accurate way to track the time information of data packets in the network, which is particularly useful for application scenarios that require high-precision time synchronization or performance analysis. By inserting the timestamp into the second control field of the data packet, it can ensure that the time information remains intact and accessible during the data packet transmission process.

For example, the receiving direction data packet may also be a Sync message, a Follow_up message, a Delay_Req message, and a Delay_Req message. As shown in FIG7 , the receiving direction data packet may include a 16-byte control field and a 1588 data packet, wherein byte1:0xb5 indicates the receiving direction, byte2:channel id indicates the address of the target second device or, when there are multiple master clock devices, indicates the address of the first device sending the packet, byte3~12:rx_ts indicates the receiving timestamp, byte13~14:0x0600 indicates the data packet type (such as Ethernet 2), and byte15~16:reserve indicates a spare bit for data alignment.

In single-step mode, the slave (slave clock device) receives the sync message. When the FPGA receives the sync message, it performs a hardware timestamp t ₂ and adds t ₂ to the private field of the sync message header. The software parses the reassembled message with the FPGA adding the timestamp t ₂ to obtain the timestamps t ₁ and t _2. The subsequent steps are the same as the double-step mode.

In the dual-step mode, the slave receives the sync message. When the FPGA receives the sync message, it performs a hardware timestamp t ₂ and adds t ₂ to the private field of the sync message header. It parses the reassembled message with the timestamp t ₂ added by the FPGA to obtain the timestamp t _2. Then it receives the Follow_up message and parses the timestamp t ₁ in the Follow_up message.

Send the delay_req message. The FPGA will stamp t ₃ when sending the delay_req message and record it in the register. The software reads the register to obtain the t ₃ timestamp saved by the FPGA.

Finally, the delay_resp message sent by the master carries the t ₄ timestamp. The slave parses the message to obtain t ₄ , calculates and adjusts the offset, and completes the time synchronization between the slave clock device and the master clock device.

It should be noted that the timestamping hardware on the master clock device side may be, for example, an FPGA, and the timestamping hardware on the slave clock device side may be, for example, an FPGA or other hardware. Since the data is transmitted between the master clock device and the slave clock device via a network cable or optical fiber, only the 1588 data packet is transmitted, that is, the function of the control field is to insert the timestamp in the 1588 data packet and to indicate the location of the inserted timestamp. When the timestamping hardware on the slave clock device side is other hardware, the control field may not be added, and other methods may be used, such as the timestamping tool built into the network interface, to perform the second timestamp.

According to an embodiment of the present disclosure, the control field, for example, further includes a data direction bit, a channel ID bit, a data type bit, and a spare bit. Among them, the data direction bit is used to control the transmission direction of the first data packet and the second data packet. The channel ID bit is used to record the port address. The data type bit is used to limit the network type corresponding to the first data packet and the second data packet. And the spare bit is used for data expansion or data alignment.

In some embodiments, for example, there is an industrial automation system, which includes a master clock device (with multiple master clock programs) and multiple slave clock devices, which communicate through the same network interface. The master clock device is responsible for providing accurate time information, and the slave clock device needs to be synchronized to the time of the master clock.

When a master-clock device sends a time synchronization packet to a slave-clock device, the data direction bit is set to "transmit" (for example, 0x5a).

When a slave-clock device responds to a query from a master-clock device or confirms successful synchronization, the data direction bit is set to "Receive" (for example, 0xb5).

Since there are multiple slave clock devices in the system, each slave clock device has a unique port address (or channel ID). When the master clock device sends a time synchronization data packet, it includes the channel ID of the target slave clock device in the channel ID bit of the data packet. After receiving the data packet, the slave clock device checks the channel ID bit to confirm whether the data packet is what it needs.

In this example, the data type bit is used to indicate the protocol type applicable to the transmitted data packet, such as a data packet applicable to Ethernet 2. The master clock device sets the corresponding value in the data type bit according to the requirements, and the slave clock device performs corresponding processing according to the value.

In this example, the spare bits may be used for future functional expansion or data alignment. For example, if additional synchronization parameters or control information are required in the future, the spare bits can be used for expansion.

When the system starts or a new slave clock device joins the network, the master clock device sends an initialization synchronization data packet. The channel ID bit in the data packet is set to the ID of the target slave clock device, and the data type bit is set to "0x0600". After receiving the data packet, the slave clock device sets its internal clock to the time in the data packet and completes the initialization process.

In order to maintain the accuracy of time synchronization, the master clock device can periodically send periodic synchronization data packets. The channel ID bit and data type bit in the data packet are the same as those during initial synchronization. After receiving the data packet, the slave clock device will fine-tune its own clock according to the time information in it.

In order to monitor the status of the slave clock device, the master clock device can periodically send a heartbeat signal data packet. The channel ID bit in the data packet is set to the ID of the slave clock device. After receiving the data packet, the slave clock device will reply with a confirmation signal to indicate that its status is normal.

By properly setting the bits in the control field, accurate clock synchronization can be achieved between a master clock device and multiple slave clock devices based on the same network interface. This method is not only suitable for industrial automation systems, but can also be applied to other scenarios that require high-precision time synchronization.

For example, ptp master and ptp slave register their own 1588 network ports (single or multiple) and channel IDs in netlink. In the HPS (High Performance Switch) sending direction, netlink sends all data (including channel ID) to the registered network port. In the HPS receiving direction, netlink sends different data packets to different ptp masters and ptp slaves according to the channel ID.

FIG8 schematically shows a flow chart of sending and receiving data packets according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, for example, a first timestamp is inserted into the second synchronization data packet through an FPGA, and a second timestamp is inserted into the second control field.

In some embodiments, as shown in FIG8 , for example, by adding a 16-byte control field at the front of a common Ethernet packet (1588 data packet), different PTP master and PTP slave channels are distinguished. When the message is sent through the control field of the timestamp, the FPGA timestamps, thereby reducing the time error, and the kernel uses netlink to forward data. Wherein, a represents the direction of receiving data packets, and b represents the direction of sending data packets.

It is understandable that the above-mentioned receiving and sending are relative. The master clock device can be a packet sending device or a packet receiving device. Similarly, the slave clock device can be a packet sending device or a packet receiving device. The control fields of the packet sending device and the packet receiving device are different, as shown in Figures 5 and 7.

For example, the master clock device contains an FPGA (field programmable gate array) chip to handle time synchronization related logic and data packet operations. The master clock device communicates with multiple slave clock devices through the same network interface.

During the system startup or configuration phase, the master clock device configures the network interface and clock synchronization parameters through the FPGA. This includes setting the values of control fields such as the data direction bit, channel ID bit, data type bit, and spare bit. The master clock device assigns a unique channel ID to each slave clock device and stores it in the register or memory of the FPGA.

When a time synchronization packet needs to be sent, the FPGA of the master clock device generates a packet based on the current time and the channel ID of the slave clock device. In the second synchronization packet part of the packet (such as a 1588 packet), the FPGA inserts the first timestamp (t ₁ and t ₄ ). This timestamp represents the exact time when the packet was generated or received.

The FPGA sends the generated time synchronization data packet to the network interface, which is then transmitted to the specified slave clock device. The channel ID bit in the data packet is used to ensure that the data packet is sent to the correct slave clock device.

When the slave clock device also uses FPGA to timestamp, the FPGA inserts the second timestamp t ₂ in the second control field generated by it when receiving the data packet. After receiving the time synchronization data packet through the network interface, the slave clock device parses the timestamp and control field information in the data packet. The slave clock device confirms whether the data packet is required by itself according to the channel ID bit in the data packet, and uses the timestamp information in the data packet to calibrate its own clock to achieve synchronization with the master clock device.

It is understandable that the time _t3 when the slave clock device sends out the data packet can be obtained from the register by itself without being extracted from the data packet.

After successful synchronization, the slave clock device can send a confirmation data packet to the master clock device to indicate successful synchronization. After receiving the confirmation data packet, the master clock device can record the synchronization status or perform other subsequent operations.

FPGA plays a key role in the clock synchronization process. It is responsible for generating time synchronization packets and inserting timestamp and control field information into the packets. The parallel processing capability and flexibility of FPGA enable it to efficiently and accurately handle time synchronization related logic and packet operations. Through the configuration and programming of FPGA, different clock synchronization algorithms and strategies can be implemented to meet the needs of different application scenarios.

By inserting the first timestamp in the second synchronization data packet and the second timestamp in the second control field through FPGA, accurate clock synchronization between the master clock device and multiple slave clock devices based on the same network interface can be achieved. This method takes advantage of the efficiency and flexibility of FPGA and improves the accuracy and reliability of clock synchronization. At the same time, by setting the control field, flexible control of data packet transmission direction, port address, network type and data expansion can be achieved.

Based on the above data interface-based synchronization processing method, the present disclosure further provides a data interface-based synchronization processing device. The following will describe the data interface-based synchronization processing device in detail in conjunction with FIG.

FIG. 9 schematically shows a structural block diagram of a synchronization processing device based on a data interface according to an embodiment of the present disclosure.

According to an embodiment of the present disclosure, a first device communicates with a plurality of second devices via a data interface, wherein the first device runs a plurality of master clock programs, as shown in FIG9 , a synchronization processing device 900 based on a data interface of this embodiment, for example, includes: a sending module 910 and a calibration module 920. The synchronization processing device 900 based on a data interface can execute the method described above with reference to FIG2 to FIG8 to achieve clock synchronization of a master clock device and a slave clock device.

Specifically, the sending module 910 is used to send the first time information and the second time information to at least one second device, wherein the first time information represents the moment when the master clock program sends the first data packet to the data interface, and the second time information represents the moment when the second device sends the first synchronization data packet to the data interface. In one embodiment, the sending module 910 can be used to perform the operation S210 described above, which will not be repeated here.

The calibration module 920 is used to perform clock synchronization on multiple second devices according to the first time information and the second time information. Among them, the data interface is used to identify the control field in the first data packet, or add the control field to the first synchronization data packet to obtain the second data packet. The control field is used to control the data interface to timestamp the first data packet and the second data packet, and record the port address of the second device. In one embodiment, the calibration module 920 can be used to perform the operation S220 described above, which will not be repeated here.

It is understandable that the sending module 910 and the calibration module 920 can be combined in one module, or any one of the modules can be split into multiple modules. Alternatively, at least part of the functions of one or more of these modules can be combined with at least part of the functions of other modules and implemented in one module. According to an embodiment of the present disclosure, at least one of the sending module 910 and the calibration module 920 can be at least partially implemented as a hardware circuit, such as a field programmable gate array (FPGA), a programmable logic array (PLA), a system on a chip, a system on a substrate, a system on a package, an application-specific integrated circuit (ASIC), or can be implemented in hardware or firmware in any other reasonable way of integrating or packaging the circuit, or in a proper combination of software, hardware and firmware. Alternatively, at least one of the sending module 910 and the calibration module 920 can be at least partially implemented as a computer program module, and when the program is run by a computer, the function of the corresponding module can be executed.

FIG10 schematically shows a block diagram of an electronic device suitable for implementing a synchronization processing method based on a data interface according to an embodiment of the present disclosure.

As shown in FIG10 , the electronic device 1000 according to an embodiment of the present disclosure includes a processor 1001, which can perform various appropriate actions and processes according to a program stored in a read-only memory (ROM) 1002 or a program loaded from a storage part 1008 into a random access memory (RAM) 1003. The processor 1001 may include, for example, a general-purpose microprocessor (e.g., a CPU), an instruction set processor and/or a related chipset and/or a dedicated microprocessor (e.g., an application-specific integrated circuit (ASIC)), etc. The processor 1001 may also include an onboard memory for caching purposes. The processor 1001 may include a single processing unit or multiple processing units for performing different actions of the method flow according to an embodiment of the present disclosure.

In RAM 1003, various programs and data required for the operation of electronic device 1000 are stored. Processor 1001, ROM 1002 and RAM 1003 are connected to each other via bus 1004. Processor 1001 performs various operations of the method flow according to the embodiment of the present disclosure by executing the program in ROM 1002 and/or RAM 1003. It should be noted that the program can also be stored in one or more memories other than ROM 1002 and RAM 1003. Processor 1001 can also perform various operations of the method flow according to the embodiment of the present disclosure by executing the program stored in the one or more memories.

According to an embodiment of the present disclosure, the electronic device 1000 may further include an input/output (I/O) interface 1005, which is also connected to the bus 1004. The electronic device 1000 may further include one or more of the following components connected to the I/O interface 1005: an input portion 1006 including a keyboard, a mouse, etc.; an output portion 1007 including a cathode ray tube (CRT), a liquid crystal display (LCD), etc., and a speaker, etc.; a storage portion 1008 including a hard disk, etc.; and a communication portion 1009 including a network interface card such as a LAN card, a modem, etc. The communication portion 1009 performs communication processing via a network such as the Internet. A drive 1010 is also connected to the I/O interface 1005 as needed. A removable medium 1011', such as a magnetic disk, an optical disk, a magneto-optical disk, a semiconductor memory, etc., is installed on the drive 1010 as needed, so that a computer program read therefrom is installed into the storage portion 1008 as needed.

The present disclosure also provides a computer-readable storage medium, which may be included in the device/apparatus/system described in the above embodiment; or may exist independently without being assembled into the device/apparatus/system. The above computer-readable storage medium carries one or more programs, and when the above one or more programs are executed, the synchronization processing method based on the data interface according to the embodiment of the present disclosure is implemented.

According to an embodiment of the present disclosure, a computer-readable storage medium may be a non-volatile computer-readable storage medium, for example, may include but is not limited to: a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination thereof. In the present disclosure, a computer-readable storage medium may be any tangible medium containing or storing a program, which may be used by or in combination with an instruction execution system, an apparatus, or a device. For example, according to an embodiment of the present disclosure, a computer-readable storage medium may include the ROM 1002 and/or RAM 1003 described above and/or one or more memories other than ROM 1002 and RAM 1003.

The embodiment of the present disclosure also includes a computer program product, which includes a computer program, and the computer program contains program code for executing the method shown in the flowchart. When the computer program product is run in a computer system, the program code is used to enable the computer system to implement the synchronization processing method based on the data interface provided by the embodiment of the present disclosure.

The above functions defined in the system/device of the embodiment of the present disclosure are performed when the computer program is executed by the processor 1001. According to the embodiment of the present disclosure, the system, device, module, unit, etc. described above can be implemented by a computer program module.

In one embodiment, the computer program may be based on a tangible storage medium such as an optical storage device, a magnetic storage device, etc. In another embodiment, the computer program may also be transmitted and distributed in the form of a signal on a network medium, and downloaded and installed through the communication part 1009, and/or installed from a removable medium 1011'. The program code contained in the computer program may be transmitted using any appropriate network medium, including but not limited to: wireless, wired, etc., or any suitable combination of the above.

In such an embodiment, the computer program can be downloaded and installed from the network through the communication part 1009, and/or installed from the removable medium 1011'. When the computer program is executed by the processor 1001, the above functions defined in the system of the embodiment of the present disclosure are performed. According to the embodiment of the present disclosure, the system, device, apparatus, module, unit, etc. described above can be implemented by a computer program module.

According to an embodiment of the present disclosure, the program code for executing the computer program provided by the embodiment of the present disclosure can be written in any combination of one or more programming languages. Specifically, these computing programs can be implemented using high-level process and/or object-oriented programming languages, and/or assembly/machine languages. Programming languages include, but are not limited to, Java, C++, python, "C" language or similar programming languages. The program code can be executed entirely on the user computing device, partially on the user device, partially on the remote computing device, or entirely on the remote computing device or server. In the case of a remote computing device, the remote computing device can be connected to the user computing device through any type of network, including a local area network (LAN) or a wide area network (WAN), or can be connected to an external computing device (for example, using an Internet service provider to connect through the Internet).

The flow chart and block diagram in the accompanying drawings illustrate the possible architecture, function and operation of the system, method and computer program product according to various embodiments of the present disclosure. In this regard, each box in the flow chart or block diagram can represent a module, a program segment, or a part of a code, and the above-mentioned module, program segment, or a part of a code contains one or more executable instructions for realizing the specified logical function. It should also be noted that in some alternative implementations, the functions marked in the box can also occur in a different order from the order marked in the accompanying drawings. For example, two boxes represented in succession can actually be executed substantially in parallel, and they can sometimes be executed in the opposite order, depending on the functions involved. It should also be noted that each box in the block diagram or flow chart, and the combination of the boxes in the block diagram or flow chart can be implemented with a dedicated hardware-based system that performs a specified function or operation, or can be implemented with a combination of dedicated hardware and computer instructions.

It will be appreciated by those skilled in the art that the features described in the various embodiments and/or claims of the present disclosure may be combined and/or combined in a variety of ways, even if such combinations and/or combinations are not explicitly described in the present disclosure. In particular, the features described in the various embodiments and/or claims of the present disclosure may be combined and/or combined in a variety of ways without departing from the spirit and teachings of the present disclosure. All of these combinations and/or combinations fall within the scope of the present disclosure.

The embodiments of the present disclosure are described above. However, these embodiments are only for illustrative purposes and are not intended to limit the scope of the present disclosure. Although the embodiments are described above separately, this does not mean that the measures in the various embodiments cannot be used in combination to advantage. The scope of the present disclosure is defined by the attached claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art may make a variety of substitutions and modifications, which should all fall within the scope of the present disclosure.

Claims (10)

1. A synchronous processing method based on a data interface, through which a first device communicates with a plurality of second devices, wherein the first device runs a plurality of master clock programs, the method comprising:

Transmitting first time information and second time information to at least one second device, wherein the first time information characterizes the moment when the master clock program transmits a first data packet to the data interface, and the second time information characterizes the moment when the second device transmits a first synchronous data packet to the data interface;

according to the first time information and the second time information, clock synchronization is carried out on the plurality of second devices;

The data interface is used for identifying a control field in the first data packet or adding the control field to the first synchronous data packet to obtain a second data packet;

The control field is used for controlling the data interface to timestamp the first data packet and the second data packet and recording the port address of the second device.

2. The method of claim 1, wherein the data interface is a hardware interface for time stamping data packets, and the transmitting first time information and second time information to at least one of the second devices comprises:

inserting a first timestamp in a second synchronization packet of the first data packet in response to identifying a first control field of the first data packet;

transmitting a second synchronization packet including the first timestamp to at least one of the plurality of second devices according to the port address;

Inserting a second timestamp in a second control field in response to adding the second control field to the first synchronization packet; and

And sending a second synchronous data packet containing the second timestamp to at least one of the plurality of second devices according to the port address.

3. The method of claim 2, wherein the first device and the second device are clocked using a precision time protocol, the first data packet comprising an event message and a generic message.

4. A method according to claim 3, wherein the generic message does not include a follow-up message.

5. The method of claim 3, wherein the first control field includes a timestamp insert bit, a timestamp operate bit, and a timestamp save bit, the inserting a first timestamp in a second synchronous data packet of the first data packet in response to identifying the first control field of the first data packet comprising:

In the case that the general message does not include a following message, responding to a first control field for identifying the event message, setting the timestamp inserting bit and the timestamp operating bit, and inserting the first timestamp into a second synchronous data packet of the event message; or alternatively

In the case that the general packet includes a follow packet, in response to identifying a first control field of the event packet, setting the timestamp holding bit and the timestamp operating bit, and holding the first timestamp in a register;

and in response to sending the following message, reading the first timestamp from the register, and inserting the first timestamp into a second synchronous data packet of the following message.

6. The method of claim 2, wherein the second control field comprises a timestamp receipt bit, the inserting a second timestamp in the second control field in response to adding a second control field to the first synchronization data packet comprising:

in response to adding a second control field to the first synchronization packet, the timestamp receiving bit and the timestamp operating bit are set and the second timestamp is inserted into the second control field.

7. The method of claim 2, wherein the control field comprises a data direction bit, a channel ID bit, a data type bit, and a spare bit;

wherein the data direction bit is used for controlling the transmission directions of the first data packet and the second data packet;

the channel ID bit is used for recording the port address;

the data type bit is used for limiting the network type corresponding to the first data packet and the second data packet; and

The spare bits are used for data expansion or data alignment.

8. The method according to any of claims 2-7, wherein the first timestamp is inserted in the second synchronization data packet and the second timestamp is inserted in the second control field by an FPGA.

9. A synchronous processing apparatus based on a data interface through which a first device communicates with a plurality of second devices, wherein the first device runs a plurality of master clock programs, the apparatus comprising:

A sending module, configured to send first time information and second time information to at least one second device, where the first time information characterizes a time when the master clock program sends a first data packet to the data interface, and the second time information characterizes a time when the second device sends a first synchronization data packet to the data interface;

the calibration module is used for carrying out clock synchronization on the plurality of second devices according to the first time information and the second time information;

The data interface is used for identifying a control field in the first data packet or adding the control field to the first synchronous data packet to obtain a second data packet;

The control field is used for controlling the data interface to timestamp the first data packet and the second data packet and recording the port address of the second device.

10. An electronic device, comprising:

One or more processors;

Storage means for storing one or more programs,

Wherein the one or more programs, when executed by the one or more processors, cause the one or more processors to perform the method of any of claims 1-8.