CN118567869B - Memory access method and device - Google Patents
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- CN118567869B CN118567869B CN202411045702.1A CN202411045702A CN118567869B CN 118567869 B CN118567869 B CN 118567869B CN 202411045702 A CN202411045702 A CN 202411045702A CN 118567869 B CN118567869 B CN 118567869B
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5011—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals
- G06F9/5016—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resources being hardware resources other than CPUs, Servers and Terminals the resource being the memory
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F12/00—Accessing, addressing or allocating within memory systems or architectures
- G06F12/02—Addressing or allocation; Relocation
- G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
- G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
- G06F12/0877—Cache access modes
- G06F12/0884—Parallel mode, e.g. in parallel with main memory or CPU
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F9/00—Arrangements for program control, e.g. control units
- G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
- G06F9/46—Multiprogramming arrangements
- G06F9/50—Allocation of resources, e.g. of the central processing unit [CPU]
- G06F9/5005—Allocation of resources, e.g. of the central processing unit [CPU] to service a request
- G06F9/5027—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals
- G06F9/5038—Allocation of resources, e.g. of the central processing unit [CPU] to service a request the resource being a machine, e.g. CPUs, Servers, Terminals considering the execution order of a plurality of tasks, e.g. taking priority or time dependency constraints into consideration
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- G—PHYSICS
- G06—COMPUTING OR CALCULATING; COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
- G06F2212/10—Providing a specific technical effect
- G06F2212/1016—Performance improvement
- G06F2212/1021—Hit rate improvement
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Abstract
The invention belongs to the technical field of computers, and particularly relates to a memory access method and device. In the technical scheme of the embodiment of the invention, the memory access method is applied to the multi-core processor, firstly, the priority of the access request type, the cache state, the request emergency degree and the core activity of the request source of each memory access request is assigned, the priority score is calculated through a weighting method based on the priority assignment, and the memory transmission queue dynamically adjusts the scheduling strategy according to the ordering of the priority score, so that the request with high priority can be responded more quickly, and the memory access efficiency and the overall system throughput of the multi-core processor are improved.
Description
Technical Field
The present invention relates to the field of computer technologies, and in particular, to a memory access method and apparatus.
Background
In modern computing systems, multi-core processors have become one of the key technologies to improve computing performance. However, as the number of cores increases, problems of conflict and resource contention are inevitably encountered when multiple processor cores access shared memory resources simultaneously. This situation may not only lead to an increase in memory access latency, but may also cause cache coherency problems, thereby severely affecting overall system performance.
Conventional memory access scheduling algorithms, such as static priority scheduling and fixed policy scheduling, are often designed with simplified issues and ease of implementation in mind. These algorithms often determine the order of memory accesses based on some preset rules or static parameters, and lack the ability to dynamically perceive and adapt to the current system state and memory access patterns. When facing complex and changeable memory access modes and dynamically changing system loads, the algorithms are hard to take optimal scheduling decisions, so that full play of the performance of the processor is limited.
Disclosure of Invention
The invention provides a memory access method and a memory access device, which calculate priority scores for access request types, cache states, request urgency and core liveness of request sources of each memory access request through a weight method, dynamically adjust memory access queues and improve memory access efficiency.
In order to solve the above problems, the present invention provides a memory access method, where the memory access method is applied to a multi-core processor, and the multi-core processor processes a plurality of current memory access requests, and the method includes:
Step 1: assigning priorities of access request types, cache states, request urgency and core liveness of request sources of each memory access request as w1, w2, w3 and w4 respectively;
step 2: the priority score of each memory access request is calculated according to the following formula:
the priority score = w1×access request type weight + w2×cache state weight + w3×request urgency weight + w4×core liveness weight;
step 3: sorting the current multiple memory access requests from top to bottom according to the priority value;
step 4: the memory transmission queue dispatches the memory access requests according to the sequence of the sequencing in the step S3;
Step 5: the steps S1 to S4 are repeated every unit time.
Optionally, in the access request type weight, the read operation weight is 3, and the write operation weight is 2.
Optionally, in the cache state weight, the cache miss weight is 3, and the cache hit weight is 1.
Optionally, in the request emergency degree weight, the real-time task weight is 5, the common task weight is 2, and the background task weight is 1.
Optionally, in the core liveness weight, the high liveness is 3, the medium liveness is 2, and the low liveness is 1.
Optionally, the method further comprises: constructing a memory access pattern prediction model based on historical access data, wherein the prediction model is used for predicting a memory access trend, and the memory access trend comprises: access location, time window.
Optionally, constructing the prediction model based on a machine learning algorithm; wherein the machine learning algorithm comprises: markov Chain, LSTM.
Optionally, the historical access data includes: access address data, request type data, request time data, belonging process data.
Optionally, the method further comprises: and (2) monitoring the memory performance index to form memory performance index real-time data, and dynamically adjusting the priority assignment in the step (1) based on the memory performance index real-time data.
Optionally, the memory performance index data includes: memory access latency data, core utilization data.
Optionally, the method further comprises: dividing the memory transmitting queue into a plurality of sub-queues, and dynamically adjusting memory access request allocation according to the memory access mode data and the current load condition data of each core.
Optionally, the step of dynamically adjusting memory access request allocation further includes: adjusting the number of the sub-queues and the service objects; including merging, splitting, or reassigning the sub-queues.
Optionally, the memory access mode data includes: read-write ratio data and cache hit rate data.
Optionally, the load condition data includes: CUP utilization, task urgency data.
The invention also provides a memory access device, which is applied to the multi-core processor, and comprises:
A memory controller, the memory controller comprising:
The dynamic transmission queue scheduling logic module is used for realizing the memory s access method;
The access mode analysis module is used for analyzing the memory access mode;
the prediction algorithm interface is used for communicating with a user or a system administrator to realize a scheduling strategy;
And the intelligent scheduling algorithm module is used for adjusting the scheduling strategy according to the requirements by a user or a system administrator.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following advantages:
In the technical scheme of the embodiment of the invention, the memory access method is applied to the multi-core processor, firstly, the priority of the access request type, the cache state, the request emergency degree and the core activity of the request source of each memory access request is assigned, the priority score is calculated through a weighting method based on the priority assignment, and the memory transmission queue dynamically adjusts the scheduling strategy according to the ordering of the priority score, so that the request with high priority can be responded more quickly, and the memory access efficiency and the overall system throughput of the multi-core processor are improved.
Drawings
FIG. 1 is a flow chart of a memory access method according to an embodiment of the present invention;
FIG. 2 is a schematic diagram of a memory access method according to an embodiment of the present invention;
FIG. 3 is a schematic diagram of another memory access method according to an embodiment of the present invention;
FIG. 4 is a schematic diagram of another memory access method according to an embodiment of the present invention;
Fig. 5 is a schematic diagram of a memory access device according to an embodiment of the present invention.
Detailed Description
Embodiments of the present application will now be described more fully hereinafter with reference to the accompanying drawings, in which it is shown, however, in which some, but not all embodiments of the application are shown. All other embodiments, which can be made by those skilled in the art based on the embodiments of the application without making any inventive effort, are intended to be within the scope of the application.
In order that the above-recited objects, features and advantages of the present application will become more readily apparent, a more particular description of the application will be rendered by reference to the appended drawings and appended detailed description.
Referring to fig. 1, fig. 1 is a flow chart of a memory access method according to an embodiment of the present invention. The memory access method is applied to a multi-core processor, the multi-core processor processes a plurality of current memory access requests, and the method comprises the following steps:
step S1: assigning priorities of access request types, cache states, request urgency and core liveness of request sources of each memory access request as w1, w2, w3 and w4 respectively;
Step S2: the priority score of each memory access request is calculated according to the following formula:
the priority score = w1×access request type weight + w2×cache state weight + w3×request urgency weight + w4×core liveness weight;
Step S3: sorting the current multiple memory access requests from top to bottom according to the priority value;
Step S4: the memory transmission queue dispatches the memory access requests according to the sequence of the sequencing in the step S3;
step S5: the steps S1 to S4 are repeated every unit time.
Assume that three memory access requests occur simultaneously in a multi-core processor system in an embodiment of the present invention:
Request a: from the core1 with higher activity, the access request type is read operation, the cache state is miss, and the data is used for a real-time task.
Request B: from the core 2 with lower activity, the access request type is write operation, the cache state is hit, and the data belongs to a background processing task.
Request C: from core 3 of moderate liveness, the access request type is a read operation, the cache state is a miss, and the data is used for a common task.
Suppose that w1, w2, w3, w4 for memory access request a, request B, request C are assigned respectively as follows,
Request a: w1=30 w2=20 w3=30 w4=10;
Request B: w1=20 w2=10 w3=10 w4=20;
request C: w1=30 w2=20 w3=20 w4=30.
In the embodiment of the present invention, in the access request type weight, the read operation weight is 3, and the write operation weight is 2. In the cache state weight, the cache miss weight is 3, and the cache hit weight is 1. In the request emergency degree weight, the real-time task weight is 5, the common task weight is 2, and the background task weight is 1. In the core liveness weight, the high liveness is 3, the medium liveness is 2, and the low liveness is 1.
According to the priority score calculation formula, in unit time, there are:
priority score of request a = 3 x w1+3 x w2+5 x w3+1 x w4 = 310;
Priority score of request B = 2 x w1+1 x w2+1 x w3+2 x w4 = 100;
priority score of request C = 3x w1+2 x w2+2 x w3+3 x w4 = 260.
The current memory access requests are sequenced from top to bottom according to the priority values of the request A, the request B and the request C, wherein the priority values are as follows: request a, request C, request B;
the memory transmitting queue dispatches the access requests according to the sequence of the request A, the request C and the request B.
Referring to fig. 2, fig. 2 is a schematic diagram of a memory access method according to an embodiment of the present invention. With reference to fig. 2, it can be seen that, in each unit time, the above steps are repeatedly performed, and the priority score is calculated according to the access request type, the cache state, the request urgency degree and the core activity degree of the request source of each memory access request, and the memory controller dynamically adjusts the memory transmit queue schedule according to the priority score in each unit time, so as to ensure that the request with high priority gets faster response, and improve the access efficiency of the memory.
Referring to fig. 3, fig. 3 is a schematic diagram of another memory access method according to an embodiment of the present invention.
The method comprises the following steps: constructing a memory access pattern prediction model based on historical access data, wherein the prediction model is used for predicting a memory access trend, and the memory access trend comprises: access location, time window.
In an embodiment of the present invention, feature extraction in the process of constructing the prediction model includes the following aspects: access sequence, timestamp, core liveness, etc.
The prediction model is constructed based on a machine learning algorithm; wherein the machine learning algorithm comprises: markov Chain, LSTM.
The history access data includes: access address data, request type data, request time data, belonging process data.
And a prediction model is constructed based on the historical access data, so that future access trend of the memory can be predicted, the pre-fetching operation is scheduled in advance, the waiting time in actual access is reduced, and the continuity and efficiency of the memory access are improved.
Referring to fig. 4, fig. 4 is a schematic diagram of another memory access method according to an embodiment of the present invention.
With reference to fig. 4, the method further includes: the memory transmitting queue is divided into a plurality of sub queues, and memory access request allocation is dynamically adjusted according to memory access mode data (including read-write proportion data and cache hit rate data) of each core and current load condition data (including CUP utilization rate and task emergency degree data). Adjusting the number of the sub-queues and the service objects; the method comprises merging, splitting or reassigning the sub-queues, so as to ensure that the queue configuration is always matched with the system state.
The memory access method further comprises the following steps: and (2) monitoring the memory performance index to form memory performance index real-time data, and dynamically adjusting the priority assignment in the step (1) based on the memory performance index real-time data. Wherein, the memory performance index data includes: memory access latency data, core utilization data.
It is assumed that during a memory access request, cores that frequently generate cache state misses may be allocated to queues that exclusively handle the miss requests, and cores that perform a large number of read operations may be allocated to queues for the read operations.
By automatically adjusting the request allocation of the sub-queue parts according to the memory access mode data and the current load of each core, the balanced allocation of the memory access requests can be realized, the queue blocking and the resource contention are reduced, and the memory access efficiency is further improved.
Referring to fig. 5, fig. 5 is a schematic diagram of a memory access device according to an embodiment of the present invention. The apparatus is applied to a multi-core processor, the apparatus comprising:
A memory controller, the memory controller comprising:
the dynamic transmission queue scheduling logic module is used for realizing the memory access method;
the access mode analysis module is used for analyzing the memory access mode and comprises the steps of constructing a prediction model and the like;
the prediction algorithm interface is used for communicating with a user or a system administrator to realize a scheduling strategy; specifically, the prediction model algorithm adjusts the communication between the strategies in real time with the user or the administrator;
And the intelligent scheduling algorithm module is used for adjusting the scheduling strategy according to the requirements by a user or a system administrator.
In the present specification, each embodiment is described in a progressive manner, or a parallel manner, or a combination of progressive and parallel manners, and each embodiment is mainly described as a difference from other embodiments, and identical and similar parts between the embodiments are all enough to refer to each other. For the memory access device disclosed in the embodiment, since the memory access device corresponds to the memory access method disclosed in the embodiment, the description is relatively simple, and the relevant points are only described in the memory access method section.
It is further noted that relational terms such as first and second, and the like are used solely to distinguish one entity or action from another entity or action without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms "comprises," "comprising," or any other variation thereof, are intended to cover a non-exclusive inclusion, such that an article or apparatus that comprises a list of elements does not include only those elements but may include other elements not expressly listed or inherent to such article or apparatus. Without further limitation, an element defined by the phrase "comprising one … …" does not exclude the presence of other like elements in an article or device comprising the element.
The previous description of the disclosed embodiments is provided to enable any person skilled in the art to make or use the present application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and the generic principles defined herein may be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not intended to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.
Claims (15)
1. A memory access method, applied to a multi-core processor, wherein the multi-core processor processes a plurality of current memory access requests, the method comprising:
Step 1: assigning priorities of access request types, cache states, request urgency and core liveness of request sources of each memory access request as w1, w2, w3 and w4 respectively;
step 2: the priority score of each memory access request is calculated according to the following formula:
the priority score = w1×access request type weight + w2×cache state weight + w3×request urgency weight + w4×core liveness weight;
step 3: sorting the current multiple memory access requests from top to bottom according to the priority value;
step 4: the memory transmission queue dispatches the memory access requests according to the sequence of the sequencing in the step S3;
Step 5: the steps S1 to S4 are repeated every unit time.
2. The memory access method according to claim 1, wherein in the access request type weight, a read operation weight is 3 and a write operation weight is 2.
3. The memory access method according to claim 1, wherein in the cache state weight, a cache miss weight is 3 and a cache hit weight is 1.
4. The memory access method according to claim 1, wherein in the request urgency weight, a real-time task weight is 5, a normal task weight is 2, and a background task weight is 1.
5. The memory access method of claim 1, wherein the core liveness weight has a high liveness of 3, a medium liveness of 2, and a low liveness of 1.
6. The memory access method of claim 1, further comprising: constructing a memory access pattern prediction model based on historical access data, wherein the prediction model is used for predicting a memory access trend, and the memory access trend comprises: access location, time window.
7. The memory access method of claim 6, wherein the predictive model is constructed based on a machine learning algorithm; wherein the machine learning algorithm comprises: markov Chain, LSTM.
8. The memory access method of claim 6, wherein the history access data comprises: access address data, request type data, request time data, belonging process data.
9. The memory access method of claim 1, further comprising: and (2) monitoring the memory performance index to form memory performance index real-time data, and dynamically adjusting the priority assignment in the step (1) based on the memory performance index real-time data.
10. The memory access method of claim 9, wherein the memory performance index data comprises: memory access latency data, core utilization data.
11. The memory access method of claim 1, further comprising: dividing the memory transmitting queue into a plurality of sub-queues, and dynamically adjusting memory access request allocation according to the memory access mode data and the current load condition data of each core.
12. The memory access method of claim 11, wherein the step of dynamically adjusting memory access request allocation further comprises: adjusting the number of the sub-queues and the service objects; including merging, splitting, or reassigning the sub-queues.
13. The memory access method according to claim 11, wherein the memory access pattern data includes: read-write ratio data and cache hit rate data.
14. The memory access method of claim 11, wherein the load condition data comprises: CUP utilization, task urgency data.
15. A memory access device for use with a multi-core processor, the device comprising:
A memory controller, the memory controller comprising:
a dynamic transmit queue scheduling logic module to implement the method of claim 1;
The access mode analysis module is used for analyzing the memory access mode;
the prediction algorithm interface is used for communicating with a user or a system administrator to realize a scheduling strategy;
And the intelligent scheduling algorithm module is used for adjusting the scheduling strategy according to the requirements by a user or a system administrator.
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN102012881A (en) * | 2010-11-29 | 2011-04-13 | 杭州中天微系统有限公司 | Bus monitor-based system chip bus priority dynamic configuration device |
| CN109255055A (en) * | 2018-08-06 | 2019-01-22 | 四川蜀天梦图数据科技有限公司 | A kind of diagram data access method and device based on packet associated table |
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| JP7443195B2 (en) * | 2020-08-21 | 2024-03-05 | キオクシア株式会社 | Memory system and control method |
| CN114490012B (en) * | 2020-11-13 | 2025-03-21 | 中国移动通信集团设计院有限公司 | Memory scheduling method, device and readable storage medium |
| CN115357377A (en) * | 2022-07-25 | 2022-11-18 | 芯来智融半导体科技(上海)有限公司 | Memory control scheduling method and device, computer equipment and storage medium |
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|---|---|---|---|---|
| CN102012881A (en) * | 2010-11-29 | 2011-04-13 | 杭州中天微系统有限公司 | Bus monitor-based system chip bus priority dynamic configuration device |
| CN109255055A (en) * | 2018-08-06 | 2019-01-22 | 四川蜀天梦图数据科技有限公司 | A kind of diagram data access method and device based on packet associated table |
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