CN118539902A - True single-phase clock master-slave type all-static D trigger - Google Patents

Abstract

The present invention discloses a true single-phase clock master-slave type fully static D flip-flop, the D flip-flop comprises a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit connected in sequence; the data input circuit is used to receive a data input signal; the master trigger circuit and the slave trigger circuit are both controlled by a clock signal CK; when the clock signal CK is at a low level, the master trigger circuit receives the data input signal, and the slave trigger circuit is in a holding state; when the clock signal CK is at a high level, the master trigger circuit is in a holding state, and the slave trigger circuit receives the storage state of the master trigger circuit. The present invention has the advantages of a small number of transistors, a small number of clock control transistors, and a simple circuit structure, and overcomes the defect of a traditional true single-phase clock D flip-flop that the storage state changes due to leakage, and the delay is reduced by 7% to 12% compared with the traditional D flip-flop; in addition, the differential input can enhance the anti-noise performance.

Description

A true single-phase clock master-slave type fully static D flip-flop

Technical Field

The invention mainly relates to the technical field of digital circuit design, and in particular to a true single-phase clock master-slave type fully static D flip-flop.

Background Art

Since the advent of CMOS integrated circuit technology, the trigger has always been one of the core components of digital integrated circuits. It is the basic unit for realizing sequential logic such as pipelines, state machines, counters, and register files. Its speed directly affects the performance of digital circuits and chips. There are many types of triggers in digital circuits, and the most common ones are RS triggers, JK triggers, D triggers, and T triggers. According to the different structures of the trigger circuits, they are divided into master-slave triggers, sensitive amplifier triggers, and maintenance blocking triggers. Among them, the master-slave D trigger is the most applicable and widely used in digital integrated circuit technology.

Figure 1 shows a schematic diagram of a D flip-flop circuit unit. Figure 2 shows the basic circuit structure of a traditional D flip-flop circuit unit widely used in the design of commercial digital circuit standard cell libraries at various process nodes, usually called a conventional transmission-gate flip-flop (TGFF). The advantage of this structure is its simplicity, and the disadvantage is that it requires a complementary clock signal. The concept of a true single-phase clock was invented in the late 1980s and used in flip-flop design, which overcomes the disadvantage of traditional D flip-flops based on transmission gates or C2MOS logic requiring complementary clock signals. This flip-flop or its variants were used in the design and implementation of the Alpha 21064 (launched in 1992) microprocessor. According to research by Bowhill et al., its speed is 10% higher than that of traditional D flip-flop/latch solutions.

Mohamed Elgamel et al. systematically expounded the design principle of the traditional true single-phase clock D flip-flop (see M. Elgamel, T. Darwish, and M. Bayoumi, “Noise Tolerant Low Power DynamicTSPCL D Flip-Flops”, in Proceeding of the IEEE Computer Society AnnualSymposium on VLSI, pp. 89-94, 2002. doi: 10.1109/ISVLSI.2002.1016880.). FIG3 shows the practical structure of the traditional true single-phase clock D flip-flop (see the invention patent US20080106315A1 of Ting-Sheng Jau et al.), which is called True single phase clock basic flip-flop (TSPCBFF), and has advantages over TCFF in terms of area and performance. However, the traditional true single phase clock D flip-flop is not a master-slave type flip-flop, but a dynamic flip-flop, which makes the flip-flop likely to have a state error due to charge leakage when it does not flip for a long time, thereby causing a logic function error. This defect limits the application of traditional true single-phase clock triggers.

Summary of the invention

In view of the technical problems existing in the prior art, the present invention provides a true single-phase clock master-slave type fully static D flip-flop with full static state, low clock power consumption and good delay characteristics.

In order to solve the above technical problems, the technical solution proposed by the present invention is:

A true single-phase clock master-slave type fully static D flip-flop, comprising a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit; the data input circuit, the master trigger circuit, the slave trigger circuit and the data output circuit are connected in sequence;

A data input circuit is used to receive a data input signal; a data output circuit is used to output an output signal from the trigger circuit;

Both the master trigger circuit and the slave trigger circuit are controlled by the clock signal CK;

When the clock signal CK is at a low level, the master trigger circuit receives the data input signal, and the slave trigger circuit is in a holding state;

When the clock signal CK is at a high level, the master trigger circuit is in a holding state, and the slave trigger circuit receives the storage state of the master trigger circuit;

The main trigger circuit includes PMOS tubes MP1-MP5 and NMOS tubes MN6-MN7;

The substrate and source of the PMOS tube MP1 are connected to the power supply VDD, and the gate is connected to the clock signal CK;

The substrate of the PMOS tube MP2 is connected to the power supply VDD, the gate is connected to the signal dn, the source is connected to the drain of MP1, and the drain driving signal ml_b;

The substrate of the PMOS tube MP3 is connected to the power supply VDD, the gate is connected to the signal dnn, the source is connected to the drain of MP1 and the source of MP2, and the drain drive signal ml_ax;

The substrate and source of the PMOS tube MP4 are connected to the power supply VDD, the gate is driven by the signal ml_ax, and the drain is driven by the signal ml_b;

The substrate and source of the PMOS tube MP5 are connected to the power supply VDD, the gate is driven by the signal ml_b, and the drain is driven by the signal ml_ax;

The substrate and source of NMOS tube MN6 are grounded to VSS, the gate is driven by signal ml_ax, and the drain is driven by signal ml_b;

The substrate and source of NMOS tube MN7 are grounded to VSS, the gate is driven by signal ml_b, and the drain is driven by signal ml_ax;

The signal ml_ax and the signal ml_b are a complementary signal pair in the main trigger circuit; the signal dn and the signal dnn are a complementary or differential signal pair generated by the data input circuit.

Preferably, the slave trigger circuit includes NMOS tubes MN1-MN5 and PMOS tubes MP6-MP7;

The substrate and source of the NMOS tube MN1 are grounded to VSS, and the gate is connected to the clock signal CK;

The substrate of NMOS tube MN2 is grounded to VSS, the gate is connected to the signal ml_ax, the source is connected to the drain of MN1, and the drain is driven by the signal sl_a;

The substrate of NMOS tube MN3 is grounded to VSS, the gate is connected to the signal ml_b, the source is connected to the drain of MN1 and the source of NM2, and the drain drives the signal sl_bx;

The substrate and source of the NMOS tube MN4 are grounded to VSS, the gate is driven by the signal sl_bx, and the drain is driven by the signal sl_a;

The substrate and source of NMOS tube MN5 are grounded to VSS, the gate is driven by the signal sl_a, and the drain is driven by the signal sl_bx;

The substrate and source of the PMOS tube MP6 are connected to the power supply VDD, the gate is driven by the signal sl_bx, and the drain is driven by the signal sl_a;

The substrate and source of the PMOS tube MP7 are connected to the power supply VDD, the gate is driven by the signal sl_a, and the drain is driven by the signal sl_bx;

The signal sl_bx and the signal sl_a are a complementary signal pair in the slave trigger circuit.

Preferably, the data output circuit comprises an inverter X3, the input end of the inverter X3 is driven by the signal sl_bx, and the output end drives the output signal Q.

Preferably, the data input circuit comprises an inverter X1 and an inverter X2, which are used to receive a data input signal D and generate a complementary or differential signal pair dn and dnn;

The input terminal of the inverter X1 is connected to the data input signal D, and the output signal of the inverter X1 is dn; the input terminal of the inverter X2 is connected to the signal dn, and the output signal of the inverter X2 is dnn.

Preferably, the data input circuit includes inverters X2, X4, PMOS transistors MP11-MP14, and NMOS transistors MN11-MN14;

The inverter X4 is used to generate a complementary signal sen of the enable signal SE;

The inverter X2 is used to generate a complementary signal dnn of the signal dn;

The substrate and source of the PMOS tube MP11 are connected to the power supply VDD, and the gate is controlled by the enable signal SE;

The substrate and source of the PMOS tube MP12 are connected to the power supply VDD, and the gate is controlled by the scanning signal SI;

The substrate of the PMOS tube MP13 is connected to the power supply VDD, the source is connected to the drain of MP11, and the gate is controlled by the data input signal D; and the drain drive signal dn;

The substrate of the PMOS tube MP14 is connected to the power supply VDD, its source is connected to the drain of MP12, the gate is controlled by the signal sen, and the drain drives the signal dn;

The substrate and source of the NMOS tube MN11 are connected to the power supply VSS, and the gate is controlled by the complementary signal sen of the enable signal SE;

The substrate and source of the NMOS tube MN12 are connected to the power supply VSS, and the gate is controlled by the scan signal SI;

The substrate of NMOS tube MN13 is connected to the power supply VSS, its source is connected to the drain of MN11, the gate is controlled by the data input signal D, and the drain is driven by the signal dn;

The substrate of the NMOS tube MN14 is connected to the power supply VSS, the source thereof is connected to the drain of MN12, the gate is controlled by the enable signal SE, and the drain is driven by the signal dn.

Preferably, the data input circuit comprises an inverter X1, an input terminal of the inverter X1 is connected to a data input signal D, an output signal of the inverter X1 is dn; and the data input signal D is used as a signal dnn.

Compared with the prior art, the advantages of the present invention are:

Compared with the traditional true single-phase clock D flip-flop TSPCBFF, the true single-phase clock master-slave type fully static D flip-flop of the present invention overcomes the defect that the dynamic flip-flop cannot maintain the storage state for a long time. When the clock is at a low level for a long time, the slave trigger circuit is in a maintenance state, and the states of the signals sl_a and sl_bx will not be changed due to leakage, so the Q value can be maintained for a long time; it is more suitable for digital integrated circuit design and can be applied to the design of chips such as CPU, GPU, and ASIC.

Compared with the traditional D flip-flop TGFF, the true single-phase clock master-slave type fully static D flip-flop of the present invention greatly reduces the clock load, reduces the number of transistors driven by the clock signal, and can save dynamic power consumption; and the number of transistors is smaller, which can save area; at the rising edge of the clock, only two levels of reverse logic are needed to transmit the input change to the output Q, and the circuit delay characteristic is good; at the same time, differential input is adopted to have better anti-noise performance, and it is more suitable for digital integrated circuit design.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a circuit diagram of a conventional flip-flop; D is a data input signal, CK is a clock signal, and Q is an output signal.

FIG. 2 is a circuit diagram of a conventional D flip-flop TGFF.

FIG3 is a circuit diagram of a conventional true single-phase clock D flip-flop TSPCBFF.

FIG4 is a circuit diagram of a true single-phase clock master-slave type fully static trigger in the first embodiment of the present invention.

FIG5 is a circuit diagram of a true single-phase clock master-slave type fully static trigger with a scan structure in the second embodiment of the present invention.

FIG6 is a circuit diagram of a simplified true single-phase clock master-slave type fully static trigger in Embodiment 3 of the present invention.

DETAILED DESCRIPTION

The present invention is further described below in conjunction with the accompanying drawings and specific embodiments.

Embodiment 1:

As shown in FIG1 , the true single-phase clock master-slave type fully static D flip-flop of the embodiment of the present invention comprises a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit, wherein the master trigger circuit and the slave trigger circuit are controlled by a clock signal CK;

When the clock signal CK is at a low level, the master trigger circuit receives data input, while the slave trigger circuit is in a holding state;

When the clock signal CK is at a high level, the main trigger circuit is not affected by the input signal and is in a holding state, while the slave trigger circuit receives the storage state of the main trigger circuit, so that the trigger state is updated.

Specifically, the data input circuit includes an inverter X1 and an inverter X2, which are used to receive a data input signal D and generate a complementary or differential signal pair dn and dnn;

The input terminal of the inverter X1 is connected to the data input signal D, and the output signal of the inverter X1 is dn; the input terminal of the inverter X2 is connected to the signal dn, and the output signal of the inverter X2 is dnn.

Specifically, the main trigger circuit includes PMOS tubes MP1-MP5 and NMOS tubes MN6-MN7;

The substrate and source of the PMOS tube MP1 are connected to the power supply VDD, and the gate is connected to the clock signal CK;

The substrate of the PMOS tube MP2 is connected to the power supply VDD, the gate is connected to the signal dn, the source is connected to the drain of MP1, and the drain driving signal ml_b;

The substrate of the PMOS tube MP3 is connected to the power supply VDD, the gate is connected to the signal dnn, the source is connected to the drain of MP1 and the source of MP2, and the drain drive signal ml_ax;

The substrate and source of the PMOS tube MP4 are connected to the power supply VDD, the gate is driven by the signal ml_ax, and the drain is driven by the signal ml_b;

The substrate and source of the PMOS tube MP5 are connected to the power supply VDD, the gate is driven by the signal ml_b, and the drain is driven by the signal ml_ax;

The substrate and source of NMOS tube MN6 are grounded to VSS, the gate is driven by signal ml_ax, and the drain is driven by signal ml_b;

The substrate and source of NMOS tube MN7 are grounded to VSS, the gate is driven by signal ml_b, and the drain is driven by signal ml_ax;

Wherein the signal ml_ax and the signal ml_b are complementary signal pairs in the main trigger circuit;

Specifically, the slave trigger circuit includes NMOS tubes MN1-MN5 and PMOS tubes MP6-MP7;

The substrate and source of the NMOS tube MN1 are grounded to VSS, and the gate is connected to the clock signal CK;

The substrate of NMOS tube MN2 is grounded to VSS, the gate is connected to the signal ml_ax, the source is connected to the drain of MN1, and the drain is driven by the signal sl_a;

The substrate of NMOS tube MN3 is grounded to VSS, the gate is connected to the signal ml_b, the source is connected to the drain of MN1 and the source of NM2, and the drain drives the signal sl_bx;

The substrate and source of the NMOS tube MN4 are grounded to VSS, the gate is driven by the signal sl_bx, and the drain is driven by the signal sl_a;

The substrate and source of NMOS tube MN5 are grounded to VSS, the gate is driven by the signal sl_a, and the drain is driven by the signal sl_bx;

The substrate and source of the PMOS tube MP6 are connected to the power supply VDD, the gate is driven by the signal sl_bx, and the drain is driven by the signal sl_a;

The substrate and source of the PMOS tube MP7 are connected to the power supply VDD, the gate is driven by the signal sl_a, and the drain is driven by the signal sl_bx.

The data output circuit includes an inverter X3, the input end of the inverter X3 is driven by the signal sl_bx, and the output end drives the output signal Q.

When the true single-phase clock master-slave type fully static D flip-flop is used in a specific application, the specific working principle is as follows:

When the clock signal CK is at a low level, MP1 is turned on and MN1 is turned off; at this time, the slave trigger circuit is in a holding state, stably driving the inverter X3 so that the output signal Q value is maintained; at the same time, the master trigger circuit is in a data receiving state. When the data input signal D is at a high level, the dn and dnn signals are low and high levels respectively, so MP2 is turned on and MP3 is turned off, and the signal ml_b is pulled up to a high level by the MP2 tube. At the same time, the pull-up of the signal ml_b turns on MN7, pulling down the signal ml_ax to a low level. Conversely, when the data input signal D is at a low level, the signals dn and dnn are high and low levels respectively, so MP2 is turned off and MP3 is turned on, and the signal ml_ax is pulled up to a high level by the MP3 tube. At the same time, the pull-up of the signal ml_ax turns on MN6, pulling down the signal ml_b to a low level;

When the clock signal CK is at a high level, MP1 is turned off and MN1 is turned on; at this time, the master trigger circuit is in a holding state, so that the ml_b and ml_ax signals remain stable; at the same time, the slave trigger circuit is in a data receiving state. If the ml_b signal is at a high level, MN3 is turned on and MN2 is turned off, and the signal sl_bx is pulled down to a low level. The pull-down of the signal sl_bx turns on MP6, so that the signal sl_a is pulled up to a high level; if the signal ml_b is at a low level, MN3 is turned off and MN2 is turned on, and the signal sl_a is pulled down to a low level. The pull-down of the signal sl_a turns on MP7, so that the signal sl_bx is pulled up to a high level; the update of the signal sl_bx drives the inverter X3, so that the output signal Q value is updated.

During the time period when the clock signal CK is at a high level, because the main trigger circuit is in a holding state, the signals ml_b and ml_ax are not affected by the data input signal D and remain stable. Therefore, the state update of the slave trigger circuit occurs at the moment when the clock signal CK changes from a low level to a high level, that is, the trigger of the present invention is a D trigger triggered by a rising edge.

Compared with the traditional true single-phase clock D flip-flop TSPCBFF, the true single-phase clock master-slave fully static D flip-flop (True single-phase clock master-slave flip-flop, abbreviated as TSPCMSFF) of the present invention overcomes the defect that the dynamic flip-flop cannot maintain the storage state for a long time. When the clock is at a low level for a long time, the slave trigger circuit is in a maintenance state, and the states of the signals sl_a and sl_bx will not be changed due to leakage, so the Q value can be maintained for a long time; it is more digital integrated circuit design and can be applied to the chip design of CPU, GPU, ASIC, etc.

Compared with the traditional D flip-flop TGFF, the true single-phase clock master-slave fully static D flip-flop (TSPCMSFF) of the present invention greatly reduces the clock load and the number of transistors driven by the clock signal (from 12 in FIG. 2 to 2 in FIG. 4), which can save dynamic power consumption; and the number of transistors is smaller, which can save area; at the rising edge of the clock, only two levels of reverse logic are needed to transmit the input change to the output Q, and the circuit delay characteristic is good; at the same time, differential input is used to have better noise resistance performance, which is more suitable for digital integrated circuit design.

The present invention as a whole has the characteristics of full static state, low clock power consumption and good delay characteristics.

Embodiment 2:

The D flip-flop in the first embodiment is easily expanded into a true single-phase clock master-slave type fully static D flip-flop with a scan structure, thereby supporting a wide range of testability design requirements in digital integrated circuit design. As shown in FIG5 , the circuit structure of the true single-phase clock master-slave type fully static D flip-flop with a scan structure is different from that of the flip-flop in the first embodiment, except that only the data input circuit has changed. Specifically, the data input circuit includes inverters X2, X4, PMOS tubes MP11-MP14, and NMOS tubes MN11-MN14;

The inverter X4 is used to generate a complementary signal sen of the enable signal SE;

The inverter X2 is used to generate a complementary signal dnn of the signal dn;

The substrate and source of the PMOS tube MP11 are connected to the power supply VDD, and the gate is controlled by the enable signal SE;

The substrate and source of the PMOS tube MP12 are connected to the power supply VDD, and the gate is controlled by the scanning signal SI;

The substrate of the PMOS tube MP13 is connected to the power supply VDD, its source is connected to the drain of MP11, and the gate is controlled by the data input signal D; and the drain drive signal dn;

The substrate of the PMOS tube MP14 is connected to the power supply VDD, its source is connected to the drain of MP12, the gate is controlled by the signal sen, and the drain drives the signal dn;

The substrate and source of the NMOS tube MN11 are connected to the power supply VSS, and the gate is controlled by the complementary signal sen of the enable signal SE;

The substrate and source of the NMOS tube MN12 are connected to the power supply VSS, and the gate is controlled by the scan signal SI;

The substrate of NMOS tube MN13 is connected to the power supply VSS, its source is connected to the drain of MN11, the gate is controlled by the data input signal D, and the drain is driven by the signal dn;

The substrate of the NMOS tube MN14 is connected to the power supply VSS, the source thereof is connected to the drain of MN12, the gate is controlled by the enable signal SE, and the drain is driven by the signal dn.

Other contents not described are the same as those in the first embodiment and will not be described again.

Embodiment three:

In application scenarios that do not need to support scan structures or testability design, the D flip-flop in the first embodiment can be further simplified, that is, the inverter X2 is removed, the inverter X1 is retained, and the gate of MP3 originally driven by the signal dnn is directly driven by the data input signal D. The simplified circuit structure diagram is shown in FIG6 , where only the data input circuit is changed.

Other contents not described are the same as those in the first embodiment and will not be described again.

Finally, in order to compare the performance characteristics of the TSPCMSFF of the present invention, a SPICE simulation analysis and comparison is performed on the traditional D flip-flop TGFF, the traditional TSPC type D flip-flop TSPCBFF and the TSPCMSFF in the first embodiment of the present invention respectively under a commercial FinFET bulk silicon process based on the circuit simulation tool HSPICE. The analysis and comparison results are shown in Table 1:

Table 1 Comparison of transistor count and CK2Q delay simulation results

As can be seen from the comparison of trigger-related parameters in Table 1, compared with the traditional D trigger, the number of trigger transistors of the present invention is reduced by 16.7%, and the number of clock-controlled transistors is reduced by 83.3%, which is the design style with the least number of clock-controlled transistors in current trigger designs.

In the circuit simulation, the clock signal CK is a quasi-square wave signal with a frequency of 1 GHz, a duty cycle of 50%, and a rise/fall transition time of 20 ps; the data input D is a quasi-square wave signal of 500 MHz, a duty cycle of 50%, and a rise/fall transition time of 50 ps; a 10 fF capacitor is mounted at the output end of the trigger circuit as a load.

Under the same conditions, the CK2Q delay of the trigger TSPCMSFF of the present invention is reduced by 7% to 12% compared with the traditional D trigger TGFF. Therefore, the true single-phase clock master-slave type fully static D trigger of the present invention has a smaller area, lower clock power consumption, and smaller CK2Q delay than the traditional D trigger, and is more suitable for the design of standard cell libraries, and has broad prospects in digital integrated circuit design and chip design.

The above are only preferred embodiments of the present invention. The protection scope of the present invention is not limited to the above embodiments. All technical solutions under the concept of the present invention belong to the protection scope of the present invention. It should be pointed out that for ordinary technicians in this technical field, some improvements and modifications without departing from the principle of the present invention should be regarded as the protection scope of the present invention.

Claims (6)

1. The true single-phase clock master-slave type all-static D trigger is characterized by comprising a data input circuit, a master trigger circuit, a slave trigger circuit and a data output circuit; the data input circuit, the master trigger circuit, the slave trigger circuit and the data output circuit are connected in sequence;

A data input circuit for receiving a data input signal; a data output circuit for outputting an output signal from the trigger circuit;

The master trigger circuit and the slave trigger circuit are controlled by a clock signal CK;

when the clock signal CK is in a low level, the master trigger circuit receives a data input signal, and the slave trigger circuit is in a maintenance state;

When the clock signal CK is at a high level, the main trigger circuit is in a maintenance state, and the slave trigger circuit receives a storage state of the main trigger circuit;

The main trigger circuit comprises PMOS transistors MP1-MP5 and NMOS transistors MN6-MN7;

the PMOS tube MP1 substrate and the source electrode are connected with a power supply VDD, and the grid electrode is connected with a clock signal CK;

the PMOS tube MP2 substrate is connected with a power supply VDD, the grid electrode is connected with a signal dn, the source electrode is connected with the drain electrode of MP1, and the drain electrode drives a signal ml_b;

the PMOS tube MP3 substrate is connected with a power supply VDD, the grid electrode is connected with a signal dnn, the source electrode is connected with the drain electrode of MP1 and the source electrode of MP2, and the drain electrode drives a signal ml_ax;

the PMOS tube MP4 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_ax, and the drain electrode is driven by a signal ml_b;

the PMOS tube MP5 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal ml_b, and the drain electrode is driven by a signal ml_ax;

NMOS transistor MN6 substrate and source electrode are grounded VSS, the grid electrode is driven by signal ml_ax, and the drain electrode is driven by signal ml_b;

NMOS transistor MN7 has substrate and source grounded VSS, gate driven by signal ml_b, drain driven signal ml_ax;

Wherein signal ml_ax and signal ml_b are complementary signal pairs in the primary trigger circuit; the signal dn and signal dnn are complementary or differential signal pairs generated by the data input circuit.

2. The true single-phase clock master-slave type all-static D trigger according to claim 1, wherein the slave trigger circuit comprises NMOS transistors MN1-MN5 and PMOS transistors MP6-MP7;

NMOS transistor MN1 substrate and source ground VSS, the grid electrode is connected with a clock signal CK;

the substrate of the NMOS tube MN2 is grounded to VSS, the grid electrode is connected with a signal ml_ax, the source electrode is connected with the drain electrode of the MN1, and the drain electrode drives the signal sl_a;

the substrate of the NMOS tube MN3 is grounded, the grid electrode is connected with a signal ml_b, the source electrode is connected with the drain electrode of the MN1 and the source electrode of the NM2, and the drain electrode drives the signal sl_bx;

The substrate and the source electrode of the NMOS tube MN4 are grounded and the grid electrode is driven by a signal sl_bx, and the drain electrode drives a signal sl_a;

The substrate and the source electrode of the NMOS tube MN5 are grounded and the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx;

the PMOS tube MP6 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal sl_bx, and the drain electrode is driven by a signal sl_a;

the PMOS tube MP7 substrate and the source electrode are connected with a power supply VDD, the grid electrode is driven by a signal sl_a, and the drain electrode is driven by a signal sl_bx;

Where the signal sl_bx and the signal sl_a are complementary signal pairs in the slave flip-flop.

3. The true single phase clock master slave type all static D flip-flop according to claim 2, wherein said data output circuit comprises an inverter X3, the input of the inverter X3 being driven by a signal sl_bx and the output driving an output signal Q.

4. A true single phase clock master slave full static D flip-flop according to claim 1 or 2 or 3, wherein said data input circuit comprises an inverter X1 and an inverter X2 for receiving an input signal D and generating complementary or differential signal pairs dn and dnn;

The input end of the inverter X1 is connected with the data input signal D, and the output signal of the inverter X1 is dn; the input of the inverter X2 is connected with the signal dn, and the output signal of the inverter X2 is dnn.

5. A true single-phase clock master-slave type all-static D flip-flop according to claim 1, 2 or 3, wherein said data input circuit comprises inverters X2, X4, PMOS transistors MP11-MP14, NMOS transistors MN11-MN14;

the inverter X4 is used for generating a complementary signal sen of the enable signal SE;

Inverter X2 is used to generate a complementary signal dnn to signal dn;

The PMOS tube MP11 substrate and the source electrode are connected with a power supply VDD, and the grid electrode is controlled by an enable signal SE;

The substrate and the source electrode of the PMOS tube MP12 are connected with a power supply VDD, and the grid electrode is controlled by a scanning signal SI;

The PMOS tube MP13 substrate is connected with a power supply VDD, the source electrode is connected with the drain electrode of MP11, and the grid electrode is controlled by a data input signal D; and a drain driving signal dn;

The substrate of the PMOS tube MP14 is connected with a power supply VDD, the source electrode of the PMOS tube MP14 is connected with the drain electrode of the MP12, the gate is controlled by the signal sen, the drain driving signal dn;

The substrate and the source of the NMOS transistor MN11 are connected with a power supply VSS, and the grid is controlled by a complementary signal sen of an enable signal SE;

the substrate and the source of the NMOS tube MN12 are connected with a power supply VSS, and the grid is controlled by a scanning signal SI;

The substrate of NMOS transistor MN13 is connected with power source VSS, its source is connected with drain electrode of MN11, the grid is controlled by a data input signal D, and the drain electrode drives a signal dn;

The NMOS transistor MN14 has a substrate connected to a power source VSS, a source connected to the drain of MN12, a gate controlled by an enable signal SE, and a drain driving signal dn.

6. A true single phase clock master slave type all static D flip-flop according to claim 1,2 or 3, wherein said data input circuit comprises an inverter X1, the input of the inverter X1 being connected to the data input signal D, the output signal of the inverter X1 being dn; the data input signal D is provided as signal dnn.