CN118503191B - High-power storage module and communication method - Google Patents

Abstract

The application relates to the technical field of semiconductor manufacturing, and provides a high-computation-power storage module and a communication method, wherein a plurality of circuit boards form a network; each circuit board comprises a bus and a plurality of chips; each of the chips includes a processing unit and a memory unit, and the processing unit and the memory unit in each of the chips are connected to the bus. The plurality of circuit boards form a network, so that the calculation power of the storage module is improved, and the method is particularly suitable for application scenes requiring high calculation power.

Description

High computing power storage module and communication method

Technical Field

The present invention relates to the field of semiconductor manufacturing technology, and in particular to a high computing power storage module and a communication method.

Background Art

Currently, the computing power of storage devices is relatively low, especially in application scenarios that directly support high-speed computing. It is difficult to support computing tasks that require a large amount of computing, such as AI model training. Therefore, with the development of technology, the computing power requirements for storage devices are getting higher and higher. Current storage devices are difficult to meet the increasing computing power needs.

Summary of the invention

In response to the shortcomings of the prior art, the present application provides a high-computing power storage module and a communication method, which is conducive to providing a high-computing power storage module, improving the computing power of the storage module, and is particularly suitable for application scenarios that require high computing power.

To solve the above problems, the present invention provides the following technical solutions:

In a first aspect, an embodiment of the present application provides a high computing power storage module, the high computing power storage module comprising: a plurality of circuit boards, the plurality of circuit boards forming a network;

Each of the circuit boards includes a bus and a plurality of chips;

Each of the chips includes a processing unit and a storage unit, and the processing unit and the storage unit in each of the chips are connected to the bus.

In some implementations, the processing unit and the storage unit communicate with each other via a UCIe protocol, each chip communicates with a PCIe bus on the circuit board via a UCIe protocol, and each PCIe bus on the circuit board is connected to each other to form a first network.

In some implementations, the chip in each circuit board communicates with the PCIe bus on the circuit board via the PCIe protocol, and the PCIe buses on each circuit board are interconnected to form a second network.

In some embodiments, the plurality of circuit boards form a tree network through a switch;

The bus of the first-level circuit board in the tree network is connected to the switch;

The switch is connected to an external device.

In some embodiments, the tree network includes N levels of circuit boards, and each Mth level circuit board is connected to an M+1th level circuit board; wherein N and M are positive integers, and M is less than or equal to N minus one.

In some embodiments, the circuit board is a 5.0 circuit board.

In some embodiments, the chip further includes at least one cache unit, the processing unit is connected to the cache unit, and the cache unit is a non-volatile memory;

The processing unit in each chip completes the computing task only according to the data in the cache unit and the storage unit in the chip where the processing unit is located.

In a second aspect, an embodiment of the present application provides a communication method of a high computing power storage module based on the first aspect, the method comprising:

Receive data sent by external devices;

Determining a data label of the data;

The data is processed according to the data tags of the data.

In some implementations, processing the data according to the data tag of the data includes:

When the data tag is a comprehensive operation tag in the operation tag, the data is split into a plurality of sub-data; each sub-data is respectively allocated to a processing unit in a different chip;

When the data tag is an independent operation tag in the operation tag, one of the idle processing units is determined as the target processing unit, and the data is allocated to the target processing unit.

In some implementations, processing the data according to the data tag of the data includes:

When the data tag is a storage tag, determining a target storage unit according to the storage tag;

The data is stored in the target storage unit.

The present application provides a high-computing power storage module and a communication method, wherein the high-computing power storage module comprises: a plurality of circuit boards, wherein the plurality of circuit boards form a network; each of the circuit boards comprises a bus and a plurality of chips; each of the chips comprises a processing unit and a storage unit, wherein the processing unit and the storage unit in each of the chips are connected to the bus. In the present application, a plurality of circuit boards form a network, which improves the computing power of the storage module, and is particularly suitable for application scenarios requiring high computing power.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG1 is a first structural diagram of a high computing power storage module provided in an embodiment of the present application.

FIG. 2 is a schematic diagram of the structure of a circuit board under PCIe communication provided in an embodiment of the present application.

FIG3 is a schematic diagram of the structure of a circuit board under UCIe communication provided in an embodiment of the present application.

FIG. 4 is a second structural diagram of the high computing power storage module provided in an embodiment of the present application.

FIG5 is a third structural diagram of the high computing power storage module provided in an embodiment of the present application.

FIG6 is a flow chart of a communication method provided in an embodiment of the present application.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

Please refer to Figure 1, which is a first structural diagram of a high computing power storage module provided in an embodiment of the present application. As shown in Figure 1, the high computing power storage module 1 includes: a plurality of circuit boards 10, and a network is formed between the plurality of circuit boards.

In some embodiments, the circuit board 10 may be a printed circuit board (PCB), a flexible printed circuit (FPC), etc., which is not limited in the present application.

In some embodiments, the circuit board is a PCIe5.0 circuit board.

Specifically, PCI-Express (Peripheral Component Interconnect Express, referred to as PCIe) is a high-speed serial computer expansion bus standard, a bus currently commonly used in high-speed computing systems, which can achieve high-speed data transmission from a certain starting address in the memory of one device to a certain starting address in the memory of another device.

Specifically, PCIe 5.0 provides a data transfer rate of up to 32GT/s, which is twice that of PCIe 4.0. This speed increase directly translates into faster data transfer rates, reduces latency, and significantly improves overall system performance. With the ability to transfer 128GB/s (gigabytes per second) in a 16-channel configuration, PCIe5.0 not only provides a high-speed, reliable data transfer channel, but also meets the processing needs of large amounts of data.

Specifically, PCIe 5.0 circuit boards are backward compatible with PCIe 4.0 devices and PCIe 3.0 devices.

Optionally, in order to achieve such a high data transmission rate, PCIe 5.0 places higher requirements on the performance of the circuit board. The circuit board must have excellent dielectric constant (Dk) characteristics, low dissipation factor (Df) and good thermal conductivity to cope with the heat generated by high-speed signal transmission.

Optionally, at high frequencies, PCIe 5.0 has very high requirements for signal integrity, and the channel loss of the PCIe 5.0 circuit board should be less than 36dB at a frequency of 16GHz to ensure the quality and integrity of the signal during transmission.

In some implementations, the circuit board is a PCIe circuit board, and the PCIe circuit board may be a structure as shown in FIG. 2 or FIG. 3 .

Please refer to FIG2 again, which is a schematic diagram of the structure of a circuit board under PCIe communication provided by an embodiment of the present application. As shown in FIG2 , a circuit board 10 includes a PCIe bus 11 and a plurality of chips 12 .

In some embodiments, each of the chips 12 includes a processing unit 121 and a storage unit 122 , and the processing unit 121 and the storage unit 122 in each of the chips 12 are connected to the bus 11 .

In some embodiments, the processing unit 121 and the storage unit 122 in the chip 12 on each circuit board 10 communicate with each other via the PCIe protocol, the chip 12 on each circuit board 10 communicates with the PCIe bus 11 on the circuit board via the PCIe protocol, and the PCIe buses 11 on each circuit board 10 are connected to each other to form a second network.

Optionally, the processing unit 121 is a central processing unit (CPU) or a micro controller unit (MCU).

Optionally, the storage unit 122 is a flash memory.

In some embodiments, the chip 12 also includes at least one cache unit 123, the processing unit 121 is connected to the cache unit 123, and the cache unit 123 is a non-volatile memory; the processing unit 121 in each chip 12 completes the computing task only based on the data in the cache unit 123 and the storage unit 122 in the chip 12 where it is located.

Optionally, the cache unit 123 is a double data rate synchronous dynamic random access memory (DDR SRAM).

Fig. 3 is a schematic diagram of the structure of a circuit board under UCIe communication provided by an embodiment of the present application. As shown in Fig. 3 , the circuit board 10 is a PCIe circuit board, and the circuit board 10 includes a PCIe bus 11 and a plurality of chips 12 .

The processing unit 121 and the storage unit 122 in the chip 12 on each circuit board 10 communicate with each other via the UCIe protocol, and each chip 12 communicates with the PCIe bus 11 on the circuit board 10 via the UCIe protocol. The PCIe buses 11 on each circuit board are interconnected to form a first network.

The UCIe protocol in FIG. 3 plays the role of a bridge, allowing the chips 12 to communicate internally through the UCIe standard first, and then communicate more extensively with other components in the system (such as the CPU, memory, or peripherals) through the PCIe bus integrated in the circuit board 10.

Please refer to Figure 4 again, which is a second structural diagram of a high computing power storage module provided in an embodiment of the present application. As shown in Figure 4, the multiple PCIe circuit boards 10 in the high computing power storage module 1 form a tree-like PCIe network through a PCIe switch 20.

In some implementations, a bus (not shown in the figure) of a first-level PCIe circuit board in the tree-like PCIe network is connected to a PCIe switch 20 ; and the PCIe switch 20 is connected to an external device 100 .

In some embodiments, the tree-like PCIe network includes N levels of PCIe circuit boards, and each M-th level PCIe circuit board is connected to an M+1-th level PCIe circuit board; wherein N and M are positive integers, and M is less than or equal to N minus one.

Exemplarily, N is equal to 2 in FIG. 4 .

Specifically, through the PCIe switch, the lower-level PCIe circuit board needs to receive the data sent by the external device 100 through the bus of the upper-level PCIe circuit board, but the lower-level PCIe circuit board does not need to pass through the processing unit or storage unit of the upper-level PCIe circuit board to receive the data. Therefore, although the transmission path seems to be long, the impact on the transmission time is very small, thereby ensuring the transmission speed of the above-mentioned tree-like PCIe network, and the data sent by the external device 100 can be quickly allocated to the corresponding processing unit or storage unit.

Please refer to Figure 5 again, which is a third structural diagram of a high computing power storage module provided by an embodiment of the present application. As shown in Figure 5, the multiple PCIe circuit boards 10 form a chain PCIe network, and the PCIe circuit board 10 located at the head of the chain PCIe network is connected to an external device 100.

In some embodiments, the PCIe buses of each PCIe circuit board 10 are connected to each other in a chain PCIe network, so that the head PCIe circuit board 10 can transmit data to the tail PCIe circuit board 10 .

In some embodiments, the chain PCIe network does not have a switch, so each chip also includes a management unit, which is connected to the PCIe bus, and the processing unit and the storage unit are connected to the management unit; the management unit is used to receive data from the PCIe bus and control the processing unit and the storage unit according to the data.

Through the above method, the management unit replaces the PCIe switch to distribute data and realize the integration of computing power and storage space.

The chain-like PCIe network connection relationship is simple and does not require the setting of a PCIe switch. It can also meet high computing power requirements when the number of PCIe circuit boards is small.

Optionally, when the number of PCIe circuit boards is less than or equal to three, a chain-like PCIe network is adopted, and when the number of PCIe circuit boards is greater than three, a tree-like PCIe network is adopted.

Furthermore, the PCIe protocol is a duplex communication, which allows data to be transmitted in both directions at the same time, meaning that both communicating parties can send and receive information at the same time. Therefore, in order to support full-duplex communication, each PCIe bus includes two independent communication channels, one for sending and the other for receiving, to ensure that the data streams do not interfere with each other.

Optionally, two independent communication channels form one channel, and the PCIe bus may include different numbers of channels such as 1, 2, 4, 8, 16, etc.

Furthermore, the PCIe protocol supports hot plugging, so when the PCIe network communicates with external devices, the PCIe circuit board can be unplugged or plugged in at any time to form a PCIe network with different numbers of PCIe circuit boards.

Please refer to Figure 6 again, which is a flow chart of a communication method of a high computing power storage module provided in an embodiment of the present application. The communication method of the high computing power storage module is based on the high computing power storage module in the above embodiment, and the high computing power storage module is connected to an external device. As shown in Figure 6, the method 100 includes: steps 110 to 130.

Step 110: Receive data sent by an external device.

In some implementations, the data sent by the external device may be embodied as instructions, data to be written, computing tasks, and the like.

Step 120: Determine the data label of the data.

In some implementations, the data tags include computation tags and storage tags.

In some implementations, the operation tags include integrated operation tags and independent operation tags.

Step 130: Process the data according to the data tags of the data.

In some embodiments, step 130 includes the following steps.

(1) When the data tag is a comprehensive operation tag in the operation tag, the data is split into multiple sub-data; and each sub-data is respectively allocated to a processing unit in a different chip.

(2) When the data tag is an independent operation tag in the operation tag, one of the idle processing units is determined as the target processing unit, and the data is allocated to the target processing unit.

Through the above method, the processing units can process data in parallel to maximize the use of the computing power of the processing units.

In some embodiments, step 130 includes the following steps.

(1) when the data tag is a storage tag, determining a target storage unit according to the storage tag;

(2) Storing the data in the target storage unit.

Through the above method, data can be stored in the storage units of different chips, thereby expanding the storage space.

In some embodiments, step 130 includes the step of processing the data according to data labels of the data and a network structure of the network.

Specifically, the step of processing the data according to the data label of the data and the network structure of the network includes:

(1) If the data label of the data is a comprehensive operation label in the operation label, and the network structure of the network is a tree structure, the data is split into multiple sub-data;

(2) Copy each sub-data to generate a copy sub-data;

(3) allocating a sub-data and a replica sub-data different from the sub-data to each processing unit;

(4) After receiving the operation results of all processing units, the first operation results of the sub-data are summarized and the second operation results of the sub-data are copied.

(5) When the first operation result and the second operation result are the same, sending a final operation result to an external device; wherein the final operation result is the same as the first operation result and the second operation result.

In the above method, because there are a large number of circuit boards in the tree structure, the amount of computation required to split the data into sub-data is usually small, so allowing one processing unit to compute two sub-data will not slow down the computing speed. After the above method finally summarizes the computing results, the computing results will be corrected to ensure computing security and reliability.

In some embodiments, the code of the data stored in each storage unit in each circuit board is recorded in the external device connected to the high-computing power storage module and/or the cache unit of each chip, thereby supporting the hot plug function. Therefore, after the circuit board is unplugged, it will wait for the new circuit board to be inserted. After the new circuit board is inserted, the data will be restored to the storage unit of the new circuit board according to the code of the data stored in each storage unit in the unplugged circuit board.

In some implementations, a code name storage area is specially allocated in the cache unit of the first-level PCIe circuit board of the tree network to store the code name of the data stored in each storage unit.

In summary, the present application provides a high-computing power storage module and a communication method, wherein the high-computing power storage module comprises: a plurality of circuit boards, wherein the plurality of circuit boards form a network; each of the circuit boards comprises a bus and a plurality of chips; each of the chips comprises a processing unit and a storage unit, wherein the processing unit and the storage unit in each of the chips are connected to the bus. In the present application, a plurality of circuit boards form a network, which improves the computing power of the storage module, and is particularly suitable for application scenarios requiring high computing power.

Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present application, rather than to limit it. Although the present application has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims (3)

1. A communication method for a high computing power storage module, characterized in that it is applied to a high computing power storage module, wherein the high computing power storage module comprises: a plurality of circuit boards, wherein the plurality of circuit boards form a network; Each of the circuit boards includes a bus and a plurality of chips; Each of the chips comprises a processing unit and a storage unit, and the processing unit and the storage unit in each of the chips are connected to the bus; The circuit board is a PCIe circuit board; N and M are positive integers, N is greater than or equal to two, and M is less than or equal to N minus one; When the number of the PCIe circuit boards is greater than 3, the multiple PCIe circuit boards form a tree-like PCIe network through a PCIe switch; a bus of a first-level PCIe circuit board in the tree-like PCIe network is connected to the PCIe switch; and the PCIe switch is connected to an external device; The tree-like PCIe network includes N levels of PCIe circuit boards, each M-th level PCIe circuit board is connected to an M+1-th level PCIe circuit board; The chip further includes at least one cache unit, the processing unit is connected to the cache unit, and the cache unit is a non-volatile memory; The processing unit in each chip completes the computing task only according to the data in the cache unit and the storage unit in the chip where it is located; The method comprises: Receive data sent by external devices; Determining a data label of the data; processing the data according to data labels of the data; The processing of the data according to the data label of the data includes: If the data label of the data is a comprehensive operation label in the operation label, and the network structure of the network is a tree structure, the data is split into multiple sub-data; Copy each sub-data to generate a copy sub-data; Allocating a sub-data and a duplicate sub-data different from the sub-data to each processing unit; After receiving the operation results of all processing units, summarizing the first operation results of the sub-data and copying the second operation results of the sub-data; When the first operation result and the second operation result are the same, sending a final operation result to an external device; The method further comprises: A code storage area is specially divided in the cache unit of the first-level PCIe circuit board in the tree network to store the code of the data stored in each storage unit in the PCIe circuit board. After the PCIe circuit board is pulled out, wait for a new circuit board to be inserted. After the new circuit board is inserted, the data is restored to the storage unit of the new PCIe circuit board based on the code of the data stored in each storage unit in the pulled-out PCIe circuit board stored in any first-level PCIe circuit board. 2. The communication method according to claim 1, wherein processing the data according to the data tag of the data comprises: When the data tag is an independent operation tag in the operation tag, one of the idle processing units is determined as the target processing unit, and the data is allocated to the target processing unit. 3. The communication method according to claim 1, wherein processing the data according to the data tag of the data comprises: When the data tag is a storage tag, determining a target storage unit according to the storage tag; The data is stored in the target storage unit.