CN118502825A

CN118502825A - Instruction processing method, device, equipment and medium in processor simulator

Info

Publication number: CN118502825A
Application number: CN202410660277.0A
Authority: CN
Inventors: 杜步瀛; 田野; 张亚林
Original assignee: Beijing Suiyuan Intelligent Technology Co ltd
Current assignee: Beijing Suiyuan Intelligent Technology Co ltd
Priority date: 2024-05-27
Filing date: 2024-05-27
Publication date: 2024-08-16

Abstract

The embodiment of the invention discloses an instruction processing method, device, equipment and medium in a processor simulator. The method comprises the following steps: acquiring an instruction packet in a preset format, and identifying a processing stage described by each instruction in the instruction packet; and reordering the processing stages according to the arrangement sequence of the descriptions of the instructions in the instruction packet and the preset pipeline stage sequence matched with the hardware execution sequence to generate a software simulation execution code. The method can identify the execution sequence of the hardware execution program, and further automatically generate a software simulation execution code according to the hardware execution program, thereby realizing the simulation of hardware equipment and saving the workload of writing the manual code.

Description

Instruction processing method, device, equipment and medium in processor simulator

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a method, an apparatus, a device, and a medium for processing instructions in a processor simulator.

Background

In the simulation test of a hardware device, it is generally necessary to rewrite a hardware execution program originally applied to the hardware device into a software simulation execution code to realize the software simulation of the hardware device.

For example, in a static multi-issue processor, a compiler typically organizes multiple instructions into instruction packets for instruction issue in instruction packet units. The processor can transmit a plurality of instructions in one instruction packet in parallel in one clock cycle so as to improve the running efficiency. In software simulation of a static multi-issue processor, parallel behavior of instruction packets needs to be simulated.

In conventional implementations, developers need to manually write software-concurrent execution code for each instruction package. With the complexity of the structure and the function of the processor, the workload of the developer is more and more complex, and the technical requirements on the developer are higher and higher. For example, in tensor processors, the behavior of instructions and the structure of instruction packages are complex, and the manual writing of software simulates the execution of code is very labor intensive.

Disclosure of Invention

The invention provides an instruction processing method, device, equipment and medium in a processor simulator, which are used for realizing the simulation of hardware equipment and saving the workload of writing artificial codes.

According to an aspect of the present invention, there is provided a method of instruction processing in a processor simulator, the method comprising:

Acquiring an instruction packet in a preset format, and identifying a processing stage described by each instruction in the instruction packet;

And reordering the processing stages according to the arrangement sequence of the description of each instruction in the instruction packet and the preset pipeline stage sequence matched with the hardware execution sequence to generate a software simulation execution code.

Optionally, identifying a processing stage described by each instruction in the instruction packet includes:

And identifying the operation type described by each instruction in the instruction packet, and determining the processing stage corresponding to the instruction description according to the operation type.

Optionally, identifying an operation type of each instruction description in the instruction packet, and determining a processing stage of the corresponding instruction description according to the operation type, where the processing stage includes at least one of the following:

when the operation type of the instruction description is single-element or multi-element operation, determining the processing stage of the instruction description as execution;

Determining the processing stage of the instruction description as executing and writing the register when the operation type of the instruction description is the register assignment;

when the operation type described by the instruction is read-write memory, determining the processing stage described by the instruction as executing and accessing;

when the operation type described by the instruction is jump control, determining the processing stage described by the instruction as execution and flow control; and

When the operation type described by the instruction is conditional execution, determining the sub-operation type under the conditional branch; and determining the processing stage corresponding to the instruction description according to the execution condition and the sub-operation type.

Optionally, the preset pipeline stage sequence matched with the hardware execution sequence includes: sequentially arranging execution, access, register writing and flow control;

reordering each processing stage according to the arrangement sequence of each instruction description in the instruction packet and the preset pipeline stage sequence matched with the hardware execution sequence to generate a software simulation execution code, wherein the software simulation execution code comprises the following steps:

extracting execution instruction sentences in instruction descriptions corresponding to execution processing stages in the instruction packet, and sequencing each execution instruction sentence according to the sequence of each instruction description in the instruction packet to generate an execution processing stage sequencing result;

Extracting access instruction sentences in the instruction descriptions corresponding to the access processing stages in the instruction packet, and sequencing each access instruction sentence according to the sequence of the instruction descriptions in the instruction packet to generate a sequencing result of the access processing stages;

Extracting write register instruction sentences in instruction descriptions corresponding to write register processing stages in an instruction packet, and sequencing each write register instruction sentence according to the sequence of each instruction description in the instruction packet to generate a write register processing stage sequencing result;

Extracting flow control instruction sentences in the instruction descriptions corresponding to the flow control processing stages in the instruction packet, and sequencing each flow control instruction sentence according to the sequence of each instruction description in the instruction packet to generate a sequencing result of the flow control processing stages;

and sequentially sequencing the execution processing stage sequencing result, the access processing stage sequencing result, the write register processing stage sequencing result and the flow control processing stage sequencing result to generate a software simulation execution code.

Carrying out grammar checking on each instruction description in the instruction packet, and generating a corresponding abstract grammar tree according to each instruction description when the grammar checking is passed; the structure of the abstract syntax tree is that a current leaf node obtains a next father node through one-step execution;

Sequentially deducing and determining the data types of the father nodes from the leaf nodes in the abstract syntax tree until the data types of the root nodes are determined; when the data types of the nodes meet the operation requirements, generating an intermediate representation of a linear structure according to the abstract syntax tree;

processing stages of each intermediate representation corresponding to each instruction description are identified.

Optionally, before identifying the processing stage of each intermediate representation corresponding to each instruction description, further comprising:

and when the instruction is described as a multithreaded parallel instruction, performing multithreaded copying according to the intermediate representation, and generating the intermediate representation under the multithreaded parallel.

Optionally, generating the software simulation execution code includes:

acquiring an execution platform identifier corresponding to a software simulation execution platform, and determining a corresponding software executable program type according to the execution platform identifier;

And performing code conversion on the sequencing result according to the type of the software executable program to generate a software simulation execution code corresponding to the software simulation execution platform.

According to another aspect of the present invention, there is provided an instruction processing apparatus in a processor simulator, the apparatus comprising:

the processing stage identification module is used for acquiring an instruction packet in a preset format and identifying the processing stage described by each instruction in the instruction packet;

and the software simulation execution code generation module is used for reordering the processing stages according to the arrangement sequence described by the instructions in the instruction packets and the preset pipeline stage sequence matched with the hardware execution sequence to generate the software simulation execution code.

According to another aspect of the present invention, there is provided an electronic apparatus including:

At least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the instruction processing method in the processor simulator of any one of the embodiments of the invention.

According to another aspect of the present invention, there is provided a computer readable storage medium storing computer instructions for causing a processor to execute an instruction processing method in a processor simulator according to any embodiment of the present invention.

According to the technical scheme, the instruction packet in the preset format is obtained, and the processing stage described by each instruction in the instruction packet is identified; according to the arrangement sequence of the description of each instruction in the instruction packet and the sequence of the preset pipeline stages matched with the hardware execution sequence, the processing stages are reordered to generate a software simulation execution code, so that the code conversion problem in simulation of hardware equipment is solved, the execution sequence of the hardware execution program can be identified, and the software simulation execution code is automatically generated according to the hardware execution program, thereby realizing the simulation of the hardware equipment and saving the labor capacity for writing the manual code.

It should be understood that the description in this section is not intended to identify key or critical features of the embodiments of the invention or to delineate the scope of the invention. Other features of the present invention will become apparent from the description that follows.

Drawings

In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings required for the description of the embodiments will be briefly described below, and it is apparent that the drawings in the following description are only some embodiments of the present invention, and other drawings may be obtained according to these drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a method for processing instructions in a processor simulator according to a first embodiment of the invention;

FIG. 2 is a flow chart of a determining instruction description processing stage according to a first embodiment of the present invention;

FIG. 3 is a schematic diagram of an abstract syntax tree according to a first embodiment of the present invention;

FIG. 4 is a flow chart of generating software simulation execution code according to a first embodiment of the present invention;

FIG. 5 is a schematic diagram of an instruction processing apparatus in a processor simulator according to a second embodiment of the present invention;

Fig. 6 is a schematic structural diagram of an electronic device implementing an instruction processing method in a processor simulator according to an embodiment of the present invention.

Detailed Description

In order that those skilled in the art will better understand the present invention, a technical solution in the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in which it is apparent that the described embodiments are only some embodiments of the present invention, not all embodiments. All other embodiments, which can be made by those skilled in the art based on the embodiments of the present invention without making any inventive effort, shall fall within the scope of the present invention.

It should be noted that the terms "first," "second," and the like in the description and the claims of the present invention and the above figures are used for distinguishing between similar objects and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments of the invention described herein may be implemented in sequences other than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Example 1

Fig. 1 is a flowchart of an instruction processing method in a processor simulator according to an embodiment of the present invention, where the embodiment is applicable to software simulation of a hardware device, for example, when a static multi-emission processor performs software simulator design, the method may be performed by an instruction processing device in the processor simulator, where the instruction processing device in the processor simulator may be implemented in the form of hardware and/or software, and where the instruction processing device in the processor simulator may be configured in an electronic device, such as a compiler.

The simulator of the processor is a software simulation of the design of the processor chip. For example, the simulator of the processor is computer software running on a workstation such as Linux or Windows. The simulator of the processor may be used as an operating platform for executable software programs on the chip, providing functional simulation, functional testing, performance evaluation, etc. of the processor chip. In particular, before the processor chip is available, the processor chip may be subjected to a simulation test by a simulator of the processor to improve the feasibility of the processor chip development.

In processor chip development, typically the hardware executable program is formed by the developer programming. In emulating a processor chip, what is needed is a software executable. There is a certain difference between a software executable program and a hardware executable program. For example, a software execution program needs to mimic the execution order of instruction pipeline stages in a hardware executable program. In the prior art, a developer is often required to rewrite a hardware executable program into a software executable program. By the instruction processing method in the processor simulator provided by the embodiment of the invention, the automatic generation from a hardware execution program to a software simulation execution code can be realized.

As shown in fig. 1, the method includes:

step 110, obtaining an instruction packet in a preset format, and identifying a processing stage described by each instruction in the instruction packet.

Wherein the instruction packet comprises at least one instruction description. The instruction descriptions may be placed in a certain order. The instruction description may follow a certain format. For example, the preset format may be a format of an instruction description language (Tiny Simulator Language, TSL). The TSL may describe the behavior of an instruction. By way of example, descriptors may describe various operations and flow control operations of scalar and tensor instructions. The TSL descriptor may have the following characteristics: has an expression style of a high-level language. Expressions can be nested without frequently defining and releasing temporary variables. Vectors are first-class citizens and are the underlying data types. Vector registers, temporary vectors, scalar registers, constants can be used easily, directly calculated, and vector memory can be managed automatically. Various rich mathematical computation operations of scalar, vector are supported. Bit operations on registers, intercept vector, subscript operations are supported. Instruction packets in a vector processor can be described, as well as multi-hardware thread instructions. Strict type checking is not easy to use by mistake. The syntax tree of the TSL is constructed directly by using the C language API interface, and the syntax tree can be conveniently embedded into the native code of the software simulator.

The instruction packet with the preset format can be obtained by converting the hardware executable program to a certain extent. For example, information identification may be performed on the hardware executable program to determine the corresponding operation command. For example, operational commands such as addition, subtraction, multiplication, division, assignment, displacement, etc., in a hardware executable program may be identified by an instruction decoder. The compiler can map information of the hardware executable program according to the operation command, and determines the corresponding TSL descriptor, namely, the instruction packet with the preset format is obtained.

In an alternative implementation of the embodiment of the present invention, the following specific description may be used for the TSL descriptor: SR denotes a scalar register, and VR denotes a vector register. For example, SR2 is scalar register 2 and vr3 is vector register 3.add represents a multi-operation addition. If "add SR2 SR3" represents a binary operation, the values of scalar registers SR2 and SR3 are added. sub represents a multi-operation subtraction. For example, "sub VR0 VR1" represents a binary operation, and vector registers VR0 and VR1 are subtracted by element. scalar _set represents a scalar register assignment. For example, "scalar _setsr2sr3" means that the value of SR3 is written into SR 2. vec_copy represents tensor register assignments. If "vec_copy VR2 VR3" indicates a register assignment, vector VR3 is copied to vector VR2.vec_store represents a write memory, e.g. "vec_store SR3 VR4" represents a memory where the value in vector VR4 is written to an address with the value in scalar register SR3 as the address. goto represents a jump. For example, "goto R5" indicates that the processor program address jumps to the address indicated by the value of register SR 5. "if (condition)" indicates a conditional execution statement block, and one of the branch statements is decided to be executed based on the result of the conditional expression. For example, the number of the cells to be processed,

(if(condition)

(vec_copy VR1(add VR2 VR3))

(vec_copy VR1 VR4))

Indicating that this branch "vec_copy VR1 (add VR2 VR 3)" is executed when the condition is true; when the condition is false, this branch "vec_copy VR1 VR 4" is executed.

The above-mentioned exemplary instruction descriptors can be used in a nested manner, so that the behavior of complex tensor instructions can be conveniently described. For example, "vec_copy VR1 (add VR2 VR 3)" means that the values in vector registers VR2 and VR3 are summed and the result is written into VR 1. "vec_store (mul SR3 64) VR4" means that SR3 is multiplied by 64 to get an address, and then vector VR4 is written to the memory of this address.

The instruction descriptors described above may be embodied in blocks of statements. "pblock" represents a statement block key that may be used to describe the behavior of an instruction packet or hardware multithreading, etc. For example, the number of the cells to be processed,

(pblock

(vec_copy VR1(add VR2 VR3))

(vec_store(mul SR3 64)VR4))

A TSL description representing an instruction packet containing two parallel instructions.

In embodiments of the present invention, the processing stage described by an instruction may be a pipeline stage in accordance with which the instruction is executed. For example, the processing stages described by the instructions may include: fetching instructions, fetching operands, executing, accessing memory, writing back, flow control, and the like. The processing stage of identifying the instruction description may be determined by extracting key information of the instruction description and decomposing the instruction. The key information may include: calculation, accessing registers, accessing memory, flow control, etc.

In an alternative implementation of the embodiment of the present invention, identifying a processing stage described by each instruction in the instruction packet includes: the operation type of each instruction description in the instruction packet is identified, and the processing stage corresponding to the instruction description is determined according to the operation type.

Among the types of operations include, but are not limited to: single or multiple operations, register assignments, read and write memory, jump control, and conditional execution. In an embodiment of the present invention, from a pipeline stage analysis of a software simulation, it may be determined that the processing stage includes: execution, access, register writing, and flow control. The processing stages of a particular instruction description are related to the particular type of operation described by the instruction.

Fig. 2 is a flow chart of a determining instruction description processing stage according to a first embodiment of the present invention. As shown in fig. 2, in an alternative implementation manner of the embodiment of the present invention, the operation type described by each instruction in the instruction packet is identified, and a processing stage corresponding to the instruction description is determined according to the operation type, including at least one of the following: when the operation type of the instruction description is single-element or multi-element operation, determining the processing stage of the instruction description as execution; determining the processing stage of the instruction description as executing and writing the register when the operation type of the instruction description is the register assignment; when the operation type described by the instruction is read-write memory, determining the processing stage described by the instruction as executing and accessing; when the operation type described by the instruction is jump control, determining the processing stage described by the instruction as execution and flow control; and determining a sub-operation type under the conditional branch when the operation type described by the instruction is conditional execution; and determining the processing stage corresponding to the instruction description according to the execution condition and the sub-operation type.

When the operation type described by the instruction is conditional execution, determining the sub-operation type under the conditional branch; and determining a processing stage corresponding to the instruction description according to the execution condition and the sub-operation type, wherein the processing stage comprises at least one of the following steps: when the sub operation type under the conditional branch is single-element or multi-element operation, determining the processing stage described by the instruction under the current execution condition as execution; when the sub operation type under the conditional branch is register assignment, determining the processing stage described by the instruction under the current execution condition as an execution register and a write register; when the sub operation type under the conditional branch is read-write memory, determining the processing stage described by the instruction under the current execution condition as execution and memory access; when the sub-operation type under the conditional branch is jump control, determining the processing stage described by the instruction under the current execution condition as execution and flow control; when the sub-operation type under the conditional branch is still conditional execution, determining the next stage operation type under the sub-conditional branch, and determining the processing stage corresponding to the instruction description according to the execution condition and the next stage operation type. The processing stages under the deterministic conditional branches are similar to those under the deterministic conditional branches described above and will not be described again.

It should be noted that the processing stages described above for determining the corresponding instruction according to the operation type may be nested with each other. That is, an instruction description may be composed of one or more operation types, and when determining a corresponding processing stage, only the operation types of each instruction description need to be split, so that according to the technical scheme provided by the embodiment of the invention, the corresponding processing stage is obtained.

Illustratively, one instruction packet in the tensor processor includes the following instructions:

jmp SR2,8 # jump to SR2+8 this address

vadd VR4,VR5,VR6 #VR4＝VR5+VR6

Vst VR7, [ SR8,16] # uses the result of SR8+16 as the address of the memory, and the value of vector VR7 is written into this address

sub SR9,SR10,SR11#SR9＝SR10-SR11

According to the preset format described by TSL, mapping and compiling the instruction packet instructions in the tensor processor can obtain the instruction packet with the following preset format:

(pblock

(goto(add SR2 8))

(vec_copy VR4(add VR5 VR6))

(vec_store(add SR8 16)VR7)

(sreg_set SR9(sub SR10 SR11))

)

According to the method of determining the processing stage described by the instruction provided in the embodiment of the present invention, the (goto (add SR2 8)) may be split into an execution stage t0=sr2+8 and a flow control stage goto T0. (vec_copy VR4 (add VR5 VR 6)) can be split into an execution phase t1=vr5+vr6, and a write-back phase vr4=t1. (vec_store (add SR8 16) VR 7) can be split into an execution phase t2=sr8+1, and an access phase [ T2] =vr 7. Where T2 is the address of the memory to which the VR7 value is written. (sreg _setsr9 (sub SR10 SR 11)) can be split into an execution phase t3=sr10-SR 11, and a write-back phase sr9=t3.

Step 120, reorder the processing stages according to the arrangement order described by the instructions in the instruction packet and the preset pipeline stage order matched with the hardware execution order, and generate the software simulation execution code.

The preset pipeline stage sequence matched with the hardware execution sequence is a software simulation sequence determined according to the hardware execution sequence. The instruction simulation execution according to the software simulation sequence is consistent with the execution result of the instruction execution according to the hardware execution sequence, so that the accuracy and the rationality of the hardware equipment simulation execution are ensured.

In an alternative implementation of the embodiment of the present invention, the preset pipeline stage sequence matched with the hardware execution sequence includes: execution, access, register writing and flow control are sequentially arranged.

The reordering of the processing stages may be based on following an ordering order described by instructions in the instruction packet, satisfying a predetermined pipeline stage order matching the hardware execution order.

Specifically, in an optional implementation manner of the embodiment of the present invention, reordering each processing stage according to an arrangement order described by each instruction in the instruction packet and a preset pipeline stage order matched with a hardware execution order, to generate a software simulation execution code includes: extracting execution instruction sentences in instruction descriptions corresponding to execution processing stages in the instruction packet, and sequencing each execution instruction sentence according to the sequence of each instruction description in the instruction packet to generate an execution processing stage sequencing result; extracting access instruction sentences in the instruction descriptions corresponding to the access processing stages in the instruction packet, and sequencing each access instruction sentence according to the sequence of the instruction descriptions in the instruction packet to generate a sequencing result of the access processing stages; extracting write register instruction sentences in instruction descriptions corresponding to write register processing stages in an instruction packet, and sequencing each write register instruction sentence according to the sequence of each instruction description in the instruction packet to generate a write register processing stage sequencing result; extracting flow control instruction sentences in the instruction descriptions corresponding to the flow control processing stages in the instruction packet, and sequencing each flow control instruction sentence according to the sequence of each instruction description in the instruction packet to generate a sequencing result of the flow control processing stages; and sequentially sequencing the execution processing stage sequencing result, the access processing stage sequencing result, the write register processing stage sequencing result and the control processing stage sequencing result to generate a software simulation execution code.

For the instruction packet example, the generated execution processing stage ordering result is:

T0＝SR2+8

T1＝VR5+VR6

T2＝R8+16

T3＝SR10-SR11

the generated sequencing result of the memory access processing stage is as follows:

[T2]＝VR7

the generated sequencing result of the write register processing stage is as follows:

VR4＝T1

SR9＝T3

The generated control processing stage sequencing result is as follows:

Goto T0

Re-ordering after identifying the processing stage of each instruction description, the final ordering result is generated as follows:

T0＝SR2+8

T1＝VR5+VR6

T2＝R8+16

T3＝SR10-SR11

[T2]＝VR7

VR4＝T1

SR9＝T3

Goto T0

That is, the result of the reordering of the various processing stages is: executing stages contained in all instruction descriptions in an instruction packet, accessing and storing stages contained in all instruction descriptions, writing back a register contained in all instruction descriptions, and controlling stages contained in all instruction descriptions; wherein the plurality of instruction statements in each stage are arranged according to the arrangement order of the corresponding instruction descriptions in the instruction packet.

By the above-described processing, the parallel execution order of the pipeline level can be automatically generated from the instruction descriptions in the instruction packet. The further compiler may generate corresponding software simulation execution codes according to the parallel execution order and the code compiling process.

The code compiling process can adopt an optimization mode of a classical compiler. For example, code compilation includes instruction selection, instruction scheduling, and register allocation. The embodiment of the invention does not limit the code compiling process in detail.

Based on the above embodiment, optionally, generating software simulation execution code includes: acquiring an execution platform identifier corresponding to the software simulation execution platform, and determining a corresponding software executable program type according to the execution platform identifier; and performing code conversion on the sequencing result according to the type of the software executable program to generate a software simulation execution code corresponding to the software simulation execution platform.

Among them, the execution platform identification includes, but is not limited to, an X86 platform identification and an ARM platform identification. Different execution platforms correspond to different software executable program types. According to the type of the software executable program, code conversion is carried out on the sequencing result, and a software simulation execution code corresponding to the software simulation execution platform is generated, which can be: first, different machine instructions, such as x86 instructions, ARM64 instructions, are selected for different platforms. When the instructions are scheduled, corresponding reordering of the machine instruction sequence is performed aiming at pipeline characteristics of different execution platform processors. In register allocation, registers are allocated for instructions according to different platform processor register conventions. And finally, inserting the operation codes of the operation platform to generate the software simulation execution codes which finally correspond to the execution platform. The platform code generating step can be realized by user definition, and can also be realized by means of a third party compiling tool. In addition, the user can generate the hard implementation code of the processor through the custom compiler.

The hardware execution code can be converted into the software execution code through the compiler, so that the simulator automatic simulation of the tensor processor is realized, and a developer is liberated from complicated instruction details. And moreover, the simulation efficiency of the simulator can be improved through the compiler, so that the chip design rate is improved. The code conversion of multiple platforms is realized through the instruction descriptor processor, so that the simulation of the processor chip can be realized on the multiple platforms, and the compatibility of chip design is improved.

On the basis of the above embodiment, optionally, identifying a processing stage described by each instruction in the instruction packet includes: carrying out grammar checking on each instruction description in the instruction packet, and generating a corresponding abstract grammar tree according to each instruction description when the grammar checking is passed; the structure of the abstract syntax tree is that the current leaf node obtains the next father node through one-step execution; sequentially deducing and determining the data types of the father nodes from the leaf nodes in the abstract syntax tree until the data types of the root nodes are determined; when the data types of the nodes meet the operation requirements, generating an intermediate representation of the linear structure according to the abstract syntax tree; processing stages of each intermediate representation corresponding to each instruction description are identified.

The syntax checking may be to check whether the descriptor satisfies a preset format. And alarming for the descriptors which do not meet the preset format so as to correct the descriptors. An abstract syntax tree is a data structure of a program preamble in code. Specifically, the structure of the abstract syntax tree is that the current leaf node obtains the next parent node through one-step instruction execution. For example, fig. 3 is a schematic structural diagram of an abstract syntax tree according to a first embodiment of the present invention. For the TSL descriptors "(a: fp+b: fp) - (c: fp x d: fp)", an abstract syntax tree as shown in fig. 3 can be generated. Wherein, ": fp "indicates that the data type is floating point type.

As shown in fig. 3, the root node of the abstract syntax tree is a subtraction, and the corresponding leaf nodes are an addition (decremented) and a multiplication (decremented). The leaf nodes corresponding to the summing node are the data sources, namely A and b. The leaf nodes corresponding to the multiplication nodes are the data sources, namely c and d. That is, in the abstract syntax tree shown in fig. 3, a and b get an addition node through one-step instruction execution (addition), c and d get a multiplication node through one-step instruction execution (multiplication), and the addition node and the multiplication node get a root node through one-step instruction execution (subtraction).

In an abstract syntax tree, the data type of a certain parent node may be deduced starting from the leaf node. Among them, data types include, but are not limited to integer and floating point types. The data may be scalar data or vector data. As shown in fig. 3, the data types of a and b are floating-point types, and further the corresponding addition nodes are floating-point types; c and d are of floating-point type, and the corresponding multiplication node is of floating-point type; the addition node and the multiplication node are of the floating-point type, and the root node (subtraction) is of the floating-point type. When the data type is deduced, the data type needs to be ensured to meet the operation requirement. For example, floating point and integer data cannot be operated on, otherwise data errors may be caused.

The intermediate representation of the linear structure generated from the abstract syntax tree may be a concrete description of one-step instructions in the abstract syntax tree. For example, the intermediate representation that the abstract syntax tree as shown in fig. 3 may generate is: t0=a+b; t1=c×d; t2=t0-T1. Wherein T0, T1, and T2 are temporary variables.

The specific manner of identifying the processing stage of each intermediate representation corresponding to each instruction description is the same as the foregoing processing stage identification manner, that is, the processing stage is determined according to the operation type, and will not be described herein again.

On the basis of the above embodiment, optionally, before identifying the processing stage of each intermediate representation corresponding to each instruction description, the method further includes: when the instruction is described as a multithreaded parallel instruction, multithreaded replication is performed according to the intermediate representation, and the intermediate representation under multithreaded parallel is generated.

Wherein, multithreading can be understood as that when the processor is multi-core, the multi-cores execute in parallel. The intermediate representation for each core is similar. For example, the intermediate representation in multi-threaded parallelism generated for the intermediate representation t0=a+b may be t0.thread0=a.thread0+b.thread0, t0.thread1=a.thread1+b.thread1, and so on.

Fig. 4 is a flowchart of generating software simulation execution code according to a first embodiment of the present invention. As shown in fig. 4, for a hardware executable program, the instruction description may be converted into a TSL format, and the instruction description is subjected to syntax checking to generate an abstract syntax tree; performing type deduction on the abstract syntax tree to form an intermediate representation of the linear structure; when the multithreading is executed, the intermediate representation of the linear structure is subjected to multithreading copying, and the intermediate representation under the multithreading parallelism is generated; then splitting the processing stage of the intermediate representation under the multithreading parallel and rearranging to generate a sequencing result which is executed according to the pipeline stage; and finally, performing code conversion according to the program type of the execution platform to generate a software simulation execution code corresponding to the software simulation execution platform. Through the processing flow shown in fig. 4, the execution sequence of the hardware execution program can be identified, and then the software simulation execution code is automatically generated according to the hardware execution program, so that the simulation of the hardware equipment is realized, and the workload of writing the manual code is saved.

The application scenario of the instruction processing method in the processor simulator provided by the embodiment of the invention can be that instruction processing is performed in a compiler of a hardware programming language or in a compiler of the processor simulator. The instruction processing is carried out through the compiler, and the obtained software simulation execution code can be executed through the operator in the processor simulator, so that the simulation of the processor is realized.

An exemplary processor simulator architecture, comprising: program loader, analog memory, analog registers, compiler, analog memory, and runner. Wherein: a program loader for reading a hardware execution program; an analog register for simulating a physical register of the processor; the compiler is used for acquiring a hardware execution program and executing the instruction processing method provided by the embodiment of the invention to obtain a software simulation execution code; the simulation memory is used for storing a hardware execution program and a software simulation execution code; and the operator is used for executing the software simulation execution code to obtain a simulation result.

Example two

Fig. 5 is a schematic diagram of an instruction processing apparatus in a processor simulator according to a second embodiment of the present invention. As shown in fig. 5, the apparatus includes: the processing stage identification module 510 and the software simulation execution code generation module 520. Wherein:

The processing stage identifying module 510 is configured to obtain an instruction packet in a preset format, and identify a processing stage described by each instruction in the instruction packet;

The software simulation execution code generating module 520 is configured to reorder each processing stage according to the arrangement order described by each instruction in each instruction packet and the preset pipeline stage order matched with the hardware execution order, so as to generate a software simulation execution code.

Optionally, the processing stage identifying module 510 includes:

The processing stage identification unit is used for identifying the operation type described by each instruction in the instruction packet and determining the processing stage described by the corresponding instruction according to the operation type.

Optionally, the processing stage identifying unit is specifically configured to at least one of the following:

the software simulation execution code generation module 520 includes:

the execution processing stage sequencing result generation unit is used for extracting execution instruction sentences in the instruction descriptions corresponding to the execution processing stages in the instruction packet, sequencing the execution instruction sentences according to the sequence of the instruction descriptions in the instruction packet, and generating an execution processing stage sequencing result;

The memory access processing stage sequencing result generating unit is used for extracting memory access instruction sentences in the instruction descriptions corresponding to the memory access processing stages in the instruction packet, sequencing the access instruction sentences according to the sequence of the instruction descriptions in the instruction packet, and generating a memory access processing stage sequencing result;

The write register processing stage sequencing result generation unit is used for extracting write register instruction sentences in the instruction description corresponding to the write register processing stages in the instruction packet, sequencing each write register instruction sentence according to the sequence of each instruction description in the instruction packet, and generating a write register processing stage sequencing result;

the flow control processing stage sequencing result generating unit is used for extracting flow control instruction sentences in the instruction descriptions corresponding to the flow control processing stages in the instruction packet, sequencing the flow control instruction sentences according to the sequencing order of the instruction descriptions in the instruction packet, and generating a flow control processing stage sequencing result;

and the software simulation execution code generating unit is used for sequentially sequencing the execution processing stage sequencing result, the access processing stage sequencing result, the write register processing stage sequencing result and the flow control processing stage sequencing result to generate the software simulation execution code.

Optionally, the processing stage identifying module 510 includes:

the abstract syntax tree generation unit is used for carrying out syntax checking on each instruction description in the instruction packet, and generating a corresponding abstract syntax tree according to each instruction description when the syntax checking is passed; the structure of the abstract syntax tree is that the current leaf node obtains the next father node through one-step execution;

An intermediate representation determining unit, configured to sequentially derive and determine the data types of the parent nodes from the leaf nodes in the abstract syntax tree until the data types of the root node are determined; when the data types of the nodes meet the operation requirements, generating an intermediate representation of the linear structure according to the abstract syntax tree;

And a processing stage determining unit for identifying the processing stage of each intermediate representation corresponding to each instruction description.

Optionally, the device further includes:

And the multithread copying module is used for carrying out multithread copying according to the intermediate representation to generate the intermediate representation under the multithread parallelism when the instruction is described as the multithread parallel instruction before identifying the processing stage of each intermediate representation corresponding to each instruction description.

Optionally, the software simulation execution code generation module 520 includes:

The program type determining unit is used for acquiring an execution platform identifier corresponding to the software simulation execution platform and determining a corresponding software executable program type according to the execution platform identifier;

and the software simulation execution code generating unit is used for performing code conversion on the sequencing result according to the type of the software executable program to generate a software simulation execution code corresponding to the software simulation execution platform.

The instruction processing device in the processor simulator provided by the embodiment of the invention can execute the instruction processing method in the processor simulator provided by any embodiment of the invention, and has the corresponding functional modules and beneficial effects of the execution method.

Example III

Fig. 6 shows a schematic diagram of the structure of an electronic device 10 that may be used to implement an embodiment of the invention. The electronic device may be used in various forms of digital computers, such as laptops, desktops, workstations, personal digital assistants, servers, blade servers, mainframes, and other appropriate computers. The components shown herein, their connections and relationships, and their functions, are meant to be exemplary only, and are not meant to limit implementations of the inventions described and/or claimed herein.

As shown in fig. 6, the electronic device 10 includes at least one processor 11, and a memory, such as a Read Only Memory (ROM) 12, a Random Access Memory (RAM) 13, etc., communicatively connected to the at least one processor 11, in which the memory stores a computer program executable by the at least one processor, and the processor 11 may perform various appropriate actions and processes according to the computer program stored in the Read Only Memory (ROM) 12 or the computer program loaded from the storage unit 18 into the Random Access Memory (RAM) 13. In the RAM 13, various programs and data required for the operation of the electronic device 10 may also be stored. The processor 11, the ROM 12 and the RAM 13 are connected to each other via a bus 14. An input/output (I/O) interface 15 is also connected to bus 14.

Various components in the electronic device 10 are connected to the I/O interface 15, including: an input unit 16 such as a keyboard, a mouse, etc.; an output unit 17 such as various types of displays, speakers, and the like; a storage unit 18 such as a magnetic disk, an optical disk, or the like; and a communication unit 19 such as a network card, modem, wireless communication transceiver, etc. The communication unit 19 allows the electronic device 10 to exchange information/data with other devices via a computer network, such as the internet, and/or various telecommunication networks.

The processor 11 may be a variety of general and/or special purpose processing components having processing and computing capabilities. Some examples of processor 11 include, but are not limited to, a Central Processing Unit (CPU), a Graphics Processing Unit (GPU), various specialized Artificial Intelligence (AI) computing chips, various processors running machine learning model algorithms, digital Signal Processors (DSPs), and any suitable processor, controller, microcontroller, etc. The processor 11 performs the various methods and processes described above, such as instruction processing methods in a processor simulator.

In some embodiments, the instruction processing method in the processor simulator may be implemented as a computer program tangibly embodied on a computer-readable storage medium, such as the storage unit 18. In some embodiments, part or all of the computer program may be loaded and/or installed onto the electronic device 10 via the ROM 12 and/or the communication unit 19. When the computer program is loaded into RAM 13 and executed by processor 11, one or more steps of the instruction processing method in the processor simulator described above may be performed. Alternatively, in other embodiments, processor 11 may be configured to perform the instruction processing method in the processor simulator in any other suitable manner (e.g., by means of firmware).

Various implementations of the systems and techniques described here above may be implemented in digital electronic circuitry, integrated circuit systems, field Programmable Gate Arrays (FPGAs), application Specific Integrated Circuits (ASICs), application Specific Standard Products (ASSPs), systems On Chip (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various embodiments may include: implemented in one or more computer programs, the one or more computer programs may be executed and/or interpreted on a programmable system including at least one programmable processor, which may be a special purpose or general-purpose programmable processor, that may receive data and instructions from, and transmit data and instructions to, a storage system, at least one input device, and at least one output device.

A computer program for carrying out methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus, such that the computer programs, when executed by the processor, cause the functions/acts specified in the flowchart and/or block diagram block or blocks to be implemented. The computer program may execute entirely on the machine, partly on the machine, as a stand-alone software package, partly on the machine and partly on a remote machine or entirely on the remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that can contain, or store a computer program for use by or in connection with an instruction execution system, apparatus, or device. The computer readable storage medium may include, but is not limited to, an electronic, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any suitable combination of the foregoing. Alternatively, the computer readable storage medium may be a machine readable signal medium. More specific examples of a machine-readable storage medium would include an electrical connection based on one or more wires, a portable computer diskette, a hard disk, a Random Access Memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disc read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide for interaction with a user, the systems and techniques described here can be implemented on an electronic device having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or a trackball) through which a user can provide input to the electronic device. Other kinds of devices may also be used to provide for interaction with a user; for example, feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form, including acoustic input, speech input, or tactile input.

The systems and techniques described here can be implemented in a computing system that includes a background component (e.g., as a data server), or that includes a middleware component (e.g., an application server), or that includes a front-end component (e.g., a user computer having a graphical user interface or a web browser through which a user can interact with an implementation of the systems and techniques described here), or any combination of such background, middleware, or front-end components. The components of the system can be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: local Area Networks (LANs), wide Area Networks (WANs), blockchain networks, and the internet.

The computing system may include clients and servers. The client and server are typically remote from each other and typically interact through a communication network. The relationship of client and server arises by virtue of computer programs running on the respective computers and having a client-server relationship to each other. The server can be a cloud server, also called a cloud computing server or a cloud host, and is a host product in a cloud computing service system, so that the defects of high management difficulty and weak service expansibility in the traditional physical hosts and VPS service are overcome.

It should be appreciated that various forms of the flows shown above may be used to reorder, add, or delete steps. For example, the steps described in the present invention may be performed in parallel, sequentially, or in a different order, so long as the desired results of the technical solution of the present invention are achieved, and the present invention is not limited herein.

The above embodiments do not limit the scope of the present invention. It will be apparent to those skilled in the art that various modifications, combinations, sub-combinations and alternatives are possible, depending on design requirements and other factors. Any modifications, equivalent substitutions and improvements made within the spirit and principles of the present invention should be included in the scope of the present invention.

Claims

1. A method of instruction processing in a processor simulator, comprising:

2. The method of claim 1, wherein identifying the processing stage described by each instruction in the instruction packet comprises:

3. The method of claim 2, wherein identifying the type of operation described by each instruction in the instruction packet and determining the processing stage of the corresponding instruction description based on the type of operation comprises at least one of:

4. The method of claim 1, wherein the predetermined pipeline stage order matching the hardware execution order comprises: sequentially arranging execution, access, register writing and flow control;

5. The method of claim 1, wherein identifying the processing stage described by each instruction in the instruction packet comprises:

6. The method of claim 5, further comprising, prior to identifying the processing stage of each intermediate representation corresponding to each instruction description:

7. The method of claim 1, wherein generating software simulation execution code comprises:

8. An instruction processing apparatus in a processor simulator, comprising:

9. An electronic device, the electronic device comprising:

At least one processor; and

A memory communicatively coupled to the at least one processor; wherein,

The memory stores a computer program executable by the at least one processor to enable the at least one processor to perform the instruction processing method in the processor simulator of any of claims 1-7.

10. A computer readable storage medium storing computer instructions for causing a processor to execute the method of instruction processing in a processor simulator of any of claims 1-7.