CN118483867A - Exposure method for photoetching process - Google Patents
Exposure method for photoetching process Download PDFInfo
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- CN118483867A CN118483867A CN202410779921.6A CN202410779921A CN118483867A CN 118483867 A CN118483867 A CN 118483867A CN 202410779921 A CN202410779921 A CN 202410779921A CN 118483867 A CN118483867 A CN 118483867A
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- 238000000034 method Methods 0.000 title claims abstract description 64
- 238000001259 photo etching Methods 0.000 title abstract description 7
- 238000012360 testing method Methods 0.000 claims abstract description 51
- 238000005520 cutting process Methods 0.000 claims abstract description 7
- 238000004519 manufacturing process Methods 0.000 claims description 14
- 238000000206 photolithography Methods 0.000 claims description 12
- 238000012544 monitoring process Methods 0.000 abstract description 8
- 238000009826 distribution Methods 0.000 abstract description 5
- 235000012431 wafers Nutrition 0.000 description 129
- 239000004065 semiconductor Substances 0.000 description 12
- 238000005516 engineering process Methods 0.000 description 4
- 238000004364 calculation method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 230000005856 abnormality Effects 0.000 description 1
- 230000009286 beneficial effect Effects 0.000 description 1
- 239000000356 contaminant Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000001459 lithography Methods 0.000 description 1
- 238000005259 measurement Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
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- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F1/00—Originals for photomechanical production of textured or patterned surfaces, e.g., masks, photo-masks, reticles; Mask blanks or pellicles therefor; Containers specially adapted therefor; Preparation thereof
- G03F1/38—Masks having auxiliary features, e.g. special coatings or marks for alignment or testing; Preparation thereof
- G03F1/44—Testing or measuring features, e.g. grid patterns, focus monitors, sawtooth scales or notched scales
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70616—Monitoring the printed patterns
- G03F7/70625—Dimensions, e.g. line width, critical dimension [CD], profile, sidewall angle or edge roughness
-
- G—PHYSICS
- G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
- G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
- G03F7/00—Photomechanical, e.g. photolithographic, production of textured or patterned surfaces, e.g. printing surfaces; Materials therefor, e.g. comprising photoresists; Apparatus specially adapted therefor
- G03F7/70—Microphotolithographic exposure; Apparatus therefor
- G03F7/70483—Information management; Active and passive control; Testing; Wafer monitoring, e.g. pattern monitoring
- G03F7/70605—Workpiece metrology
- G03F7/70681—Metrology strategies
- G03F7/70683—Mark designs
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- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)
Abstract
The invention provides an exposure method of a photoetching process, which takes a pattern of a mask plate as an exposure unit on a wafer to repeatedly expose the wafer for a plurality of times, and comprises the following steps: step S1: exposing a first part of the edge exposure unit of the wafer and an exposure unit of the middle area of the wafer according to a first preset exposure sequence; step S2: after rotating the mask plate/wafer by 180 degrees, exposing a second part of the edge exposure unit of the wafer according to a second preset exposure sequence; the exposure unit comprises a chip part and a test structure of a cutting path between chips. The problem that the distribution range and the quantity of the test structures capable of effectively detecting the edge of the wafer are insufficient to meet the requirement of monitoring the quality of the chips at the edge of the wafer is solved.
Description
Technical Field
The invention relates to the field of semiconductor devices, in particular to an exposure method of a photoetching process.
Background
The semiconductor manufacturing process flow is very many and complex, and is easily interfered by a plurality of factors in the manufacturing process, and the interference factors in the manufacturing process can influence the yield of the wafer. These include whether the lithography and etch dimensions are within a stable process window, contaminants, film thickness, etc. Once an abnormality occurs in a certain process step and is not found in time, a situation may result in the rejection of a large number of wafers. In an actual semiconductor process, some measured test structures are disposed on scribe lines of a wafer to monitor the stability of the semiconductor process.
As the wafer size increases, the area of the edge region of the wafer also gradually increases. However, the wafer edge is affected by the semiconductor process, and the yield is not high. Because the area of the cutting path on the wafer is limited, under the condition that the test structure which can be put is limited, the phenomenon of insufficient monitoring of the semiconductor process at the edge part of the wafer exists, and therefore, the yield at the edge part of the wafer is difficult to predict in advance.
For the technology in the art, the problem of monitoring the semiconductor process at the edge of the wafer is solved, and some test structures can be directly added on the photomask. This is not an ideal solution for the situation where the semiconductor technology node is moving towards more advanced technology nodes, the chip size is smaller and the dicing street area is smaller.
Disclosure of Invention
The invention provides an exposure method of a photoetching process, which aims to solve the problem that a test structure for monitoring a manufacturing process cannot effectively monitor the edge position of a wafer when the wafer is manufactured by the semiconductor process in the background technology.
In order to solve the above technical problems, an embodiment of the present invention provides an exposure method for a photolithography process, in which a wafer is repeatedly exposed with a pattern of a mask plate as an exposure unit, the exposure method includes:
Step S1: exposing a first part of the edge exposure unit of the wafer and an exposure unit of the middle area of the wafer according to a first preset exposure sequence;
Step S2: after rotating the mask plate/wafer by 180 degrees, exposing a second part of the edge exposure unit of the wafer according to a second preset exposure sequence;
the exposure unit comprises a chip part and a test structure of a cutting path between chips.
Optionally, the test structures in the plurality of exposure units in the second partial edge exposure unit are close to the edge of the wafer/the test structures in the plurality of exposure units in the second partial edge exposure unit fall into the wafer.
Optionally, the second partial edge exposure unit, the first partial edge exposure unit and the exposure unit in the middle area of the wafer are distributed on the wafer.
Optionally, in step S2, the wafer is rotated 180 degrees.
Optionally, at least one exposure unit is overlapped in the paths of the first preset exposure sequence and the second preset exposure sequence.
An embodiment of the present invention provides a wafer manufacturing method using the exposure method of the photolithography process in the foregoing embodiment, where the wafer manufacturing method includes exposing a plurality of layers of reticles with different patterns, respectively, where the positions of a plurality of layers of corresponding first partial edge exposure units on the wafer are the same; and the positions of the second part edge exposure units corresponding to the layers are the same on the wafer.
Compared with the prior art, the technical scheme of the embodiment of the invention has the following beneficial effects:
In the exposure method of the photoetching process, the first part of the edge exposure unit of the wafer and the exposure unit of the middle area of the wafer are exposed according to the first preset exposure sequence, and after the mask plate/wafer is rotated 180 degrees, the second part of the edge exposure unit of the wafer is exposed according to the second preset exposure sequence. The exposure unit comprises a chip part and a test structure of a cutting path between chips. The second part of the edge exposure unit mainly has a test structure relatively close to the inside of the wafer, and after the rotating mask plate/wafer rotates 180 degrees, the test structure of the second part of the edge exposure unit can be relatively close to the edge of the wafer before the rotation. Therefore, the exposure method provided by the invention can effectively monitor the state of the semiconductor process at the edge part of the wafer under the condition that the test structure of the wafer is not increased.
Drawings
FIG. 1 is a schematic diagram of the distribution of test structures formed on a wafer after exposure by an exposure method of a photolithography process according to an embodiment;
FIG. 2 is a flow chart of an exposure method of a photolithography process according to an embodiment of the present invention;
Fig. 3 to 5 are schematic views of a wafer at different exposure stages in an exposure process according to an exposure method of a photolithography process according to an embodiment of the present invention.
Detailed Description
As described in the background, the distribution range and the number of test structures capable of effectively detecting the wafer edge are insufficient to meet the requirement of monitoring the quality of the wafer edge chip. The following detailed description will be given with reference to the accompanying drawings.
A single wafer may be used to fabricate a plurality of chips, each of which is disposed in a device region, the device regions being separated by a plurality of dicing regions, the dicing regions being referred to as scribe lanes, the scribe lanes having a certain area and generally having test structures fabricated therein that are consistent with the fabrication process of the chips.
In a specific wafer manufacturing process, a currently common wafer exposure method is: firstly customizing test structures with specific patterns at positions corresponding to scribing channels in a mask plate, wherein the mask plate also comprises a semiconductor structure layer of a chip with the specific patterns, and repeatedly exposing a wafer for a plurality of times by taking the mask plate as an exposure unit until the whole wafer is fully exposed; the manufacture of a wafer requires a plurality of layers of masks, and semiconductor structure layers with different patterns are corresponding in different layers of masks. After the multiple layers of masks on the wafer are all fully exposed, multiple complete chips and multiple test structures are formed on the wafer. And finally, simulating the parameters of the critical dimension, the electrical property and the like of the wafer edge chip according to the parameters of the critical dimension, the electrical property and the like of a plurality of test structures close to the wafer edge.
FIG. 1 is a schematic diagram showing the distribution of test structures formed on a wafer after exposure according to the wafer exposure method described above.
Referring to fig. 1, the wafer 10 includes a first partial edge exposure unit 105, a second partial edge exposure unit 103, and an exposure unit 104 in a middle region of the wafer. Test structure 1021 is disposed within scribe line 102 and the chip is located in device region 101. The first partial edge exposure unit 105, the second partial edge exposure unit 103, and the exposure unit 104 of the wafer middle area constitute all exposure units on the wafer. The out-of-wafer exposure unit in fig. 1 is only used to assist in illustrating the wafer exposure sequence. The arrow direction is the exposure sequence.
The test structures 1021 formed in the second part edge exposure unit 103 are far away from the edge of the same wafer 10, so that only the test structures 1021 at the position of the first part edge exposure unit 105 can simulate the edge chips of the wafer 10, and the test structures 1021 at the position of the second part edge exposure unit 103 cannot simulate the edge chips of the wafer 10, so that the distribution and the number of effective edge test structures prepared by the exposure method are less, and the requirement of monitoring the quality of the edge chips of the wafer is not satisfied.
Based on the above-mentioned problems, those skilled in the art have provided some improved embodiments to increase the number of test structures on scribe lanes at the position of the exposure unit on the wafer as much as possible, but this improved method cannot fundamentally solve the problem because the number of total scribe lanes in the wafer is limited and the scribe lanes at a specific position have a specific effect, so that the test structures cannot be placed for placing as many test structures as possible.
In order to solve the above problems, an embodiment of the present invention provides an exposure method for a photolithography process. Fig. 2 is a flow chart of an exposure method of a photolithography process according to an embodiment of the present invention.
Referring to fig. 2, the present invention provides an exposure method for a photolithography process, in which a pattern of a mask plate is repeatedly used as an exposure unit on a wafer to expose the wafer, the exposure method includes:
step S1: and exposing the first part of the edge exposure unit of the wafer and the exposure unit of the middle area of the wafer according to a first preset exposure sequence.
Step S2: and after rotating the mask plate/wafer by 180 degrees, exposing a second part of the edge exposure unit of the wafer according to a second preset exposure sequence.
The exposure unit comprises a chip part and a test structure of a cutting path between chips.
In the exposure method of the photoetching process, the second part of edge exposure unit is exposed after the mask plate/wafer is rotated 180 degrees, so that a test structure formed by exposing the wafer at the position of the second part of edge exposure unit after the wafer is rotated 180 degrees is closer to the edge position of the wafer, the accuracy of detecting the performance of chips at the edge position in the wafer is improved, and the effective on-line monitoring of the edge of the wafer is realized.
In order to make the above objects, features and advantages of the present invention more comprehensible, embodiments accompanied with figures are described in detail below.
Fig. 3 to 5 are schematic views of a wafer at different exposure stages in an exposure process according to an exposure method of a photolithography process according to an embodiment of the present invention.
The invention takes the pattern of a mask plate as an exposure unit on a wafer to repeatedly expose the wafer for a plurality of times.
Referring to fig. 3, the second partial edge exposure unit 103 is calculated. The second partial edge exposure unit 103 refers to: when the wafer 10 is rotated 180 ° to obtain a test structure, the test structure is relatively rotated to the test structure obtained by exposing the wafer before the rotation, the test structure is closer to the wafer edge and may represent the wafer edge chip, and the plurality of exposure units corresponding to the test structures on the wafer are the second partial edge exposure units. The exposure unit comprises a chip part and a test structure in a cutting path between chips.
The calculation mode of the second part edge exposure unit can be based on the position of the pattern of the test structure in the exposure unit before rotation, and the second part edge exposure unit can be obtained after comparing the positions of the test structures at the same exposure unit position on the surface of the wafer after rotating 180 degrees in combination with the positions of the test structures at the same exposure unit position on the surface of the wafer.
Referring to fig. 2 and 3 in combination, step S1 is performed: the first part of the edge exposing unit 105 of the wafer 10 and the exposing unit 104 of the middle area of the wafer 10 are exposed according to a first preset exposure sequence. The first exposure sequence is the exposure sequence indicated by the broken line portion and the arrow direction in fig. 3.
The first preset exposure sequence is obtained according to the foregoing calculation result of the second partial edge exposure unit, and when exposure is performed by the first preset exposure sequence, only the first partial edge exposure unit 105 and the exposure unit 104 of the middle area are passed. The specific exposure mode can be scanning type (Scanner) or stepping type (Stepper).
After exposing the first part edge exposure unit 105 and the middle area exposure unit 104 of the wafer, a number of test structures 1021 and chip part structures (not shown) are formed on the wafer 10.
Referring to fig. 2 and 4, step S2 is performed: after the reticle/wafer is rotated 180 degrees, a second portion of the edge exposure unit 103 of the wafer is exposed in a second predetermined exposure sequence. The second preset exposure sequence is the exposure sequence indicated by the dotted line part and the arrow in fig. 4.
The second partial edge exposure unit 103, the first partial edge exposure unit 105 and the exposure unit 104 in the middle area of the wafer are distributed over the wafer 10.
When exposure is performed by the second preset exposure sequence, only the second partial edge exposure unit 103 is passed. The specific exposure mode can be scanning type (Scanner) or stepping type (Stepper).
After exposing the second partial edge exposure unit 103 of the wafer, a number of test structures 1021 and chip partial structures are formed on the wafer 10.
And the test structures in the plurality of exposure units in the second part edge exposure unit are close to the edge of the wafer/the test structures in the plurality of exposure units in the second part edge exposure unit fall into the wafer.
The second part of the edge exposure unit of the wafer is exposed according to the second preset sequence after the mask/wafer is rotated 180 degrees, so that a test structure formed by exposing the wafer at the position of the second part of the edge exposure unit after the wafer is rotated 180 degrees is closer to the edge position of the wafer, the wafer edge chip can be represented more effectively, the number of the test structures which can represent the chip at the edge of the wafer is expanded, and the accuracy of detecting the performance of the chip at the edge position in the wafer is improved.
The mask/wafer rotation of 180 ° means: in one embodiment, in the step S2, the wafer is rotated 180 degrees. In another embodiment, in the step S2, the mask is rotated 180 degrees.
At least one exposure unit is overlapped in the paths of the first preset exposure sequence and the second preset exposure sequence.
Referring to fig. 2 and 5, the second partial edge exposure unit is rotated 180 degrees, and there is a partial exposure unit that coincides with the partial exposure unit in the first partial edge exposure unit before being rotated 180 degrees, however, in the actual wafer position, there is no overlapping exposure unit between the positions of the first partial edge exposure unit and the second partial edge exposure unit.
The structure after the wafer 10 after the exposure is rotated in the opposite direction is shown in fig. 5 after completing the one-layer exposure process.
Referring to fig. 5, compared to fig. 1, the test structures 1021 in the second partial exposure unit 103 in fig. 5 are all close to the edge of the wafer 10, and can simulate the chips at the edge of the wafer 10.
In summary, the technical scheme provided by the invention adopts a twice exposure mode, and the second part exposure unit is reserved on the basis of one normal exposure of the first part exposure unit, so that the wafer is rotated clockwise or anticlockwise by 180 degrees and then exposed, the test structure formed by exposure after rotation can represent chips at the edge of the wafer, the test structure formed on the wafer can simulate chips in more areas, the accuracy of detecting the performance of chips at the edge position in the wafer is improved, the wafer realizes effective online monitoring of the edge of the wafer, and the wafer has high operability.
An embodiment of the present invention provides a wafer manufacturing method using the exposure method of the photolithography process according to the previous embodiment, where the wafer manufacturing method includes exposing a plurality of layers of reticles with different patterns, respectively, and repeating the steps above: exposing a first part of the edge exposure unit of the wafer and an exposure unit of the middle area of the wafer according to a first preset exposure sequence; and after the mask plate/wafer is rotated 180 degrees, exposing a second part of the edge exposure unit of the wafer according to a second preset exposure sequence until the chip part structure is completely prepared. The positions of the first part of edge exposure units corresponding to the layers are the same on the wafer; and the positions of the second part edge exposure units corresponding to the layers are the same on the wafer.
In order to enable effective alignment between a plurality of layers of structures on a final wafer and form a complete and expected measurement structure of a chip structure and a dicing street, the product adopting the exposure method needs to divide the exposure units of the wafer uniformly according to a first part of edge exposure units, an exposure unit of a middle area of the wafer and a second part of edge exposure units, and the second part of edge exposure units need to be exposed according to a second preset exposure sequence after rotating 180 degrees.
In summary, according to the wafer manufacturing method provided by the invention, the positions of the first partial edge exposure units corresponding to the layers are the same, and the positions of the second partial edge exposure units corresponding to the layers are the same, so that an ideal chip structure can be formed.
Although the present invention is disclosed above, the present invention is not limited thereto. Various changes and modifications may be made by one skilled in the art without departing from the spirit and scope of the invention, and the scope of the invention should be assessed accordingly to that of the appended claims.
Claims (6)
1. An exposure method of a photolithography process, in which a pattern of a mask plate is repeatedly exposed to a wafer as an exposure unit, the exposure method comprising:
Step S1: exposing a first part of the edge exposure unit of the wafer and an exposure unit of the middle area of the wafer according to a first preset exposure sequence;
Step S2: after rotating the mask plate/wafer by 180 degrees, exposing a second part of the edge exposure unit of the wafer according to a second preset exposure sequence;
the exposure unit comprises a chip part and a test structure of a cutting path between chips.
2. The exposure method according to claim 1, wherein the test structures in the plurality of exposure units in the second partial edge exposure unit are close to the edge of the wafer/the test structures in the plurality of exposure units in the second partial edge exposure unit fall into the wafer.
3. The exposure method according to claim 1, wherein the second partial edge exposure unit, the first partial edge exposure unit, and the exposure unit of the wafer middle area are distributed over the wafer.
4. The exposure method according to claim 1, wherein the wafer is rotated 180 degrees in the step S2.
5. The exposure method according to claim 4, wherein at least one exposure unit is overlapped in a path of the first preset exposure sequence and the second preset exposure sequence.
6. A wafer manufacturing method using the exposure method of the photolithography process according to claim 1, the wafer manufacturing method comprising exposing a plurality of layers of reticles of different patterns, respectively, characterized in that a plurality of layers of corresponding first partial edge exposure units are identical in position on the wafer; and the positions of the second part edge exposure units corresponding to the layers are the same on the wafer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410779921.6A CN118483867A (en) | 2024-06-17 | 2024-06-17 | Exposure method for photoetching process |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN202410779921.6A CN118483867A (en) | 2024-06-17 | 2024-06-17 | Exposure method for photoetching process |
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| Publication Number | Publication Date |
|---|---|
| CN118483867A true CN118483867A (en) | 2024-08-13 |
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| Application Number | Title | Priority Date | Filing Date |
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| CN202410779921.6A Pending CN118483867A (en) | 2024-06-17 | 2024-06-17 | Exposure method for photoetching process |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119965135A (en) * | 2025-04-02 | 2025-05-09 | 杭州广立测试设备有限公司 | Wafer automated testing method, device and electronic equipment |
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- 2024-06-17 CN CN202410779921.6A patent/CN118483867A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN119965135A (en) * | 2025-04-02 | 2025-05-09 | 杭州广立测试设备有限公司 | Wafer automated testing method, device and electronic equipment |
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