CN118451554A - Nitride-based semiconductor device and method for manufacturing the same - Google Patents

Abstract

A nitride-based semiconductor device comprises a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first etch stop layer, a gate and a gate isolation layer. The second nitride-based semiconductor layer is arranged on the first nitride-based semiconductor layer and has a larger band gap than the first nitride-based semiconductor layer. The first etch stop layer is arranged on the second nitride-based semiconductor layer and has inner side walls facing each other. The gate is arranged on the first etch stop layer. The gate isolation layer is arranged on the second nitride-based semiconductor layer and is located between the first etch stop layer and the gate. The gate isolation layer has a first corner portion abutting against the inner side wall of the first etch stop layer.

Description

Nitride-based semiconductor device and method for manufacturing the same

Technical Field

The present invention relates generally to nitride-based semiconductor devices and more particularly to nitride-based semiconductor devices having an etch stop layer to improve device reliability.

Background technique

In recent years, research on high electron mobility transistors (HEMTs) has become increasingly prevalent, especially for high power switching and high frequency applications. Group III nitride-based HEMTs utilize a heterojunction interface between two materials with different band gaps to form a quantum well-like structure that accommodates a two-dimensional electron gas (2DEG) region to meet the needs of high power/frequency devices. In addition to HEMTs, examples of devices with heterostructures include heterojunction bipolar transistors (HBTs), heterojunction field effect transistors (HFETs), and modulation doped FETs (MODFETs).

Summary of the invention

In one aspect, the present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first etch stop layer, a gate and a gate isolation layer. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a larger band gap than the first nitride-based semiconductor layer. The first etch stop layer is disposed on the second nitride-based semiconductor layer and has inner side walls facing each other. The gate is disposed on the first etch stop layer. The gate isolation layer is disposed on the second nitride-based semiconductor layer and is located between the first etch stop layer and the gate. The gate isolation layer has a first corner portion abutting against the inner side wall of the first etch stop layer.

In another aspect, the present invention provides a method for manufacturing a nitride-based semiconductor device. The method has the following steps: forming a first nitride-based semiconductor layer; forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer; forming a first etch stop layer on the second nitride-based semiconductor layer; forming a first dielectric layer on the first etch stop layer; removing a portion of the first dielectric layer to expose the first etch stop layer; removing the exposed portion of the first etch stop layer to form an opening; forming a gate isolation layer on the second nitride-based semiconductor layer and extending to the opening; forming a gate on the gate isolation layer.

In yet another aspect, the present invention provides a nitride-based semiconductor device. The nitride-based semiconductor device includes a first nitride-based semiconductor layer, a second nitride-based semiconductor layer, a first etch stop layer, a second etch stop layer, a gate isolation layer and a gate. The second nitride-based semiconductor layer is disposed on the first nitride-based semiconductor layer and has a band gap greater than the band gap of the first nitride-based semiconductor layer. The first etch stop layer is disposed on the second nitride-based semiconductor layer. The second etch stop layer is disposed on the first etch stop layer. The gate isolation layer is disposed on the second nitride-based semiconductor layer and extends from the first etch stop layer to the second etch stop layer. The gate is disposed on the first etch stop layer and the second etch stop layer and is separated from the first etch stop layer and the second etch stop layer by the gate isolation layer.

Through the above configuration, the etch stop layer extending from the gate isolation layer to other components can be electrically isolated from the gate, thereby blocking leakage current from the gate.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects of the present invention may be readily understood from the following detailed description when read in conjunction with the accompanying drawings. It should be noted that various features may not be drawn to scale. That is, the dimensions of various features may be arbitrarily increased or decreased for clarity. Embodiments of the present invention are described in more detail below with reference to the accompanying drawings, in which:

1 is a vertical cross-sectional view of a nitride-based semiconductor device according to some embodiments of the present invention; and

2A , 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J and 2K illustrate different stages of a method for manufacturing a nitride-based semiconductor device according to some embodiments of the present invention.

Detailed ways

The same reference numerals are used in the drawings and detailed description to indicate the same or similar components. Embodiments of the present invention will be readily understood from the following detailed description taken in conjunction with the accompanying drawings.

Spatial descriptions such as "upper", "lower", "left", "right", "top", "bottom", "vertical", "horizontal", "side", "higher", "lower", etc. are specified relative to a component or a group of components, or a plane of a component or a group of components, for the orientation of the components shown in the figures. It should be understood that the spatial descriptions used herein are for illustrative purposes only, and the specific implementations of the structures described herein may be spatially arranged in any orientation or manner as long as such arrangement does not deviate from the spirit of the present invention.

Furthermore, it should be noted that, subject to device manufacturing conditions, in actual devices, the actual shapes of various structures depicted as approximately rectangular may be curved, or have rounded corners, or have slightly non-uniform thicknesses, etc. Straight lines and right angles are used only for convenience in representing layers and features.

In the following description, semiconductor devices/die/packages and methods for manufacturing the same are described as preferred examples. It is apparent that modifications, including additions and/or substitutions, may be made without departing from the scope and spirit of the present invention. Specific details may be omitted to avoid confusion. However, the purpose of writing the present invention is to enable those skilled in the art to practice its teachings without excessive experimentation.

1 is a vertical cross-sectional view of a nitride-based semiconductor device 1A according to some embodiments of the present invention. The nitride-based semiconductor device 1A includes a substrate 10, nitride-based semiconductor layers 12, 14, etch stop layers 20, 24, 27, a gate dielectric layer 22, dielectric layers 26, 28, 30, 32, 34, 36, an isolation structure 38, electrodes 40, 42, a conductive layer 44, a gate isolation layer 50, a gate 52, patterned conductive layers 60, 66, contact vias 62, 64, 68 and a pad 70.

The substrate 10 may be a semiconductor substrate. Exemplary materials of the substrate 10 may include, but are not limited to, Si, SiGe, SiC, gallium arsenide, p-doped Si, n-doped Si, sapphire, semiconductor on insulator (e.g., silicon on insulator (SOI)), or other suitable substrate materials. In some embodiments, the substrate 10 may include, but is not limited to, group III elements, group IV elements, group V elements, or combinations thereof (e.g., III-V compounds). In other embodiments, the substrate 10 may include, but is not limited to, one or more other features, such as doped regions, buried layers, epitaxial (epi) layers, or combinations thereof.

In some embodiments, the nitride-based semiconductor device 1A may further include a buffer layer (not shown). The buffer layer is disposed between the substrate 10 and the nitride-based semiconductor layer 12. The buffer layer may be configured to reduce the lattice and thermal mismatch between the substrate 10 and the nitride-based semiconductor layer 12, thereby overcoming defects caused by the mismatch/difference. The buffer layer may include a III-V compound. The III-V compound may include, but is not limited to, aluminum, gallium, indium, nitrogen, or a combination thereof. Therefore, exemplary materials of the buffer layer may further include, but are not limited to, GaN, AlN, AlGaN, InAlGaN, or a combination thereof.

In some embodiments, the semiconductor device 1A may further include a nucleation layer (not shown). The nucleation layer may be formed between the substrate 10 and the buffer layer. The nucleation layer is configured to provide a transition to accommodate the mismatch/difference between the substrate 10 and the group III nitride layer of the buffer layer. Exemplary materials of the nucleation layer may include, but are not limited to, AlN or any alloy thereof.

The nitride-based semiconductor layer 12 may be disposed on the buffer layer. The nitride-based semiconductor layer 14 may be disposed on the nitride-based semiconductor layer 12. Exemplary materials of the nitride-based semiconductor layer 12 may include, but are not limited to, nitrides or III-V compounds, such as GaN, AlN, InN, In _{x AlyGa (1-xy)} N (where x+y≤1), or Al _x Ga _(1-x) N (where x≤1). Exemplary materials of the nitride-based semiconductor layer 14 may include, but are not limited to, nitrides or III-V compounds, such as GaN, AlN, InN, In _{x AlyGa (1-xy)} N (where x+y≤1), or Al _y Ga _(1-y) N (where y≤1).

The exemplary materials of the nitride-based semiconductor layers 12 and 14 are selected so that the band gap (i.e., the forbidden band width) of the nitride-based semiconductor layer 14 is greater than the band gap of the nitride-based semiconductor layer 12, so that their electron affinities are different from each other and a heterojunction is formed therebetween. For example, when the nitride-based semiconductor layer 12 is an undoped GaN layer with a band gap of about 3.4 eV, the nitride-based semiconductor layer 14 may be selected as an Algan layer with a band gap of about 4.0 eV. In this way, the nitride-based semiconductor layers 12 and 14 can be used as a channel layer and a barrier layer, respectively. A triangular well potential is generated at the bonding interface between the channel layer and the barrier layer, so that electrons accumulate in the triangular well, thereby generating a two-dimensional electron gas (2DEG) region adjacent to the heterojunction. Therefore, the semiconductor device 1A can be used to include at least one GaN-based high electron mobility transistor (HEMT).

The etch stop layer 20 is provided on the nitride-based semiconductor layer 14. The etch stop layer 20 covers the nitride-based semiconductor layer 14.

The gate dielectric layer 22 is disposed on the etch stop layer 20 . The gate dielectric layer 22 covers the etch stop layer 20 .

The etch stop layer 20 can remain stable during the etching phase of the gate dielectric layer 22. The etch stop layer 20 and the gate dielectric layer 22 have different materials. In some embodiments, the etch stop layer 20 includes AlN and the gate dielectric layer 22 includes SiN. In some embodiments, the etch stop layer 20 is an aluminum nitride layer and the gate dielectric layer 22 is a silicon nitride layer. The etch stop layer 20 is thinner than the gate dielectric layer 22. In some embodiments, the etch stop layer 20 has a thickness in the range of about 1 nm to 3 nm. In some embodiments, the gate dielectric layer 22 has a thickness in the range of about 25 nm to about 35 nm.

The etch stop layer 24 is disposed on the nitride-based semiconductor layer 14. The etch stop layer 24 is disposed on the etch stop layer 20 and the gate dielectric layer 22. The etch stop layer 24 has inner side walls facing each other.

The dielectric layer 26 is disposed on the etch stop layer 24. The dielectric layer 26 has inner sidewalls facing each other. The dielectric layer 26 covers the etch stop layer 24.

Etch stop layer 24 can remain stable during the etching phase of dielectric layer 26. Etch stop layer 24 and dielectric layer 26 have different materials. In some embodiments, etch stop layer 24 includes AlN, and dielectric layer 26 includes an oxide, such as _SiOx . In some embodiments, etch stop layer 24 is an aluminum nitride layer, and dielectric layer 26 is a silicon oxide layer. Etch stop layer 24 is thinner than dielectric layer 26. In some embodiments, etch stop layer 24 has a thickness in the range of about 1 nm to 3 nm. In some embodiments, gate dielectric layer 22 has a thickness in the range of about 15 nm to about 25 nm.

The etch stop layer 27 is disposed on the nitride-based semiconductor layer 14. The etch stop layer 27 is disposed on the etch stop layer 24 and the dielectric layer 26. The etch stop layer 27 has inner side walls facing each other. The distance between the inner side walls of the etch stop layer 27 is greater than the distance between the inner side walls of the etch stop layer 24. The distance between the inner side walls of the etch stop layer 27 is greater than the distance between the inner side walls of the dielectric layer 26.

Dielectric layer 28 is disposed on etch stop layer 27. Dielectric layer 28 has inner sidewalls facing each other. Dielectric layer 28 covers etch stop layer 27. The distance between the inner sidewalls of dielectric layer 28 is greater than the distance between the inner sidewalls of etch stop layer 24. The distance between the inner sidewalls of dielectric layer 28 is greater than the distance between the inner sidewalls of dielectric layer 26.

Etch stop layer 27 can remain stable during the etching phase of dielectric layer 28. Etch stop layer 27 and dielectric layer 28 have different materials. In some embodiments, etch stop layer 27 includes AlN, and dielectric layer 28 includes an oxide, such as _SiOx . In some embodiments, etch stop layer 27 is an aluminum nitride layer, and dielectric layer 28 is a silicon oxide layer. Etch stop layer 27 is thinner than dielectric layer 28. In some embodiments, etch stop layer 27 has a thickness in the range of about 1 nm to 3 nm. In some embodiments, dielectric layer 28 has a thickness in the range of about 50 nm to about 70 nm.

In some embodiments, etch stop layers 20, 24, 27 are parallel to each other. In some embodiments, etch stop layers 20, 24, 27 have the same material or compound, which is different from the material or compound of gate dielectric layer 22, dielectric layer 26, and dielectric layer 28. In some embodiments, dielectric layer 26 and dielectric layer 28 have the same material or compound, which is different from the material or compound of gate dielectric layer 22.

Dielectric layer 30 is disposed on dielectric layer 28. Dielectric layer 30 covers dielectric layer 28. Dielectric layer 30 has inner sidewalls facing each other. The distance between the inner sidewalls of dielectric layer 30 is substantially the same as the distance between the inner sidewalls of dielectric layer 28. In some embodiments, dielectric layer 28 includes an oxide, such as _SiOx . In some embodiments, dielectric layer 30 is a silicon oxide layer.

Electrodes 40 and 42 are disposed on the nitride-based semiconductor layer 14. Electrode 40 may be covered by dielectric layer 30. Electrode 40 may sequentially penetrate dielectric layer 28, etch stop layer 27, dielectric layer 26, etch stop layer 24, gate dielectric layer 22, and etch stop layer 20 to contact nitride-based semiconductor layer 14. Electrode 42 may be covered by dielectric layer 30. Electrode 42 may sequentially penetrate dielectric layer 28, etch stop layer 27, dielectric layer 26, etch stop layer 24, gate dielectric layer 22, and etch stop layer 20 to contact nitride-based semiconductor layer 14. Each electrode 40 and may be used as a source or a drain. In some embodiments, electrodes 40 and 42 may be referred to as ohmic electrodes. Conductive layer 44 is located between dielectric layer 28 and electrode 40 and between dielectric layer 28 and electrode 42. Conductive layer 44 includes TiN.

In some embodiments, electrodes 40 and 42 may include, but are not limited to, metals, alloys, doped semiconductor materials (e.g., doped crystalline silicon), compounds such as silicides and nitrides, other conductor materials, or combinations thereof. Exemplary materials of electrodes 40 and 42 may include, but are not limited to, Ti, AlSi, TiN, or combinations thereof. Electrodes 40 and 42 may be single layers or multiple layers of the same or different compositions. In some embodiments, electrodes 40 and 42 may form ohmic contacts with nitride-based semiconductor layer 14. Ohmic contacts may be achieved by applying Ti, Al, or other suitable materials to electrodes 40 and 42.

In some embodiments, each electrode 40 and 42 is formed by at least one conformal layer and a conductive filler. The conformal layer may encapsulate the conductive filler. Exemplary materials of the conformal layer include but are not limited to Ti, Ta, TiN, Al, Au, AlSi, Ni, Pt, or a combination thereof. Exemplary materials of the conductive filler may include but are not limited to AlSi, AlCu, or a combination thereof.

The gate isolation layer 50 is disposed on the nitride-based semiconductor layer 14. The gate isolation layer 50 is located between the electrodes 40 and 42. The gate isolation layer 50 is located on the etch stop layer 20 and the gate dielectric layer 22, so that the etch stop layer 20 and the gate dielectric layer 22 are located between the nitride-based semiconductor layer 14 and the gate isolation layer 50. The gate isolation layer 50 may be in contact with the top surface of the gate dielectric layer 22. The gate isolation layer 50 may be in contact with the top surface and the inner sidewall of the dielectric layer 26. The gate isolation layer 50 may extend from the etch stop layer 24 to the etch stop layer 27. More specifically, the gate isolation layer 50 may extend from the top surface of the gate dielectric layer 22 to the top surface of the dielectric layer 30. The gate isolation layer 50 may extend along the inner sidewalls of the dielectric layer 30, the dielectric layer 28, the etch stop layer 27, the dielectric layer 26, and the etch stop layer 24. The inner sidewalls of the etch stop layers 24 and 27 are in contact with the gate isolation layer 50. The gate isolation layer 50 has a stepped profile. In some embodiments, the material of the gate isolation layer 50 may include, but is not limited to, a dielectric material. For example, the gate isolation layer 50 may include _SiNx , _SiOx , SiON, SiC, SiBN, SiCBN, oxide, nitride, plasma enhanced oxide (PEOX), or a combination thereof.

The gate 52 is disposed on the dielectric layer 30, the dielectric layer 28, the etch stop layer 27, the dielectric layer 26, the etch stop layer 24, the gate dielectric layer 22, and the etch stop layer 20. The gate isolation layer 50 is located between the etch stop layer 24 and the gate 52. The gate isolation layer 50 is located between the etch stop layer 27 and the gate 52. The gate 52 may be formed as a single layer, or multiple layers of the same or different compositions. Exemplary materials of the metal or metal compound may include, but are not limited to, W, Au, Pd, Ti, Ta, Co, Ni, Pt, Mo, TiN, TaN, a metal alloy or a compound thereof, or other metal compounds. The electrodes 40, 42 and the gate 52 may constitute a depletion-mode GaN-based HEMT.

Gate 52 has portions 522, 524, 526. Portion 524 is located on portion 522. Portion 524 is wider than portion 522. Portion 526 is located on portion 524. Portion 526 is wider than portion 524. Due to the different widths, gate 52 can be used as multiple field plates. For example, the end of portion 524 outside portion 522 can be used as a field plate. Similarly, the end of portion 526 outside portion 524 can be used as a field plate.

In order to achieve such a profile of the gate 52, multiple etching stages are performed before forming the gate 52. Therefore, the etching stop layers 24 and 27 are applied thereon. Thus, the device applying at least one etching stop layer to the structure may cause leakage current because the etching stop layer may become a leakage current path in the structure. In order to improve this defect, a gate isolation layer 50 and a gate 52 may be provided.

More specifically, the gate isolation layer 50 may wrap at least the bottom surface of the gate 52. Therefore, the gate 52 may be separated from the etch stop layers 24 and 27 by the gate isolation layer 50. The gate isolation layer 50 has a bottom corner portion abutting against the inner sidewall of the etch stop layer 24. The gate isolation layer 50 has a bottom surface connecting one of the bottom corner portions to another. The gate isolation layer 50 has an intermediate corner portion abutting against the inner sidewall of the etch stop layer 27.

The reason for this configuration is that the inner sidewalls of the etch stop layers 24 and 27 may become a leakage current entrance, so the gate isolation layer 50 can cover the entrance and isolate the entrance from the gate 52. In this way, the etch stop layer 24 extending from the gate isolation layer 50 to the electrode 40 or 42 is electrically isolated from the gate 52, thereby blocking potential leakage current from the gate 52. Similarly, the etch stop layer 27 extending from the gate isolation layer 50 to the electrode 40 or 42 is electrically isolated from the gate 52, thereby blocking potential leakage current from the gate 52. Therefore, a plurality of field plate configurations can be implemented through a single gate, and the reliability of the device can be avoided from being impaired.

The dielectric layer 32 is disposed on the dielectric layer 30. The dielectric layer 32 is disposed on the gate 52. The dielectric layer 32 covers the dielectric layer 30 and the gate 52. In some embodiments, the material of the dielectric layer 32 may include, but is not limited to, a dielectric material. For example, the dielectric layer 32 may include _SiNx , _SiOx , SiON, SiC, SiBN, SiCBN, oxide, nitride, plasma enhanced oxide (PEOX), or a combination thereof.

Dielectric layer 34 is disposed on dielectric layer 32. In some embodiments, the material of dielectric layer 34 may include, but is not limited to, dielectric materials. For example, dielectric layer 34 may include _SiNx , _SiOx , SiON, SiC, SiBN, SiCBN, oxide, nitride, PEOX, or a combination thereof.

Dielectric layer 36 is disposed on dielectric layer 34. In some embodiments, the material of dielectric layer 34 may include, but is not limited to, dielectric materials. For example, dielectric layer 34 may include _SiNx , _SiOx , SiON, SiC, SiBN, SiCBN, oxide, nitride, PEOX, or a combination thereof.

The isolation structure 38 is disposed on the nitride-based semiconductor layer 12. The isolation structure 38 may extend from the nitride-based semiconductor layer 12 to the dielectric layer 32 and further to the bottom surface of the dielectric layer 34. The isolation structure 38 may be doped with ions for electrical isolation purposes. The ions may include, but are not limited to, nitrogen ions, fluorine ions, oxygen ions, argon atoms, aluminum atoms, or combinations thereof. These dopants may give the isolation structure 38 a high resistivity and thus act as an electrical isolation region.

The patterned conductive layer 60 is disposed on the dielectric layer 32. The patterned conductive layer 60 is covered by the dielectric layer 34. The patterned conductive layer 60 may include metal lines, pads, traces, or a combination thereof, so that the patterned conductive layer 60 may form at least one circuit. The patterned conductive layer 60 may include a single-layer film or a multi-layer film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or a combination thereof.

Contact vias 62 are disposed within dielectric layers 32 and 34. Contact vias 62 extend longitudinally to electrically connect electrodes 40 and 42. Exemplary materials of contact vias 62 may include, but are not limited to, conductive materials such as metals or alloys.

The contact via 64 is disposed in the dielectric layer 34. The contact via 64 extends longitudinally to electrically connect the patterned conductive layer 60. Exemplary materials of the contact via 64 may include, but are not limited to, conductive materials such as metals or alloys.

The patterned conductive layer 66 is disposed on the dielectric layer 34. The patterned conductive layer 66 is covered by the dielectric layer 36. The patterned conductive layer 66 may include metal lines, pads, traces, or a combination thereof, so that the patterned conductive layer 66 may form at least one circuit. The patterned conductive layer 66 may include a single-layer film or a multi-layer film having Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or a combination thereof.

Contact vias 68 are disposed within dielectric layer 36. Contact vias 68 extend longitudinally to electrically connect patterned conductive layer 66. Exemplary materials of contact vias 66 may include, but are not limited to, conductive materials such as metals or alloys.

The pad 70 is disposed on the contact via 68. The pad 70 is disposed within the dielectric layer 36. The pad 70 has an area not covered by the dielectric layer 36. The pad 70 may include a single-layer film or a multi-layer film including Ag, Al, Cu, Mo, Ni, Ti, alloys thereof, oxides thereof, nitrides thereof, or combinations thereof.

As described below, Figures 2A, 2B, 2C, 2D, 2E, 2F, 2G, 2H, 2I, 2J and 2K illustrate different stages of a method for manufacturing a semiconductor device 1A. Hereinafter, deposition techniques may include, but are not limited to, atomic layer deposition (ALD), physical vapor deposition (PVD), chemical vapor deposition (CVD), metal organic CVD (MOCVD), plasma enhanced CVD (PECVD), low pressure CVD (LPCVD), plasma assisted vapor deposition, epitaxial growth or other processes.

2A , a substrate 10 is provided. A nitride-based semiconductor layer 12 is formed on the substrate 10. A nitride-based semiconductor layer 14 is formed on the nitride-based semiconductor layer 12. An etch stop layer 20 is formed on the nitride-based semiconductor layer 14. A gate dielectric layer 22 is formed on the etch stop layer 20.

2B , an etch stop layer 24 is formed on the gate dielectric layer 22. A dielectric layer 26 is formed on the etch stop layer 24. An etch stop layer 27 is formed on the dielectric layer 26. A dielectric layer 28 is formed on the etch stop layer 27. A conductive layer 44 is formed on the dielectric layer 28.

2C, the conductive layer 44 is patterned. Electrodes 40 and 42 are formed on the conductive layer 44. Electrodes 40 and 42 sequentially penetrate dielectric layer 28, etch stop layer 27, dielectric layer 26, etch stop layer 24, gate dielectric layer 22, and etch stop layer 20 to contact nitride-based semiconductor layer 14. Before forming electrodes 40 and 42, a plurality of etching stages are performed. In the etching stage, etch stop layers 20, 24, 27 may function. For example, during the etching stage of gate dielectric layer 22, etch stop layer 20 may remain stable so that nitride-based semiconductor layer 14 may be protected from damage in the etching stage of gate dielectric layer 22.

2D, a dielectric layer 30 is formed on the dielectric layer 28. The dielectric layer 30 covers the electrodes 40 and 42.

2E, some portions of dielectric layers 28 and 30 are removed. After removal, a portion of etch stop layer 27 is exposed. The removal of dielectric layers 28 and 30 may be achieved through an etching phase. During the etching phase of dielectric layers 28 and 30, etch stop layer 27 may provide an etching stop function. For example, for the same etchant applied during the etching phase, etch stop layer 27 and dielectric layers 28 and 30 have different etching rates.

2E, some portions of dielectric layers 28 and 30 are removed. After removal, a portion of etch stop layer 27 is exposed. The removal of dielectric layers 28 and 30 can be achieved by using an etching phase. During the etching phase of dielectric layers 28 and 30, etch stop layer 27 can provide an etching stop function. For example, for the same etchant applied during the etching phase, etch stop layer 27 and dielectric layers 28 and 30 have different etching rates.

2F, the exposed portion of the etch stop layer 27 is removed to form an opening so that a portion of the dielectric layer 26 is exposed from the opening. The removal of the etch stop layer 27 can be achieved through an etching stage. The removal of the portions of the dielectric layers 28 and 30 as described in FIG. 2E and the removal of the exposed portion of the etch stop layer 27 as described in FIG. 2F are performed by using different etchants. In addition, during the etching stage, the dielectric layer 26 remains almost undamaged due to the high etching selectivity.

Referring to FIG. 2G , a portion of dielectric layer 26 is removed. After removal, a portion of etch stop layer 24 is exposed. Removal of dielectric layer 26 may be achieved through an etching phase. During the etching phase of dielectric layer 26, etch stop layer 24 may provide an etching stop function. For example, for the same etchant applied to dielectric layer 26 during the etching phase, etch stop layer 24 and dielectric layer 26 have different etching rates. Thereafter, the exposed portion of etch stop layer 24 is removed to form an opening so that a portion of gate dielectric layer 22 is exposed from the opening. Removal of etch stop layer 24 may be achieved through an etching phase. Removal of portions of dielectric layer 26 and removal of exposed portions of etch stop layer 24 are performed by using different etchants. In addition, during the etching phase of etch stop layer 24, gate dielectric layer 22 remains almost undamaged due to high etching selectivity.

Through multiple etching stages, a stepped profile can be formed.

2H, a gate isolation layer 50 is formed on the nitride-based semiconductor layer 14. The gate isolation layer 50 extends into the openings of the etch stop layers 24 and 27. The gate isolation layer 50 may extend from the dielectric layer 30 to the gate dielectric layer 22 through the dielectric layer 28, the etch stop layer 27, the dielectric layer 26, and the etch stop layer 24.

2I , a gate 52 is formed on the gate isolation layer 50 . The gate 52 is physically separated from the etch stop layers 24 and 27 by the gate isolation layer 52 .

2J, a dielectric layer 32 is formed on the gate 52. A patterned conductive layer 60 is formed on the dielectric layer 32. An isolation structure 38 is formed by doping ions into the structure.

2K, a dielectric layer 34 is formed on dielectric layer 32. Contact vias 62 and 64 are formed in dielectric layer 34. Conductive layer 66 is formed on dielectric layer 34. Conductive layer 66 may be patterned after its formation. Thereafter, a dielectric layer, contact vias and pads are formed on dielectric layer 34 to obtain the structure as described in FIG. 1.

The embodiments were chosen and described in order to best explain the principles of the invention and its practical application, thereby enabling others skilled in the art to understand the invention for various embodiments and with various modifications as are suited to the particular use contemplated.

As used herein and not otherwise defined, the terms "substantially," "essentially," "approximately," and "about" are used to describe and illustrate small variations. When used in conjunction with an event or circumstance, the terms may include instances where the event or circumstance occurs exactly as well as instances where the event or circumstance occurs approximately. For example, when used in conjunction with a numerical value, these terms may encompass a range of variation less than or equal to ±10% of the numerical value, such as less than or equal to ±5%, less than or equal to ±4%, less than or equal to ±3%, less than or equal to ±2%, less than or equal to ±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or less than or equal to ±0.05%. The term "substantially coplanar" may refer to two surfaces within a micrometer distance placed along the same plane, such as two surfaces within 40 μm, 30 μm, 20 μm, 10 μm, or 1 μm placed along the same plane.

As used herein, the singular terms "a", "an", and "the" may include plural referents unless the context clearly indicates otherwise. In the description of some embodiments, a component disposed "on" or "over" another component may encompass the case where the former component is directly disposed on (e.g., physically in contact with) the latter component, as well as the case where one or more intermediate components are located between the former component and the latter component.

Although the present invention has been described and illustrated with reference to specific embodiments of the present invention, these descriptions and illustrations are not restrictive. It should be understood by those skilled in the art that various changes may be made and equivalents may be substituted without departing from the true spirit and scope of the present invention as defined by the appended claims. The illustrations are not necessarily drawn to scale. Due to manufacturing processes and tolerances, there may be differences between the artistic reproduction in the present invention and the actual device. In addition, it should be understood that due to manufacturing processes such as conformal deposition, etching, etc., the actual devices and layers may deviate from the rectangular layer depictions of the drawings and may include corner surfaces or edges, rounded corners, etc. There may be other embodiments of the present invention that are not specifically shown. The description and drawings are to be considered illustrative rather than restrictive. Modifications may be made to adapt specific circumstances, materials, compositions of matter, methods or processes to the objectives, spirit and scope of the present invention. All such modifications are included within the scope of the appended claims. Although the methods disclosed herein have been described with reference to specific operations performed in a particular order, it should be understood that these operations may be combined, subdivided or reordered to form equivalent methods without departing from the teachings of the present invention. Therefore, unless specifically noted herein, the order and grouping of operations are not restrictive.

Claims (25)

1. A nitride-based semiconductor device comprising:

a first nitride-based semiconductor layer;

A second nitride-based semiconductor layer provided on the first nitride-based semiconductor layer and having a larger band gap than the first nitride-based semiconductor layer;

A first etch stop layer disposed on the second nitride-based semiconductor layer and having inner sidewalls facing each other;

A gate electrode disposed on the first etch stop layer; and

A gate isolation layer disposed on the second nitride-based semiconductor layer and between the first etch stop layer and the gate electrode, wherein the gate isolation layer has a first corner portion abutting the inner sidewall of the first etch stop layer.

2. The nitride-based semiconductor device of any one of the preceding claims, wherein the gate spacer has a bottom surface connecting one of the first corner portions to another of the first corner portions.

3. The nitride-based semiconductor device of any one of the preceding claims, further comprising a second etch stop layer disposed on the first etch stop layer and having inner sidewalls facing each other, wherein the gate isolation layer has a second corner abutting the inner sidewalls of the second etch stop layer.

4. The nitride-based semiconductor device of any one of the preceding claims, wherein a distance between the inner sidewalls of the second etch stop layer is greater than a distance between the inner sidewalls of the first etch stop layer.

5. The nitride-based semiconductor device of any one of the preceding claims, further comprising a first dielectric layer disposed between the first and second etch stop layers, wherein the first dielectric layer comprises at least one material different from the first and second etch stop layers.

6. The nitride-based semiconductor device of any one of the preceding claims, wherein the first dielectric layer has a top surface in contact with the gate isolation layer.

7. The nitride-based semiconductor device of any one of the preceding claims, wherein the first dielectric layer has an inner sidewall in contact with the gate isolation layer.

8. A nitride-based semiconductor device according to any one of the preceding claims, wherein the gate isolation layer has a stepped profile.

9. The nitride-based semiconductor device of any one of the preceding claims, wherein the gate has a first portion and a second portion, and the second portion is located on and wider than the first portion.

10. The nitride-based semiconductor device of any one of the preceding claims, further comprising a gate dielectric layer disposed between the second nitride-based semiconductor layer and the gate isolation layer.

11. The nitride-based semiconductor device of any one of the preceding claims, further comprising a third etch stop layer disposed between the second nitride-based semiconductor layer and the gate isolation layer.

12. The nitride-based semiconductor device of any one of the preceding claims, further comprising a source disposed on the second nitride-based semiconductor layer and penetrating the first etch stop layer.

13. The nitride-based semiconductor device of any one of the preceding claims, wherein the first etch stop layer extends from the gate isolation layer to the source.

14. A nitride-based semiconductor device according to any one of the preceding claims, wherein the gate isolation layer surrounds at least a bottom surface of the gate.

15. The nitride-based semiconductor device of any one of the preceding claims, wherein the first etch stop layer comprises an aluminum nitride layer.

16. A method for fabricating a nitride-based semiconductor device, comprising:

Forming a first nitride-based semiconductor layer;

forming a second nitride-based semiconductor layer on the first nitride-based semiconductor layer;

Forming a first etch stop layer on the second nitride-based semiconductor layer;

forming a first dielectric layer on the first etch stop layer;

removing a portion of the first dielectric layer to expose the first etch stop layer;

removing the exposed portion of the first etch stop layer to form an opening;

Forming a gate isolation layer on the second nitride-based semiconductor layer and extending to the opening; and

And forming a grid electrode on the grid isolating layer.

17. The method of any of the preceding claims, wherein the first etch stop layer and the first dielectric layer have different etch rates relative to the same etchant.

18. The method of any of the preceding claims, wherein the gate is physically separated from the first etch stop layer by the gate isolation layer.

19. The method of any of the preceding claims, further comprising forming a source prior to removing the portion of the first dielectric layer.

20. The method of any of the preceding claims, wherein the portion of the first dielectric layer and the exposed portion of the first etch stop layer are removed by different etchants.

21. A nitride-based semiconductor device comprising:

a first nitride-based semiconductor layer;

A second nitride-based semiconductor layer provided on the first nitride-based semiconductor layer and having a larger band gap than the first nitride-based semiconductor layer;

A first etch stop layer disposed on the second nitride-based semiconductor layer;

a second etch stop layer disposed on the first etch stop layer;

a gate isolation layer disposed on the second nitride-based semiconductor layer and extending from the first etch stop layer to the second etch stop layer; and

And a gate electrode disposed on the first and second etch stop layers and separated from the first and second etch stop layers by the gate isolation layer.

22. The nitride-based semiconductor device of any one of the preceding claims, wherein the first and second etch stop layers are parallel to one another.

23. The nitride-based semiconductor device of any one of the preceding claims, further comprising a source disposed on the second nitride-based semiconductor layer and penetrating the first and second etch stop layers.

24. The nitride-based semiconductor device of any one of the preceding claims, wherein the first and second etch stop layers extend from the gate isolation layer to the source.

25. The nitride-based semiconductor device of any one of the preceding claims, wherein the first and second etch stop layers comprise the same compound.