CN118394703B - On-chip interconnection system and on-chip communication method - Google Patents

Abstract

The present invention discloses an on-chip interconnection system and an on-chip communication method, and relates to the field of chip technology. The on-chip interconnection system includes: two interface communication components and an intermediate transmission component; one interface communication component connects an on-chip module, and the other interface communication component connects other on-chip modules or other on-chip interconnection systems; the interface communication component performs clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on the data to be transmitted through a clock domain conversion module, a verification execution module, a protocol conversion module and a bit-frequency conversion module respectively; the intermediate transmission component realizes the step-by-step beat of the transmission data through a cache module. According to the technical solution of the embodiment of the present invention, the on-chip interconnection system not only reduces the routing area of the chip and increases the available area of the on-chip module, but also can realize high-frequency transmission by using a smaller bit width when performing high-bit width data transmission tasks, thereby ensuring higher data transmission efficiency.

Description

In-chip interconnection system and in-chip communication method

Technical Field

The present invention relates to the field of chip technology, and in particular to an intra-chip interconnection system and an intra-chip communication method.

Background Art

With the continuous development of artificial intelligence (AI) technology, AI chips are gradually moving towards high performance and low power consumption. The evolution of upper-level models has made processing large amounts of data and achieving high-bandwidth interconnection important goals in AI chip design.

In the prior art, AI chips usually use traditional Internet networks (for example, FlexNoC structure, etc.) to interconnect multiple on-chip IPs (Intellectual Properties). However, with this interconnection method, as the amount of data processed increases, the bus width will also increase, which will make the routing area larger and in disguise compress the available area of the functional modules.

In addition, due to the relatively complex routing structure of the traditional Internet design itself, it is difficult to achieve high-frequency transmission at high bit widths and cannot meet high-performance requirements. At the same time, when it comes to multiple groups of one-to-one interconnection scenarios within the chip, the internal redundant design of the traditional Internet network will bring more area overhead.

Summary of the invention

The present invention provides an on-chip interconnection system and an on-chip interconnection method to solve the problem that the traditional wiring method has a large wiring area and a low transmission efficiency of the on-chip interconnection system.

According to one aspect of the present invention, there is provided an on-chip interconnection system, comprising:

Two interface communication components and an intermediate transmission component located between the two interface communication components; one interface communication component connects the on-chip module, and the other interface communication component connects other on-chip modules or other on-chip interconnection systems; the interface communication component includes a clock domain conversion module, a check execution module, a protocol conversion module, a bit-frequency conversion module and a configuration management module; the intermediate transmission component includes at least one cache module;

The clock domain conversion module is connected to the verification execution module and is used for clock domain conversion processing of the data to be transmitted;

A verification execution module, connected to a protocol conversion module, is used for verification processing of data to be transmitted;

The protocol conversion module is connected to the bit-frequency conversion module and is used for the communication protocol conversion processing of the data to be transmitted;

A bit-frequency conversion module, connected to the protocol conversion module, is used for bit width conversion and frequency conversion of data to be transmitted;

A configuration management module, used for providing configuration parameters for a clock domain conversion module, a check execution module, a protocol conversion module and a bit-frequency conversion module;

The intermediate transmission component is used to perform the beat transmission of the data to be transmitted through at least one cache module.

According to another aspect of the present invention, there is provided an intra-chip communication method, which is applied to the intra-chip interconnection system described in any embodiment of the present invention, comprising:

The first interface communication component sequentially performs clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on the data to be transmitted sent by the first on-chip module through the internal clock domain conversion module, verification execution module, protocol conversion module and bit-frequency conversion module, so as to send the data to be transmitted to the intermediate transmission component;

The intermediate transmission component performs a beat transmission of the data to be transmitted through at least one buffer module to send the data to be transmitted to the second interface communication component;

The second interface communication component sequentially performs bit width conversion processing, frequency conversion processing, communication protocol conversion processing, verification processing and clock domain conversion processing on the data to be transmitted through the internal bit-frequency conversion module, protocol conversion module, verification execution module and clock domain conversion module, so as to send the data to be transmitted to the second on-chip module.

According to another aspect of the present invention, there is provided an intra-chip communication device, which is applied to the intra-chip interconnection system described in any embodiment of the present invention, comprising:

A first conversion processing module, configured in the first interface communication component, is used to sequentially perform clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on the data to be transmitted sent by the first on-chip module through the internal clock domain conversion module, verification execution module, protocol conversion module and bit-frequency conversion module, so as to send the data to be transmitted to the intermediate transmission component;

A beat transmission execution module, configured in the intermediate transmission component, for executing the beat transmission of the data to be transmitted through at least one buffer module, so as to send the data to be transmitted to the second interface communication component;

The second conversion processing module is configured in the second interface communication component, and is used to perform bit width conversion processing, frequency conversion processing, communication protocol conversion processing, verification processing and clock domain conversion processing on the data to be transmitted through the internal bit-frequency conversion module, protocol conversion module, verification execution module and clock domain conversion module in sequence, so as to send the data to be transmitted to the second on-chip module.

According to another aspect of the present invention, a computer-readable storage medium is provided, wherein the computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a processor to implement the intra-chip communication method described in any embodiment of the present invention when executed.

According to another aspect of the present invention, a computer program product is provided, comprising a computer program, wherein when the computer program is executed by a processor, the computer program implements the intra-chip communication method according to any embodiment of the present invention.

According to the technical solution of the embodiment of the present invention, the interface communication component performs clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on the transmission data through the clock domain conversion module, the verification execution module, the protocol conversion module and the bit-frequency conversion module, respectively, thereby realizing data transmission between the on-chip interconnection system and the on-chip modules, and the intermediate transmission component ensures the step-by-step beating of the data through the cache module. Therefore, the on-chip interconnection system not only reduces the routing area of the chip and expands the available area of the on-chip modules, but also can still use a smaller bit width to achieve high-frequency transmission when performing high-bit-width data transmission tasks, thereby ensuring higher data transmission efficiency. At the same time, for multiple groups of one-to-one interconnection scenarios within the chip, the current on-chip interconnection system only needs to occupy a smaller chip area, avoiding the emergence of redundant area overhead.

It should be understood that the contents described in this section are not intended to identify the key or important features of the embodiments of the present invention, nor are they intended to limit the scope of the present invention. Other features of the present invention will become easily understood through the following description.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

FIG1 is a schematic diagram of the structure of an on-chip interconnection system provided according to a first embodiment of the present invention;

FIG2 is a schematic diagram of the structure of a bit-to-frequency conversion module provided according to Embodiment 1 of the present invention;

FIG3 is a schematic diagram of the structure of an intermediate transmission component provided according to Embodiment 1 of the present invention;

FIG4 is a schematic diagram of data flow of an intermediate transmission component provided according to Embodiment 1 of the present invention;

5 is a schematic diagram of the structure of an interface communication component provided according to Embodiment 2 of the present invention;

6 is a timing diagram of a clock signal shutting down of an intermediate transmission component provided according to a second embodiment of the present invention;

7 is a schematic diagram of an application scenario of an on-chip interconnection system provided according to a specific application scenario 1 of the present invention;

FIG8 is a flow chart of an intra-chip communication method provided according to Embodiment 3 of the present invention;

FIG9 is a schematic diagram of the structure of an intra-chip communication device provided according to a fourth embodiment of the present invention.

DETAILED DESCRIPTION

In order to enable those skilled in the art to better understand the scheme of the present invention, the technical scheme in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of the present invention.

It should be noted that the terms "first", "second", etc. in the specification and claims of the present invention and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the data used in this way can be interchanged where appropriate, so that the embodiments of the present invention described herein can be implemented in an order other than those illustrated or described herein. In addition, the terms "including" and "having" and any variations thereof are intended to cover non-exclusive inclusions, for example, a process, method, system, product or device that includes a series of steps or units is not necessarily limited to those steps or units that are clearly listed, but may include other steps or units that are not clearly listed or inherent to these processes, methods, products or devices.

Embodiment 1

Figure 1 is a structural schematic diagram of an on-chip interconnection system provided in Embodiment 1 of the present invention. As shown in Figure 1, the on-chip interconnection system includes two interface communication components 100 and an intermediate transmission component 200 located between the two interface communication components 100. One interface communication component 100 connects the on-chip module, and the other interface communication component 100 connects other on-chip modules or other on-chip interconnection systems; the intermediate transmission component 200 includes at least one cache module 210.

Circuit modules with different functions are distributed in the chip, namely, on-chip IP (Intellectual Property), which specifically refers to reusable and verified integrated circuit modules, also called on-chip modules; the interface communication component 100 is connected to the on-chip modules or other on-chip interconnection systems on the chip; wherein, the above-mentioned other on-chip interconnection systems can be the traditional interconnection systems already existing on the chip, or can be the on-chip interconnection systems disclosed in the embodiments of the present invention.

When two interface communication components 100 are respectively connected to different on-chip modules, point-to-point (i.e., on-chip module to on-chip module) interconnection communication is realized; when one interface communication component 100 is connected to an on-chip module and the other interface communication component 100 is connected to other on-chip interconnection systems, the on-chip module is conveniently connected to the existing communication network on the chip, that is, the on-chip module is communicatively connected to one or more existing on-chip modules on the chip.

The intermediate transmission component 200 serves as a communication medium between the two interface communication components 100, and is respectively connected to the above-mentioned two interface communication components 100; when the intermediate transmission component 200 includes multiple cache modules 210, it is connected to each interface communication component 100 through the cache modules 210 at both ends; when the intermediate transmission component 200 includes only one cache module 210, it is obvious that it is simultaneously connected to the above-mentioned two interface communication components 100 through the cache module 210; wherein, the cache module 210 can perform caching of transmission data through a register.

The interface communication component 100 includes a clock domain conversion module 110, a check execution module 120, a protocol conversion module 130, a bit-frequency conversion module 140 and a configuration management module 150; wherein the clock domain conversion module 110 is connected to the check execution module 120 and is used for clock domain conversion processing of data to be transmitted. The data transmission frequencies of different functional modules may be different, and the above-mentioned cross-clock domain problem often exists between on-chip modules and on-chip interconnection systems. The clock domain conversion module 110 specifically uses registers as data storage devices, which receive data sent by the upstream module at rate A, and then store the data locally, and send the data to the downstream module at rate B (which may be different from the value of rate A).

The clock domain conversion module 110 can specifically use an asynchronous FIFO (First Input First Output) as a data storage device to send the data to be transmitted in clock domain A to clock domain B; the data bit width and the depth of the internal FIFO of the clock domain conversion module 110 can be pre-configured as needed; accordingly, the clock domain conversion module 110 solves the cross-clock domain problem between the on-chip module and the interface communication component 100; at the same time, when the on-chip interconnection system is configured and generated, in order to ensure the convenience of data transmission, the interface communication component 100 and the cache module 210 also use the same clock domain and communication protocol. Therefore, the clock domain conversion module 110 actually also solves the cross-clock domain problem between the on-chip module and the intermediate transmission component 200.

The configuration management module 150 is used to provide configuration parameters for the clock domain conversion module 110, the verification execution module 120, the protocol conversion module 130 and the bit-frequency conversion module 140; wherein, for the clock domain conversion module 110, the configuration management module 150 provides it with the clock domain information of the on-chip module and the clock domain information of the interface communication component 100; when the on-chip module or the on-chip interconnection system changes the clock domain information, or the interface communication component 100 changes the connection object (i.e., changes to connect with other on-chip modules), the configuration management module 150 is used to update the recorded clock domain information on the on-chip module side and the clock domain information on the interface communication component 100 side.

Optionally, in an embodiment of the present invention, the interface communication component 100 further includes a first selection switch; the first selection switch is respectively connected to the clock domain conversion module 110 and the verification execution module 120; the configuration management module 150 is also used to establish a transmission path between the on-chip module and the clock domain conversion module 110 or the verification execution module 120 through the first selection switch. Specifically, when the clock domain information of the on-chip interconnection component and the on-chip module is different, the configuration management module 150 establishes a transmission channel between the on-chip module and the verification execution module 120 through the first selection switch, and at this time, the clock domain conversion module 110 is actually in an open circuit state and does not participate in the data transmission between the on-chip module and the interface communication component 100.

When the clock domain information of the on-chip interconnect component is the same as that of the on-chip module, for example, the on-chip module connected to the on-chip interconnect component has changed its clock domain, or the on-chip interconnect component is changed to be connected to other on-chip modules, the configuration management module 150 establishes a transmission channel between the on-chip module and the clock domain conversion module 110 through the first selection switch, thereby ensuring that when the clock domains of the on-chip module and the on-chip interconnect component are different, the cross-clock domain problem is solved by the clock domain conversion module 110, and that when the clock domains of the on-chip module and the on-chip interconnect component are the same, the clock domain conversion module 110 does not participate in data transmission, thereby improving data transmission efficiency.

The verification execution module 120 is connected to the protocol conversion module 130, and is used for verification processing of the data to be transmitted; wherein the verification execution module 120 can verify the transmission data according to the verification method of the data transmitted by the on-chip module itself; for example, when the on-chip module transmits data, a parity check bit (Parity) is configured for the transmission data, that is, a parity check bit (Parity) is added for every 8 data bits sent, and the verification execution module 120 can perform parity check on the transmission data according to the verification method of the transmission data itself; the configuration management module 150 can provide the verification execution module 120 with the data verification method of the on-chip module; when the transmission data fails the verification, the verification execution module 120 can report the verification result in the form of an interrupt; wherein the verification result can be reported to the on-chip module through the clock domain conversion module 110, and can also be directly reported to the control module of the current chip through other interfaces.

Optionally, in an embodiment of the present invention, the verification execution module 120 is specifically used to perform a first verification process on the first transmission data sent by the first on-chip module, and to transform the first transmission data into second transmission data matching the second verification process, and to send the second transmission data to the protocol conversion module 130; wherein the number of check bits in the second verification process is less than the number of check bits in the first verification process; the verification execution module 120 is also used to perform a third verification process on the third transmission data sent by the intermediate transmission component 200, and to restore the third transmission data to fourth transmission data matching the fourth verification process, and to send the fourth transmission data to the clock domain conversion module 110; wherein the number of check bits in the fourth verification process is more than the number of check bits in the third verification process.

Specifically, when the A chip module sends out transmission data (i.e., the first transmission data), the A verification execution module 120 in the A interface communication component 100 performs a first verification process on the first transmission data according to the verification method of the first transmission data (i.e., the first verification method). At the same time, since the first verification method has more data bits and the data transmission efficiency is slower, the verification execution module 120 needs to convert the first transmission data into the second transmission data with fewer data verification bits.

Taking the above technical solution as an example, the parity check needs to add a parity check bit for every 8 data bits. Therefore, when sending 1024 bits of data, 128 parity check bits need to be configured, and the error checking and correction (ECC) check only needs to configure 12 data bits for the 1024 bits of data. Therefore, the A check execution module 120 changes the first transmission data of 1024 data bits + 128 check bits into the second transmission data of 1024 data bits + 12 check bits; then the A check execution module 120 transmits the second transmission data to the B interface communication component 100 at the other end through the protocol conversion module 130, the bit-frequency conversion module 140 and the intermediate transmission component 200.

Similarly, when the B chip module sends out transmission data (i.e., the fourth transmission data), the B verification execution module 120 in the B interface communication component 100 performs a fourth verification process on the fourth transmission data according to the verification method of the fourth transmission data (i.e., the fourth verification method). At the same time, since the fourth verification method has a large number of data bits and the data transmission efficiency is slow, the B verification execution module 120 needs to convert the fourth transmission data into the third transmission data with a smaller number of data verification bits.

Taking the above technical solution as an example, the fourth check process can be a parity check, and the third check process can be an ECC check. For the A check execution module 120, it obtains the third transmission data sent by the B check execution module 120, first performs an ECC check on it, and then restores the third transmission data of 1024 data bits + 12 check bits to the fourth transmission data of 1024 data bits + 128 check bits, and then sends it to the A on-chip module through the A clock domain conversion module 110 to ensure that the data sent by the on-chip interconnection component is exactly the same as the received data. In this way, while realizing multi-type data verification, the data transmission efficiency of the on-chip interconnection system is improved, and it is ensured that the data sent by the on-chip module at one end is exactly the same as the received data of the on-chip module at the other end.

The protocol conversion module 130 is connected to the bit-frequency conversion module 140 and is used for the communication protocol conversion processing of the data to be transmitted; the protocol conversion module 130 specifically completes the data conversion between the communication protocol supported by the on-chip module and the communication protocol supported by the on-chip interconnection system; wherein, the configuration management module 150 provides the protocol conversion module 130 with the communication protocol type of the on-chip module and the communication protocol type of the on-chip interconnection system; when the on-chip module or the on-chip interconnection system changes the transmission protocol type, or the interface communication component 100 changes the connection object, the communication protocol on the recorded on-chip module side and the communication protocol on the interface communication component 100 side are configured and updated through the configuration management module 150.

The bit-frequency conversion module 140 is connected to the protocol conversion module 130 and is used for bit width conversion and frequency conversion of data to be transmitted. In order to reduce the chip area occupied by the on-chip interconnection system, the data bit width of the intermediate transmission component 200 needs to be configured to a smaller value, and the data sent by the on-chip module usually has a larger data bit width. Therefore, the bit-frequency conversion module 140 needs to perform frequency doubling processing on the large bit width data to meet the transmission requirements of the intermediate transmission component 200. For example, if 1024 bits of data sent by the on-chip module at a frequency of 2 GHz is obtained, the bit-frequency conversion module 140 converts the data into 512 bits of data sent at a frequency of 4 GHz; and when the small bit width data sent by the intermediate transmission component 200 is obtained, if the data bit width required by the on-chip module as the data receiver is larger, the bit-frequency conversion module 140 also needs to perform frequency division processing on the small bit width data; for example, if 512 bits of data sent by the intermediate transmission component 200 at a frequency of 4 GHz is obtained, the bit-frequency conversion module 140 converts the data into 1024 bits of data sent at a frequency of 2 GHz.

Optionally, in an embodiment of the present invention, the bit-frequency conversion module 140 is specifically configured to perform bit width conversion processing and frequency conversion processing through a synchronous dual-clock first-in-first-out queue. As shown in FIG2 , the source clock unit 142 and the destination clock unit 143 of the bit-frequency conversion module 140 convert the handshake protocol (i.e., the vld/rdy protocol) of the interfaces on both sides into the read and write enable of the first-in-first-out queue 141. The first-in-first-out queue 141 under the synchronous dual clock in the middle can realize frequency division data conversion or frequency multiplication data conversion; wherein, the synchronous dual clock means that the clock domain of the clock signal a and the clock signal b are the same; and the read pointer unit 144 is used to point to the data reading position of the first-in-first-out queue 141 of the synchronous dual clock, and the write pointer unit 145 is used to point to the data writing position of the first-in-first-out queue 141 of the synchronous dual clock. The read judgment unit 146 is used to judge whether the first-in-first-out queue 141 is empty, which affects the data reading of the downstream module, and the write judgment unit 147 is used to judge whether the first-in-first-out queue 141 is full, which affects the data writing of the upstream module.

The synchronous dual-clock first-in-first-out queue configured by the bit-frequency conversion module 140 has a relatively simple control logic because there is no cross-clock domain problem. Compared with the traditional asynchronous dual-clock first-in-first-out queue, it avoids the frequency limitation under the current chip manufacturing process (usually limited to below 2 GHz), increases the data transmission frequency (can be increased to above 5 GHz), and at the same time, the transmission data after frequency division processing greatly compresses the bus bit width, saving chip resources.

The intermediate transmission component 200 is used to perform the beat transmission of the data to be transmitted through at least one cache module 210. The intermediate transmission component 200 is composed of one or more cache modules 210, and the specific number can be pre-configured according to the beat requirement; data beat transmission is actually to delay the transmission data by adding a cache module 210 on the transmission path to eliminate the influence of metastable state.

Optionally, in the embodiment of the present invention, the intermediate transmission component 200 includes at least one second selection switch; the intermediate transmission component 200 is further used to manage the number of cache modules 210 in the transmission channel through the at least one second selection switch. Specifically, one or more second selection switches can be configured in the intermediate transmission component 200, which can select one or more of all cache modules 210 to be added to the transmission channel according to different specific transmission requirements, for example, according to the data type of the transmitted data or the type of the on-chip module, and isolate the remaining cache modules 210 outside the transmission channel, so as to realize flexible configuration of the cache modules 210 in the transmission channel.

For example, the first cache module 210 can be connected to other cache modules 210 through the second selection switch respectively, and then the other cache modules 210 except the first cache module 210 are connected in series in sequence, and finally the first cache module 210 is also connected to the interface communication component 100 at a longer distance through the second selection switch; taking Figure 3 as an example, if the intermediate transmission component 200 includes four cache modules 210, namely, cache module A, cache module B, cache module C and cache module D, the cache module A can be connected to the cache module B, cache module C and cache module D respectively through different second selection switches, and then the cache module B, cache module C and cache module D are connected in series, and finally the cache module A is also connected to the interface communication component 100 at a longer distance through the second selection switch, so that the intermediate transmission component 200 can add any number of cache modules 210 to the transmission channel, realize the control of any beat level, and improve the data transmission range applicable to the intermediate transmission component 200.

Optionally, in an embodiment of the present invention, the intermediate transmission component 200 is also used to split the data to be transmitted into multiple packet transmission data, and split the handshake communication signal into multiple packet handshake signals, so that the packet handshake signal matches the packet transmission data one by one. Specifically, as shown in FIG4, there is often a problem of too high fanout when transmitting large data bit widths, which leads to difficulty in timing convergence. Therefore, the intermediate transmission component 200 can split the transmission data into multiple packet transmission data (i.e., date0 to dateN) according to the number of data bits, and also split the handshake protocol signal (i.e., vld/rdy protocol signal) into multiple groups, i.e., multiple packet handshake signals (i.e., vld0 to vldN, rdy0 to rdyN), and each packet handshake signal drives part of the bit field of the data bus respectively, thereby ensuring the timing convergence of the intermediate transmission component 200.

In particular, the interface communication component 100 and the cache module 210 in the embodiment of the present invention can be pre-stored in the database after development is completed. The computer selects one or more cache modules 210 to form the intermediate transmission component 200 according to the task template, and then the two interface communication components 100 and the intermediate transmission component 200 configured as above are combined into an on-chip interconnection system, and the on-chip interconnection system is parameterized according to the configuration parameters in the parameter configuration table (for example, the bit width and frequency of the intermediate transmission component, the bit width and frequency of the on-chip module connected to the interface communication component, etc.), thereby completing the development of a customized on-chip interconnection system.

According to the technical solution of the embodiment of the present invention, the interface communication component performs clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on the transmission data through the clock domain conversion module, the verification execution module, the protocol conversion module and the bit-frequency conversion module, respectively, thereby realizing data transmission between the on-chip interconnection system and the on-chip modules, and the intermediate transmission component ensures the step-by-step beating of the data through the cache module. Therefore, the on-chip interconnection system not only reduces the routing area of the chip and expands the available area of the on-chip modules, but also can still use a smaller bit width to achieve high-frequency transmission when performing high-bit-width data transmission tasks, thereby ensuring higher data transmission efficiency. At the same time, for multiple groups of one-to-one interconnection scenarios within the chip, the current on-chip interconnection system only needs to occupy a smaller chip area, avoiding the emergence of redundant area overhead.

Embodiment 2

Figure 5 is a structural diagram of an interface communication component provided in Embodiment 2 of the present invention. As shown in Figure 5, the interface communication component 100 also includes a power consumption control module 160; the power consumption control module 160 is connected to the clock domain conversion module 110, the verification execution module 120, the protocol conversion module 130 and the bit-frequency conversion module 140, and is used to control the clock start and stop of the interface communication component 100, and send clock start and stop signals to the downstream cache module, and obtain the clock start and stop signals sent by the upstream cache module.

Specifically, the power consumption control module 160 monitors the transmission data in each channel in real time. If no transmission data is detected passing through a transmission channel within a preset number of clock cycles, the clock signal of the transmission channel in the current interface communication component 100 is turned off, and a clock stop signal is sent to the cache module 210 connected to the current interface communication component 100. The cache module is also used to send the acquired clock start and stop signal to the downstream interface communication component 100 or other downstream cache modules.

After obtaining the clock stop signal, the cache module turns off the clock signal of the current channel, and then continues to send it to the downstream cache module until it is sent to the end cache module. After turning off the clock signal of the current channel, the end cache module continues to send a clock stop signal to the interface communication component 100 connected to it; after obtaining the clock stop signal transmitted by the cache module, the power consumption control module 160 of the interface communication component 100 also turns off the clock signal of the channel, thereby completing the step-by-step shutdown of the clock signal.

Taking Figure 6 as an example, assuming that the data transmission directions of each transmission channel of the cache module are the same, and are all transmitted from the first on-chip module to the second on-chip module, if the intermediate transmission component includes four cache modules, namely, cache module A, cache module B, cache module C and cache module D; then in the T1 stage, the clock signal of each cache module is enabled, that is, each cache module is in a working state; when it comes to the T2 stage, according to the interface communication component 100 connected to the first on-chip module, that is, the interface communication component 100 on the left side, the power consumption control module 160 inside it calculates that the clock signal of cache module A will be turned off, and at this time, cache module B, cache module C and cache module D can still continue to work.

At the T3 stage, the clock signals of cache modules A and B have been turned off, while cache modules C and D are still in working state; at the T4 stage, the clock signals of cache modules A, B and C have been turned off, while cache module D is still in working state; at the T5 stage, the clock signals of cache modules A, B, C and D have been turned off, and each cache module enters an idle state, thereby realizing power consumption monitoring of the intra-chip interconnection system and step-by-step transmission of the clock stop signal, greatly reducing the clock power consumption of the intra-chip interconnection system.

In particular, if the data transmission directions of each transmission channel are different, then it is necessary to shut down the clock signals of each transmission channel separately from the transmission channel dimension. In addition, when the power consumption control module 160 shuts down the clock signal of the current interface communication component 100, it can retain the clock signal of the clock domain conversion module 110, and shut down the clock signals of the verification execution module 120, the protocol conversion module 130, the bit-frequency conversion module 140 and the configuration management module 150, so that when the on-chip module sends transmission data, the clock domain conversion module 110 can obtain it in time to avoid data loss.

Similarly, after the interface communication component 100 turns off the clock signal, if the power consumption control module 160 detects that the clock domain conversion module 110 has received the transmission data, the power consumption control module 160 turns on the clock signals of the verification execution module 120, the protocol conversion module 130, the bit-frequency conversion module 140 and the configuration management module 150, and sends a clock start signal to the cache module connected to the current interface communication component 100. After obtaining the clock start signal, the cache module turns on the clock signal of the current channel, and then continues to send it to the downstream cache module until it is sent to the end cache module. After turning on the clock signal of the current channel, the end cache module continues to send a clock start signal to the interface communication component 100 connected to it; after obtaining the clock start signal transmitted by the cache module, the power consumption control module 160 of the interface communication component 100 also turns on the clock signal of the channel, thereby completing the step-by-step transmission of the clock start signal.

The technical solution of the embodiment of the present invention is a power consumption control module, which realizes the clock start and stop management and clock start and stop signal transmission of the interface communication component by controlling the clock start and stop of the interface communication component, sending the clock start and stop signal to the downstream cache module, and obtaining the clock start and stop signal sent by the upstream cache module. The cache module controls the clock start and stop according to the obtained clock start and stop signal, and sends the clock start and stop signal to the downstream interface communication component or other downstream cache modules, thereby greatly reducing the clock power consumption of the on-chip interconnection system.

Specific application scenario 1

FIG7 is a schematic diagram of an application scenario of an on-chip interconnection system provided by a specific application scenario 1 of the present invention. As shown in FIG7 , four original on-chip modules have been planned on the chip, namely, original on-chip module 1, original on-chip module 2, original on-chip module 3 and original on-chip module 4, and the middle area of the above four original on-chip modules is built by a traditional interconnection system. If four additional on-chip modules are required on the chip at this time, namely, on-chip module A, on-chip module B, on-chip module C and on-chip module D, since the above four original on-chip modules and the traditional interconnection system have occupied a large area, the remaining chip area cannot meet the traditional interconnection system. In this case, the on-chip module A, the on-chip module B, the on-chip module C and the on-chip module D can be respectively configured at different positions of the remaining area, and then an on-chip interconnection system can be respectively configured for the on-chip module A, the on-chip module B, the on-chip module C and the on-chip module D, and the corresponding on-chip module can be connected to the traditional interconnection system through the on-chip interconnection system. Therefore, on the basis of not changing the existing original on-chip module and the traditional interconnection system, the on-chip interconnection system in the embodiment of the present invention only needs to occupy a small chip area, and the newly added on-chip module can be added to the chip with the layout completed, and the interconnection of the newly added on-chip module can be completed.

Embodiment 3

FIG8 is a flow chart of an intra-chip communication method provided in Embodiment 3 of the present invention. The method can be executed by an intra-chip communication device. The intra-chip communication device can be implemented in the form of hardware and/or software. The intra-chip communication device can be configured in the intra-chip interconnection system in any embodiment of the present invention. As shown in FIG8 , the method includes:

S301, the first interface communication component sequentially performs clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on the data to be transmitted sent by the first on-chip module through the internal clock domain conversion module, verification execution module, protocol conversion module and bit-frequency conversion module, so as to send the data to be transmitted to the intermediate transmission component.

S302. The intermediate transmission component performs beat transmission of the data to be transmitted through at least one cache module to send the data to be transmitted to the second interface communication component.

S303, the second interface communication component sequentially performs bit width conversion processing, frequency conversion processing, communication protocol conversion processing, verification processing and clock domain conversion processing on the data to be transmitted through the internal bit-frequency conversion module, protocol conversion module, verification execution module and clock domain conversion module, so as to send the data to be transmitted to the second on-chip module.

According to the technical solution of the embodiment of the present invention, the interface communication component performs clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on the transmission data through the clock domain conversion module, the verification execution module, the protocol conversion module and the bit-frequency conversion module, respectively, thereby realizing data transmission between the on-chip interconnection system and the on-chip modules, and the intermediate transmission component ensures the step-by-step beating of the data through the cache module. Therefore, the on-chip interconnection system not only reduces the routing area of the chip and expands the available area of the on-chip modules, but also can still use a smaller bit width to achieve high-frequency transmission when performing high-bit-width data transmission tasks, thereby ensuring higher data transmission efficiency. At the same time, for multiple groups of one-to-one interconnection scenarios within the chip, the current on-chip interconnection system only needs to occupy a smaller chip area, avoiding the emergence of redundant area overhead.

Embodiment 4

FIG9 is a structural block diagram of an intra-chip communication device provided by Embodiment 4 of the present invention, the device specifically comprising:

The first conversion processing module 401 is configured in the first interface communication component, and is used to perform clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on the data to be transmitted sent by the first on-chip module through the internal clock domain conversion module, verification execution module, protocol conversion module and bit-frequency conversion module in sequence, so as to send the data to be transmitted to the intermediate transmission component;

A beat transmission execution module 402, configured in the intermediate transmission component, is used to execute the beat transmission of the data to be transmitted through at least one buffer module to send the data to be transmitted to the second interface communication component;

The second conversion processing module 403 is configured in the second interface communication component, and is used to perform bit width conversion processing, frequency conversion processing, communication protocol conversion processing, verification processing and clock domain conversion processing on the data to be transmitted through the internal bit-frequency conversion module, protocol conversion module, verification execution module and clock domain conversion module in sequence, so as to send the data to be transmitted to the second on-chip module.

According to the technical solution of the embodiment of the present invention, the interface communication component performs clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on the transmission data through the clock domain conversion module, the verification execution module, the protocol conversion module and the bit-frequency conversion module, respectively, thereby realizing data transmission between the on-chip interconnection system and the on-chip modules, and the intermediate transmission component ensures the step-by-step beating of the data through the cache module. Therefore, the on-chip interconnection system not only reduces the routing area of the chip and expands the available area of the on-chip modules, but also can still use a smaller bit width to achieve high-frequency transmission when performing high-bit-width data transmission tasks, thereby ensuring higher data transmission efficiency. At the same time, for multiple groups of one-to-one interconnection scenarios within the chip, the current on-chip interconnection system only needs to occupy a smaller chip area, avoiding the emergence of redundant area overhead.

The above device can execute the intra-chip communication method provided by any embodiment of the present invention, and has the corresponding functional modules and beneficial effects of the execution method. For technical details not described in detail in this embodiment, please refer to the intra-chip communication method provided by any embodiment of the present invention.

Embodiment 5

In some embodiments, the intra-chip communication method may be implemented as a computer program, which is tangibly contained in a computer-readable storage medium, such as a storage unit. In some embodiments, part or all of the computer program may be loaded and/or installed on a heterogeneous hardware accelerator via a ROM and/or a communication unit. When the computer program is loaded into RAM and executed by a processor, one or more steps of the intra-chip communication method described above may be performed. Alternatively, in other embodiments, the processor may be configured to perform the intra-chip communication method in any other appropriate manner (e.g., by means of firmware).

Various implementations of the systems and techniques described above herein can be implemented in digital electronic circuit systems, integrated circuit systems, field programmable gate arrays (FPGAs), application specific integrated circuits (ASICs), application specific standard products (ASSPs), systems on chips (SOCs), load programmable logic devices (CPLDs), computer hardware, firmware, software, and/or combinations thereof. These various implementations can include: being implemented in one or more computer programs that can be executed and/or interpreted on a programmable system including at least one programmable processor, which can be a special purpose or general purpose programmable processor that can receive data and instructions from a storage system, at least one input device, and at least one output device, and transmit data and instructions to the storage system, the at least one input device, and the at least one output device.

Computer programs for implementing the methods of the present invention may be written in any combination of one or more programming languages. These computer programs may be provided to a processor of a general-purpose computer, a special-purpose computer, or other programmable data processing device, so that when the computer program is executed by the processor, the functions/operations specified in the flow chart and/or block diagram are implemented. The computer program may be executed entirely on the machine, partially on the machine, partially on the machine and partially on a remote machine as a stand-alone software package, or entirely on a remote machine or server.

In the context of the present invention, a computer-readable storage medium may be a tangible medium that may contain or store a computer program for use by or in conjunction with an instruction execution system, device, or equipment. A computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, devices, or equipment, or any suitable combination of the foregoing. Alternatively, a computer-readable storage medium may be a machine-readable signal medium. A more specific example of a machine-readable storage medium may include an electrical connection based on one or more lines, a portable computer disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the foregoing.

To provide interaction with a user, the systems and techniques described herein may be implemented on a heterogeneous hardware accelerator having: a display device (e.g., a CRT (cathode ray tube) or LCD (liquid crystal display) monitor) for displaying information to a user; and a keyboard and a pointing device (e.g., a mouse or trackball) through which a user can provide input to the heterogeneous hardware accelerator. Other types of devices may also be used to provide interaction with a user; for example, the feedback provided to the user may be any form of sensory feedback (e.g., visual feedback, auditory feedback, or tactile feedback); and input from the user may be received in any form (including acoustic input, voice input, or tactile input).

The systems and techniques described herein may be implemented in a computing system that includes backend components (e.g., as a data server), or a computing system that includes middleware components (e.g., an application server), or a computing system that includes frontend components (e.g., a user computer with a graphical user interface or a web browser through which a user can interact with implementations of the systems and techniques described herein), or a computing system that includes any combination of such backend components, middleware components, or frontend components. The components of the system may be interconnected by any form or medium of digital data communication (e.g., a communication network). Examples of communication networks include: a local area network (LAN), a wide area network (WAN), a blockchain network, and the Internet.

A computing system may include a client and a server. The client and the server are generally remote from each other and usually interact through a communication network. The client and server relationship is generated by computer programs running on the corresponding computers and having a client-server relationship with each other. The server may be a cloud server, also known as a cloud computing server or cloud host, which is a host product in the cloud computing service system to solve the defects of difficult management and weak business scalability in traditional physical hosts and VPS services.

It should be understood that the various forms of processes shown above can be used to reorder, add or delete steps. For example, the steps described in the present invention can be executed in parallel, sequentially or in different orders, as long as the desired results of the technical solution of the present invention can be achieved, and this document does not limit this.

The above specific implementations do not constitute a limitation on the protection scope of the present invention. It should be understood by those skilled in the art that various modifications, combinations, sub-combinations and substitutions can be made according to design requirements and other factors. Any modification, equivalent substitution and improvement made within the spirit and principle of the present invention should be included in the protection scope of the present invention.

Claims (8)

1. An on-chip interconnect system, comprising: two interface communication components and an intermediate transmission component positioned between the two interface communication components; one interface communication assembly connects the intra-chip modules, and the other interface communication assembly connects other intra-chip modules or other inter-chip interconnection systems; the interface communication assembly comprises a clock domain conversion module, a verification execution module, a protocol conversion module, a bit frequency conversion module and a configuration management module; the intermediate transmission assembly comprises at least one buffer module;

the clock domain conversion module is connected with the verification execution module and is used for clock domain conversion processing of data to be transmitted;

The verification execution module is connected with the protocol conversion module and is used for verifying the data to be transmitted;

the protocol conversion module is connected with the bit frequency conversion module and is used for carrying out communication protocol conversion processing on data to be transmitted;

the bit frequency conversion module is connected with the protocol conversion module and is used for bit width conversion processing and frequency conversion processing of data to be transmitted;

The configuration management module is used for providing configuration parameters for the clock domain conversion module, the verification execution module, the protocol conversion module and the bit frequency conversion module;

the intermediate transmission component is used for executing beat transmission of data to be transmitted through at least one buffer module;

The verification execution module is further used for performing first verification processing on the first transmission data sent by the first intra-chip module, converting the first transmission data into second transmission data matched with the second verification processing, and sending the second transmission data to the protocol conversion module; wherein the check bit number of the second check processing is less than the check bit number of the first check processing;

The checking execution module is further used for performing third checking processing on third transmission data sent by the intermediate transmission component, restoring the third transmission data into fourth transmission data matched with fourth checking processing, and sending the fourth transmission data to the clock domain conversion module; wherein, the check bit number of the fourth check processing is more than that of the third check processing;

the interface communication assembly further comprises a power consumption control module; the power consumption control module is connected with the clock domain conversion module, the verification execution module, the protocol conversion module, the bit frequency conversion module and the configuration management module and is used for controlling the clock start and stop of the interface communication module, sending a clock start and stop signal to the downstream cache module and obtaining the clock start and stop signal sent by the upstream cache module; the buffer module is also used for controlling the clock start and stop according to the acquired clock start and stop signal and sending the clock start and stop signal to the downstream interface communication assembly or other downstream buffer modules.

2. The on-chip interconnect system of claim 1, wherein the interface communication component further comprises a first selection switch; the first selector switch is respectively connected with the clock domain conversion module and the verification execution module;

the configuration management module is further configured to establish a transmission channel between the on-chip module and the clock domain conversion module or the verification execution module through the first selection switch.

3. The system of claim 1, wherein the bit-to-frequency conversion module is configured to perform a bit-width conversion process and a frequency conversion process by synchronizing a dual-clock fifo queue.

4. The on-chip interconnect system of claim 1, wherein the intermediate transmission component is further configured to split data to be transmitted into a plurality of packet transmission data and split the handshake communication signal into a plurality of packet handshake signals such that the packet handshake signals match the packet transmission data one-to-one.

5. The on-chip interconnect system of claim 1, wherein the intermediate transmission component includes at least one second selector switch;

The intermediate transmission assembly is further configured to manage, through the at least one second selection switch, the number of cache modules that form the transmission channel.

6. An on-chip communication method, applied to the on-chip interconnection system of any one of claims 1-5, comprising:

The first interface communication assembly sequentially passes through an internal clock domain conversion module, a verification execution module, a protocol conversion module and a bit frequency conversion module, and performs clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on data to be transmitted sent by the first in-chip module so as to send the data to be transmitted to the intermediate transmission assembly;

The intermediate transmission assembly executes beat transmission of the data to be transmitted through at least one buffer module so as to send the data to be transmitted to the second interface communication assembly;

The second interface communication assembly sequentially passes through an internal bit frequency conversion module, a protocol conversion module, a verification execution module and a clock domain conversion module, and performs bit width conversion processing, frequency conversion processing, communication protocol conversion processing, verification processing and clock domain conversion processing on data to be transmitted so as to send the data to be transmitted to the second on-chip module.

7. An on-chip communication device, applied to the on-chip interconnection system of any one of claims 1-5, comprising:

The first conversion processing module is configured on the first interface communication assembly and is used for carrying out clock domain conversion processing, verification processing, communication protocol conversion processing, bit width conversion processing and frequency conversion processing on data to be transmitted, which are sent out by the first intra-chip module, sequentially through the internal clock domain conversion module, the verification execution module, the protocol conversion module and the bit frequency conversion module so as to send the data to be transmitted to the intermediate transmission assembly;

The beat transmission execution module is configured in the middle transmission assembly and is used for executing beat transmission of data to be transmitted through the at least one buffer module so as to send the data to be transmitted to the second interface communication assembly;

The second conversion processing module is configured on the second interface communication assembly and is used for sequentially performing bit width conversion processing, frequency conversion processing, communication protocol conversion processing, verification processing and clock domain conversion processing on data to be transmitted through the internal bit frequency conversion module, the protocol conversion module, the verification execution module and the clock domain conversion module so as to send the data to be transmitted to the second on-chip module.

8. A computer-readable storage medium, wherein the computer-readable storage medium stores computer instructions, the computer instructions for causing a processor to perform the on-chip communication method of claim 6.