CN118331919B - Data communication method, address conversion device and electronic equipment - Google Patents

Abstract

The application discloses a data communication method, an address conversion device and electronic equipment, which relate to the memory processing technology, wherein the data communication method is applied to the address conversion device, the address conversion device comprises a translation buffer unit, and the method comprises the following steps: receiving an address conversion request sent by a first node, wherein the address conversion request comprises a virtual address; querying address conversion data corresponding to the virtual address from the translation buffer unit, wherein the address conversion data comprises a corresponding relation between the virtual address and a physical address, the translation buffer unit comprises a first-level buffer unit and a second-level buffer unit, the first-level buffer unit is only associated with the first node, the second-level buffer unit is associated with at least two control nodes including the first node, and a buffer space for the address conversion data can be provided for the at least two control nodes; and converting the virtual address into a corresponding target physical address to be accessed based on the searched address conversion data.

Description

Data communication method, address conversion device and electronic equipment

Technical Field

The present application relates to memory processing technology, and more specifically, to a data communication method, an address conversion device and an electronic device.

Background Art

SMMU (system memory manage unit) is a system-level memory management unit that implements the conversion of virtual addresses to physical addresses.

Figure 1 is a schematic diagram of the principle of address conversion of SMMU. As shown in Figure 1, in the traditional SMMU solution, its address conversion function is mainly implemented by TBU (Translation Buffer Unit) and TCU (Translation Control Unit). When the processor Master issues a virtual address, the TBU in the SMMU obtains the virtual address and searches its own TLB (Translation Lookaside Buffer) to see whether there is an address conversion table corresponding to the virtual address. If it exists, it is directly used. If not, the query request for the virtual address conversion table is sent to the TCU through the switch switch, and the TCU queries the corresponding address conversion table from the memory. Overall, the address conversion delay of the above solution is relatively large, and there is a lot of room for optimization.

Summary of the invention

In view of this, this application provides the following technical solutions:

A first aspect of the present application provides a data communication method, which is applied to an address conversion device, wherein the address conversion device includes a translation buffer unit, and the method includes:

receiving an address translation request sent by the first node, wherein the address translation request includes a virtual address;

Querying address conversion data corresponding to the virtual address from the translation buffer unit, the address conversion data including a correspondence between a virtual address and a physical address, the translation buffer unit including a first-level cache unit and a second-level cache unit, the first-level cache unit is associated only with the first node, and the second-level cache unit is associated with at least two control nodes including the first node, and can provide a cache space for address conversion data for the at least two control nodes;

Based on the found address conversion data, the virtual address is converted into a corresponding target physical address to be accessed.

In one possible implementation, the method further includes:

If the address conversion data is not found from the translation buffer unit, obtaining the address conversion data corresponding to the virtual address based on a translation control unit, wherein the translation control unit is associated with all control nodes;

Wherein, obtaining the address conversion data corresponding to the virtual address based on the translation control unit includes: obtaining the address conversion data corresponding to the virtual address from the translation control unit, or obtaining the address conversion data corresponding to the virtual address from the memory based on the translation control unit.

In a possible implementation, the method further includes:

The storage resources of the current second-level cache unit are dynamically allocated inside each second-level cache unit, and the allocation represents allocating the storage resources to at least two control nodes associated with the current second-level cache unit for use.

In a possible implementation, dynamically allocating storage resources of the current second-level cache unit within each second-level cache unit includes:

Determining priorities of the at least two control nodes based on characteristic parameters of the at least two control nodes associated with the current second-level cache unit;

The storage resources of the second-level cache unit are allocated to each control node based on the priority of the at least two control nodes.

In a possible implementation, after obtaining the address conversion data corresponding to the virtual address based on the translation control unit, the method further includes:

Caching the address translation data in the second-level cache unit includes at least one of the following:

directly caching the address conversion data in the second-level cache unit;

When the first-level cache unit is full of data, the address conversion data is cached in the second-level cache unit;

When the virtual address is a virtual address that is accessed by processing services of at least two control nodes associated with the second-level cache unit, cache the address conversion data in the second-level cache unit;

When the second-level cache unit is full of data, the cache data that meets the first requirement is deleted, and the address conversion data is cached in the second-level cache unit.

In a possible implementation, determining the at least two control nodes associated with the second-level cache unit includes:

Matching the control nodes with the same virtual address involved in the business processing to the same second-level cache unit;

or,

Control nodes with mutually exclusive working states are matched to the same second-level cache unit, wherein the mutual exclusivity indicates that data access instructions will not be issued simultaneously.

A second aspect of the present application provides an address conversion device, including:

A translation buffer unit, comprising a plurality of address translation units, a plurality of first-level buffer units and a plurality of second-level buffer units;

Each address translation unit is associated with a control node, and is used to receive an address translation request sent by the corresponding control node, query corresponding address translation data based on the virtual address in the address translation request, and translate the virtual address into a physical address based on the obtained address translation data;

Each first-level cache unit is connected to an address translation unit, associated with a corresponding control node, and used to cache the obtained address translation data;

Each second-level cache unit is connected to a plurality of the first-level cache units, and is associated with at least two corresponding control nodes, and can simultaneously provide cache space for the at least two control nodes for caching the obtained address conversion data.

In a possible implementation, the method further includes:

The translation control unit is used to query the address translation data corresponding to the virtual address from its own storage space when the address translation data corresponding to the virtual address is not queried in the translation buffer unit, or to control the query from the memory to obtain the address translation data corresponding to the virtual address.

In one possible implementation, where:

At least two control nodes associated with the second-level cache unit are control nodes whose service processing involves the same virtual address;

Alternatively, at least two control nodes associated with the second-level cache unit are control nodes with mutually exclusive working states, wherein the mutual exclusivity indicates that data access instructions will not be issued at the same time.

A third aspect of the present application provides an electronic device, including:

processor;

A memory, configured to store executable instructions of the processor;

Among them, the executable instructions include: receiving an address conversion request sent by a first node, the address conversion request including a virtual address; querying address conversion data corresponding to the virtual address from the translation buffer unit, the address conversion data including the correspondence between the virtual address and the physical address, the translation buffer unit including a first-level cache unit and a second-level cache unit, the first-level cache unit is only associated with the first node, and the second-level cache unit is associated with at least two control nodes including the first node, and can provide cache space for address conversion data for the at least two control nodes; based on the found address conversion data, converting the virtual address into a corresponding target physical address to be accessed.

In a fourth aspect, the present application provides a computer program product, comprising computer-readable instructions. When the computer-readable instructions are executed on an electronic device, the electronic device implements the data communication method of the first aspect or any implementation of the first aspect.

In a fifth aspect, the present application provides a computer storage medium, which carries one or more computer programs. When the one or more computer programs are executed by an electronic device, the electronic device can implement the data communication method of the first aspect or any implementation method of the first aspect.

In the solution provided by the present application, the translation buffer unit used to cache address conversion data includes not only a first-level cache unit associated with a single control node, but also a second-level cache unit associated with multiple control nodes at the same time. Therefore, the cache space of the address conversion data is expanded as a whole, and more address conversion data corresponding to multiple control nodes can be stored; therefore, when the control node subsequently accesses the memory data, it is very likely that the corresponding address conversion data can be found from the translation buffer unit to complete the address conversion, without having to search for the address conversion data in the memory, thereby reducing the delay of address conversion as a whole and improving processing efficiency.

BRIEF DESCRIPTION OF THE DRAWINGS

In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without paying any creative work.

FIG1 is a schematic diagram showing the principle of address conversion performed by SMMU;

FIG2 is a flow chart of a data communication method disclosed in an embodiment of the present application;

FIG3 is a schematic diagram of the architecture principle of the address conversion device disclosed in an embodiment of the present application;

FIG4 is a schematic diagram of query paths for obtaining address conversion data using the conventional solution disclosed in the embodiment of the present application and the solution of the present application;

FIG5 is a flow chart of allocating storage resources to a second-level cache unit disclosed in an embodiment of the present application;

FIG6 is a diagram showing an example of the division of cache sharing groups disclosed in an embodiment of the present application;

FIG7 is a schematic diagram of the structure of an address conversion device disclosed in an embodiment of the present application;

FIG8 is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present application.

DETAILED DESCRIPTION

The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

The embodiments of the present application can be applied to electronic devices. The present application does not limit the product form of the electronic device, which can include but is not limited to smart phones, tablet computers, wearable devices, personal computers (PCs), netbooks, etc., and can be selected according to application requirements.

FIG2 is a flow chart of a data communication method disclosed in an embodiment of the present application. The method shown in FIG2 can be applied to an address translation device, and the address translation device includes a translation buffer unit. The address translation device can be a system memory management unit SMMU. As shown in FIG2, the data communication method can include:

Step 201: Receive an address translation request sent by a first node, where the address translation request includes a virtual address.

Among them, the first node can be any control node inside the electronic device that can access the memory, including but not limited to CPU (Central Processing Unit), GPU (graphics processing unit), TPU (Tensor Processing Unit), NPU (Neural network Processing Unit), FPGA (Field Programmable Gate Array), etc.

When the first node needs to access the target data in the memory, it will send an address conversion request to the address conversion device. The address conversion request includes the virtual address of the data it wants to access, which is not the real physical address of the target data that the first node wants to access. Therefore, the address conversion device needs to convert the virtual address into the physical address corresponding to the target data based on the pre-stored address conversion data representing the mapping relationship between the virtual address and the physical address, so that the first node can read the required target data from the real physical address.

Step 202: Query the address conversion data corresponding to the virtual address from the translation buffer unit, the address conversion data including the correspondence between the virtual address and the physical address, the translation buffer unit including a first-level cache unit and a second-level cache unit, the first-level cache unit is only associated with the first node, and the second-level cache unit is associated with at least two control nodes including the first node, and can provide cache space for address conversion data for the at least two control nodes.

Among them, the address conversion data is the data stored in the translation buffer unit during the historical query process. That is, when the control node previously queried certain data in the memory, it issued an address conversion request carrying the virtual address, and the translation buffer unit of the address conversion device obtained the address conversion data corresponding to the data from the memory and cached it. If a control node subsequently accesses the same virtual address again, the corresponding address conversion data can be directly obtained from the cache without having to search for the address conversion data from the memory. It should be noted that since the storage space of the translation buffer unit is limited, the cached address conversion data therein is also dynamically updated, and the specific update strategy can be set based on scenario requirements.

FIG3 is a schematic diagram of the architecture principle of the address conversion device disclosed in the embodiment of the present application. Among them, the top includes multiple control nodes Master, TLB is a first-level cache unit, shared TLB is a second-level cache unit, TBU represents a translation buffer unit, Switch is a conversion switch, and TCU is a translation control unit. As shown in FIG3, the storage space of the first-level cache unit is small, and it can only cache the address conversion data related to the first node associated with it; the storage space of the second-level cache unit is large, and it can be connected to multiple first-level cache units at the same time. It can be associated with at least two control nodes and cache the address conversion data related to at least two control nodes associated with it. When searching for the address conversion data corresponding to the virtual address from the translation buffer unit, it can be searched step by step, that is, first search from the first-level cache unit whether there is address conversion data corresponding to the virtual address; if not found, continue to search for the address conversion data corresponding to the virtual address from the second-level cache unit.

Combined with Figure 3, from a structural point of view, the first-level cache unit TLB and the translation buffer unit TBU can be integrated into the same hardware module, which is directly connected to the control node Master; each shared TLB can be a separate storage component. The TLB in the address translation device can all use SRAM (Static Random-Access Memory). Since the read and write efficiency of SRAM is very high, it can ensure the efficient processing of address translation.

Step 203: Based on the found address conversion data, convert the virtual address into a corresponding target physical address to be accessed.

After finding the address conversion data corresponding to the virtual address from the translation cache module, the virtual address can be converted into the corresponding target physical address to be accessed and returned to the bus based on the mapping relationship recorded in the found address conversion data, so that the data access process of the control node can continue and access to the target data can be achieved.

Figure 4 is a schematic diagram of the query path for obtaining address conversion data using the traditional solution and the solution of the present application disclosed in the embodiment of the present application, wherein the arrowed curve in the upper figure is the query path of the traditional solution, and the arrowed curve in the lower figure is the query path of the solution of the present application.

Combined with the upper diagram in Figure 4, in the query path of the traditional solution, the control node sends an address conversion request, the translation buffer unit TBU obtains the request, and based on the virtual address carried in the request, searches for the corresponding address conversion data from its corresponding storage module TLB; if the corresponding address conversion data is not found in the TLB, it is necessary to send the address conversion request to the translation control unit TCU through multiple conversion switches, and the control unit TCU obtains the corresponding address conversion data from its own storage module or from the memory, and returns the queried address conversion data to the translation control unit in the original path, and the translation control unit performs address conversion processing based on the address conversion data. This solution is implemented by the translation buffer unit TBU and the translation control unit TCU, and the address conversion delay is about 50~120 processing cycles.

Combined with the following figure in FIG4, in the query path of the solution of the present application, since the second-level cache unit shared TLB is added to the translation buffer unit, the cache space is greatly increased, and the amount of address conversion data that can be cached will also be greatly increased. Therefore, after receiving the address conversion request, it is very likely that the required address conversion data can be queried from the translation buffer unit without having to search in the translation control unit or memory. Therefore, after receiving the address conversion request sent by the control node, the translation buffer unit TBU can find the address conversion data of the virtual address in the corresponding address conversion request from the second-level cache unit shared TLB, and perform address conversion processing based on the queried address conversion data. The implementation of this solution is completed only by the translation cache unit, and after two levels of cache units, the address conversion delay is about 40 to 60 processing cycles, thereby significantly reducing the address conversion delay compared to the traditional technical solution.

In the data communication method described in this embodiment, the device for caching address conversion data includes not only a first-level cache unit associated with a single control node, but also a second-level cache unit associated with multiple control nodes at the same time. Therefore, the cache space of the address conversion data is expanded as a whole, and more address conversion data corresponding to multiple control nodes can be stored; therefore, when the control node subsequently accesses the memory data, it is very likely that the corresponding address conversion data can be found from the translation buffer unit to complete the address conversion, without having to search for the address conversion data in the memory, thereby reducing the delay of address conversion as a whole and improving processing efficiency.

Based on the contents of the foregoing embodiments, the data communication method may further include: if the address conversion data is not queried from the translation buffer unit, obtaining the address conversion data corresponding to the virtual address based on the translation control unit, wherein the translation control unit is associated with all control nodes.

If the address conversion data corresponding to the virtual address is not found in the translation buffer unit, it is necessary to search for the address conversion data from a deeper module or storage space. In the application, when there is no address conversion data corresponding to the virtual address in the translation buffer unit, the address conversion data can be searched from the translation control unit connected to the translation buffer unit; if the address conversion data is still not found in the translation control unit, the translation control unit can control the search for the address conversion data from the memory.

In the above content, whether searching for the address conversion data from the translation control unit or the memory, it can be controlled and implemented by the translation control unit. Therefore, obtaining the address conversion data corresponding to the virtual address based on the translation control unit includes: obtaining the address conversion data corresponding to the virtual address from the translation control unit, or obtaining the address conversion data corresponding to the virtual address from the memory based on the translation control unit.

In one implementation, the data communication method may further include: dynamically allocating storage resources of the current second-level cache unit within each second-level cache unit, wherein the allocation represents allocating storage resources to at least two control nodes associated with the current second-level cache unit for use.

As shown in FIG3, since the second-level cache unit is associated with multiple control nodes, it can provide cache space for multiple control nodes associated with it. In implementation, the translation buffer unit can dynamically allocate the storage space in a second-level cache unit to multiple control nodes associated with the second-level cache unit, and the address conversion data corresponding to each control node can only be stored in the storage space allocated to the corresponding control node in the second-level cache unit. As shown in FIG3, Master0, Master1 and Master2 are control nodes associated with the same second-level cache unit, and the second-level cache unit allocates cache space to Master0, Master1 and Master2 at the same time; if the storage space of the second-level cache unit is 10, the storage space allocated to Master0 is 4, the storage space allocated to Master1 is 3, and the storage space allocated to Master2 is 3. Of course, the above allocation is only an example, and the storage space allocated to multiple control nodes associated with the same second-level cache unit can be the same or different. This application does not limit this, and the specific allocation method can be determined in combination with actual application requirements.

FIG5 shows a flowchart of allocating storage resources to the second-level cache unit disclosed in an embodiment of the present application. In conjunction with FIG5, the dynamic allocation of storage resources of the current second-level cache unit within each second-level cache unit may include:

Step 501: Determine the priorities of at least two control nodes associated with the current second-level cache unit based on characteristic parameters of the at least two control nodes.

Among them, the characteristic parameters include at least any one of the following: control node type, real-time requirements and data transmission volume. In this embodiment, the storage space size of multiple control nodes associated with the same second-level cache unit in the second-level cache unit is not fixed and can be adjusted dynamically. In one example, the importance of different types of control nodes is not limited. For example, the importance of CPU is higher than that of TPU, so the priority of CPU is higher. In order to ensure the processing performance of CPU, it is necessary to allocate more cache space to it, and allocate relatively less cache space to TPU. In other examples, the priority of control node can also be determined according to the real-time requirements and data transmission volume of control node; it can be understood that control nodes with high real-time requirements and large data transmission volume will also be allocated more cache space. Of course, the priority of control node can also be determined based on a comprehensive consideration of multiple factors at the same time. For example, real-time requirements and data transmission volume can be combined at the same time, and the two can be weighted and summed to obtain a comprehensive score, and the priority of different control nodes can be determined based on the comprehensive score.

Step 502: Allocate storage resources of a second-level cache unit to each control node based on the priority of the at least two control nodes.

After the priorities of different control nodes are determined, the storage resources of the second-level cache unit can be allocated to each control node according to the priority level, so as to ensure that each control node can run smoothly on this allocation scheme.

The previous article also introduced the dynamic allocation of storage resources of the current second-level cache unit. In the application, the data transmission volume of a control node is different in different working states. For example, when the device has video output, the GPU must perform a large amount of data transmission and processing. Therefore, when there is video output, more storage resources can be allocated to the GPU in the second-level storage unit; when the device has no video output content, less storage resources can be allocated to the GPU in the second-level storage unit to meet its different resource requirements.

The data communication method described in this embodiment can dynamically allocate storage resources to each control node according to the characteristic parameters of multiple control nodes associated with the second-level cache unit during implementation, thereby ensuring reasonable storage resource allocation and guaranteeing smooth progress of related work of each control node.

In the aforementioned embodiment, after the translation control unit obtains the address conversion data corresponding to the virtual address, the method may further include: caching the address conversion data in the second-level cache unit. The address conversion data is cached in the second-level cache unit so that when a control node subsequently accesses data at the same virtual address, the corresponding address conversion data can be quickly found from the second-level cache unit for address conversion processing.

In one implementation, after obtaining the address translation data, the address translation data can be directly cached in the second-level cache unit. In this implementation, other situations are not considered, and whether the first-level cache unit will store the address translation data is not considered. As long as the address translation data is obtained from the translation control unit, it will be stored in the second-level cache unit.

In another implementation, the address conversion data is cached in the second-level cache unit. When the first-level cache unit is full of data, the address conversion data can be cached in the second-level cache unit.

When the first-level cache unit is full of data, the address conversion data may be cached in the second-level cache unit to ensure that the overall cache has more address conversion data; when the first-level cache unit is not full of data, the second-level cache unit may be configured to store the address conversion data or not.

In another implementation, the address conversion data is cached in the second-level cache unit. When the virtual address is a virtual address that is accessed by processing services of at least two control nodes associated with the second-level cache unit, the address conversion data can be cached in the second-level cache unit.

If the obtained address conversion data corresponds to two or more control nodes corresponding to the second-level cache unit, the address conversion data can be cached in the second-level cache unit so that other control nodes other than the first node currently accessing the data can query the corresponding address access data from the second-level cache unit shared with the first node when accessing the same data.

In another implementation, the address conversion data is cached in the second-level cache unit. When the second-level cache unit is full of data, the cache data that meets the first requirement can be deleted and the address conversion data can be cached in the second-level cache unit.

Wherein, the first requirement may include at least one of the following: the longest cache time, the lowest query frequency, and the lowest real-time requirement of the corresponding control node. In the case where the first requirement is the longest cache time, if new address conversion data is received, the address conversion data first stored in the second-level cache unit will be deleted to release storage space to store the latest address conversion data. In the case where the first requirement is the lowest query frequency, the address conversion data that has not been queried for the longest time in the second-level cache unit will be deleted to release storage space to store the latest address conversion data. In the case where the first requirement is the lowest real-time requirement of the corresponding control node, the address conversion data corresponding to the control node with the lowest real-time requirement among the control nodes corresponding to the second-level cache unit will be deleted to release storage space to store the latest address conversion data; it can be understood that since the real-time requirement of the corresponding control node is the lowest, even if the required address conversion data is not queried in the second-level cache unit, searching for the required address conversion data from the translation control unit or the memory can basically meet the latency requirements of the corresponding control node and meet its work requirements.

The above content introduces a variety of different implementations of caching the address conversion data in the second-level cache unit, which is convenient for technicians in the field to better understand and implement the technical solution of this application. It should be noted that the different implementations are not exclusive, and in actual application scenarios, multiple storage strategies can also be combined to control the storage of address conversion data in the second-level storage unit, and this application does not have fixed restrictions on this.

In the aforementioned embodiment, the determination of at least two control nodes associated with the second-level cache unit may include: matching control nodes with the same virtual address involved in service processing to the same second-level cache unit.

That is, based on the sharing association between different control nodes (there is shared data), the control nodes that access the same virtual address are divided into a cache sharing group, and the control nodes in the group are matched to the same second-level cache unit at the same time. It can be understood that since the control nodes in a cache sharing group will access the same data, when one of the control nodes accesses a certain data to obtain an address conversion data and caches it in the second-level cache unit, and other control nodes in the cache sharing group also access the same data later, the previously cached address conversion data can be quickly found in the second-level cache unit.

In another implementation, determining at least two control nodes associated with the second-level cache unit may include: matching control nodes with mutually exclusive working states to the same second-level cache unit, wherein the mutual exclusivity indicates that data access instructions will not be issued simultaneously.

Among them, the control nodes with mutually exclusive working states, that is, when one control node is in working state (issuing instructions), the other control node is in non-working state (will not issue instructions), and they can work in different scenarios respectively. In this way, the mutually exclusive working nodes will not use the second-level cache unit at the same time, so the storage space of the second-level cache unit does not need to be set too large, thereby saving resource configuration. If two mutually exclusive nodes share a second-level cache unit, the storage space of the second-level cache unit can meet the use of one control node.

In this embodiment, a resource optimization combination strategy combining "sharing/mutual exclusion" at the system level is adopted to automatically divide all control nodes into cache sharing groups. The cache sharing groups can be divided based on sharing associations to improve the hit rate of address conversion data found in the translation buffer unit; based on mutual exclusion associations, low-cost configuration of overall resources is achieved. Figure 6 is an example diagram of the division of cache sharing groups disclosed in the embodiment of the present application, in which the two dotted circles indicate the configuration resource architecture of the two cache sharing groups. In conjunction with Figure 6, Master0, Master1 and Master2 contained in the dotted circle on the left belong to the same cache sharing group, and the three control nodes share the first second-level cache unit; Master3 and Master4 contained in the dotted circle on the right belong to the same cache sharing group, and the two control nodes share the second second-level cache unit.

For the aforementioned method embodiments, for the sake of simplicity, they are all described as a series of action combinations, but those skilled in the art should be aware that the present application is not limited by the order of the actions described, because according to the present application, some steps can be performed in other orders or simultaneously. Secondly, those skilled in the art should also be aware that the embodiments described in the specification are all preferred embodiments, and the actions and modules involved are not necessarily required by the present application.

The method is described in detail in the embodiments disclosed in the above-mentioned application. The method of the application can be implemented by various forms of devices. Therefore, the application also discloses a device, and a specific embodiment is given below for detailed description.

FIG7 is a schematic diagram of the structure of an address conversion device disclosed in an embodiment of the present application. Referring to FIG7 , the address conversion device 70 may include:

The translation buffer unit 701 includes a plurality of address conversion units 7011, a plurality of first-level buffer units 7012, and a plurality of second-level buffer units 7013 (one second-level buffer unit is shown as an example in FIG. 7 );

Each address conversion unit 7011 is associated with a control node, and is used to receive an address conversion request sent by the corresponding control node, query corresponding address conversion data based on the virtual address in the address conversion request, and convert the virtual address into a physical address based on the obtained address conversion data;

Each first-level cache unit 7012 is connected to an address translation unit, associated with a corresponding control node, and is used to cache the obtained address translation data;

Each second-level cache unit 7013 is connected to multiple first-level cache units, associated with at least two corresponding control nodes, and can simultaneously provide cache space for the at least two control nodes for caching the obtained address conversion data.

The translation buffer unit of the address conversion device described in this embodiment is used to cache address conversion data. It not only includes a first-level cache unit associated with a control node alone, but also includes a second-level cache unit associated with multiple control nodes at the same time. Therefore, the cache space of the address conversion data is expanded as a whole, and more address conversion data corresponding to multiple control nodes can be stored. Therefore, when the control node accesses the memory data subsequently, it is very likely that the corresponding address conversion data can be found from the translation buffer unit to complete the address conversion without having to search for the address conversion data in the memory. This reduces the delay of address conversion as a whole and improves processing efficiency.

In one implementation, referring to FIG. 3 , the address conversion device may further include, in addition to the translation buffer unit: a translation control unit for querying the address conversion data corresponding to the virtual address from its own storage space when the address conversion data corresponding to the virtual address is not found in the translation buffer unit, or for controlling the query from the memory to obtain the address conversion data corresponding to the virtual address.

In one implementation, at least two control nodes associated with the second-level cache unit are control nodes whose business processing involves the same virtual address; or, at least two control nodes associated with the second-level cache unit are control nodes with mutually exclusive working states, wherein the mutual exclusivity indicates that data access instructions will not be issued at the same time.

Any one of the address conversion devices described in the above embodiments includes a processor and a memory. The translation buffer unit, address conversion unit, first-level buffer unit, multiple second-level buffer units, translation control unit, etc. in the above embodiments are all stored in the memory as program modules, and the processor executes the above program modules stored in the memory to implement corresponding functions.

The processor includes a kernel, which retrieves the corresponding program module from the memory. One or more kernels can be set, and the processing of the access data can be realized by adjusting the kernel parameters.

The memory may include non-permanent memory in a computer-readable medium, random access memory (RAM) and/or non-volatile memory in the form of read-only memory (ROM) or flash RAM, and the memory includes at least one memory chip.

In an exemplary embodiment, a computer-readable storage medium is also provided, which can be directly loaded into the internal memory of a computer and contains software code. After being loaded and executed by a computer, the computer program can implement the steps shown in any embodiment of the above-mentioned data communication method.

In an exemplary embodiment, a computer program product is also provided, which can be directly loaded into the internal memory of a computer and contains software codes. After being loaded and executed by a computer, the computer program can implement the steps shown in any embodiment of the data communication method described above.

Furthermore, an embodiment of the present application provides an electronic device. FIG8 is a schematic diagram of the structure of an electronic device disclosed in an embodiment of the present application. Referring to FIG8 , the electronic device 80 includes at least one processor 801, and at least one memory 802 and a bus 803 connected to the processor; wherein the processor and the memory communicate with each other through the bus; and the processor is used to call the program instructions in the memory to execute the above-mentioned data communication method.

In this specification, each embodiment is described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the embodiments can be referred to each other. For the device disclosed in the embodiment, since it corresponds to the method disclosed in the embodiment, the description is relatively simple, and the relevant parts can be referred to the method part.

It should also be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the presence of other identical elements in the process, method, article or device including the elements.

The steps of the method or algorithm described in conjunction with the embodiments disclosed herein may be implemented directly using hardware, a software module executed by a processor, or a combination of the two. The software module may be placed in a random access memory (RAM), a memory, a read-only memory (ROM), an electrically programmable ROM, an electrically erasable programmable ROM, a register, a hard disk, a removable disk, a CD-ROM, or any other form of storage medium known in the art.

The above description of the disclosed embodiments enables those skilled in the art to implement or use the present application. Various modifications to these embodiments will be apparent to those skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application will not be limited to the embodiments shown herein, but will conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims (8)

1. A data communication method applied to an address conversion apparatus including a translation buffer unit, the method comprising:

Receiving an address conversion request sent by a first node, wherein the address conversion request comprises a virtual address;

Querying address conversion data corresponding to the virtual address from the translation buffer unit, wherein the address conversion data comprises a corresponding relation between the virtual address and a physical address, the translation buffer unit comprises a first-level buffer unit and a second-level buffer unit, the first-level buffer unit is only associated with the first node, the second-level buffer unit is associated with at least two control nodes including the first node, and a buffer space for the address conversion data can be provided for the at least two control nodes;

converting the virtual address into a corresponding target physical address to be accessed based on the searched address conversion data;

wherein the determining of the at least two control nodes associated with the second level cache unit includes:

Matching control nodes with the same virtual address in service processing to the same second-level cache unit;

Or alternatively, the first and second heat exchangers may be,

And matching the control nodes with the mutual exclusivity in the working state to a second-level cache unit which is the same, wherein the mutual exclusivity is characterized in that the data access instructions are not sent out at the same time.

2. The data communication method of claim 1, the method further comprising:

If the address conversion data is not queried from the translation buffer unit, obtaining the address conversion data corresponding to the virtual address based on a translation control unit, wherein the translation control unit is associated with all control nodes;

wherein obtaining address conversion data corresponding to the virtual address based on the translation control unit includes: and obtaining address conversion data corresponding to the virtual address from the translation control unit or obtaining the address conversion data corresponding to the virtual address from the memory based on the translation control unit.

3. The data communication method of claim 1, further comprising:

and dynamically allocating storage resources of the current second-level cache unit in each second-level cache unit, wherein the allocation process represents allocation of the storage resources to at least two control nodes associated with the current second-level cache unit.

4. A data communication method according to claim 3, wherein said dynamically allocating storage resources of a current second level cache unit within each second level cache unit comprises:

determining the priority of at least two control nodes based on the characteristic parameters of the at least two control nodes associated with the current second-level cache unit;

And distributing storage resources of a second-level cache unit for each control node based on the priorities of the at least two control nodes.

5. The data communication method according to claim 2, further comprising, after the translation-based control unit obtains address conversion data corresponding to the virtual address:

caching the address translation data in the second level cache unit, including at least one of:

directly caching the address conversion data in the second-level caching unit;

Under the condition that the first-level caching unit is full of data, caching the address conversion data in the second-level caching unit;

Under the condition that the virtual address is a virtual address which is accessed by processing services of at least two control nodes associated with the second-level caching unit, caching the address conversion data in the second-level caching unit;

And deleting the cache data meeting the first requirement under the condition that the second-level cache unit is full of data, and caching the address conversion data in the second-level cache unit.

6. An address translation apparatus comprising:

a translation buffer unit including a plurality of address conversion units, a plurality of first-stage buffer units, and a plurality of second-stage buffer units;

Each address conversion unit is associated with a control node and is used for receiving an address conversion request sent by the corresponding control node, inquiring corresponding address conversion data based on a virtual address in the address conversion request and converting the virtual address into a physical address based on the obtained address conversion data;

Each first-level buffer unit is connected with one address conversion unit, and is associated with a corresponding control node for buffering the obtained address conversion data;

Each second-level cache unit is connected with a plurality of first-level cache units, and is associated with at least two corresponding control nodes, so that cache space can be provided for the at least two control nodes at the same time, and the cache space is used for caching the obtained address conversion data;

wherein, at least two control nodes associated with the second-level cache unit are control nodes with the same virtual address for business processing;

Or at least two control nodes associated with the second-level cache unit are control nodes with mutual exclusivity in a working state, wherein the mutual exclusivity is characterized in that data access instructions are not sent out at the same time.

7. The address translation device of claim 6, further comprising:

And the translation control unit is used for inquiring the address conversion data corresponding to the virtual address from the storage space of the translation buffer unit or controlling the inquiry of the address conversion data corresponding to the virtual address from the memory when the address conversion data corresponding to the virtual address is not inquired in the translation buffer unit.

8. An electronic device, comprising:

A processor;

A memory for storing executable instructions of the processor;

Wherein the executable instructions comprise: receiving an address conversion request sent by a first node, wherein the address conversion request comprises a virtual address; inquiring address conversion data corresponding to the virtual address from a translation buffer unit, wherein the address conversion data comprises a corresponding relation between the virtual address and a physical address, the translation buffer unit comprises a first-level buffer unit and a second-level buffer unit, the first-level buffer unit is only associated with the first node, the second-level buffer unit is associated with at least two control nodes including the first node, and a buffer space for the address conversion data can be provided for the at least two control nodes; converting the virtual address into a corresponding target physical address to be accessed based on the searched address conversion data;

the determining of the at least two control nodes associated with the second-level cache unit includes: matching control nodes with the same virtual address in service processing to the same second-level cache unit; or matching the control nodes with the mutual exclusivity in the working state to the same second-level cache unit, wherein the mutual exclusivity characterization does not send out data access instructions at the same time.