CN118331905B - Extensible on-chip interconnection bus structure - Google Patents

Abstract

The invention relates to the technical field of on-chip interconnection bus design, and specifically proposes an expandable on-chip interconnection bus structure, which comprises a plurality of host interface circuits and a plurality of slave arbitration selection logic circuits, wherein the plurality of host interface circuits and the plurality of slave arbitration selection logic circuits are connected to form a hardware interconnection matrix structure, wherein the management of the host port is completed by the host interface circuit, and the management of the slave port is completed by the slave arbitration selection logic circuit; the expansion or reduction of the host port and the slave port is completed by adding or removing the host interface circuit and the slave arbitration selection logic circuit; the slave arbitration selection logic circuit supports two arbitration logics, namely a fixed priority comparison algorithm and a cyclic priority algorithm, and satisfies the arbitration requirements when multiple bus hosts access the same slave in different application scenarios by selecting different arbitration modes.

Description

A Scalable On-Chip Interconnect Bus Architecture

Technical Field

The invention belongs to the technical field of on-chip interconnection bus design, and in particular relates to an expandable on-chip interconnection bus structure.

Background technique

As the level of integrated circuit manufacturing continues to improve, the scale of system chip design continues to increase, the types and numbers of functional modules integrated in system chips are increasing, and all functional modules rely on on-chip interconnect buses to achieve on-chip interaction. The design of the on-chip interconnect bus determines the operating performance of the system chip.

In order to ensure operational performance, most current system chips have a high degree of customization in their on-chip interconnect bus design structure and have limited flexible expansion capabilities.

Summary of the invention

In order to solve the technical problems existing in the above-mentioned background technology, the present invention proposes an expandable on-chip interconnect bus structure (hereinafter referred to as: expandable bus), which realizes the flexible expansion of the on-chip interconnect bus master and slaves while ensuring good bus operation performance, and significantly improves the scalability and versatility of the on-chip interconnect bus structure.

Specifically, the present invention provides an expandable on-chip interconnect bus structure, including multiple host interface circuits and multiple slave arbitration selection logic circuits, multiple host interface circuits and multiple slave arbitration selection logic circuits are connected to form a hardware interconnect matrix structure, the hardware interconnect matrix structure supports connecting multiple buses through bus host extension interfaces and extension access interfaces, and the host can access any slave on the multiple buses, together forming an on-chip interconnect bus; wherein the management of the host port is completed by the host interface circuit, and the management of the slave port is completed by the slave arbitration selection logic circuit;

The expansion or reduction of the host port and the slave port is accomplished, on the one hand, by connecting multiple buses through the bus host expansion interface and the expansion access interface to form an on-chip interconnect bus; on the other hand, by adding the same bus or removing the host interface circuit and the slave arbitration selection logic circuit;

The slave arbitration selection logic circuit supports hierarchical arbitration logic. Each slave interface divides the hosts connected to the bus into several groups through the hierarchical arbitration logic circuit. The hosts in the same group adopt one priority mode, and different groups adopt another priority mode. The priority mode supports a fixed priority comparison algorithm or a circular priority algorithm. The hierarchical arbitration logic circuit supports refined control of the host access to the slave, which can better meet the arbitration requirements when multiple bus hosts access the same slave in different application scenarios, and improve access efficiency.

Preferably, the host interface circuit is used to send a host access control signal and write data to the target host, and simultaneously receive a response signal and read data from the slave, and includes a read data selection circuit and a host interface control state machine;

The input signals of the host interface circuit include clock and reset signals, host data signals, host control signals, slave read data signals, and slave response signals, and the output signals include host data signals, host control signals, target slave read data signals, slave response signals, and host status indication signals;

The host interface circuit outputs the target slave read data signal to the host according to the slave selection signal, and outputs the host data signal and the host control signal to the slave arbitration selection logic circuit; the host interface control state machine takes the slave response signal and the host control signal as input, controls the state of the host interface circuit, and outputs the slave response signal, the host state indication signal, and the current slave selection signal.

Preferably, the input signal of the read data selection circuit is the read data signal of all slaves on the bus and the slave selection signal, and the output signal is the read data signal of the target slave;

The read data selection circuit selects a target slave read data signal from all input slave read data signals according to the slave selection signal, and outputs it to the corresponding host; when the current host has no access request, the output of the read data selection circuit remains constant.

Preferably, the input signals of the host interface control state machine are the clock and reset signals of the bus, the slave response signal and the host control signal, and the output signals are the host state indication signal, the slave response signal and the slave selection signal;

The host data signal and host control signal are output from the host, and after passing through the host interface circuit, are output to each slave arbitration selection logic circuit; when the current host has no access request, the host control signal and host data signal output remain in a constant state.

Preferably, the slave arbitration selection logic circuit is used to receive data and control signals from each host on the bus, give access priorities of multiple hosts accessed simultaneously based on the priority mode and configuration, select the currently valid host access control and write data to output to the slave according to the priority of each host accessed simultaneously, and output the response signal and read data of the slave to the corresponding host port, including a host selection circuit, a hierarchical arbitration logic circuit, a slave arbitration selection logic state machine and a slave register;

The input signals of the slave arbitration selection logic circuit include all host data and control signals on the bus, slave configuration signals, slave read data signals and response signals, slave configuration clock and reset signals, slave arbitration selection logic circuit working clock and reset signals, and the output signals include current host data and control signals, slave access status signals, slave read data signals and response signals;

The slave arbitration selection logic circuit selects a valid host port from all host ports on the bus according to the slave state and the host control signal, based on the priority mode and the configuration signal, and outputs the host data and control signal to the slave.

Preferably, the input signal of the host selection circuit includes all host data and control signals on the bus, and the host selection signal, and the output signal is the current host data and control signal;

The host selection signal is generated by the slave arbitration selection logic state machine. The host selection circuit determines the current valid host port and grants it control authority over the current host based on the host selection signal, and outputs the current host data and control signals; when the slave has no host port access, the current host data and control signal outputs remain in a constant state.

Preferably, the input signal of the slave register includes a slave configuration signal, a slave configuration clock and a reset signal; the slave configuration signal includes a slave arbitration mode and an arbitration priority configuration;

The slave register stores the configuration of the slave arbitration mode and arbitration priority, and outputs the priority mode and configuration signals to the hierarchical arbitration logic circuit.

Preferably, the input signal of the slave arbitration selection logic state machine is the slave arbitration selection logic circuit working clock and reset signal, and the arbitration result of the hierarchical arbitration logic circuit, and the output is the slave access state signal;

The slave arbitration selection logic state machine generates the latest host selection signal and slave access status signal according to the arbitration result and the current slave controlled state, and the latest host selection signal is output to the hierarchical arbitration logic circuit and the host selection circuit.

Preferably, the hierarchical arbitration logic circuit is used to implement the hierarchical arbitration logic of the scalable bus, and its input signal is the host selection signal, the priority mode and the configuration signal, and the output signal is the access priority arbitration result of each host;

Each slave interface of the hierarchical arbitration logic circuit can hierarchically configure the priorities of all hosts on the expandable bus through the hierarchical arbitration logic structure. For any slave interface, the hosts at the same level complete arbitration based on a priority arbitration logic. The priority arbitration logics at different levels are different. The priority arbitration logic algorithms include two priority arbitration algorithms: a fixed priority comparison algorithm and a circular priority algorithm. Different levels select different arbitration logic algorithms as the arbitration logic of the level.

The workflow of the hierarchical arbitration logic circuit is that all host selection signals, priority modes and configurations, and priority group configuration signals are used as inputs of the priority group configuration circuit. When the host selection signal is valid, its corresponding host ID is also used as input of the priority allocation circuit; the priority group configuration circuit groups all host selection signals according to the host ID and the priority group configuration signal, and inputs the priority mode and configuration signal within the group and the valid host selection signals of the same group into the hierarchical arbitration logic circuit. Each group includes i hosts, and there are j groups in total. The host selection signals of the same group pass through the hierarchical arbitration logic circuit, and the group priority of each host in the group is output; the priority group configuration circuit inputs all host selection signals in the group into the OR circuit. When any host selection signal in the group is valid, the host selection signal of the group is valid. The group host selection signals of all groups are input into the hierarchical arbitration logic circuit, and the circuit outputs the priorities of all groups; the group priority signal and the group priority results of all hosts in the group are input into the priority combination circuit. The priority combination circuit will perform the multiplication operation of the host group priority and the corresponding group priority, and output the access priority of each host. The access priority of the host is used as the arbitration basis when multiple hosts access the slave at the same time.

Preferably, when the hierarchical arbitration logic circuit adopts a fixed priority comparison algorithm, the hierarchical arbitration logic circuit directly outputs the input priority configuration of each host as the arbitration result of each host priority; if two hosts request to access the slave port, the host with a higher priority will obtain the control authority over the slave port; when the host port sends a request to the slave port, the slave port will check whether the priority of the new requesting host port is higher than the priority of the host port currently controlling the slave port; the slave port performs an arbitration check on each clock edge, and if the priority of the new requesting host is higher than the priority of the host currently controlling the slave port, the new requesting host will obtain the control authority over the slave port at the next clock edge; if the host currently controlling the slave port is performing a fixed-length burst transmission or a locked transmission, then regardless of whether the priority of the new requesting host is higher than that of the host currently performing access, it must wait until the burst transmission or the locked transmission ends before obtaining the control authority over the slave port;

When the hierarchical arbitration logic circuit adopts a round-robin priority algorithm, each host port is assigned a relative priority according to the physical host port number, and the relative priority is compared with the last host port that performs transmission on the bus. The highest priority request host obtains control authority for the next transmission boundary slave; when the host obtains control authority for the target slave, the host can perform data transmission to the port until another host sends a request to the same slave port; the next host is allowed to access the slave port at the next transmission boundary, and if there is no pending access request on the current master line, it is accessed in the next clock cycle.

The beneficial effects of the present invention are:

The scalable on-chip interconnect bus structure proposed in the present invention can flexibly select the number of integrated masters and slaves according to actual needs. The main advantages of the scalable bus are as follows:

(1) The expandable on-chip interconnect bus of the present invention supports connecting multiple buses through a bus host expansion interface and an expansion access interface. The host can access any slave on the multiple buses to form an on-chip interconnect bus, thereby realizing the expansion of the on-chip interconnect bus and improving the flexibility of bus expansion.

(2) The expansion bus in the present invention uses a hardware interconnection matrix to connect all host and slave ports on the bus, supports flexible expansion, supports all bus hosts to access different bus slaves at the same time, and effectively improves the bus access efficiency. At the same time, in order to alleviate the problem of increased power consumption caused by the hardware interconnection matrix structure in the expandable bus, all inactive host ports in the bus maintain a constant output to reduce circuit power consumption;

(3) The scalable bus in the present invention designs a hierarchical arbitration logic circuit for each slave arbitration selection. The slave can classify the hosts connected to the slave according to the host type, classify the hosts of the same type into a group and adopt a priority arbitration mode, and the host group containing different types of hosts adopts a priority arbitration mode. The hierarchical arbitration logic circuit design realizes the refined control of the host access to the slave arbitration, which can better meet the arbitration requirements when multiple bus hosts access the same slave in different application scenarios, and improve the access efficiency. The technical solution of the present invention is further described in detail below through the accompanying drawings and embodiments.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings are used to provide a further understanding of the present invention and constitute a part of the specification. Together with the embodiments of the present invention, they are used to explain the present invention and do not constitute a limitation of the present invention. In the accompanying drawings:

FIG. 1 is a scalable on-chip interconnect bus structure provided by the present invention.

FIG. 2 is an example of an expandable on-chip bus interconnection bus cascade structure provided by the present invention.

FIG. 3 is a circuit structure of a host port provided by the present invention.

FIG. 4 is a slave arbitration selection logic circuit structure provided by the present invention.

FIG. 5 is a hierarchical arbitration logic circuit structure provided by the present invention.

FIG6 is a hierarchical arbitration logic circuit structure for eight hosts provided by the present invention.

Detailed ways

The preferred embodiments of the present invention are described below in conjunction with the accompanying drawings. It should be understood that the preferred embodiments described herein are only used to illustrate and explain the present invention, and are not used to limit the present invention.

In order to ensure the operation efficiency of most system chips at present, the on-chip interconnection bus design structure has a high degree of customization and weak flexible expansion capability. The present invention proposes an expandable on-chip interconnection bus structure. The expandable on-chip interconnection bus uses a hardware interconnection matrix to connect the host and the slave, supports connecting multiple buses through a bus host expansion interface and an expansion access interface, and the host can access any slave on multiple buses, which together constitute an on-chip interconnection bus to achieve the expansion of the on-chip interconnection bus. As shown in Figure 1, the expandable bus structure is shown, and as shown in Figure 2, the expandable bus after cascade expansion, in Figures 1 and 2, M0, M1, and Mn represent n+1 host interfaces, and S0, S1, and Sm represent m+1 slave interfaces. The expandable on-chip interconnection bus uses a hardware interconnection matrix to connect the bus host and the slave, and the management of the host port is completed by the host interface circuit, and the management of the slave port is completed by the slave arbitration selection logic circuit. Multiple host interface circuit units are connected with multiple slave arbitration selection logic circuit units to form a hardware interconnection matrix structure.

The scalable bus has designed a hierarchical arbitration logic circuit for each slave arbitration selection. Each slave interface can hierarchically configure the priority configuration of the host connected to the bus through the hierarchical arbitration logic circuit, that is, the host is divided into several groups, and the hosts in the same group adopt a priority mode, and different groups adopt a priority mode. The priority mode supports a fixed priority comparison algorithm or a circular priority algorithm. For a host accessing a slave, the host's intra-group priority is multiplied by the group priority to which it belongs to obtain the final access priority when the host accesses a slave. For the slave, the hosts connected to the slave can be classified according to the host type, and the hosts of the same type can be divided into a group and adopt a priority arbitration mode. For example, the access characteristics of hosts of the same type are the same, and the circular arbitration priority can be configured, which is conducive to the balanced access rights of each host; different types of host groups adopt a priority arbitration mode. For example, a fixed priority mode is adopted between each host group, and the host characteristics of each host group are different. The fixed priority can better confirm that certain types of hosts are responded to first. The hierarchical arbitration logic circuit supports the refined control of the host accessing the slave, which can better meet the arbitration requirements when multiple bus hosts access the same slave in different application scenarios, and improve the access efficiency.

All accesses on the scalable bus are initiated by the host. When the host accesses the slave, if the target slave to be accessed is available (idle), the host can access the target slave immediately (zero wait state), and access the slave through the scalable bus in a single clock cycle. The scalable bus returns all response information of the slave to the host requesting access; if the target slave port to be accessed is busy, the host access is inserted into the wait state until the target slave port can respond to the host request. The delay of the service request depends on the priority of each host and the access time of the responding slave. After the host completes the access to the target slave, the host still retains the right to control the slave port until an idle cycle or the host initiates access to another slave. When another host port with a higher priority sends a request to the slave port, if the current host is performing a fixed-length burst transmission, the current host continues to retain control of the slave port until the burst transmission is completed; otherwise, the current host port loses control of the slave port.

Specifically, the above-mentioned scalable on-chip interconnect bus structure includes:

1) Host interface circuit, the circuit structure of which is shown in Figure 3;

The host interface circuit is mainly used to send host access control signals and write data to the target host, and receive response signals and read data from the slave. It mainly includes two parts: read data selection circuit and host interface control state machine.

The input signals of the host interface circuit include clock and reset signals, host data signals, host control signals, slave read data signals, and slave response signals. The output signals mainly include host data signals, host control signals, target slave read data signals, slave response signals, and host status indication signals.

The host interface circuit outputs the target slave read data signal to the host according to the slave selection signal, and outputs the host data and control signal to the slave arbitration selection logic circuit of the expandable bus. The host interface control state machine takes the slave response signal and the host control signal as input, controls the state of the host interface circuit, and outputs the slave response signal, the host state indication signal, and the current slave selection signal.

(101) Read data selection circuit

The input signal of the read data selection circuit is the read data signal of all slaves on the bus and the slave selection signal, and the output signal is the read data signal of the target slave; the read data selection circuit selects the read data signal of the target slave from the read data signals of all input slaves according to the slave selection signal, and outputs it to the corresponding host. When the current host has no access request, the output of the read data selection circuit remains constant to reduce the power consumption of the circuit.

(102) Host interface control state machine

The host interface control state machine is a host interface circuit controller. Its input signals are the clock and reset signals of the expandable bus, the slave response signal, and the host control signal. Its output signals are the host status indication, the slave response signal, and the slave selection signal. At the same time, the host data signal and the host control signal are output from the host, and after passing through the host interface circuit, they are output to each slave arbitration selection logic circuit. When the current host has no access request, the host control signal and the host data signal output remain in a constant state to reduce circuit power consumption.

2) Slave arbitration selection logic circuit, whose circuit structure is shown in Figure 4;

The slave arbitration selection logic circuit is mainly used to receive data and control signals from each host on the bus, give access priorities to multiple hosts accessing simultaneously based on the priority mode and configuration, and select the currently valid host access control and write data to output to the slave according to the priority of each host accessing simultaneously. At the same time, the response signal and read data of the slave are output to the corresponding host port, which mainly includes four parts: host selection circuit, hierarchical arbitration logic circuit, slave arbitration selection logic state machine, and slave register.

The input signals of the slave arbitration selection logic circuit mainly include the data and control signals of all host ports on the expandable bus, slave configuration signals, slave read data and response signals, slave configuration clock and reset signals, slave arbitration selection logic circuit working clock and reset signals; the output signals mainly include the current host data and control signals, slave access status signals, slave read data and response signals.

The slave arbitration selection logic circuit selects a valid host port from all host ports on the expandable bus according to the slave state and the host access control signal, based on the priority mode and the configuration signal, and outputs the host data and control signal to the slave.

(201) Host selection circuit

The input signals of the host selection circuit are the host data and control signal and the host selection signal. The host data and control signal include the data and control signals of all host ports on the expandable bus. The host selection signal is generated by the slave arbitration selection logic state machine. The host selection circuit determines the current valid host port based on the host selection signal and gives it control authority over the current host, and outputs the current host data and control signal. When the slave has no host port access, the current host data and control signal output remains constant to reduce circuit power consumption.

(202) Slave register

The input signals of the slave register are the slave configuration signal, the slave configuration clock and the reset signal. The slave configuration signal includes the arbitration mode and arbitration priority configuration. The slave register saves the configuration of the slave arbitration mode and arbitration priority and outputs it to the hierarchical arbitration logic circuit.

(203) Slave arbitration selection logic state machine

The input signals of the slave arbitration selection logic state machine are the slave arbitration selection logic circuit working clock and reset signal, and the arbitration result of the hierarchical arbitration logic circuit, and the output is the slave access status signal. The slave arbitration selection logic state machine will generate the latest host selection signal and slave access status signal according to the arbitration result and the current slave controlled state, and the latest host selection signal will be output to the hierarchical arbitration logic circuit and the host selection circuit.

(204) Hierarchical arbitration logic circuit

The hierarchical arbitration logic circuit can realize the hierarchical arbitration structure of the scalable bus. The hierarchical arbitration logic circuit design is shown in Figure 5, where M0_ID[7:0], M1_ID[7:0], and Mn_ID[7:0] represent the port numbers of host 0, host 1, and host n, respectively, and INT(0) represents the input value of 0. Each slave interface can hierarchically set the priority of all hosts on the scalable bus through the hierarchical arbitration logic structure, and the hierarchical methods of different slave interfaces can be different. For any slave interface, the hosts at the same level complete arbitration based on a priority arbitration logic, and the priority arbitration logics between different levels can be different. The priority arbitration logic algorithm includes two priority arbitration algorithms: a fixed priority comparison algorithm and a circular priority algorithm. Different levels can flexibly select different arbitration logic algorithms as the arbitration logic of the level, thereby improving the arbitration flexibility of different types of hosts accessing slaves.

The working logic of the hierarchical arbitration logic circuit is that all host selection signals, priority modes and configurations, and priority group configuration signals are used as inputs of the priority group configuration circuit. When the host selection signal is valid, its corresponding host ID is also used as input of the priority allocation circuit. The priority group configuration circuit groups all host selection signals according to the host ID and the priority group configuration signal, and inputs the priority mode and configuration signals within the group and the valid host selection signals of the same group into the hierarchical arbitration logic circuit. Each group includes i hosts, and there are j groups in total. The host selection signals of the same group pass through the hierarchical arbitration logic circuit and output the group priority of each host in the group; the priority group configuration circuit inputs all host selection signals in the group into the OR circuit. When any host selection signal in the group is valid, the host selection signal of the group is valid. The group host selection signals of all groups are input into the hierarchical arbitration logic circuit, and the circuit outputs the priority of all groups; the group priority signal and the group priority of all hosts in the group are input into the priority combination circuit. The priority combination circuit will perform the multiplication operation of the host group priority and the corresponding group priority, and output the access priority of each host. The master's access priority serves as the arbitration basis when multiple masters access the slave at the same time.

(205) Hierarchical Arbitration Logic Circuit

The hierarchical arbitration logic circuit implements two arbitration methods for the scalable bus, including a fixed priority comparison algorithm and a round-robin priority algorithm. The input signals of the hierarchical arbitration logic circuit are the host selection signal, the priority mode and the configuration signal. The output signal is the arbitration result of each host access priority. The hierarchical arbitration logic circuit selects to execute the fixed priority comparison algorithm arbitration logic or the round-robin priority algorithm arbitration logic through the priority mode signal.

When the hierarchical arbitration logic circuit adopts a fixed priority comparison algorithm, the hierarchical arbitration logic circuit directly outputs the input priority configuration of each host as the arbitration result of each host priority. When operating in fixed priority mode, each host is assigned a unique fixed priority. If two hosts request access to a slave port, the host with a higher priority will obtain control of the slave port. When a host port sends a request to a slave port, the slave port will check whether the priority of the new requesting host port is higher than the priority of the host port currently controlling the slave port. The slave port performs an arbitration check on each clock edge. If the priority of the new requesting host is higher than the priority of the host currently controlling the slave port, the new requesting host will obtain control of the slave port on the next clock edge. The exception to this arbitration method is that the host currently controlling the slave port is performing a fixed-length burst transfer or a locked transfer. In this case, even if the priority of the new requesting host is higher than that of the host currently performing access, it must wait until the burst transfer or locked transfer ends before obtaining control of the slave port.

When the hierarchical arbitration logic circuit adopts a round-robin priority algorithm, each host port is assigned a relative priority based on the physical host port number. This relative priority is compared with the last host port that performed a transfer on the bus. The highest priority requesting host obtains control authority for the next transfer boundary slave. When the host obtains control authority for the target slave, the host can perform data transfers to that port until another host issues a request to the same slave port. The next host is allowed to access the slave port at the next transfer boundary, and in the next clock cycle if there is no pending access request for the current master line.

FIG6 shows an example of a hierarchical arbitration logic circuit with 8 hosts, where current_m[0:7] represents the selection signals of the 8 hosts, current_m[0] represents the selection signal of host 0, and current_m[7] represents the selection signal of host 7. When the arbitration mode selects the fixed priority comparison algorithm mode, the hierarchical arbitration logic circuit directly outputs the arbitration priority configuration in the fixed priority mode as the unique fixed arbitration priority of each host; when the arbitration mode selects the round-robin priority algorithm mode, the arbitration priority of each host port is a relative priority, and the priority of the host under a certain slave port will change with the change of the host port currently accessing the slave. Assuming that the expandable bus host ports 0, 1, 2, 3, 4, 5, and 7 are used, if the host port controlling a certain slave port is host port 3 at this time, and host ports 0, 2, 4, 5, and 7 send requests at the same time, they will obtain access rights to the target slave in the order of 4, 5, 7, 0, and 2.

Obviously, those skilled in the art can make various changes and modifications to the technical solution without departing from the spirit and scope of the technical solution. Thus, if these modifications and variations of the technical solution fall within the scope of the claims of the technical solution and their equivalents, the technical solution is also intended to include these modifications and variations.

Claims (10)

1. An expandable on-chip interconnect bus structure, characterized in that it comprises a plurality of host interface circuits and a plurality of slave arbitration selection logic circuits, wherein the plurality of host interface circuits and the plurality of slave arbitration selection logic circuits are connected to form a hardware interconnect matrix structure, wherein the hardware interconnect matrix structure supports connecting a plurality of buses through a bus host extension interface and an extension access interface, and the host can access any slave on the plurality of buses, which together form an on-chip interconnect bus; wherein the host port is managed by the host interface circuit, and the slave port is managed by the slave arbitration selection logic circuit; The expansion or reduction of the host port and the slave port is accomplished, on the one hand, by connecting multiple buses through the bus host expansion interface and the expansion access interface to form an on-chip interconnect bus; on the other hand, by adding the same bus or removing the host interface circuit and the slave arbitration selection logic circuit; The slave arbitration selection logic circuit supports hierarchical arbitration logic. Each slave interface divides the hosts connected to the bus into several groups through the hierarchical arbitration logic circuit. The hosts in the same group adopt one priority mode, and different groups adopt another priority mode. The priority mode supports a fixed priority comparison algorithm or a circular priority algorithm. 2. The scalable on-chip interconnect bus structure according to claim 1, wherein the host interface circuit is used to send a host access control signal and write data to a target host, and simultaneously receive a response signal and read data from a slave, and comprises a read data selection circuit and a host interface control state machine; The input signals of the host interface circuit include clock and reset signals, host data signals, host control signals, slave read data signals, and slave response signals, and the output signals include host data signals, host control signals, target slave read data signals, slave response signals, and host status indication signals; The host interface circuit outputs the target slave read data signal to the host according to the slave selection signal, and outputs the host data signal and the host control signal to the slave arbitration selection logic circuit; the host interface control state machine takes the slave response signal and the host control signal as input, controls the state of the host interface circuit, and outputs the slave response signal, the host state indication signal, and the current slave selection signal. 3. The scalable on-chip interconnect bus structure according to claim 2, wherein the input signal of the read data selection circuit is the read data signal of all slaves on the bus and the slave selection signal, and the output signal is the read data signal of the target slave; The read data selection circuit selects a target slave read data signal from all input slave read data signals according to the slave selection signal, and outputs it to the corresponding host; when the current host has no access request, the output of the read data selection circuit remains constant. 4. The expandable on-chip interconnect bus structure according to claim 2, wherein the input signals of the host interface control state machine are the clock and reset signals of the bus, the slave response signal and the host control signal, and the output signals are the host status indication signal, the slave response signal and the slave selection signal; The host data signal and host control signal are output from the host, and after passing through the host interface circuit, are output to each slave arbitration selection logic circuit; when the current host has no access request, the host control signal and host data signal output remain in a constant state. 5. The scalable on-chip interconnect bus structure as claimed in claim 1, characterized in that the slave arbitration selection logic circuit is used to receive data and control signals from each host on the bus, give access priorities of multiple hosts accessed simultaneously based on priority mode and configuration, select the currently valid host access control and write data to output to the slave according to the priority of each host accessed simultaneously, and output the response signal and read data of the slave to the corresponding host port, including a host selection circuit, a hierarchical arbitration logic circuit, a slave arbitration selection logic state machine and a slave register; The input signals of the slave arbitration selection logic circuit include all host data and control signals on the bus, slave configuration signals, slave read data signals and response signals, slave configuration clock and reset signals, slave arbitration selection logic circuit working clock and reset signals, and the output signals include current host data and control signals, slave access status signals, slave read data signals and response signals; The slave arbitration selection logic circuit selects a valid host port from all host ports on the bus according to the slave state and the host control signal, based on the priority mode and the configuration signal, and outputs the host data and control signal to the slave. 6. The expandable on-chip interconnect bus structure as claimed in claim 5, characterized in that the input signal of the host selection circuit includes all host data and control signals on the bus and the host selection signal, and the output signal is the current host data and control signal; The host selection signal is generated by the slave arbitration selection logic state machine. The host selection circuit determines the current valid host port and grants it control authority over the current host based on the host selection signal, and outputs the current host data and control signals; when the slave has no host port access, the current host data and control signal outputs remain in a constant state. 7. The scalable on-chip interconnect bus structure according to claim 5, characterized in that the input signal of the slave register includes a slave configuration signal, a slave configuration clock and a reset signal; the slave configuration signal includes a slave arbitration mode and an arbitration priority configuration; The slave register stores the configuration of the slave arbitration mode and arbitration priority, and outputs the priority mode and configuration signals to the hierarchical arbitration logic circuit. 8. The scalable on-chip interconnect bus structure according to claim 5, characterized in that the input signal of the slave arbitration selection logic state machine is the slave arbitration selection logic circuit working clock and reset signal, and the arbitration result of the hierarchical arbitration logic circuit, and the output is the slave access state signal; The slave arbitration selection logic state machine generates the latest host selection signal and slave access status signal according to the arbitration result and the current slave controlled state, and the latest host selection signal is output to the hierarchical arbitration logic circuit and the host selection circuit. 9. The scalable on-chip interconnect bus structure as claimed in claim 5, characterized in that the hierarchical arbitration logic circuit is used to implement the hierarchical arbitration logic of the scalable bus, and its input signal is the host selection signal, the priority mode and the configuration signal, and the output signal is the arbitration result of each host access priority; Each slave interface of the hierarchical arbitration logic circuit can hierarchically configure the priorities of all hosts on the expandable bus through the hierarchical arbitration logic structure. For any slave interface, the hosts at the same level complete arbitration based on a priority arbitration logic. The priority arbitration logics at different levels are different. The priority arbitration logic algorithms include two priority arbitration algorithms: a fixed priority comparison algorithm and a circular priority algorithm. Different levels select different arbitration logic algorithms as the arbitration logic of the level. The workflow of the hierarchical arbitration logic circuit is that all host selection signals, priority modes and configurations, and priority group configuration signals are used as inputs of the priority group configuration circuit. When the host selection signal is valid, its corresponding host ID is also used as input of the priority allocation circuit; the priority group configuration circuit groups all host selection signals according to the host ID and the priority group configuration signal, and inputs the priority mode and configuration signal within the group and the valid host selection signals of the same group into the hierarchical arbitration logic circuit. Each group includes i hosts, and there are j groups in total. The host selection signals of the same group pass through the hierarchical arbitration logic circuit, and the group priority of each host in the group is output; the priority group configuration circuit inputs all host selection signals in the group into the OR circuit. When any host selection signal in the group is valid, the host selection signal of the group is valid. The group host selection signals of all groups are input into the hierarchical arbitration logic circuit, and the circuit outputs the priorities of all groups; the group priority signal and the group priority results of all hosts in the group are input into the priority combination circuit. The priority combination circuit will perform the multiplication operation of the host group priority and the corresponding group priority, and output the access priority of each host. The access priority of the host is used as the arbitration basis when multiple hosts access the slave at the same time. 10. The scalable on-chip interconnect bus structure as claimed in claim 9, characterized in that when the hierarchical arbitration logic circuit adopts a fixed priority comparison algorithm, the hierarchical arbitration logic circuit directly outputs the input priority configuration of each host as the arbitration result of each host priority; if two hosts request to access the slave port, the host with a higher priority will obtain the control authority over the slave port; when the host port sends a request to the slave port, the slave port will check whether the priority of the new requesting host port is higher than the priority of the host port currently controlling the slave port; the slave port performs arbitration check at each clock edge, and if the priority of the new requesting host is higher than the priority of the host currently controlling the slave port, the new requesting host will obtain the control authority over the slave port at the next clock edge; if the host currently controlling the slave port is performing a fixed-length burst transmission or a locked transmission, then regardless of whether the priority of the new requesting host is higher than that of the host currently performing access, it must wait until the burst transmission or the locked transmission ends before obtaining the control authority over the slave port; When the hierarchical arbitration logic circuit adopts a round-robin priority algorithm, each host port is assigned a relative priority according to the physical host port number, and the relative priority is compared with the last host port that performs transmission on the bus. The highest priority request host obtains control authority for the next transmission boundary slave; when the host obtains control authority for the target slave, the host can perform data transmission to the port until another host sends a request to the same slave port; the next host is allowed to access the slave port at the next transmission boundary, and if there is no pending access request on the current master line, it is accessed in the next clock cycle.