CN118276780A - Traffic shaping data access method, control module, network chip and equipment - Google Patents
Traffic shaping data access method, control module, network chip and equipment Download PDFInfo
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Abstract
The invention discloses a traffic shaping data access method, a control module, a network chip and equipment. The invention is applied to a memory of a multi-port multi-queue flow shaping control module in a network chip, and the flow shaping data access method comprises configuration reading operation, configuration writing operation, barrel-reducing reading operation, barrel-reducing writing operation, barrel-filling reading operation and barrel-filling writing operation. The invention stores the configuration data and the token data in the memory respectively, solves the problem of large storage resources by adopting the register by changing the storage mode and realizing the correct reading of the configuration data and the token data, can provide a plurality of bucket filling formulas, can meet the shaping precision requirements of all ports and queues, can flexibly adjust the jitter problem, and can save resources.
Description
Technical Field
The invention belongs to the technical field of network communication. In particular, it relates to a traffic shaping data access method, a multi-port multi-queue traffic shaping control module, a network chip and a network device.
Background
Traffic shaping is often used for bandwidth rate adjustment of ports and queues to limit traffic and bursts out of a connection of a network so that messages are sent at a relatively uniform rate. Traffic shaping uses a token bucket to periodically fill the token bucket with tokens, and when the tokens consume light but do not reach the filling time, sending of messages is suspended until the next token filling.
In the existing multi-port multi-queue design of the network chip, the flow shaping logic of each port and each queue is independent and is not affected by each other, in order to limit the speed of the multi-port multi-queue at the same time, registers are often used to store configuration data and token calculation data, but when the number of ports or the number of queues is larger, the chip resources used in the mode are also larger.
Disclosure of Invention
In view of this, the present invention aims to solve the problem that the traffic shaping logic in the existing network device chip uses large resources.
To achieve the above object, in a first aspect, the present invention provides a traffic shaping data access method, which is applied to a memory of a multi-port multi-queue traffic shaping control module in a network chip; wherein the port shaping and the queue shaping each use a pair of memories to store configuration data and token data, respectively; the resources in each pair of memories, the first memory stores configuration data and is connected with the first channel and the second channel, and the second memory stores token data and is connected with the third channel; the storage address depth of the configuration data and the token data is the same; the configuration data and the token data of each port and each queue have corresponding storage addresses;
The method comprises configuration read operation, configuration write operation, barrel-reduction read operation, barrel-reduction write operation, barrel-filling read operation and barrel-filling write operation:
the configuration reading operation is to read out the corresponding configuration data in the first memory from the first channel according to the memory address;
the configuration writing operation is to write the configuration data from the first channel into the corresponding storage address in the first memory;
The bucket filling read operation is to read out the corresponding configuration data in the first memory from the second channel according to the storage address, and read out the token data before the bucket filling calculation corresponding to the second memory from the third channel according to the storage address;
the bucket filling write operation is to write the token data after bucket filling calculation into the corresponding storage address in the second memory from the third channel according to the storage address;
The bucket-reducing reading operation is to read out corresponding token data before bucket reduction in the second memory from the third channel according to the memory address;
The bucket reduction write operation is to write the token data after the bucket reduction calculation from the third channel to the corresponding storage address in the second storage.
In some embodiments of the present invention, when the first memory is a single-port memory, the bucket-filling read operation is performed in a time-sharing manner with the configuration read operation and the configuration write operation; the second memory is a single-port memory, and the bucket-reducing read operation, the bucket-reducing write operation, the bucket-filling read operation and the bucket-filling write operation are required to be executed in a time-sharing mode, and when bucket-filling calculation is performed, the bucket-filling read operation is performed first and then the bucket-filling write operation is performed; when the bucket reduction is calculated, the bucket reduction reading operation is performed first, and then the bucket reduction writing operation is performed.
In some embodiments of the invention, the configuration data includes a bucket depth and a bucket fill rate.
In some embodiments of the present invention, the bucket depth is stored by a bucket depth factor cbs_mul and a bucket depth index cbs_exp, which represent the bucket depth CBS, where CBS = cbs_mul x 2 cbs_exp.
In some embodiments of the present invention, the bucket depth factor cbs_mul has a storage space of 4 bits and the bucket depth exponent has a storage space of 4 bits.
In some embodiments of the present invention, the fill rate is stored by storing a fill frequency F, a fill granularity grty _mul, and a fill granularity trim value grty _delt, which represent a fill rate grty, where grty = (F-1) x grty _mul+ grty _delt.
In some embodiments of the present invention, the bucket filling frequency F is stored by storing an index value of the bucket filling frequency F.
In some embodiments of the present invention, the index value storage space of the bucket filling frequency F is 2 bits, the storage space of the bucket filling granularity grty _mul is 14 bits, and the storage space of the bucket filling granularity fine tuning value grty _delt is 8 bits.
In some embodiments of the present invention, at least one bucket filling frequency F is preset, and each port and queue select the bucket filling frequency F according to the traffic shaping requirement.
In some embodiments of the present invention, four fill frequencies F are preset.
In some embodiments of the present invention, the fill frequency F takes values of 250, 50, 25, and 4.
In a second aspect, the present invention provides a multi-port multi-queue control module of a network chip, including a memory and a data access control module; wherein the port shaping and the traffic shaping each use a pair of memories to store configuration data and token data, respectively; the resources in each pair of memories, the first memory stores configuration data and is connected with the first channel and the second channel, and the second memory stores token data and is connected with the third channel; the storage address depth of the configuration data and the token data is the same; the configuration data and the token data of each port and each queue have corresponding storage addresses; the data access control module adopts the flow shaping data access method to read the memory.
In some embodiments of the present invention, the system further includes a token calculating unit, wherein the token calculating unit is used for completing the bucket filling calculation and the bucket subtracting calculation, and the token calculating unit is electrically connected with the first memory through the second channel and electrically connected with the second memory module through the third channel.
In some embodiments of the invention, the first memory and the second memory are single-port memories.
In some embodiments of the present invention, the first channel is a system bus of the network chip, and the second channel and the third channel are hardware logic lines connected to the network chip barrel-reduction and barrel-filling calculation module.
In a third aspect, the present invention provides a network chip, including the multi-port multi-queue control module.
In a fourth aspect, the present invention provides a network device, including the network chip.
In some embodiments of the invention, the network device is an ethernet switch.
The invention has the following beneficial effects:
The invention stores the configuration data and the token data in the memory respectively, solves the problem of large storage resources by adopting the register by changing the storage mode and realizing the correct reading of the configuration data and the token data, can provide a plurality of bucket filling formulas, can meet the shaping precision requirements of all ports and queues, can flexibly adjust the jitter problem, and can save resources.
Drawings
FIG. 1 is a schematic diagram illustrating a memory structure of a multi-port multi-queue traffic shaping control module according to an embodiment of the invention.
Fig. 2 is a timing allocation scheme according to an embodiment of the present invention.
Fig. 3 is a schematic diagram of another timing distribution scheme according to an embodiment of the present invention.
FIG. 4 is a block diagram illustrating a multi-port multi-queue control module of a network chip according to an embodiment of the invention.
Reference numerals
100 (100') First memory
200 (200') Second memory
300. A first channel
400 (400') A second channel
500 (500') Third channel
600. Data access control module
700. Token calculation unit
Detailed Description
Other advantages and effects of the present invention will become apparent to those skilled in the art from the following disclosure, which describes the embodiments of the present invention with reference to specific examples. The invention may be practiced or carried out in other embodiments that depart from the specific details, and the details of the present description may be modified or varied from the spirit and scope of the present invention. It should be noted that the following embodiments and features in the embodiments may be combined with each other without conflict.
It should be noted that the illustrations provided in the following embodiments merely illustrate the basic concept of the present invention by way of illustration, and only the components related to the present invention are shown in the drawings and are not drawn according to the number, shape and size of the components in actual implementation, and the form, number and proportion of the components in actual implementation may be arbitrarily changed, and the layout of the components may be more complicated.
The invention is used for controlling network quality of service (QoS), in particular for bandwidth rate adjustment of ports and queues of network devices using traffic shaping. One of the existing schemes for traffic shaping is to use a token bucket mechanism in the network chip for rate control of ports and queues. However, since the configuration data and the token calculation data are stored by using the register, the more the number of ports or the number of queues, the more the chip resources are used. To solve this problem, a memory is used in the traffic shaping design to complete the traffic shaping token bucket configuration and data storage during computation.
Example 1
The present embodiment is used to describe the traffic shaping data access method of the present invention in detail.
When the bit number of the data exceeds a certain amount, the area occupied by the register with the same bit number using the chip resource is larger than that of the memory, and the more the bit number is, the more the area advantage of the memory is obvious. In addition, when shaping the multi-port multi-queue traffic, only one port is scheduled at any moment after the exit scheduling is performed, and only one queue is output under the port at the moment. Therefore, the invention adopts the memory to complete the configuration of the traffic shaping token bucket and the data storage in the calculation process.
According to the port and the queue, the method firstly separates the resources for shaping the chip, and then the resources of the port or the queue are respectively put in two memories according to the configuration data and the token data, namely, the port shaping and the queue shaping are respectively provided with two memories. The storage method is applied to a memory of a multi-port multi-queue traffic shaping control module in a network chip, as shown in fig. 1. Wherein port shaping and queue shaping each use a pair of memories and store configuration data and token data, respectively; the resources in each pair of memories, the first memory 100 storing configuration data and being connected to the first channel 300 and the second channel 400, the second memory 200 storing token data and being connected to the third channel 500; the storage address depth of the configuration data and the token data is the same; the configuration data and token data for each port and queue have corresponding memory addresses, as shown in fig. 1, address 1 corresponds to port 1 or queue 1, address 2 corresponds to port 2 or queue 2, … …, and address n corresponds to port n or queue n.
In the actual network environment in the embodiment of the invention, such as an ethernet system, the number of queues is often 8 times that of ports, and the memory allocated to the queues is generally much larger than the memory allocated to the ports.
Configuration data is generally accessed and set from outside the chip by a manufacturer or a user according to the needs, and token data only needs to be accessed internally when traffic shaping and bucket filling and bucket reduction calculation are performed. Thus, the read-write of configuration data for configuration uses a different data channel than the token data, and each data operation required for traffic shaping is designed to ensure proper access to the memory for both purposes.
The method includes a configuration read operation, a configuration write operation, a reduced bucket read operation, a reduced bucket write operation, a filled bucket read operation, and a filled bucket write operation. Specifically, as shown in fig. 1, the configuration read operation is to read out corresponding configuration data in the first memory 100 from the first channel 300 according to the memory address; the configuration write operation is to write configuration data from the first channel 300 to a corresponding memory address in the first memory 100; the bucket filling read operation is to read out the corresponding configuration data in the first memory 100 from the second channel 400 according to the memory address, and read out the corresponding token data before bucket filling in the second memory 200 from the third channel 500 according to the memory address; the bucket filling write operation is to write the token data after bucket filling calculation from the third channel 500 to the corresponding memory address in the second memory 200 according to the memory address; the bucket-reducing read operation is to read out the token data before the bucket-reducing calculation corresponding to the second memory 200 from the third channel 500 according to the memory address; the reduced bucket write operation is to write the token data after the reduced bucket calculation from the third channel 500 to the corresponding memory address in the second memory 200 resource.
In some embodiments of the present invention, in order to meet the requirements of access functions and efficiency, and further reduce the occupation of chip resources, the first channel uses a system bus of a chip or a module; the second channel and the third channel adopt hardware logic lines which are directly connected with a bucket filling and subtracting calculation circuit in the network chip. Further, for the first memory storing configuration data, the system bus can access the first memory in a read-write manner, and the hardware logic can only access the first memory in a read manner; for the second memory to hold the calculated token value, the hardware logic has read and write access to it, but the system bus cannot do anything to it.
In some embodiments of the present invention, the single-port memory is more resource-efficient based on the same width and depth of the memory, and the first memory and the second memory are single-port memories, and the memories are typically RAM memories.
The invention stores the configuration data and the token data in the memory respectively, and solves the problem of large storage resources by adopting the register by changing the storage mode and realizing the correct reading of the configuration data and the token data.
Example 2
In this embodiment, the first channel is a system bus, the second channel is a hardware logic line, and the memory is a single-port memory. This embodiment further details how the traffic shaping data access method of the present invention is implemented based on a single port memory.
The single-port memory can only execute read operation or write operation in one clock period, so when the method is implemented by adopting the single-port memory, the time sequence of each read-write operation needs to be distributed, and the requirements of dynamically changing configuration data and correctly executing barrel filling and barrel reducing in an actual flow shaping application scene can be met.
Because the flow shaping of the port or the queue needs to be independently controlled, the method of the invention respectively puts the flow shaping of the port or the queue into the single-port memory adopted in the two memories according to the configuration data and the token data. Therefore, when the first memory is a single-port memory, configuration read operation and configuration write operation need to be executed on the first memory to avoid conflict with bucket filling read operation, and the bucket filling read operation needs to be executed in a time sharing manner with the configuration read operation and the configuration write operation; the second memory is a single-port memory, and the bucket-reducing read operation, the bucket-reducing write operation, the bucket-filling read operation and the bucket-filling write operation are required to be executed in a time-sharing mode, and when bucket-filling calculation is performed, the bucket-filling read operation is performed first and then the bucket-filling write operation is performed; when the bucket reduction is calculated, the bucket reduction reading operation is performed first, and then the bucket reduction writing operation is performed.
Fig. 2 shows a timing allocation scheme in this embodiment. In this scheme, a processing cycle consisting of four processing slots is set. In each processing cycle, three read-write operations of the first memory RAM1 are allocated in three of the processing slots, and four read-write operations of the second memory RAM2 are allocated in four of the processing slots. Because the clock cycles occupied by various read-write operations are different, each processing time slot occupies at least one clock cycle, and the clock cycles occupied by different processing time slots can be the same or different. As shown in fig. 2, in particular, a configuration write operation and a reduced-bucket read operation are allocated for execution in a first processing slot; the configuration read operation and the barrel-reduction write operation are distributed to the second processing time slot for execution; the bucket filling write operation is distributed to the third processing time slot for execution; the bucket filling write operation is allocated for execution in the fourth processing slot. Further, as can be seen from fig. 2, the fourth time slot is followed by the first time slot of the next processing cycle, and the first processing time slot, the second processing time slot, etc. are described for convenience of description, not for limitation. Since the operations of the above-described timing allocation scheme are cyclically performed, a plurality of allocation schemes can be derived. For example, processing cycles starting at the third time slot, configuration write and configuration read exchange time slots, or configuration write or configuration read allocation to the fourth time slot, all of which derived equivalents may be implemented to meet the requirements.
Furthermore, it should be noted that the read/write operations need not be performed in every processing cycle, but may be performed in different processing cycles depending on configuration and computing requirements. For processing periods in which read and write operations exist, to avoid the seven operations conflicting with each other, the allocations are made in different time slots according to the schedule described above.
The present example may also use other timing allocation schemes in implementing the traffic shaping data access method of the present invention based on a single port memory, and is not limited to one timing allocation scheme.
Fig. 3 shows another timing allocation scheme in the present embodiment. In the scheme, the time sequence is distributed according to the clock period occupied by each read-write operation. Wherein,
The configuration read operation includes three steps of the system bus reading the first memory receiving the read instruction (system bus read memory 1 in fig. 3), executing the read instruction (memory 1 read return data in fig. 3), and returning the corresponding data (memory 1 read return data return system bus in fig. 3), with three clock cycles allocated. The configuration write operation includes a step of executing a write instruction (system bus write memory 1 in fig. 3), allocated one clock cycle.
The bucket-reducing calculation and the bucket-filling calculation are sequentially operated by firstly reading and then writing. The bucket-reducing read operation includes two operations of receiving a read instruction (the memory 2 at the time of the bucket-reducing operation in fig. 3), executing the read instruction (the memory 2-degree return data in fig. 3), allocating two clock cycles, and the bucket-reducing write operation includes two operations of waiting for a calculation result (the memory read return data calculation in fig. 3) and a result write (the calculated data write-back memory 2 in fig. 3), allocating two clock cycles. The bucket filling read operation includes two operations of receiving a read instruction (the bucket filling operation room read memory 1 and the read memory 2 in fig. 3), executing the read instruction (the memory 1 and the memory 2 read return data in fig. 3), allocating two clock cycles, and the bucket filling write operation includes two operations of waiting for a calculation result (the memory 1 read return data in fig. 3 participates in calculation and the memory 2 read return data calculation) and a result write (the calculated data write back memory 2 in fig. 3), allocating two clock cycles.
The invention supports the external configuration and the internal token calculation requirement at any moment through time sequence distribution, and avoids the conflict of various operations, so that the invention can be more flexibly suitable for various application scenes.
Example 3
This embodiment is used to further describe the configuration data storage and the token data calculation in the traffic shaping data access method of the present invention in detail.
The reasonable arrangement of configuration data and token data in the flow shaping process can further reduce temporary chip resources, and in the embodiment, the configuration data is at least barrel depth and barrel filling rate.
In some embodiments of the present invention, the bucket depth is stored by storing a bucket depth factor cbs_mul and a bucket depth index cbs_exp, which represent the bucket depth CBS, wherein,
CBS＝cbs_mul×2cbs_exp。
Through the storage mode, the bucket depth can reduce the resources occupied by the storage bucket depth as far as possible, and the resources occupied by a calculation circuit can be reduced by adopting a shift register for calculation.
In some embodiments of the present invention, the fill rate is stored by storing a fill frequency F, a fill granularity grty _mul, and a fill granularity trim value grty _delt, which represent the fill rate grty, wherein,
grty＝(F-1)×grty_mul+grty_delt。
The method for storing three key parameters of the bucket filling rate can reduce the resources occupied by the bucket filling rate as much as possible on one hand, and can correspond to the bucket filling rate, the bucket filling granularity and the fine adjustment value of the bucket filling granularity through the bucket filling frequency on the other hand.
The bucket filling frequency F is at least one, and each port and each queue select the bucket filling frequency F according to the traffic shaping requirement by setting a plurality of bucket filling frequencies.
In this embodiment, four formulas, that is, four bucket filling frequencies are provided, and different formulas are selected according to the flow emergency, so that bucket filling is ensured to be as uniform as possible, and burst is supported.
The fill rate is generally defined as the number of fill buckets per unit time. In this embodiment, the fill rate is determined by the total number of bytes that need to be filled in 1000 microseconds. Typically, the minimum shaping rate is 8kbps (kilobits per second), i.e., 1 byte into the bucket within 1000 microseconds. The step-up is also 8kbps, i.e. the supported shaping rate is a multiple of 8 kbps. Knowing the shaping rate, one can calculate how many bytes into the bucket a total of 1000 microseconds need to be filled from equation 1, equation 1 as follows:
grty＝rate*0.001/8
wherein grty denotes the number of bucket bytes filled in 1000 microseconds and rate denotes the shaping rate.
In this embodiment, dynamic rate change configuration is supported, and in a short time for changing the configuration, the rate fluctuates, but then the rate stabilizes to a limited rate, and for a first memory (RAM 1) storing rate configuration data, the content table below is stored in each address.
| [31:30] | [29:16] | [15:8] | [7:4] | [3:0] |
| sel | grty_mul | grty_delt | cbs_mul | cbs_exp |
Wherein cbs_mul represents a factor value of the barrel depth CBS, cbs_exp represents an index value of the barrel depth CBS, each occupies 8 bits in total, and generates discrete barrel depth CBS values according to a barrel depth calculation formula cbs=cbs_mul× cbs_exp. If the barrel depth CBS bit width is 15 bits and the maximum value is 32767, the barrel depth can be represented by only 8 bits by adopting the scheme, and the calculation is performed by adopting a left shift register during calculation, namely, the barrel depth cbs=cbs_mul < < cbs_exp, < < represents the left shift.
Grty _mul represents the fill granularity, grty _delt represents the fill granularity trim value, sel represents the index value of the fill frequency F, which indicates the selection of the shaping rate shaping corresponding to the fill frequency F. The direct storage of the bucket filling frequency can use more chip resources, and in the practical application scene, the flow shaping generally only needs a limited number of flow shaping rates, so that the requirements can be met. Thus, the index value is set according to the number of traffic shaping rates, with fewer bits representing the traffic shaping rate or its corresponding bucket filling rate.
In this embodiment, 4 formulas are provided for the user to choose to generate a bucket filling configuration. Specific:
(1) If sel is 2' b00, which indicates that the value of F is 250, formula 2 is selected:
249*grty_mul+grty_delt＝grty；
Equation 2 shows that every 1000us is divided into 250 fill buckets, every 4us is filled, and the fill bucket rate grty is calculated according to equation 1, grty _mul is an integer part of grty/249, and grty _delt= grty-249 grty_mul. Assuming shaping to 1000Mbps, grty _mul=500 and grty_delt=500 can be calculated, fixed every 4us padding 500 bytes. The method has high bucket filling frequency and is suitable for queues with smoother flow.
(2) If sel is 2' b01, which indicates that F has a value of 50, equation 3 is selected:
49*grty_mul+grty_delt＝grty；
Equation 3 shows that 1000us is stuffed 50 times, every 20us, and the stuffing rate grty is calculated according to equation 1, grty _mul is an integer part of grty/49, grty _delt= grty-49 grty_mul. This approach is applicable to queues where traffic bursts are large.
(3) If sel is 2' b10, the value of F is 25, and formula 4 is selected;
24*grty_mul+grty_delt＝grty；
equation 4 shows that 1000us is stuffed 25 times, every 50us, and the stuffing rate grty is calculated according to equation 1, grty _mul is an integer part of grty/24, grty _delt= grty-24 grty_mul. This approach applies to queues that are larger than the traffic burst of equation 3.
(4) If sel is 2' b11, which indicates that F has a value of 5, equation 5 is selected:
4*gryt_mul+grty_delt＝grty；
Equation 5 shows that 1000us is stuffed 5 times, once every 200us, and the stuffing rate grty is calculated according to equation 1, grty _mul is an integer fraction of grty/4, grty _delt= grty-4 x grty_mul. This formula is chosen when the shaping rate is low.
(5) The purpose of setting the fill granularity fine tuning value grty _delt is to fine tune the shaping rate according to the actual situation. The grty _delt value is filled only once within 1000us, whichever formula. Therefore, the grty _delt can be increased or decreased in a proper amount on the actual calculated theoretical value so as to achieve the purpose of fine adjustment of the speed. For example, if the clock has frequency offset, the rate can be slightly larger or smaller, and the value grty _mul can be slightly changed to be larger or smaller, so that the speed can be limited to the required rate. An increase or decrease of 1 in the value grty _delt indicates an increase or decrease in the rate of 8kbps every 1 millisecond.
The upper and lower rate limits supported by the four formulas are shown in the following table:
| Sel | grty_mul | grty_delt | Upper rate limit | Lower rate limit |
| 0 | 14‘d16383 | 8’d255 | 32.6Gbps | 8kbps |
| 1 | 14‘d16383 | 8’d255 | 6.4Gbps | 8kbps |
| 2 | 14‘d16383 | 8’d255 | 3.2Gbps | 8kbps |
| 3 | 14‘d16383 | 8’d255 | 526Mbps | 8kbps |
When the shaping rates are different, the values of cbs_mul and cbs_exp need to be determined according to the specific shaping rate to ensure that the bucket depth CBS can accommodate the next bucket fill value without the traffic being cut down because the bucket depth is too small.
Cbs=12288 (12×2 10) if cbs_mul=12 and cbs_exp=10, i.e. up to 12288 bytes in the bucket, are exceeded and remain at that value. If grty _mul is set to 15000, otherwise a fill will occur to top up the bucket and the portion beyond 12288 will be discarded. This means that the flow is cut down and the final shaped flow is less than the theoretical value.
Therefore, the values of cbs_mul and cbs_exp are set such that they calculate a greater barrel depth CBS than both the fill granularity grty _mul and the fill granularity trim value grty _delt.
In this embodiment, the calculated value for each port or queue token is placed in the second memory, 16 bits wide. For a second memory (RAM 2) storing the calculated token data, the memory contents in each address are shown in the following table:
| [15:0] |
| token_count |
token_count represents the number of tokens currently remaining, in bytes. The most significant bit is used as the sign bit. The memory can only be read and write accessed by hardware logic, and the system bus is not accessible. The access to hardware logic is for two reasons, filling and subtracting. Both operations require that both memories be read simultaneously, calculated and then written back to memory 2.
When a bucket is needed, which formula is used is determined by the sel signal in the read RAM1, if not the last bucket filling in 1000us, then token_count=token_count+ grty _mul, otherwise token_count=token_count+ grty _delt, and token_count is the maximum of the bucket depth CBS.
When a bucket reduction is required, token_count=token_count-pkt_ lengt, pkt_ lengt represents the number of bytes (token number) used by the traffic, and token_count is at least 0.
Example 4
The embodiment is used for describing in detail the implementation manner of the present invention applied to a network chip, as shown in fig. 4, a multi-port and multi-queue control module of a network chip, including a memory and a data access control module 600; wherein the port shaping and the traffic shaping each use a pair of memories to store configuration data and token data, respectively; the resources in each pair of memories, the first memory stores configuration data and is connected with the first channel and the second channel, and the second memory stores token data and is connected with the third channel; the storage address depth of the configuration data and the token data is the same; the configuration data and the token data of each port and each queue have corresponding storage addresses; the data access control module adopts the memory flow shaping data access method to control the reading of the memory.
The network chip in this embodiment further includes a token calculation unit 700 for performing a bucket filling calculation and a bucket subtracting calculation. The token calculation unit 700 is electrically connected to the first memory 100 (100 ') through the second channel 400 (400'), and electrically connected to the second memory module 200 (200 ') through the third channel 500 (500').
In this embodiment, the first memory and the second memory are single-port memories.
In this embodiment, the first channel is a system bus of the network chip, and the second channel and the third channel are hardware logic lines connected to the token calculation unit.
Example 5
The embodiment is used for describing in detail an implementation manner of the method of the present invention applied to a network chip product, and the embodiment provides a network chip, which includes the multi-port multi-queue control module described in embodiment 4.
Example 6
The embodiment is used for describing in detail an implementation manner of the method of the present invention on a network device product, and the embodiment provides a network device including the network chip described in embodiment 5. In some embodiments of the invention, the network device is an ethernet switch.
The descriptions of the processes or structures corresponding to the drawings have emphasis, and the descriptions of other processes or structures may be referred to for the parts of a certain process or structure that are not described in detail.
The above embodiments are merely illustrative of the principles of the present application and its effectiveness, and are not intended to limit the application. Modifications and variations may be made to the above-described embodiments by those skilled in the art without departing from the spirit and scope of the application. Accordingly, it is intended that all equivalent modifications and variations of the application be covered by the claims, which are within the ordinary skill of the art, be within the spirit and scope of the present disclosure.
Claims (10)
1. The traffic shaping data access method is characterized in that the method is applied to a memory of a multi-port multi-queue traffic shaping control module in a network chip; wherein the port shaping and the queue shaping each use a pair of memories to store configuration data and token data, respectively; the resources in each pair of memories, the first memory stores configuration data and is connected with the first channel and the second channel, and the second memory stores token data and is connected with the third channel; the storage address depth of the configuration data and the token data is the same; the configuration data and the token data of each port and each queue have corresponding storage addresses;
The method comprises configuration read operation, configuration write operation, barrel-reduction read operation, barrel-reduction write operation, barrel-filling read operation and barrel-filling write operation;
the configuration reading operation is to read out the corresponding configuration data in the first memory from the first channel according to the memory address;
the configuration writing operation is to write the configuration data from the first channel into the corresponding storage address in the first memory;
The bucket filling read operation is to read out the corresponding configuration data in the first memory from the second channel according to the storage address, and read out the corresponding token data before bucket filling in the second memory from the third channel according to the storage address;
the bucket filling write operation is to write the token data after bucket filling calculation into the corresponding storage address in the second memory from the third channel according to the storage address;
the bucket-reducing reading operation is to read out token data before corresponding bucket-reducing calculation in the second memory from the third channel according to the memory address;
The bucket reduction write operation is to write the token data after the bucket reduction calculation from the third channel to the corresponding storage address in the second storage.
2. The traffic shaping data access method as recited in claim 1, wherein,
When the first memory is a single-port memory, the bucket filling read operation needs to be executed in a time-sharing manner with the configuration read operation and the configuration write operation;
the second memory is a single-port memory, and the bucket-reducing read operation, the bucket-reducing write operation, the bucket-filling read operation and the bucket-filling write operation are required to be executed in a time-sharing mode, and when bucket-filling calculation is performed, the bucket-filling read operation is performed first and then the bucket-filling write operation is performed; when the bucket reduction is calculated, the bucket reduction reading operation is performed first, and then the bucket reduction writing operation is performed.
3. The traffic shaping data access method as recited in claim 1, wherein,
Configuration data includes bucket depth and bucket fill rate.
4. The traffic shaping data access method as recited in claim 3, wherein,
The bucket depth is stored by storing a bucket depth factor cbs_mul and a bucket depth exponent cbs_exp, which represent the bucket depth CBS, where cbs=cbs_mul×2 cbs _ exp.
5. The traffic shaping data access method as recited in claim 3, wherein,
The manner in which the fill rate is stored is to store a fill frequency F, a fill granularity grty _mul, and a fill granularity trim value grty _delt, which represent the fill rate grty, where grty = (F-1) x grty _mul+ grty _delt.
6. The traffic shaping data access method as recited in claim 5, wherein,
At least one bucket filling frequency F is preset, and each port and each queue select the bucket filling frequency F according to the traffic shaping requirement.
7. The traffic shaping data access method as claimed in claim 5 or 6, wherein,
The manner in which the fill frequency F is stored is to store an index value of the fill frequency F.
8. The multi-port multi-queue control module of the network chip is characterized by comprising a memory and a data access control module; wherein,
Port shaping and traffic shaping each use a pair of memories to store configuration data and token data, respectively; the resources in each pair of memories, the first memory stores configuration data and is connected with the first channel and the second channel, and the second memory stores token data and is connected with the third channel; the storage address depth of the configuration data and the token data is the same; the configuration data and the token data of each port and each queue have corresponding storage addresses;
the data access control module controls the reading of the memory using the traffic shaping data access method according to any of claims 1-7.
9. A network chip comprising the multi-port multi-queue control module of claim 8.
10. A network device comprising the network chip of claim 9.
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