CN118231406A - Semiconductor device and method for forming the same - Google Patents

Abstract

A semiconductor device includes a back gate etch stop layer (ESL) on the back side of a first gate stack, wherein a plurality of first nanostructures overlap the back gate ESL. The back gate ESL may include a high-k dielectric material. The semiconductor device also includes a plurality of first nanostructures extending between first source/drain regions and a plurality of second nanostructures extending above the plurality of first nanostructures and between second source/drain regions. The first gate stack is disposed around the plurality of first nanostructures, and a second gate stack above the first gate stack is disposed around the plurality of second nanostructures. A back gate contact extends through the back gate ESL to electrically couple to the first gate stack. An embodiment of the present application also discloses a method of forming a semiconductor device.

Description

Semiconductor device and method for forming the same

Technical Field

Embodiments of the present application relate to semiconductor devices and methods of forming the same.

Background technique

Semiconductor devices are used in a variety of electronic applications, such as personal computers, cell phones, digital cameras, and other electronic devices. Semiconductor devices are typically manufactured by sequentially depositing insulating or dielectric layers, conductive layers, and semiconductor layers on a semiconductor substrate and patterning the various material layers using photolithography to form circuit components and elements thereon.

The semiconductor industry continues to increase the integration density of various electronic components (such as transistors, diodes, resistors, capacitors, etc.) by continuously reducing the minimum feature size, so that more components can be integrated into a given area. As the semiconductor industry moves further towards increasing device density, higher performance and lower cost, challenges from manufacturing and design have led to stacked device configurations, such as stacked transistors including complementary field effect transistors (CFETs). However, as the minimum feature size decreases, additional components are introduced.

Summary of the invention

According to one aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a plurality of first nanostructures, the plurality of first nanostructures extending between a first source/drain region; a plurality of second nanostructures, located above the plurality of first nanostructures, the plurality of second nanostructures extending between a second source/drain region; a first gate stack, surrounding the plurality of first nanostructures; a second gate stack, located above the first gate stack and arranged around the plurality of second nanostructures; a back gate etch stop layer, located on the back side of the first gate stack, wherein the plurality of first nanostructures overlap with the back gate etch stop layer; and a back gate contact, electrically coupled to the first gate stack, wherein the back gate contact extends through the back gate etch stop layer to reach the back side of the first gate stack.

According to another aspect of an embodiment of the present application, a semiconductor device is provided, comprising: a device layer, the device layer comprising: a first transistor, comprising a first gate stack, wherein the first gate stack comprises a first gate dielectric and a first gate electrode; and a second transistor, vertically stacked with the first transistor. The semiconductor device also comprises: a first interconnect structure, located on the front side of the device layer; a gate etch stop layer, located on the back side of the device layer, wherein the gate etch stop layer comprises a high-k dielectric material; and a gate contact, located on the back side of the device layer, wherein the gate contact extends through the gate etch stop layer and the first gate dielectric to contact the first gate electrode.

According to another aspect of an embodiment of the present application, a method for forming a semiconductor device is provided, comprising: forming a first transistor and a second transistor above a semiconductor layer, wherein the first transistor and the second transistor are vertically stacked; and wherein a back gate etch stop layer is disposed between a back side of a first gate structure of the first transistor and the semiconductor layer; removing the semiconductor layer to expose the back gate etch stop layer; depositing a back interlayer dielectric above the back gate etch stop layer; patterning an opening through the back interlayer dielectric and the back gate etch stop layer to expose the first gate structure; and forming a back gate contact in the opening, wherein the back gate contact extends through the back gate etch stop layer to be electrically connected to the first gate structure.

BRIEF DESCRIPTION OF THE DRAWINGS

Various aspects of the present disclosure can be best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are only used for illustrative purposes. In fact, for the sake of clarity of discussion, the size of the various components can be arbitrarily increased or reduced.

FIG. 1 illustrates a perspective view of an example stacked transistor in accordance with some embodiments.

2A, 2B, 3, 4, 5, 6, 7, 8A, 8B, 9, 10, 11, 12, 13, 14, 15, 16A, and 16B are views of intermediate stages in the manufacture of stacked transistors according to some embodiments.

17 , 18 , 19 , 20 , 21 , 22 , 23 , 24A , and 24B are views of intermediate stages in fabricating a stacked transistor in accordance with some embodiments.

Detailed ways

The following disclosure provides many different embodiments or examples for realizing different features of the present disclosure. Specific embodiments or examples of components and arrangements are described below to simplify the present disclosure. Of course, these are only examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include an embodiment in which the first component and the second component are directly contacted, and may also include an embodiment in which an additional component may be formed between the first component and the second component so that the first component and the second component may not be in direct contact. In addition, the present disclosure may repeat reference numbers and/or letters in various examples. This repetition is for the purpose of simplicity and clarity, and does not itself indicate the relationship between the various embodiments and/or configurations discussed.

In addition, for ease of description, spacing relation terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or component to another element or component as shown in the figures. The spacing relation terms are intended to encompass different orientations of the device in use or process of operation in addition to the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations) and the spacing relation descriptors used herein should be interpreted accordingly.

A stacked transistor such as a CFET and a method for forming the same are provided. In various embodiments, the stacked transistor includes two vertically stacked transistors, and a gate etch stop layer (ESL) is formed on the back side of a lower gate stack of the stacked transistor. The channel region of the stacked transistor may overlap with the gate ESL. In some embodiments, the gate ESL may be made of a high-k dielectric material having a k value of at least 15, for example.

The gate ESL allows the back gate contact to be formed to the lower gate stack at a position where the back gate contact overlaps the channel region of the stacked transistor during the back gate contact formation process without damaging the channel region. Therefore, when forming the back gate contact, there is no need to avoid the position overlapping the channel region, thereby allowing improved wiring flexibility. In addition, because the channel region can directly overlap the back gate contact, the channel region can be designed and manufactured to have a larger width to improve device speed. For example, by increasing the width of the channel region, device speed improvements of between 14.4% and 19% have been observed in embodiment devices. As a result, various embodiments allow for improved process integration, increased wiring flexibility, and increased device performance.

Fig. 1 shows an example of a stacked transistor 10 (including FETs (transistors) 10U and 10L) according to some embodiments. Fig. 1 is a three-dimensional view, and some components of the stacked transistor are omitted for ease of illustration.

The stacked transistor includes a plurality of vertically stacked FETs. For example, the stacked transistor may include a lower nanostructure FET 10L of a first device type (e.g., n-type/p-type) and an upper nanostructure FET 10U of a second device type (e.g., p-type/n-type). When the stacked transistor is a CFET, the second device type of the upper nanostructure FET 10U is opposite to the first device type of the lower nanostructure FET 10L. The nanostructure FETs 10U and 10L include a semiconductor nanostructure 26 (including a lower semiconductor nanostructure 26L and an upper semiconductor nanostructure 26U), wherein the semiconductor nanostructure 26 is used as a channel region of the nanostructure FET. The lower semiconductor nanostructure 26L is used for the lower nanostructure FET 10L, and the upper semiconductor nanostructure 26U is used for the upper nanostructure FET 10U. In other embodiments, the stacked transistor may also be applied to other types of transistors (e.g., finFET (fin field effect transistor), etc.).

The gate dielectric 78 surrounds the corresponding semiconductor nanostructure 26. The gate electrode 80 (including the lower gate electrode 80L and the upper gate electrode 80U) is above the gate dielectric 78. The source/drain region 62 (including the lower source/source region 62L and the upper source/drain region 62U) is disposed on opposite sides of the gate dielectric 78 and the corresponding gate electrode 80. Depending on the context, each of the source/drain regions 62 may be referred to as a source or a drain individually or collectively. Isolation features (not shown) may be formed to separate the desired source/drain region in the source/drain region 62 and/or the desired gate electrode in the gate electrode 80.

1 further illustrates reference cross sections used in the following figures. Cross section A-A' is a vertical cross section parallel to the longitudinal axis of the semiconductor nanostructure 26 of the stacked transistor 10 and in the direction of current flow, for example, between the source/drain regions 62 of the stacked transistor 10. Cross section B-B' is a vertical cross section perpendicular to cross section A-A' and along the longitudinal axis of the gate electrode 80 of the stacked transistor 10.

Figures 2A to 16B show cross-sectional views of intermediate stages in the formation of a stacked transistor (as shown in Figure 1) according to some embodiments. Figures 2A, 2B, 3, and 4 show general cross-sectional views. Figure 5 shows a perspective view similar to Figure 1. Figures 6, 7, 8A, 9, 10, and 16A show cross-sectional views similar to reference section A-A' in Figure 1. Figures 8B, 11, 12, 13, 14, 15, and 16B show cross-sectional views similar to reference section BB' in Figure 1.

In FIG. 2A and FIG. 2B , two substrates 12L and 12U are provided, respectively. FIG. 2A shows substrate 12L, and FIG. 2B shows substrate 12U. In the subsequent process, substrate 12U can be bonded to substrate 12L (see FIG. 3 ). In this way, substrate 12L can be referred to as lower substrate 12L, and substrate 12U can also be referred to as upper substrate 12U. Each of substrates 12L and 12U can be a semiconductor substrate, such as a bulk semiconductor, a semiconductor on insulator (SOI) substrate, etc., which can be doped (e.g., with p-type or n-type dopants) or undoped. Substrates 12L and 12U can each be a wafer, such as a silicon wafer. Typically, an SOI substrate is a semiconductor material layer formed on an insulator layer. The insulator layer can be, for example, a buried oxide (BOX) layer, a silicon oxide layer, etc. The insulator layer is provided on a substrate, typically a silicon or glass substrate. Other substrates, such as multilayer or gradient substrates, can also be used. In some embodiments, the semiconductor material of substrates 12L and 12U may include: silicon; germanium; compound semiconductors including carbon-doped silicon, gallium arsenide, gallium phosphide, indium phosphide, indium arsenide, and/or indium antimonide; alloy semiconductors including silicon germanium, gallium arsenic phosphide, aluminum indium arsenide, gallium aluminum arsenide, gallium indium arsenide, gallium indium phosphide, and/or gallium indium arsenic phosphide; or combinations thereof. In some embodiments, each of substrates 12L and 12U may include an embedded CMP stop layer (not separately shown), such as a silicon germanium layer embedded (e.g., sandwiched) between silicon material layers.

A multilayer stack 14 is formed over the upper substrate 12U. The multilayer stack 14 includes alternating dummy semiconductor layers 14A, 14C and semiconductor layers 14B. As described in more detail later, the dummy semiconductor layers 14A and 14C will be removed, and the semiconductor layer 14B will be patterned to form a channel region of a stacked transistor. For example, the semiconductor layer 14B disposed above the dummy semiconductor layer 14C may be patterned to form a channel region of a first transistor of the stacked transistor, and the semiconductor layer 14 disposed below the dummy semiconductor layer 14C may be patterned to form a channel region of a second transistor of the stacked transistor.

The dummy semiconductor layers 14A and 14C are formed of a first semiconductor material selected from the candidate semiconductor materials of the substrates 12L and 12U. The semiconductor layer 14B is formed of one or more second semiconductor materials also selected from the candidate semiconductor materials of the substrates 12L and 12U. The semiconductor layer 14B above the dummy semiconductor layer 14C may be formed of a semiconductor material that is the same as or different from the semiconductor layer 14B below the dummy semiconductor layer 14C. In some embodiments, each semiconductor layer 14B is formed of a semiconductor material suitable for a p-type device and an n-type device (such as silicon). In some embodiments, the semiconductor layer 14B above the dummy semiconductor layer 14C is formed of a semiconductor material suitable for a p-type device (such as germanium or silicon germanium), and the semiconductor layer 14B below the dummy semiconductor layer 14C is formed of a semiconductor material suitable for an n-type device (such as silicon or carbon-doped silicon). In some embodiments, the semiconductor layer 14B below the dummy semiconductor layer 14C is formed of a semiconductor material suitable for a p-type device (such as germanium or silicon germanium), and the semiconductor layer 14B above the dummy semiconductor layer 14C is formed of a semiconductor material suitable for an n-type device (such as silicon or carbon-doped silicon).

The semiconductor material of semiconductor layer 14B is different from the semiconductor material of dummy semiconductor layers 14A and 14C, and has a high etching selectivity relative to the semiconductor material of dummy semiconductor layers 14A and 14C. In this way, in subsequent processing, the material of dummy semiconductor layers 14A and 14C can be removed at a faster rate than the material of semiconductor layer 14B. In addition, the semiconductor material of dummy semiconductor layer 14C has a high etching selectivity relative to the semiconductor material of dummy semiconductor layer 14A. In this way, the material of dummy semiconductor layer 14C can be selectively removed in subsequent process steps without completely removing the material of dummy semiconductor layer 14A. In some embodiments, dummy semiconductor layer 14A is formed of silicon germanium, semiconductor layer 14B is formed of silicon, and dummy semiconductor 14C can be formed of germanium, or formed of silicon germanium with a higher atomic percentage of germanium than dummy semiconductor layer 14A.

The multilayer stack 14 is shown as including a specific number of dummy semiconductor layers 14A, 14C and semiconductor layers 14B. It should be understood that the multilayer stack 14 may include any number of dummy semiconductor layers 14A, 14C and/or semiconductor layers 14B. Each layer of the multilayer stack 14 may be grown by a process such as vapor phase epitaxy (VPE) or molecular beam epitaxy (MBE), deposited by a process such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), etc.

Still referring to FIG. 2B , an ESL 16 is deposited over the multilayer stack 14. In subsequent process steps, the ESL 16 may be used to control an etching process to form a backside gate contact in a region overlapping the channel region of the stacked transistor (see FIGS. 10 to 16B ). Therefore, the ESL 16 may also be referred to as a gate ESL or a backside gate ESL. The ESL 16 may be formed of a material that provides etching selectivity relative to the material of the channel region (e.g., the material of the semiconductor layer 14B) and the material of the subsequently formed gate stack. For example, the ESL 16 may be or include a high-k dielectric material such as hafnium oxide. In some embodiments, the k value of the ESL 16 is at least 15, and the ESL 16 has a thickness T ₁ in the range of 3 nm to 6 nm. It has been observed that when the ESL 16 has a k value and a thickness in the above range, it is suitable for forming a backside gate contact. For example, when the thickness of ESL 16 is less than 3 nm, backside contact formation may unacceptably damage other components of the device (e.g., gate stack and/or channel region) and cause leakage issues. When ESL 16 has a thickness greater than 6 nm, etching through may be too difficult and/or lengthy, thereby complicating the manufacturing process. ESL 16 may be deposited by any suitable process (such as CVD, ALD, etc.).

A semiconductor layer 20 is deposited over ESL 16. In some embodiments, semiconductor layer 20 is made of a material that can be subsequently patterned into semiconductor fins, such as amorphous silicon. The thickness _T2 of semiconductor layer 20 can also be selected so that it is thick enough to subsequently form a pattern of semiconductor strips (also referred to as semiconductor fins) in semiconductor layer 20. For example, the thickness _T2 of semiconductor layer 20 can be at least 100 nm. Semiconductor layer 20 can be deposited by any suitable process, such as CVD, ALD, etc.

As shown in Figures 2A and 2B, bonding layers 18L and 18U are deposited on substrates 12L and 12U, respectively. Specifically, bonding layer 18L can be deposited on substrate 12L, and bonding layer 18U can be deposited on semiconductor layer 20. Bonding layers 18L and 18U can be deposited by any suitable process, such as physical vapor deposition (PVD), CVD, ALD, etc. Bonding layers 18L and 18U can help to bond lower substrate 12L to upper substrate 12U (see Figure 3) in subsequent processes. Each of bonding layers 18L and 18U can include an insulating material suitable for subsequent dielectric-to-dielectric bonding processes. Example materials of bonding layers 18L and 18U include silicon oxide (e.g., _SiO2 ), silicon nitride, silicon oxynitride, silicon carbonitride, silicon carbonitride, etc. The material composition of bonding layer 18L can be the same or different from the material composition of bonding layer 18U. In some embodiments, the thickness _T3 of the bonding layer 18L and the thickness _T4 of the bonding layer 18U may each be at least 50 nm to provide a sufficiently thick bonding layer for a subsequent bonding process. The thicknesses _T3 and _T4 may be equal to or different from each other.

In FIG3 , the upper substrate 12U having the multilayer stack 14, the ESL 16, and the semiconductor layer 20 is flipped and bonded to the lower substrate 12L. The bonding structure includes: the lower substrate 12L; the bonding layers 18L and 18U above the lower substrate 12L; the semiconductor layer 20 above the bonding layers 18L and 18U, and the ESL 16 above the semiconductor layer 20; the multilayer stack 14 above the ESL 16 and the upper substrate 12U above the multilayer stack 14. Specifically, the bonding layers 18L and 18U can be bonded together using a suitable technique, such as dielectric-to-dielectric bonding, etc. After bonding, the lower bonding layer 18L and the upper bonding layer 18U can be collectively referred to as a bonding layer 18. The bonding layer 18 may or may not have an interface where the bonding layer 18L and the bonding layer 18U meet.

In some embodiments, the dielectric-to-dielectric bonding process includes applying a surface treatment to one or more of the bonding layers 18L and 18U to form hydroxyl groups (OH) on the exposed surfaces of the bonding layers 18R and 18U. The surface treatment may include a plasma treatment, such as a nitrogen ( _N2 ) plasma treatment. After the plasma treatment, the surface treatment may also include a cleaning process, which may be applied to one or more of the bonding layers 18L and 18U. Then, the bonding layer 18U may be placed above the bonding layer 18L and aligned with the bonding layer 18L. The two bonding layers 18L and 18U are then pressed against each other to initiate pre-bonding of the upper substrate 12U with the lower substrate 12L. The pre-bonding should be performed at room temperature (e.g., in the range of 20°C to 28°C). After the pre-bonding, an annealing process may be applied by, for example, heating the substrates 12L and 12U to a temperature of 300°C to 500°C. The annealing process triggers the formation of a covalent bond between the bonding layers 18L and 18U.

In FIG4 , a thinning process is used to reduce the thickness of the upper substrate 12U to a desired thickness to form a semiconductor layer 14B′. The thinning process may include a grinding process, chemical mechanical polishing (CMP), an etch-back process, a combination thereof, and the like. The thinning process may reduce the thickness of the upper substrate 12U to match the thickness of each semiconductor layer 14B. In subsequent process steps, the semiconductor layer 14B′ formed by the thinned upper substrate 12U may be patterned to provide a nanostructure (e.g., a channel region) of an upper nanostructure FET for a stacked transistor, and the semiconductor layer 14B′ may be referred to as a component of the multilayer stack 14.

In FIG5 , the multilayer stack 14, the ESL 16, and the semiconductor layer 20 are patterned to form semiconductor strips 28 extending upward from the semiconductor layer 20. In FIG5 and subsequent figures, the layers below the semiconductor layer 20 (e.g., the bonding layer 18 and the lower substrate 12L) are omitted for ease of illustration only. It should be understood that these layers remain below the semiconductor layer 20 unless otherwise indicated. Each semiconductor strip 28 includes a semiconductor strip 20′ (a patterned portion of the semiconductor layer 20), a patterned portion of the ESL 16, and a multilayer stack 22. The stacked components of the multilayer stack 22 are hereinafter referred to as nanostructures. Specifically, each multilayer stack 22 includes a pseudo nanostructure 24A patterned by the material of the pseudo semiconductor layer 14A; a pseudo nanostructure 24B patterned by the material of the pseudo semiconductor layer 14C; a lower semiconductor nanostructure 26L patterned by the semiconductor layer 14B below the pseudo semiconductor layer 14C (see FIG. 4 ); and an upper semiconductor nanostructure 26U patterned by the semiconductor layer 14B/14B′ above the pseudo semiconductor layer 14C (see FIG. 4 ). The pseudo nanostructure 24A and the pseudo nanostructure 24B may be further collectively referred to as a pseudo nanostructure 24, and the lower semiconductor nanostructure 26L and the upper semiconductor nanostructure 26U may be further collectively referred to as a semiconductor nanostructure 26.

The lower semiconductor nanostructure 26L will provide a channel region for the lower nanostructure FET of the stacked transistor. The upper semiconductor nanostructure 26U will provide a channel region for the upper nanostructure FET of the stacked transistor. The semiconductor nanostructure 26 directly above/below the pseudo nanostructure 24B (e.g., in contact with the pseudo nanostructure) can be used for isolation and may or may not be used as a channel region for the stacked transistor. The pseudo nanostructure 24B will then be replaced by an isolation structure that can define the boundary of the lower nanostructure FET and the upper nanostructure FET.

The semiconductor fins and nanostructures may be patterned by any suitable method. For example, the patterning process may include one or more photolithography processes, including double patterning or multiple patterning processes. Typically, double patterning or multiple patterning processes combine photolithography and self-alignment processes, thereby allowing the creation of patterns having, for example, a pitch smaller than that obtainable using a single direct photolithography process. For example, in one embodiment, a sacrificial layer is formed on a substrate and patterned using a photolithography process. Spacers are formed next to the patterned sacrificial layer using a self-alignment process. The sacrificial layer is then removed, and the remaining spacers can then be used as an etching mask for the patterning process to etch the first, second, and third semiconductor material layers and the semiconductor layer 20. Etching may be performed by any acceptable etching process, such as reactive ion etching (RIE), neutral beam etching (NBE), etc., or a combination thereof. The etching may be anisotropic.

As shown in FIG. 5 , STI regions 32 are formed above semiconductor layer 20 and between adjacent semiconductor strips 28. STI regions 32 may include a dielectric liner and a dielectric material above the dielectric liner. Each of the dielectric liner and the dielectric material may include an oxide such as silicon oxide, a nitride such as silicon nitride, or the like, or a combination thereof. The formation of STI regions 32 may include depositing a dielectric layer and performing a planarization process such as a chemical mechanical polishing (CMP) process, a mechanical polishing process, or the like to remove excess portions of the dielectric material. The deposition process may include ALD, high density plasma CVD (HDP-CVD), flowable CVD (FCVD), or the like, or a combination thereof. In some embodiments, STI regions 32 include silicon oxide formed by an FCVD process followed by an annealing process. Then, the dielectric layer is recessed to define STI regions 32. The dielectric layer may be recessed so that the upper portion of semiconductor strip 28 (including multilayer stack 22 and ESL 16) protrudes higher than the remaining STI regions 32.

After forming the STI region 32, a dummy gate stack 42 may be formed on and along the sidewalls of the upper portion of the semiconductor strip 28 (the portion protruding higher than the STI region 32). Forming the dummy gate stack 42 may include forming a dummy dielectric layer 36 on the semiconductor strip 28. The dummy dielectric layer 36 may be formed of or include materials such as silicon oxide, silicon nitride, combinations thereof, and the like, and may be deposited or thermally grown according to acceptable techniques. A dummy gate layer 38 is formed over the dummy dielectric layer 36. The dummy gate layer 38 may be deposited, for example, by physical vapor deposition (PVD), CVD, or other techniques, and then planarized, such as by a CMP process. The material of the dummy gate layer 38 is conductive or non-conductive, and may be selected from a group including amorphous silicon, polycrystalline silicon (poly-Si), polycrystalline silicon germanium (poly-SiGe), and the like. A mask layer 40 is formed over the planarized dummy gate layer 38, and may include materials such as silicon nitride, silicon oxynitride, and the like. Next, mask layer 40 may be patterned by photolithography and etching processes to form a mask, which is then used to etch and pattern dummy gate layer 38, and possibly dummy dielectric layer 36. The remaining portions of mask layer 40, dummy gate layer 38, and dummy dielectric layer 36 form dummy gate stack 42.

6, gate spacers 44 are formed along the sidewalls of dummy gate stack 42. Gate spacers 44 may be formed by conformally forming one or more dielectric layers and then anisotropically etching the dielectric layers. Applicable dielectric materials may include silicon oxide, silicon nitride, silicon oxynitride, silicon carbon nitride oxide, etc., which may be formed by deposition processes such as CVD, ALD, etc.

Subsequently, source/drain recesses 46 are formed in semiconductor strip 28. Source/drain recesses 46 are formed by etching and may extend through multilayer stack 22, through ESL 16, and into semiconductor strip 20'. The bottom surface of source/drain recess 46 may be located above, below, or at a level flush with the top surface of isolation region 32. During the etching process, gate spacers 44 and dummy gate stack 42 mask portions of semiconductor strip 28. Etching may include a single etching process or multiple etching processes. A timed etching process may be used to stop etching source/source recess 46 when source/drain recess 46 reaches a desired depth.

In FIG. 7 , an internal spacer 54 and a dielectric isolation layer 56 are formed. The formation of the internal spacer 54 and the dielectric isolation layer 56 may include an etching process that laterally etches the pseudo nanostructure 24A and removes the pseudo nanostructure 24B. The etching process may be isotropic and may be selective to the material of the pseudo nanostructure 24, so that the pseudo nanostructure 24 is etched at a faster rate than the semiconductor nanostructure 26. The etching process may also be selective to the material of the pseudo nanostructure 24B, so that the pseudo nanostructure 24B is etched at a faster rate than the pseudo nanostructure 24A. In this way, the pseudo nanostructure 24B may be completely removed from between the lower semiconductor nanostructure 26L (common) and the upper semiconductor nanostructure 26U (common) without completely removing the pseudo nanostructure 24A. In some embodiments where the pseudo nanostructure 24B is formed of germanium or silicon germanium with a high atomic percentage of germanium, the pseudo nanostructure 24A is formed of silicon germanium with a low atomic percentage of germanium, and the semiconductor nanostructure 26 is formed of silicon without germanium, the etching process may include a dry etching process using chlorine gas (with or without plasma). Since the pseudo gate stack 42 surrounds the sidewalls of the semiconductor nanostructure 26 (see FIG. 5 ), the pseudo gate stack 42 can support the upper semiconductor nanostructure 26U so that the upper semiconductor nanostructure 26U does not collapse when the pseudo nanostructure 24B is removed. In addition, although the sidewalls of the pseudo nanostructure 24A are shown as being straight after etching, the sidewalls may be concave or convex.

The internal spacer 54 is formed on the sidewall of the recessed pseudo nanostructure 24A, and the dielectric isolation layer 56 is formed between the upper semiconductor nanostructure 26U (common) and the lower semiconductor nanostructure 26L (common). As described in more detail later, the source/drain region will be subsequently formed in the source/drain recess 46, and the pseudo nanostructure 24A will be replaced by the corresponding gate structure. The internal spacer 54 acts as an isolation component between the subsequently formed source/drain region and the subsequently formed gate structure. In addition, the internal spacer 54 can be used to prevent damage to the subsequently formed source/drain region by a subsequent etching process (e.g., an etching process for forming a gate structure). On the other hand, the dielectric isolation layer 56 is used to isolate the upper semiconductor nanostructure 26U (common) from the lower semiconductor nanostructure 26L (common). In addition, the intermediate semiconductor nanostructure (the semiconductor nanostructure in the semiconductor nanostructure 26 in contact with the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundary of the lower nanostructure FET and the upper nanostructure FET.

The internal spacer 54 and the dielectric isolation layer 56 can be formed by conformally depositing an insulating material in the source/drain recess 46, on the sidewall of the pseudo nanostructure 24A, and between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L, and then etching the insulating material. The insulating material can be a hard dielectric material, for example, a carbon-containing dielectric material, such as silicon carbonitride, silicon oxycarbide, silicon oxynitride, etc. Other low dielectric constant (low-k) materials with a k value less than about 3.5 can be used. The insulating material can be formed by a deposition process, such as ALD, CVD, etc. The etching of the insulating material can be anisotropic or isotropic. When etching, the insulating material has a portion that remains in the sidewall of the pseudo nanostructure 24A (thereby forming the internal spacer 54), and has a portion that remains between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26L (thereby forming the dielectric isolation layer 56).

As shown in FIG7 , lower and upper epitaxial source/drain regions 62L and 62U are formed. Lower epitaxial source/drain region 62L is formed in the lower portion of source/drain recess 46. Lower epitaxial source/drain region 62L contacts lower semiconductor nanostructure 26L and does not contact upper semiconductor nanostructure 26U. Internal spacers 54 electrically insulate lower epitaxial source/drain region 62L from dummy nanostructure 24A, which will be replaced with a replacement gate in a subsequent process.

The lower epitaxial source/drain region 62L is epitaxially grown and has a conductivity type suitable for the device type (p-type or n-type) of the lower nanostructure FET. When the lower epitaxial source/drain region 62L is an n-type source/drain region, the corresponding material may include silicon or carbon-doped silicon, which is doped with n-type dopants such as phosphorus, arsenic, etc. When the lower epitaxial source/drain region 62L is a p-type source/drain region, the corresponding material may include silicon or silicon germanium, which is doped with p-type dopants such as boron, indium, etc. The lower epitaxial source/drain region 62L may be in-situ doped and may or may not be implanted with the corresponding p-type or n-type dopant. During the epitaxy of the lower epitaxial source/drain region 62L, the upper semiconductor nanostructure 26U may be masked to prevent undesired epitaxial growth on the upper semiconductor nanostructure 26U. After growing the lower epitaxial source/drain regions 62L, the mask on the upper semiconductor nanostructures 26U may be removed.

As a result of the epitaxial process used to form lower epitaxial source/drain regions 62L, the upper surfaces of lower epitaxial source regions 62L have facets that extend laterally outward beyond the sidewalls of multilayer stack 22. In some embodiments, adjacent lower epitaxial source/drain regions 62L remain separated after the epitaxial process is completed. In other embodiments, these facets cause adjacent lower epitaxial source/drain regions 62L of the same FET to merge.

A first contact etch stop layer (CESL) 66 and a first ILD 68 are formed on the lower epitaxial source/drain region 62L. The first CESL 66 may be formed of a dielectric material having a high etch selectivity to the etching of the first ILD 68, such as silicon nitride, silicon oxide, silicon oxynitride, etc., which may be formed by any suitable deposition process, such as CVD, ALD, etc. The first ILD 68 may be formed of a dielectric material, which may be deposited by any suitable method, such as CVD, plasma enhanced CVD (PECVD), or FCVD. Applicable dielectric materials of the first ILD 68 may include phosphosilicate glass (PSG), borosilicate glass (BSG), boron-doped phosphosilicate glass (BPSG), undoped silicate glass (USG), silicon oxide, etc.

The formation process may include depositing a conformal CESL layer, depositing a material for the first ILD 68, followed by a planarization process, and then an etch-back process. In some embodiments, the first ILD 68 is first etched, leaving the unetched first CESL 66. An anisotropic etching process is then performed to remove the portion of the first CESL 66 that is above the recessed first ILD 68. After the recess, the sidewalls of the upper semiconductor nanostructure 26U are exposed.

An upper epitaxial source/drain region 62U is then formed in the upper portion of the source/drain recess 46. The upper epitaxial source/drain region 62U may be epitaxially grown from the exposed surface of the upper semiconductor nanostructure 26U. The material of the upper epitaxial source/drain region 62U may be selected from the same candidate material group used to form the lower source/drain region 62L, depending on the desired conductivity type of the upper epitaxial source region 62U. In an embodiment where the stacked transistor is a CFET, the conductivity type of the upper epitaxial source/drain region 62U may be opposite to the conductivity type of the lower epitaxial source/drain region 62L. For example, the upper epitaxial source/drain region 62U may be doped opposite to the lower epitaxial source/drain region 63L. The upper epitaxial source/drain region 62U may be doped in situ, and/or may be implanted with n-type or p-type dopants. Adjacent upper source/drain regions 62U may remain separate or may merge after the epitaxial process.

After forming the epitaxial source/drain regions 62U, the second CESL 70 and the second ILD 72 are formed. The materials and the formation methods may be similar to those of the first CESL 66 and the first ILD 68, respectively, and are not discussed in detail herein. The formation process may include depositing layers for the CESL 70 and the ILD 72, and performing a planarization process to remove excess portions of the respective layers. After the planarization process, the top surfaces of the second ILD 72, the gate spacers 44, and the dummy gate stack 42 are coplanar (within process variations). The planarization process may remove the mask 40, or may not remove the hard mask 40.

8A and 8B show different cross-sections of a replacement gate process in which the dummy gate stack 42 and the dummy nanostructure 24A are replaced with a gate stack 90. FIG. 8A shows a cross-sectional view taken along reference line A-A' in FIG. 1 ; FIG. 8B shows a cross-sectional view taken along reference line BB' in FIG. 1 . The replacement gate process includes first removing the remaining portions of the dummy gate stack 42 and the dummy nanostructure 24A. The dummy gate stack 42 is removed in one or more etching processes so that a recess is defined between the gate spacers 44 and the upper portion of the semiconductor band 28 is exposed. The remaining portions of the dummy nanostructure 24A are then removed by etching so that the recess extends between the semiconductor nanostructures 26. In the etching process, the dummy nanostructure 24A is etched at a faster rate than the semiconductor nanostructure 26, the dielectric isolation layer 56, the internal spacer 54, and the ESL 16. The etching may be isotropic. For example, when the dummy nanostructure 24A is formed of silicon germanium, and the semiconductor nanostructure 26 is formed of silicon, the etching process may include a wet etching process using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH ₄ OH), or the like.

Then, a gate dielectric 78 is deposited in the recesses between the gate spacers 44 and on the exposed semiconductor nanostructures 26. The gate dielectric 78 is conformally formed on the exposed surface of the recess (removed dummy gate stack 42 and dummy nanostructure 24A) including the semiconductor nanostructures 26 and the gate spacers 44. In some embodiments, the gate dielectric 78 surrounds all (e.g., four) sides of the semiconductor nanostructure 26. Specifically, the gate dielectric 78 can be formed on the top surface of the semiconductor strip 20'; on the top surface, sidewalls, and bottom surface of the semiconductor nanostructure 26; and on the sidewalls of the gate spacers 90. The gate dielectric 78 can include an oxide such as silicon oxide or a metal oxide, a silicate such as a metal silicate, a combination thereof, a multilayer thereof, and the like. The gate dielectric 78 can include a high dielectric constant (high-k) material with a k value greater than about 7.0, such as a metal oxide or silicate of hafnium, aluminum, zirconium, lanthanum, manganese, barium, titanium, lead, and a combination thereof. The gate dielectric 78 may be formed by molecular beam deposition (MBD), ALD, PECVD, etc., followed by a planarization process (e.g., CMP) to remove the portion of the gate dielectric 78 above the second ILD 72. Although a single layer of gate dielectric 78 is shown, the gate dielectric 78 may include multiple layers, such as an interfacial layer and an overlying high-k dielectric layer.

The lower gate electrode 80L is formed on the gate dielectric 78 around the lower semiconductor nanostructure 26L. For example, the lower gate electrode 80L wraps around the lower semiconductor nanostructure 26L. The lower gate electrode 80L can be formed of a material including metals such as tungsten, titanium, titanium nitride, tantalum, tantalum nitride, tantalum carbide, aluminum, ruthenium, cobalt, combinations thereof, multilayers thereof, etc. Although a single-layer gate electrode is shown, the lower gate electrode 80L can include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and filler materials.

The lower gate electrode 80L is formed of a material suitable for the device type of the lower nanostructure FET. For example, the lower gate electrode 80L may include one or more work function tuning layers formed of a material suitable for the device type of the lower nanostructure FET. In some embodiments, the lower gate electrode 80L includes an n-type work function tuning layer, which may be formed of titanium aluminum, titanium aluminum carbide, tantalum aluminum, tantalum carbide, combinations thereof, and the like. In some embodiments, the lower gate electrode 80L includes a p-type work function tuning layer, which may be formed of titanium nitride, tantalum nitride, combinations thereof, and the like. Additionally or alternatively, the lower gate electrode 80L may include a dipole-inducing element suitable for the device type of the lower nanostructure FET. Acceptable dipole-inducing elements include lanthanum, aluminum, scandium, ruthenium, zirconium, erbium, magnesium, strontium, and combinations thereof.

The lower gate electrode 80L may be formed by conformally depositing one or more gate electrode layers and recessing the gate electrode layers. Any acceptable etching process, such as dry etching, wet etching, etc., or a combination thereof, may be performed to recess the gate electrode layer. The etching may be isotropic. Etching the lower gate electrode 80L may expose the upper semiconductor nanostructure 26U.

In some embodiments, an isolation layer (not explicitly shown) may be selectively formed on the lower gate electrode 80L. The isolation layer serves as an isolation member between the lower gate electrode 80L and the subsequently formed upper gate electrode 80U. The isolation layer may be formed by conformally depositing a dielectric material (e.g., silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbonitride, and combinations thereof, etc.) and then recessing the dielectric material to expose the upper semiconductor nanostructure 26U.

Then, an upper gate electrode 80U is formed on the above-mentioned isolation layer (if present) or the lower gate electrode 80L. The upper gate electrode 80U is disposed between the upper semiconductor nanostructures 26U. In some embodiments, the upper gate electrode 80U wraps around the upper semiconductor nanostructure 26U. The upper gate electrode 80U can be formed by the same candidate material and candidate process used to form the lower gate electrode 80L. The upper gate electrode 80U is formed of a material suitable for the device type of the upper nanostructure FET. For example, the upper gate electrode 80U may include one or more work function tuning layers, which are formed of a material suitable for the device type of the upper nanostructure FET. Although a single-layer gate electrode 80U is shown, the upper gate electrode 80U may include any number of work function tuning layers, any number of barrier layers, any number of glue layers, and filling materials.

In addition, a removal process is performed to make the top surfaces of the upper gate electrode 80U and the second ILD 72 flush. The removal process for forming the gate dielectric 78 may be the same removal process as the removal process for forming the upper gate electrode 80U. In some embodiments, a planarization process such as chemical mechanical polishing (CMP), an etch-back process, a combination thereof, etc. may be used. After the planarization process, the top surfaces of the upper gate electrode 80U, the gate dielectric 78, the second ILD 72, and the gate spacer 44 are substantially coplanar (within process variations). Each pair of the gate dielectric 78 and the gate electrode 80 (including the upper gate electrode 80U and/or the lower gate electrode 80L) may be collectively referred to as a "gate structure" 90 (including an upper gate structure 90U and a lower gate structure 90L). Each gate structure 90 extends along three sides (e.g., top surface, sidewall, and bottom surface) of the channel region of the semiconductor nanostructure 26 (see FIGS. 1 and 8B). The lower gate structure 90L may also extend along the sidewalls and/or top surface of the ESL 16 and the sidewalls of the semiconductor strip 20' (see FIG. 8B).

In FIG. 9 , a metal semiconductor alloy region 94 and a source/drain contact 96 are formed through the second ILD 72 to electrically couple to the upper epitaxial source/drain region 62U and/or the lower epitaxial source/drain region 62L. As an example of forming the source/drain contact 96, an opening through the second ILD 72 and the second CESL 70 is formed using acceptable photolithography and etching techniques. A liner (not shown separately) such as a diffusion barrier layer, an adhesive layer, etc. and a conductive material are formed in the opening. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A removal process may be performed to remove excess material from the top surface of the gate spacer 44 and the second ILD 72. The remaining liner and conductive material form a source/drain contact 96 in the opening. In some embodiments, a planarization process such as CMP, an etch-back process, a combination thereof, etc. is used. After the planarization process, top surfaces of the gate spacers 44 , the second ILD 72 , and the source/drain contacts 96 are substantially coplanar (within process variations).

Optionally, a metal semiconductor alloy region 94 is formed at the interface between the source/drain region 62 and the source/drain contact 96. The metal semiconductor alloy region 94 may be a silicide region formed of a metal silicide (e.g., titanium silicide, cobalt silicide, nickel silicide, etc.), a germanide region formed of a metal germanide (e.g., titanium germanide, cobalt germanide, nickel germanide, etc.), a silicon germanide region formed of both a metal silicide and a metal germanide, etc. The metal semiconductor alloy region 94 may be formed before the material of the source/drain contact 96 by depositing a metal in the opening of the source/drain contact 96 and then performing a thermal annealing process. The metal may be any metal that can react with the semiconductor material of the source/drain region 62 (e.g., silicon, silicon germanium, germanium, etc.) to form a low-resistance metal semiconductor alloy, such as nickel, cobalt, titanium, tantalum, platinum, tungsten, other precious metals, other refractory metals, rare earth metals, or alloys thereof. The metal may be deposited by a deposition process such as ALD, CVD, PVD, etc. After the thermal annealing process, a cleaning process, such as a wet clean, may be performed to remove any residual metal from the openings of the source/drain contacts 96, for example, from the surface of the metal semiconductor alloy region 94. The material of the source/drain contacts 96 may then be formed on the metal semiconductor alloy region 94.

Then, the ESL 104 and the third ILD 106 are formed. In some embodiments, the ESL 104 may include a dielectric material having a high etch selectivity to the etching of the third ILD 106, such as aluminum oxide, aluminum nitride, silicon oxycarbide, etc. The third ILD 106 may be formed using flowable CVD, ALD, etc., and the material may include PSG, BSG, BPSG, USG, etc., which may be deposited by any suitable method, such as CVD, PECVD, etc.

Subsequently, a gate contact 108 and a source/drain via 110 are formed to contact the upper gate electrode 80U and the source/drain contact 96, respectively. As an example of forming the gate contact 108 and the source/drain via 110, an opening for the gate contact 108 and the source/drain via 110 is formed through the third ILD 106 and the ESL 104. The opening can be formed using acceptable photolithography and etching techniques. A liner (not shown separately) and a conductive material such as a diffusion barrier layer, an adhesive layer, etc. are formed in the opening. The liner can include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material can be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A planarization process such as CMP can be performed to remove excess material from the top surface of the third ILD 106. The remaining liner and conductive material form a gate contact 108 and a source/drain via 110 in the opening. The gate contact 108 and the source/drain vias 110 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the gate contact 108 and the source/drain vias 110 may be formed in different cross sections, which may avoid shorting of the contacts.

A front side interconnect structure 114 is formed on the device layer 112. The front side interconnect structure 114 includes a dielectric layer 116 and a layer of conductive features 118 in the dielectric layer 116. The dielectric layer 116 may include a low-k dielectric layer formed of a low-k dielectric material. The dielectric layer 116 may also include a passivation layer formed of a non-low-k and dense dielectric material, such as undoped silicate glass (USG), silicon oxide, silicon nitride, etc., or a combination thereof, on top of the low-k dielectric material. The dielectric layer 116 may also include a polymer layer.

Conductive component 118 may include conductive lines and vias, which may be formed using a damascene process. Conductive component 118 may include metal lines and metal vias, which include a diffusion barrier layer and a copper-containing material on the diffusion barrier layer. Aluminum pads may also be present on the metal lines and vias and electrically connected to the metal lines and vias. As will be explained in more detail below, contacts to the lower gate stack 90L and the lower source/drain region 62L may be formed through the back side of device layer 112 (e.g., the side opposite to the front side interconnect structure 114).

10 to 16B show cross-sectional views of intermediate steps of forming backside gate contacts and source/drain contacts according to the lower gate stack 90L and the lower source/drain region 62L according to some embodiments. In FIG. 10 to FIG. 16A, for ease of illustration, the components on the front side of the device layer 112 that exceed the upper gate stack 80U are omitted, but it should be understood that in the cross-sections shown in FIG. 10 to FIG. 16A, the ESL 104, the third ILD 106, and the front side interconnect structure 114 are disposed below the upper gate stack 80U. Referring to FIG. 10, the direction of the device can be flipped. For example, a carrier substrate (not explicitly shown) can be bonded to the front side interconnect structure 114 by dielectric-to-dielectric bonding, and the device can be flipped to expose the back side of the device layer 112 (the side of the device layer 112 opposite to the front side interconnect structure 112). Then, a planarization process can be performed on the back side of the device layer 112. In some embodiments, the planarization process may include, for example, a combination of CMP and/or etch-back processes. The planarization process may remove the lower substrate 12L (see FIG. 4 ), the bonding layer 18 (see FIG. 4 ), and the unpatterned portion of the semiconductor layer 20. The planarization process may further expose the semiconductor strips 20' and the STI regions 32.

In FIG. 11 , one or more etching processes are performed to remove the semiconductor strips 20 ′ and the STI regions 32. Removing the semiconductor layer 20 and the semiconductor strips 20 ′ advantageously improves electrical performance by improving the isolation between the subsequently formed backside gate contacts and/or backside source/drain contacts. For example, by removing the semiconductor layer 20 and the semiconductor strips 20 ′, issues regarding shorting of the backside contacts through the semiconductor layer 20/semiconductor strips 20 ′ can be addressed. In addition, the STI regions 32 can be removed so that an isolation layer can be blanketed on the backside of the device layer 112. Providing a blanket isolation layer can provide improved film quality by removing the topography of the STI regions 32 (and the resulting interfaces). The semiconductor strips 20 ′ and the STI regions 32 can be removed in any order by any suitable etching process. In some embodiments, the semiconductor strips 20 ′ are removed by a wet etching process, while the STI regions 32 are removed by a dry etching process. In some embodiments, removing the semiconductor strips 20 ′ and the STI regions 32 exposes the gate dielectric layer 78 and the ESL 16. Optionally, in some embodiments, removal of the semiconductor strip 20' may cause the lower source/drain region 62L to be partially recessed below the ESL 16 and/or below the back side of the lower gate stack 90L (see FIG. 16A ).

In FIG. 12 , a sacrificial layer 120 is deposited over the back side of the device layer 112. The sacrificial layer 120 may include an insulating material, such as an oxide, deposited by any suitable process, such as PVD, CVD, ALD, etc. The sacrificial layer 120 may be deposited to improve load and uniformity control in a subsequent planarization process (see FIG. 13 ). For example, the sacrificial layer 120 may cover the topography and provide a uniform pattern density, thereby reducing the overall burden of the subsequent planarization process and improving the planarization results. In some embodiments, the sacrificial layer 120 has a thickness T ₅ in the range of 30 nm to 50 nm, which has been observed to substantially improve the subsequent planarization process.

In FIG13 , a planarization process (e.g., a CMP process, etc.) is performed to remove the bulk of the sacrificial layer 120 and planarize the back side of the device layer 112. The planarization process can remove the gate dielectric layer 78 on the back side of the gate stack 90 and expose the ESL 16. After the planarization process, the rear surface (e.g., backside surface) of the ESL 16 and the lower gate electrode 80L can be substantially flush (within process variation). In some embodiments, for example, the remaining portion of the sacrificial layer 120 after the planarization process can be removed by a cleaning process.

14 , a backside ESL 122, a first backside ILD 124, a backside ESL 126, and a second backside ILD 128 are sequentially deposited on the backside of the lower gate electrode 80L and the ESL 16. The backside ESLs 122 and 126 may be formed using materials and processes similar to those of the frontside ESL 104 described above, and the first and second backside ILDs 124 and 128 may be formed using materials or processes similar to those of the third ILD 106 described above. In some embodiments, the backside ESL 122 may further extend along the sidewalls of the ESL 16 to cover the backside of the lower source/drain region 62L (see FIG. 16A ).

In some embodiments, between depositing the first backside ILD 124 and depositing the backside ESL 126, a backside source/drain contact 134 and a metal semiconductor alloy region 136 (also referred to as a silicide region 136) are formed (see FIG. 16A). The backside source/drain contact 134 and the metal semiconductor alloy region 136 can be formed using materials and processes similar to the source/drain contact 96 and the metal semiconductor metal alloy region 94 described above, respectively. The backside source/drain contact 134 can extend through the first backside ILD 124 and the backside ESL 122 to electrically couple to the back side of the bottom source/drain region 62L. The backside ESL 122 can provide endpoint control for the etch opening, which is subsequently filled to form the backside source/drain contact 134.

In FIG15 , a backside gate contact opening 130 is patterned through the second backside ILD 128, the backside ESL 126, the first backside ILD 124, the backside ESL 122, the gate ESL 16, and the gate dielectric 78 to expose the lower gate electrode 80L. The patterning of the backside gate contact opening 130 can be achieved by a combination of photolithography and etching processes. Specifically, etching the gate ESL 16 can use an etchant that selectively etches the gate ESL at a faster rate than the surrounding components of the lower nanostructure FET (e.g., the lower gate electrode 80L and/or the nanostructure 26). For example, a chemical etchant including NF ₃ , BCl ₃ , etc. can be used to etch the gate ESL 16 in a dry etching process.

The backside gate contact opening 130 can overlap and laterally align with the nanostructure 26, which provides the channel region of the upper nanostructure FET and the lower nanostructure FET in the device layer 112. The gate ESL 16 is made of a suitable material and is thick enough to allow the opening 130 to be patterned with precise endpoint control. For example, the gate ESL 16 is made of a high-k material (e.g., hafnium oxide) and is at least 3nm thick in various embodiments. As a result, the backside gate contact opening 130 can overlap directly with the nanostructure 26 without damaging the nanostructure 26 (e.g., by overetching). The backside ESL 122 is also included to further improve the endpoint control of etching the backside gate contact opening 130.

Because the gate ESL 16 allows the backside gate contact opening 130 to overlap directly with the nanostructure 26, it is no longer necessary to avoid a position overlapping with the channel region (nanostructure 26) when forming the backside gate contact, thereby allowing for increased wiring flexibility. In addition, because the nanostructure 26 can be made with a larger width _W1 in order to improve device speed. For example, by increasing the width of the channel region, device speed improvements of between 14.4% and 19% have been observed in embodiment devices. In some embodiments, the width _W1 is greater than 34nm, such as in the range of 16nm to 80nm, thereby achieving improved device performance. Therefore, various embodiments allow for improved process integration, increased wiring flexibility, and increased device performance (e.g., speed).

In FIGS. 16A and 16B , a backside gate contact 132 and a backside source/drain via 138 are formed to contact the lower gate electrode 80L and the source/drain contact 134, respectively. Specifically, the backside gate contact 132 may be formed in the backside gate contact opening 130 and overlap the nanostructure 26. As an example of forming the backside gate contact 132, a liner (not shown separately) such as a diffusion barrier layer, an adhesive layer, etc. and a conductive material are formed in the backside gate contact opening 130. The liner may include titanium, titanium nitride, tantalum, tantalum nitride, etc. The conductive material may be cobalt, tungsten, copper, copper alloy, silver, gold, aluminum, nickel, etc. A planarization process such as CMP may be performed to remove excess material from the top surface of the second backside ILD 128. The remaining liner and conductive material form the backside gate contact 132 in the backside gate contact opening 130. The back side source/drain vias 138 may be formed of similar materials and processes as the source/drain vias 110 described above. The back side gate contact 132 and the back side source/drain vias 138 may be formed in different processes, or may be formed in the same process. Although shown as being formed in the same cross section, it should be understood that each of the back side gate contact 132 and the back side source/drain vias 138 may be formed in different cross sections, which may avoid shorting of the contacts.

17 to 24B show cross-sectional views of intermediate stages in the formation of a stacked transistor (as shown in FIG. 1 ) according to some embodiments. In FIGS. 17 to 24B , the gate ESL 16 (see FIGS. 2A , 2B , and 3 ) may be formed without the above-described bonding process. FIG. 17 shows a perspective view similar to FIG. 1 . FIGS. 18 , 19 , 20 , 21 , 22 , 23 , and 24A show cross-sectional views along a cross section similar to the reference cross section A-A’ in FIG. 1 . FIG. 24B shows a cross-sectional view similar to the reference cross section B-B’ in FIG. 1 . In FIGS. 17 to 24B , unless otherwise noted, the same reference numerals represent the same elements formed by the same process as described in FIGS. 2A to 16B .

17 shows a perspective view of a semiconductor substrate 12, which may be made of the same material as the semiconductor substrates 12L and 12U described above. Semiconductor strips 28 are formed extending upward from the semiconductor substrate 12. Each semiconductor strip 28 includes a semiconductor strip 12' (a patterned portion of the semiconductor substrate 12) and a multilayer stack 22' of nanostructures. Specifically, the multilayer stack 22' includes a pseudo nanostructure 24A, a pseudo nanostructure 24B, a lower semiconductor nanostructure 26L, and an upper semiconductor nanostructure 26U. The semiconductor substrate 12 may also be referred to as a semiconductor layer.

The multilayer stack 22' can be made of the same materials and processes as the multilayer stack 22, including the additional pseudo nanostructure 24B as the bottom layer of the multilayer stack 22. For example, the additional pseudo nanostructure 24B can be the bottom layer of the multilayer stack 22', which is disposed between the upper nanostructure of the multilayer stack 22' and the semiconductor strip 12' below. In a subsequent process step, the bottom nanostructure 24B can be replaced with a high-k material to provide a gate ESL (e.g., gate ESL 16, see FIG. 23). The bottom nanostructure 24B can be formed by forming a pseudo nanostructure layer (having materials/processes similar to the pseudo nanostructure layer 14C described above) on the semiconductor substrate 12, and then patterning the pseudo nanostructure layer as part of forming the multilayer stack 22'. Because the bottom nanostructure 24B will be subsequently replaced by a high-k material to form a backside gate ESL, the thickness _T5 of the bottom nanostructure 24B can be at least 3nm. In this manner, the resulting gate ESL is at least 3 nm thick, which advantageously allows the gate ESL to adequately protect the underlying nanostructures 26 during backside gate contact formation.

As shown in FIG. 17 , STI regions 32 may be formed between semiconductor strips 12 ′, and dummy gate stacks 42 (including dummy dielectric layers 36, dummy gate layers 38, and mask layers 40) may be formed on and along the sidewalls of the multilayer stack 22 ′. STI regions 32 and dummy gate stacks 42 may be formed of similar materials and processes as described above. After dummy gate stacks 42 are patterned, gate spacers 44 (see FIG. 18 ) may be formed on the sidewalls of dummy gate stacks 42 of materials and processes similar to those described above.

In FIG. 18 , a mask layer 140 is deposited and patterned over the dummy gate stack 42 and the multilayer stack 22 ′. The mask layer 140 may be deposited between adjacent dummy gate stacks 42 by, for example, a spin coating process. In some embodiments, the mask layer 140 is a photosensitive layer, such as a bottom anti-reflective coating (BARC) layer. The mask layer 140 may be patterned by a photolithography process to expose the first region 22A of the multilayer stack 22 ′ while masking the second region 22B of the multilayer stack 22 ′. Each of the first region 22A and the second region 22B is disposed between adjacent dummy gate stacks 42 in the dummy gate stack 42, and the first region 22B and the second region 22B may be alternately disposed on the semiconductor substrate 12, wherein each of the second regions 22 is disposed between adjacent first regions 22A in the first region 22A.

Then, a first source/drain recess 46A is formed in the first region 22A of the multilayer stack 22'. The first source/drain recess 46A is formed by etching and can extend through the multilayer stack 22' and into the semiconductor strip 12'. The bottom surface of the first source/drain recess 46A can be located above, below, or at a level flush with the top surface of the isolation region 32. During the etching process, the mask layer 140, the gate spacer 44, and the dummy gate stack 42 mask portions of the semiconductor strip 28. The etching can include a single etching process or multiple etching processes. A timed etching process can be used to stop etching the first source/drain recess 46 when the first source/drain recess 46A reaches a desired depth. After patterning the first source/drain recess 46A, the mask layer 140 can be removed by an acceptable process (e.g., an ashing process).

In FIG. 19 , a lateral etching process is performed to laterally etch the pseudo-nanostructure 24A and the pseudo-nanostructure 24B through the first source/drain recess 46A. The lateral etching process may be isotropic and may be selective to the material of the pseudo-nanostructure 24, so that the pseudo-nanostructure 24 is etched at a faster rate than the semiconductor nanostructure 26. The etching process may also be selective to the material of the pseudo-nanostructure 24B, so that the pseudo-nanostructure 24B is etched at a faster rate than the pseudo-nanostructure 24A. In this way, the pseudo-nanostructure 24B may be laterally etched and recessed by a greater amount than the pseudo-nanostructure 24A. In some embodiments where the pseudo-nanostructure 24B is formed of silicon germanium with germanium or a high atomic percentage of germanium, the pseudo-nanostructure 24A is formed of silicon germanium with a low atomic percentage of germanium, and the semiconductor nanostructure 26 is formed of silicon without germanium, the etching process may include a dry etching process (with or without plasma) using chlorine gas. The lateral etching process recesses the pseudo nanostructure 24A to form a first recess 48A, and the lateral etching process recesses the pseudo nanostructure 24B to form a second recess 48B having a larger lateral width than the first recess 48A. In some embodiments, the lateral etching process removes about 50% of the lateral width of the pseudo nanostructure 24A. Although the sidewalls of the pseudo nanostructure 24A are shown as being straight after etching, the sidewalls may be concave or convex.

In FIG. 20 , the internal spacer 54 is formed in the first recess 48A, and the high-k material 142A and the internal spacer 54 are formed in the second recess 48B. Forming the high-k material 142A includes conformally depositing the high-k material 142A in the first source/drain recess 46A, the first recess 48A, and the second recess 48B on the sidewalls of the pseudo nanostructure 24B, and then etching the high-k material. The high-k material can be any suitable material for protecting the nanostructure 26 during the formation of the backside gate contact and providing sufficient isolation between the upper and lower nanostructures 26U and 26L. For example, the high-k material 142A can be hafnium oxide, etc., and the high-k material 142A can have a k value of at least 15. Therefore, the high-k material 142A can be selectively etched in a subsequent process to form a backside gate contact. The high-k material 142A can be formed by a deposition process, such as ALD, CVD, etc. The etching of the high-k material 142A can be anisotropic or isotropic. When etching, high-k material 142A has a portion remaining in the sidewall of pseudo nanostructure 24B, while other portions of high-k material 142A may be removed. Etching of high-k material 142A may further cause high-k material 142A to be recessed on the sidewall of pseudo nanostructure 24B beyond the sidewall of nanostructure 26, so that nanostructure 26 protrudes beyond the remaining portion of high-k material 142A after etching.

After depositing and etching the high-k material 142A, an internal spacer 54 is formed on the exposed sidewalls of the pseudo-nanostructure 24A and the high-k material 142A. The internal spacer 54 can be formed of similar materials and similar processes as described above. The internal spacer 54 can be used to prevent short circuits between the subsequently formed gate stack and the subsequently formed source/drain regions.

In FIG. 21 , a mask layer 144 is deposited and patterned over the dummy gate stack 42 and the multilayer stack 22′. The mask layer 144 may be deposited between adjacent dummy gate stacks 42 and in the first source/drain region 46A by, for example, a spin coating process. In some embodiments, the mask layer 144 is a photosensitive layer, such as a BARC layer. The mask layer 144 may be patterned by a photolithography process to expose the second region 22B of the multilayer stack 22′ while masking the first region 22A of the multilayer stack 22′.

Then, a second source/drain recess 46B is formed in the second region 22B of the multilayer stack 22'. The second source/drain recess 46B is formed by etching and can extend through the multilayer stack 22' and into the semiconductor strip 12'. The bottom surface of the second source/drain recess 46B can be at the same level as the bottom surface of the first source/drain recess 46A (in process variations), and the mask layer 144, the gate spacer 44, and the dummy gate stack 42 mask some portions of the semiconductor strip 28 during etching. The etching can include a single etching process or multiple etching processes. A timed etching process can be used to stop etching the second source/drain recess 46B when the second source/drain recess 46B reaches a desired depth.

In FIG. 22 , a lateral etching process is performed, which etches the pseudo nanostructure 24A laterally and removes the remaining portion 24B of the pseudo nanostructure through the second source/drain recess 46B. The lateral etching process may be isotropic and may be selective to the material of the pseudo nanostructure 24, so that the pseudo nanostructure 24 is etched at a faster rate than the semiconductor nanostructure 26. The etching process may also be selective to the material of the pseudo nanostructure 24B, so that the pseudo nanostructure 24B is etched at a faster rate than the pseudo nanostructure 24A. In this way, the remaining portion of the pseudo nanostructure 24B may be completely removed without removing the pseudo nanostructure 24A. In some embodiments in which the pseudo nanostructure 24B is formed of germanium or silicon germanium with a high atomic percentage of germanium, the pseudo nanostructure 24A is formed of silicon germanium with a low atomic percentage of germanium, and the semiconductor nanostructure 26 is formed of silicon without germanium, the etching process may include a dry etching process (with or without plasma) using chlorine gas. The lateral etching process recesses the pseudo nanostructure 24A to form a third recess 50A, and the lateral etching process removes the pseudo nanostructure 24B to form a fourth recess 50B. The fourth recess 50B exposes the high-k material 142A and has a greater lateral width than the third recess 50A. Although the sidewalls of the pseudo nanostructure 24A are shown as being straight after etching, the sidewalls may be concave or convex. In addition, during the lateral etching process of FIG. 22, the mask 144 may mask the first source/drain recess 46A.

In FIG. 23 , an additional internal spacer 54 is formed in the third recess 50A, and a high-k material 142B and the internal spacer 54 are formed in the fourth recess 50B. Forming the high-k material 142B includes conformally depositing the high-k material 142B in the second source/drain recess 46B, the third recess 50A, and the fourth recess 50B on the sidewalls of the high-k material 142B, and then etching the high-k material. The high-k material 142B can be any suitable material for protecting the nanostructure 26 during the formation of the backside gate contact and providing isolation between the upper and lower nanostructures 26U and 26L. For example, the high-k material 142B can have the same material composition as the high-k material 142A. In some embodiments, the interface can be set at a location where the high-k materials 142A and 142B contact. The high-k material 142B can be formed by a deposition process, such as ALD, CVD, etc. The etching of the high-k material 142B can be anisotropic or isotropic. When etching, high-k material 142B has portions remaining in the sidewalls of high-k material 142A, while other portions of high-k material 142B may be removed. Etching of high-k material 142B may further cause high-k material 142B to be recessed on the sidewalls of high-k material 142A beyond the sidewalls of nanostructure 26, such that nanostructure 26 protrudes beyond the remaining portions of high-k material 142B after etching.

After depositing and etching high-k material 142B, internal spacers 54 are formed on the exposed sidewalls of pseudo nanostructure 24A and high-k material 142B. Internal spacers 54 can be formed of similar materials and similar processes as described above. Internal spacers 54 can be used to prevent short circuits between subsequently formed gate stacks and subsequently formed source/drain regions. Subsequently, mask 144 can be removed by an acceptable process (e.g., ashing).

In various embodiments, the high-k material 142A/142B provides a backside gate ESL 16' and provides a dielectric isolation layer 56'. Specifically, the bottom material in the high-k material 142A/142B provides a backside gate ESL 16', which allows a backside gate contact (e.g., backside gate contact 132, see Figures 16A, 16B, 24A, and 24B) to be formed at a position overlapping with the semiconductor nanostructure 26. In this way, when forming the backside gate contact, it is no longer necessary to avoid a position overlapping with the channel region (semiconductor nanostructure 26), thereby allowing for improved wiring flexibility. In addition, because the semiconductor nanostructure 26 can be made to have a larger width _W1 in order to improve device speed. Therefore, various embodiments allow for improved process integration, increased wiring flexibility, and increased device performance (e.g., speed). The gate ESL 16' has a thickness of at least 3 nm so as to provide sufficient etching control in the subsequent backside gate contact formation step. Furthermore, ESL 16 ′ may include an internal vertical interface between a first portion of ESL 16 ′ (high-k material 142A) and a second portion of ESL 16 ′ (high-k material 142B).

The top material in the high-k material 142A/142B provides a dielectric isolation layer 56' to isolate the upper semiconductor nanostructure 26U (common) from the lower semiconductor nanostructure 26L (common). In addition, the intermediate semiconductor nanostructure (the semiconductor nanostructure in the semiconductor nanostructure 26 that contacts the dielectric isolation layer 56) and the dielectric isolation layer 56 can define the boundary of the lower nanostructure FET and the upper nanostructure FET. In the embodiments of Figures 17 to 24B, the dielectric isolation layer 56' has the same material composition as the gate ESL 16'. In contrast, the embodiments of Figures 2A to 16B also include a dielectric isolation layer 56 between the upper semiconductor nanostructure 26U and the lower semiconductor nanostructure 26B, but the dielectric isolation layer 56 has a different material composition than the gate ESL 16.

Subsequently, additional processing is performed to form the source/drain regions, gate stacks, source/drain contacts, and gate contacts of the stacked transistor, thereby obtaining the device of Figures 24A and 24B. The additional processing may be similar to those described above in Figures 7 to 16B, where similar reference numbers represent similar elements formed by similar processing, and for the sake of brevity, the detailed description of these processing is not repeated here. As shown in Figures 24A and 24B, a backside gate contact 132 is formed, which is electrically connected to the back side of the lower gate stack 90L. The backside gate contact 132 overlaps the nanostructure 26, and during the formation of the backside gate contact 132, the semiconductor nanostructure 26 is protected by the gate ESL 16'. Specifically, forming the backside contact 132 may include etching an opening through the gate ESL 16 using an etchant that selectively etches the gate ESL at a faster rate than the surrounding components of the lower nanostructure FET (e.g., the lower gate electrode 80L and/or the nanostructure 26) to improve the etching endpoint control.

In various embodiments, the back gate ESL allows a back gate contact to be formed to a lower gate stack of a stacked transistor at a location where the back gate contact overlaps the channel region of the stacked transistor during a back gate contact formation process without damaging the channel region. Thus, when forming the back gate contact, it is no longer necessary to avoid a location that overlaps the channel region, thereby allowing improved routing flexibility. In addition, because the channel region can directly overlap the back gate contact, the channel region can have a larger width to increase device speed. As a result, various embodiments allow for improved process integration, increased routing flexibility, and increased device performance.

According to some embodiments, a semiconductor device includes: a plurality of first nanostructures extending between a first source/drain region; a plurality of second nanostructures located above the plurality of first nanostructures, the plurality of second nanostructures extending between the second source/drain region; a first gate stack surrounding the plurality of first nanostructures; a second gate stack located above the first gate stack and disposed around the plurality of second nanostructures; a back gate etch stop layer (ESL) located on a back side of the first gate stack, wherein the plurality of first nanostructures overlap the back gate ESL; and a back gate contact electrically coupled to the first gate stack, wherein the back gate contact extends through the back gate ESL to the back side of the first gate stack. In some embodiments, the back gate ESL is made of a high-k dielectric material. In some embodiments, the back gate ESL includes hafnium oxide. In some embodiments, the first gate stack includes a gate dielectric and a gate electrode located above the gate dielectric, and wherein the back gate contact extends through the gate dielectric to contact the gate electrode. In some embodiments, a lateral surface of the back gate ESL is flush with a back side surface of the gate electrode. In some embodiments, the semiconductor device further includes a dielectric isolation layer between the plurality of first nanostructures and the plurality of second nanostructures, wherein the dielectric isolation layer has the same material composition as the back gate ESL. In some embodiments, the back gate ESL includes an interface between a first portion of the back gate ESL and a second portion of the back gate ESL. In some embodiments, the semiconductor device further includes an internal spacer between the first gate stack and the first source/drain region, wherein the internal spacer is further disposed on a sidewall of the back gate ESL. In some embodiments, the semiconductor device further includes a dielectric isolation layer between the plurality of first nanostructures and the plurality of second nanostructures, wherein the dielectric isolation layer has a different material composition from the back gate ESL. In some embodiments, the thickness of the back gate ESL is at least 3 nm.

According to some embodiments, a semiconductor device includes: a device layer, the device layer includes: a first transistor, including a first gate stack, wherein the first gate stack includes a first gate dielectric and a first gate electrode; and a second transistor, vertically stacked with the first transistor. The semiconductor device also includes: a first interconnect structure, located on the front side of the device layer; a gate etch stop layer (ESL), located on the back side of the device layer, wherein the gate ESL includes a high-k dielectric material; and a gate contact, located on the back side of the device layer, wherein the gate contact extends through the gate ESL and the first gate dielectric to contact the first gate electrode. In some embodiments, the semiconductor device also includes an additional etch stop layer located on the back side of the device layer, wherein the gate contact extends through the additional etch stop layer, and wherein the additional etch stop layer has a different material composition than the gate ESL. In some embodiments, the gate contact overlaps with a channel region of the first transistor. In some embodiments, the first gate dielectric extends along the sidewalls of the gate ESL.

According to some embodiments, a method includes: forming a first transistor and a second transistor above a semiconductor layer, wherein the first transistor and the second transistor are vertically stacked; and wherein a back gate etch stop layer (ESL) is disposed between a back side of a first gate structure of the first transistor and the semiconductor layer; removing the semiconductor layer to expose the back gate etch stop layer; depositing a back interlayer dielectric (ILD) above the back gate ESL; patterning an opening through the back ILD and the back gate ESL to expose the first gate structure; and forming a back gate contact in the opening, wherein the back gate contact extends through the back gate ESL to be electrically connected to the first gate structure. In some embodiments, the method further comprises: forming a multilayer stack over the first semiconductor substrate, the multilayer stack comprising a first semiconductor material arranged alternately with a second semiconductor material; depositing a high-k dielectric layer over the multilayer stack; bonding the second semiconductor substrate over the multilayer stack; thinning the first semiconductor substrate; patterning the multilayer stack, wherein patterning the multilayer stack comprises forming a semiconductor nanostructure from the first semiconductor material and forming a pseudo-nanostructure from the second semiconductor material, and wherein forming the first transistor comprises replacing the pseudo-nanostructure with the first gate structure; and patterning the high-k dielectric layer to form a backside gate ESL. In some embodiments, the method further comprises: forming a semiconductor layer over the high-k dielectric layer, wherein the second semiconductor substrate is directly bonded to the semiconductor layer by dielectric-to-dielectric bonding. In some embodiments, the method further comprises: forming a pseudo-semiconductor material over the semiconductor layer; forming a multilayer stack over the pseudo-semiconductor material, the multilayer stack comprising a first semiconductor material arranged alternately with a second semiconductor material; patterning the multilayer stack and the pseudo-semiconductor material, wherein the patterning of the multilayer stack and the pseudo-semiconductor material comprises forming a first pseudo-nanostructure from the pseudo-semiconductor material, forming a semiconductor nanostructure from the first semiconductor material, and forming a second pseudo-nanostructure from the second semiconductor material, and wherein forming the first transistor comprises replacing the second pseudo-nanostructure with the first gate structure; and replacing the first pseudo-nanostructure with a high-k material to form a back gate ESL. In some embodiments, the method further comprises: depositing an additional backside ESL over the backside gate ESL after removing the semiconductor layer, wherein the backside ILD is deposited over the additional backside ESL, and wherein patterning the opening further comprises patterning the opening through the additional backside ESL. In some embodiments, the backside gate contact overlaps the first nanostructure of the first transistor and the second nanostructure of the second transistor.

The features of several embodiments are summarized above so that those skilled in the art can better understand the various aspects of the present disclosure. Those skilled in the art will appreciate that they can easily use the present disclosure as a basis for designing or modifying other processes and structures for achieving the same purpose and/or achieving the same advantages of the embodiments introduced herein. Those skilled in the art will also appreciate that such equivalent structures do not deviate from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and changes in the present disclosure without departing from the spirit and scope of the present disclosure.

Claims (10)

1. A semiconductor device comprising: a plurality of first nanostructures extending between the first source/drain regions; A plurality of second nanostructures, located above the plurality of first nanostructures, the plurality of second nanostructures extending between the second source/drain regions; a first gate stack surrounding the plurality of first nanostructures; a second gate stack located above the first gate stack and disposed around the plurality of second nanostructures; a backside gate etch stop layer on a backside of the first gate stack, wherein the plurality of first nanostructures overlap the backside gate etch stop layer; and A backside gate contact is electrically coupled to the first gate stack, wherein the backside gate contact extends through the backside gate etch stop layer to the back side of the first gate stack. 2 . The semiconductor device of claim 1 , wherein the first gate stack comprises a gate dielectric and a gate electrode over the gate dielectric, and wherein the backside gate contact extends through the gate dielectric to contact the gate electrode. 3 . The semiconductor device according to claim 1 , further comprising a dielectric isolation layer between the plurality of first nanostructures and the plurality of second nanostructures, wherein the dielectric isolation layer has a same material composition as the backside gate etch stop layer. 4 . The semiconductor device of claim 3 , wherein the backside gate etch stop layer comprises an interface between a first portion of the backside gate etch stop layer and a second portion of the backside gate etch stop layer. 5 . The semiconductor device according to claim 3 , further comprising an inner spacer between the first gate stack and the first source/drain region, wherein the inner spacer is further disposed on a sidewall of the backside gate etch stop layer. 6 . The semiconductor device according to claim 1 , further comprising a dielectric isolation layer between the plurality of first nanostructures and the plurality of second nanostructures, wherein the dielectric isolation layer has a different material composition from the backside gate etch stop layer. 7. A semiconductor device comprising: A device layer, the device layer comprising: a first transistor comprising a first gate stack, wherein the first gate stack comprises a first gate dielectric and a first gate electrode; and a second transistor, stacked vertically with the first transistor; a first interconnect structure located on the front side of the device layer; a gate etch stop layer on a back side of the device layer, wherein the gate etch stop layer comprises a high-k dielectric material; and A gate contact is located on the back side of the device layer, wherein the gate contact extends through the gate etch stop layer and the first gate dielectric to contact the first gate electrode. 8. The semiconductor device of claim 7, further comprising an additional etch stop layer on the back side of the device layer, wherein the gate contact extends through the additional etch stop layer, and wherein the additional etch stop layer has a different material composition than the gate etch stop layer. 9. A method of forming a semiconductor device, comprising: forming a first transistor and a second transistor over the semiconductor layer, wherein the first transistor and the second transistor are vertically stacked; and wherein a backside gate etch stop layer is disposed between a backside of a first gate structure of the first transistor and the semiconductor layer; removing the semiconductor layer to expose the backside gate etch stop layer; depositing a backside interlayer dielectric over the backside gate etch stop layer; patterning an opening through the backside interlayer dielectric and the backside gate etch stop layer to expose the first gate structure; and A backside gate contact is formed in the opening, wherein the backside gate contact extends through the backside gate etch stop layer to be electrically connected to the first gate structure. 10. The method according to claim 9, further comprising: forming a multilayer stack over a first semiconductor substrate, the multilayer stack comprising a first semiconductor material arranged alternately with a second semiconductor material; depositing a high-k dielectric layer over the multilayer stack; bonding a second semiconductor substrate over the multilayer stack; thinning the first semiconductor substrate; patterning the multilayer stack, wherein patterning the multilayer stack comprises forming a semiconductor nanostructure from the first semiconductor material and forming a dummy nanostructure from the second semiconductor material, and wherein forming the first transistor comprises replacing the dummy nanostructure with the first gate structure; and The high-k dielectric layer is patterned to form the backside gate etch stop layer.