CN118210622B

CN118210622B - A memory allocation method and computing device

Info

Publication number: CN118210622B
Application number: CN202410232194.1A
Authority: CN
Inventors: 姚广忠; 徐磊; 刘晓建
Original assignee: XFusion Digital Technologies Co Ltd
Current assignee: XFusion Digital Technologies Co Ltd
Priority date: 2024-02-29
Filing date: 2024-02-29
Publication date: 2025-04-11
Anticipated expiration: 2044-02-29
Also published as: CN118210622A; WO2025179931A1

Abstract

The embodiment of the present application discloses a memory allocation method and a computing device, which is applied to a computing device of an ARM architecture; the method includes: configuring the page size of a first virtual page of a first virtual address space, and the page size of a second virtual page of a second virtual address space, wherein the page size of the first virtual page is larger than the page size of the second virtual page; determining whether the task to be allocated memory belongs to a preset control group; if the task belongs to the preset control group, allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs. By configuring the first virtual address space and the second virtual address space with different page size granularities, and allocating the first virtual page or the second virtual page to different tasks based on the preset control group, memory allocation with different page size granularities can be implemented under an ARM architecture server, meeting the more diverse and flexible memory allocation requirements of an ARM architecture server.

Description

Memory allocation method and computing device

Technical Field

The present application relates to the field of memory management technologies, and in particular, to a memory allocation method and a computing device.

Background

In an advanced reduced instruction set machine (ADVANCED RISC MACHINE, ARM) architecture, memory in a computing device is managed on a physical page basis. When a central processing unit (central processing unit, CPU) of a computing device performs a task, the CPU can read and write corresponding physical pages in memory by accessing virtual pages in the virtual address space of the task.

Page Table Entries (PTEs) are data structures used to organize and manage the mapping between virtual and physical addresses, each page table entry being used to associate a virtual page with a physical page. Thus, when a task needs to access a physical page, the CPU can query the corresponding page table entry based on the virtual page, and then access the corresponding physical page.

Currently, the ARM architecture supports mapping between physical pages and virtual pages at one page size granularity of 4KB, 16KB, or 64 KB. It can be appreciated that the hit rate of the page table cache (translation lookaside buffer, TLB) can be improved by using a large page for memory allocation, and the memory allocation is more flexible by using a small page, so that it is difficult to consider different memory allocation requirements by using a scheme for memory allocation with a page size granularity.

Disclosure of Invention

The embodiment of the application provides a memory allocation method and computing equipment, which can realize memory allocation with different page sizes and granularity under an ARM architecture and meet more diversified and flexible memory allocation requirements.

An embodiment of the present application provides a memory allocation method, where the memory allocation method is applied to an ARM architecture computing device, and the method includes:

The method comprises the steps of configuring the page size of a first virtual page of a first virtual address space and the page size of a second virtual page of a second virtual address space, determining whether a task of a memory to be allocated belongs to a preset control group, and allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs under the condition that the task belongs to the preset control group.

Wherein the page size of the first virtual page is larger than the page size of the second virtual page.

The preset control group comprises a first control group and a second control group, wherein the first control group is used for controlling the allocation of the first virtual page for the preset kernel mode task, and the second control group is used for controlling the allocation of the first virtual page or the second virtual page for the preset user mode task.

In the embodiment of the application, the two intervals with different page sizes are configured in the virtual address space, and the first virtual page or the second virtual page is allocated for different tasks based on the preset control group, so that the memory allocation with different page sizes can be realized, and more memory allocation requirements are met.

In one possible implementation, the first virtual address space comprises a first sub-virtual address space and a second sub-virtual address space, wherein the first sub-virtual address space is a kernel-mode address space, the second sub-virtual address space is a user-mode address space, the first virtual page or the second virtual page is allocated to the task based on the control group to which the task belongs in the preset control group in the case that the task belongs to the preset control group, the first virtual page in the first sub-virtual address space is allocated to the task in the case that the task belongs to the first control group, and the first virtual page in the second sub-virtual address space is allocated to the task in the case that the task belongs to the second control group.

In the embodiment of the application, the first virtual address space is divided into the first virtual address space and the second virtual address space, and the first virtual address space is used as the kernel-mode address space, and the second virtual address space is used as the user-mode address space, so that the user-mode task and the kernel-mode task can use a large page in the first virtual address space, and the hit rate of the TLB is improved.

In one possible implementation, the first virtual address space comprises a first sub-virtual address space and the second virtual address space comprises a third sub-virtual address space, wherein the first sub-virtual address space is a kernel-mode address space, the third sub-virtual address space is a user-mode address space, the task is allocated with the first virtual page or the second virtual page based on the control group to which the task belongs in the preset control group in the case that the task belongs to the first control group, and the task is allocated with the first virtual page located in the first sub-virtual address space in the case that the task belongs to the first control group, and the task is allocated with the second virtual page located in the third sub-virtual address space in the case that the task belongs to the second control group.

In the embodiment of the application, the memory is allocated for the user mode task based on the smaller second virtual page by taking the third sub-virtual address space in the second virtual address space as the user mode address space, so that the memory utilization efficiency can be improved, the kernel mode address space and the user mode address space can be further isolated, and the security of memory access can be improved.

In one possible implementation, the method further includes assigning the second virtual page to the task if the task does not belong to the preset control group.

In the embodiment of the application, the second virtual pages are uniformly distributed to the tasks which are not managed by the preset control group, so that the workload of the preset control group of the staff can be reduced, and the working efficiency is improved.

In one possible implementation, the second virtual address space includes a fourth sub-virtual address space, the fourth sub-virtual address space being a kernel-mode address space, and the allocating the second virtual page to the task if the task does not belong to the preset control group includes determining whether the task is a kernel-mode task if the task does not belong to the preset control group, and allocating the second virtual page located in the fourth sub-virtual address space to the task if the task is the kernel-mode task.

In the embodiment of the application, the second virtual space is divided into the fourth sub virtual space, so that the second virtual page is allocated for the kernel mode task, and the memory allocation requirement of the kernel mode task on the small page can be met.

In one possible implementation, before the task of determining whether the task to be allocated with memory belongs to a preset control group, determining whether the task is a target task, where determining whether the task to be allocated with memory belongs to a preset control group includes determining whether the task belongs to the second control group if the task is the target task, where allocating the first virtual page or the second virtual page for the task based on the control group to which the task belongs if the task belongs to the preset control group includes determining whether an offset in an MMAP request corresponding to the task matches a page size of the first virtual page if the task belongs to the second control group, where determining whether the MMAP request is a fixed map if the offset matches a page size of the first virtual page and if a mapping address range of the MMAP request is in the third virtual address space, where the MMAP request is not a fixed map or the mapping address range is in the second virtual address space, and where the virtual address range is in the virtual address space is allocated for the second virtual address space.

Wherein, in the case that the MMAP request is a fixed mapping and the mapped address range is located in the third sub-virtual address space, the first virtual page located in the second sub-virtual address space is allocated for the task.

The second control group is specifically configured to control allocation of the first virtual page to the preset user mode task, where the first virtual address space includes a second sub-virtual address space, and the second virtual address space includes a third sub-virtual address space.

Wherein the second sub-virtual address space and the third sub-virtual address space are user-state address spaces.

The target task is a task for executing memory mapped MMAP.

In the embodiment of the application, the memory mapping behavior of the task request can be authenticated through the control group to which the task belongs and the mapping address range indicated by the MMAP request, and virtual pages with corresponding sizes are allocated, so that different memory mapping requirements can be met while the security of the memory mapping is ensured.

In one possible implementation, after the task is allocated to the first virtual page or the second virtual page based on the control group to which the task belongs, the method further comprises determining a first physical page accessed by the task based on a target virtual page and a page table, determining whether the page size of the target virtual page matches the page size of the first virtual page in response to the first physical page being missing, determining whether a virtual address corresponding to the target virtual page is located in the second sub virtual address space if the page size of the target virtual page matches the page size of the first virtual page, allocating a second physical page to the task if the virtual address corresponding to the target virtual page is located in the second sub virtual address space, and adding the mapping relationship between the second physical page and the target virtual page to the page table.

The target virtual page is a virtual page indicated by a virtual address in the access request of the task.

Wherein the second physical page has the same page size as the first virtual page.

In the embodiment of the application, the access behavior is authenticated when the occurrence of the page missing is detected, and the corresponding physical page allocation is performed when the access target is determined to be the user space, so that the security of the access behavior can be improved.

In one possible implementation, the first virtual address space includes a second sub-virtual address space, the second virtual address space includes a fourth sub-virtual address space, and the method further includes adding a first page table entry in a task_struct data structure of a first task in response to creating the first task to add a second page table entry of a current task in a second page table base address register to the task_struct data structure of the first task.

The second page table base address register is used for storing a page table base address of the second virtual address space.

The first page table entry is used for indicating a page table base address of the second sub-virtual address space, and the second page table entry is used for indicating a page table base address of the fourth sub-virtual address space.

In the embodiment of the application, when the first task is created, the first page table item of the first task and the second page table item of the current task are added in the task_struct data structure of the first task, so that the correctness of the user-mode address space and the kernel-mode address space can be ensured, and the occurrence of abnormality or failure when the processor accesses the memory can be avoided.

In one possible implementation, after the adding of the second page table entry of the current task in the second page table base address register to the task_struct data structure of the first task, the method further includes, in response to switching the first task to the second task, updating a corresponding page table entry in the first page table base address register according to the first page table entry in the task_struct data structure of the second task, updating the task_struct data structure of the second task according to the second page table entry of the first task in the second page table base address register, and then loading the PGD in the task_struct data structure of the second task to the second page table base address register.

The first page table base address register is used for storing a page table base address of the first virtual address space.

In the embodiment of the application, when the first task is switched to the second task, the page table entries in the first page table base address register and the second page table base address register are updated, so that the page table base address of the user space of the second task is correspondingly loaded, and the page table base address of the kernel space is unchanged, thereby ensuring the correctness of the user state address space and the kernel state address space and avoiding the occurrence of abnormality or failure when the processor accesses the memory.

A second aspect of an embodiment of the present application provides a computing device, the computing device including a memory and a processor, wherein the processor is an ARM architecture, the processor being coupled to the memory, the memory storing computer program instructions, the computer program instructions being loaded and executed by the processor to cause the computing device to implement any one of the methods possible to implement the method.

A third aspect of the embodiments of the present application provides a computer-readable storage medium having stored therein computer-executable instructions for execution by a computing device to implement a method as may be described in any of the first aspects.

The fourth aspect of the embodiments of the present application also provides a computer program product comprising computer-executable instructions stored in a computer-readable storage medium, the computer-executable instructions being readable by at least one processor of the apparatus from the computer-readable storage medium, the computer-executable instructions being executable by the at least one processor to cause the apparatus to perform any one of the methods as possible in the first aspect.

It should be appreciated that the benefits of the various aspects described above may be referenced to one another.

Drawings

FIG. 1 is a schematic diagram of a virtual address space distribution;

fig. 2 is a schematic diagram of an application scenario according to an embodiment of the present application;

Fig. 3 is a flow chart of a memory allocation method according to an embodiment of the present application;

FIG. 4 is a schematic diagram illustrating a virtual address space distribution according to an embodiment of the present application;

FIG. 5 is a schematic diagram of a memory mapping process according to an embodiment of the present application;

FIG. 6 is a schematic diagram of a page fault handling process according to an embodiment of the present application;

fig. 7 is a schematic structural diagram of a computing device according to an embodiment of the present application.

Detailed Description

Embodiments of the present application will now be described with reference to the accompanying drawings, in which it is evident that the embodiments described are only some, but not all embodiments of the present application. As one of ordinary skill in the art can know, with the development of technology and the appearance of new scenes, the technical scheme provided by the embodiment of the application is also applicable to similar technical problems.

The terms first, second and the like in the description and in the claims and in the above-described figures, are used for distinguishing between similar elements and not necessarily for describing a particular sequential or chronological order. It is to be understood that the data so used may be interchanged where appropriate such that the embodiments described herein may be implemented in other sequences than those illustrated or otherwise described herein. Furthermore, the terms "comprises," "comprising," and "having," and any variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, system, article, or apparatus that comprises a list of steps or elements is not necessarily limited to those steps or elements expressly listed but may include other steps or elements not expressly listed or inherent to such process, method, article, or apparatus.

Some term concepts related to the embodiments of the present application are explained below.

(1) Advanced reduced instruction set machine (ADVANCED RISC MACHINE, ARM) architecture

The ARM architecture is also called an ARM architecture, which is a hardware specification and is mainly used for specifying an instruction set and an architecture inside a chip. Computing devices employing the ARM architecture have been referred to in the past as advanced reduced instruction set machines that employ a meta-reduced instruction set (reduced instruction set computer, RISC) central processor architecture, and ARM architecture computing devices are widely used in many embedded system designs.

(2) Operating system

The operating system is system software for managing computer hardware and software resources, and is also the foundation of the computer system. The operating system needs to handle basic transactions such as managing and configuring memory, prioritizing the supply and demand of system resources, controlling input and output devices, operating networks, and managing file systems. The operating system may also provide an operator interface for a user to interact with the system.

(3) Kernel

The kernel is a program used for managing data input and output requirements sent by software, translates the requirements into data processing instructions and transmits the data processing instructions to a central processing unit (central processing unit, CPU) and other electronic components in a computer for processing, and is the most basic part in a modern operating system.

(4) Memory

Memory is an important component of a computing device, also known as internal memory or main memory, which is used to temporarily store operational data in a CPU, as well as data exchanged with external memory such as a hard disk. The memory is a bridge for communicating the external memory with the CPU, and all programs in the computer are run in the memory, so that the strength of the memory performance affects the level of the whole exertion of the computer.

(5) Tasks

A program is a description of instructions, data, and their organization, and a process is an operating entity of the program. Multiple threads may be concurrent in a process, and a thread may be the actual unit of operation of a process, where a thread may also be referred to as a lightweight process. In the ARM architecture, processes and threads are not distinguished and are uniformly managed by a task_struct data structure, and in the embodiment of the application, tasks are adopted to uniformly describe the processes and the threads.

(6) Virtual address space

The virtual address space is a set of virtual addresses, the virtual addresses are logical addresses used by a CPU when executing tasks, the CPU accesses corresponding physical addresses in a physical memory through the virtual addresses, the virtual address space can also be called a process address space, the virtual address space comprises a user space which is independently owned by each task, the situation that access conflict and access errors caused by the mutual access of the tasks can be avoided, and the virtual address space also comprises a kernel space which is shared by all the tasks.

(7) Physical page, virtual page, page table

The operating system divides the memory space into partitions of equal size, which are referred to as physical blocks, and physical pages, which are a collection of one or more physical blocks, are also referred to as page frames.

The operating system is divided from the virtual address space into regions of the same size as the physical pages, which are referred to as virtual pages.

The page mapping table established by the operating system for each process is called a page table, and for all virtual pages in the virtual address space of a process, there is a page table entry in the page table of the process in turn, where the page table entry records the mapping relationship between the virtual page and the corresponding physical page in the memory.

In memory management, in view of saving memory space and facilitating discrete storage, page table entries are generally managed in a multi-level page table manner. In the memory management model of the multi-level page table, taking a four-level page table as an example, the four-level page table is a page global directory (page global directory, PGD), a page upper level directory (page upper directory, PUD), a page middle directory (page middledirectory, PMD), and a page table, respectively.

(8) Kernel mode task and user mode tasks

The operating system divides a kernel space and a user space in the virtual address space, wherein the kernel space is used for mapping kernel codes, and the user space is used for mapping application program codes of corresponding tasks. When the task is executed in the code of the application program, the task can be called a user running state task or simply called a user state task, and when the task is executed in the kernel code after the task is called by a system execution system, the task can be called a kernel running state task or simply called a kernel state task.

(9) Control group (Cgroup)

The group members of the control group are tasks, and the control group may be used to limit the resource usage objects, the number of resource usage, and the priority of resource usage of its group members.

(10) Memory map (memory map, MMAP)

Memory mapping is a method of memory mapping files to map files or other objects to a virtual address space of a process.

(11) Page fault (page fault)

Page faults, also called page misses, refer to interrupts caused by the fact that when a CPU performs a task, it is found that the target virtual page being accessed does not have a corresponding physical page in memory. In practical application, when executing a newly created task, the CPU will continuously generate page faults in the process of accessing the virtual address space of the task, then the page fault handler allocates an actual physical page for the task, and then writes the mapping relationship between the physical page and the accessed target virtual page into the corresponding page table.

(12) Page table base register (translation table base register, TTBR)

TTBR0 and TTBR1 are included in the ARM architecture, and TTBR0 and TTBR1 are used to store primary page table base addresses of the user space and kernel space, respectively, i.e., PGD. Since all tasks share the same kernel space, the content in TTBR1 is unchanged, and the user spaces of the tasks are independent, so the content in TTBR0 is PGD in the task_struct data structure of the task executed by the current CPU.

After understanding the basic meaning of the above terms, the application scenario of the embodiment of the present application is described below.

Referring first to fig. 1, fig. 1 is a schematic diagram illustrating a virtual address space distribution. In the current ARMv8 architecture, the ARM processor supports a 64-bit virtual address space, and the memory requirements of the current application program do not need to use the entire 64-bit virtual address space, so that the ARMv8 architecture generally adopts a 48-bit address line width, and a 48-bit user space and a 48-bit kernel space are divided in the 64-bit virtual address space.

As shown in FIG. 1, the kernel space is at the top of the virtual address space, the high 16 bits are all 1, the address range is [0xFFFF 000000000000,0xFFFF FFFF FFFF FFFF ], the user space is at the bottom of the virtual address space, the high 16 bits are all 0, the address range is [0x0000000000000000,0x0000 FFFF FFFF FFFF ], and the addresses with the high 16 bits being all 1 or all 0 are called canonical addresses, and non-canonical addresses are not allowed to be used between the addresses.

Referring to fig. 2, fig. 2 is a schematic diagram of an application scenario of an embodiment of the present application, and as shown in fig. 2, the computing device 10 includes a processor 110, a memory 120, a first page table base address register TTBR1 and a second page table base address register TTBR0, the processor 110 includes a memory management unit (memory management unit, MMU) 111 and a page table cache (translation lookaside buffer, TLB) 112, and the memory 120 stores a page table 121. Wherein the processor 110, TTBR0 and TTBR1 may be integrated in the same chip. Illustratively, the processor 110 is an ARM architecture processor.

During the task execution process, the processor 110 generates a memory access request when the memory 120 needs to be accessed, wherein the memory access request comprises a virtual address in a virtual address space of the task, the processor 110 queries whether a page table item corresponding to the virtual address exists in the TLB 112 through the MMU 111, if so, the processor 110 can allocate a corresponding memory resource to the task according to the page table item, and if not, the processor 110 can further search the page table item corresponding to the virtual address in the page table 121 through the MMU 111.

If there is no page table entry corresponding to the virtual address in both the TLB 112 and the page table 121, a page miss is triggered, and at this time, the processor 110 may execute a page miss handler, allocate an actual physical page for the task, and then write the mapping relationship between the physical address of the physical page and the virtual address into the corresponding page table.

In the process of searching the page table 121, if the most significant bit of the virtual address in the memory allocation request is 0, the processor 110 may obtain the PGD of the user space from TTBR0, and search the page table corresponding to the virtual address according to the PGD. If the most significant bit of the virtual address is 1, then the processor 110 may obtain the page table base address of the kernel space from TTBR1, and then query the page table corresponding to the virtual address according to the page table base address.

Illustratively, [38:30] of this virtual address can be used to place an index of the PGD, [29:21] can be used to place an index of the PMD, [20:12] can be used to place an index of the PTE, and [11:0] can be used to place a page offset. After obtaining the physical page base address from TTBR0 or TTBR1, processor 110 may perform the following steps:

The first step, taking the PGD index in [38:30] of the virtual address as the offset of the PGD, then adding the first address in TTBR0 or TTBR1 and the offset of the PGD to obtain one item in the PGD, determining the PMD pointed by the item in the PGD, and the second step, taking the PMD index in [29:21] of the virtual address as the offset of the PMD, adding the first address of the PMD determined in the first step and the offset of the PMD to obtain one item in the PMD, and determining the PTE pointed by the item in the PMD. And thirdly, taking the PTE index in [20:12] of the virtual address as the offset of the PTE, adding the head address of the PTE determined in the second step and the offset of the PTE to obtain one item of the PTEs, determining a page table item corresponding to the item in the PTE, determining the address of a physical page corresponding to the virtual address according to the page table item, and adding the offset of the physical address placed in [11:0] of the virtual address and the address of the physical page to obtain the physical address after determining the address of the physical page.

In the application scenario shown in fig. 2, if the MMU 111 can find the corresponding page table entry, i.e. the direct access hit, when the TLB 112 is queried, the processor 110 does not need to query in the page table 121, so that a large amount of computing resources can be saved, and therefore, the mapping between the physical page and the virtual page is performed by adopting the page with the larger page size granularity, and the same number of page table entries in the TLB 112 can indicate a larger memory range, so that the hit rate of the TLB 112 can be improved.

And the page with smaller page table size granularity is adopted to map the physical page and the virtual page, so that the memory utilization rate can be improved, the generation of internal fragments is reduced, and the situation that the memory required by a task is far smaller than one memory page, so that most of the memory page is wasted is avoided.

However, the current ARM architecture supports mapping between physical pages and virtual pages with a page size of one of 4KB, 16KB or 64KB, and cannot use two or more page sizes for memory allocation at the same time, which is difficult to meet different memory allocation requirements.

Based on this, the embodiment of the application provides a memory allocation method and related equipment, which can realize memory allocation with different page sizes and granularity under the ARM architecture, thereby meeting more memory allocation requirements.

Referring to fig. 3, fig. 3 is a flowchart of a memory allocation method according to an embodiment of the present application, where the method is applied to a computing device shown in fig. 2, and the computing device includes an ARM architecture processor (hereinafter, simply referred to as a processor), so that the computing device may also be referred to as an ARM architecture computing device, and the method specifically includes steps 301 to 304.

Step 301, configuring a page size of a first virtual page of a first virtual address space and a page size of a second virtual page of a second virtual address space.

The processor may configure a TG1 field in a tcr_el1 register in the computing device during a startup phase after the computing device is powered on, so that a first virtual address space in the virtual address space is divided according to a preset page size (page length), thereby configuring a page size of a first virtual page in the first virtual address space, and then configure a page table base address in TTBR1 according to the page size of the first virtual page.

The exemplary TG1 field is set to 0b10, the page size of the first virtual page is 4KB, the TG1 field is set to 0b01, the page size of the first virtual page is 16KB, and the TG1 field is set to 0b11, the page size of the first virtual page is 64KB.

The processor may configure the TG0 field in the tcr_el1 register such that the second virtual address space of the virtual address space is divided according to a preset page size, thereby configuring a page size of a second virtual page in the second virtual address space, and then configure the virtual address portion in TTBR0 according to the page size of the second virtual page.

The exemplary setting of the TG0 field to 0b00 results in a page size of 4KB for the first virtual page, the setting of the TG1 field to 0b10 results in a page size of 16KB for the first virtual page, and the setting of the TG1 field to 0b01 results in a page size of 64KB for the first virtual page.

Wherein the page size of the first virtual page is larger than the page size of the second virtual page. Illustratively, the first virtual page has a page size of 64KB and the second virtual page has a page size of 4KB.

After the sizes of the virtual pages in the first virtual address space and the second virtual address space are configured, the processor can configure the access rights of the first virtual address space and the second virtual address space so as to control the access behaviors of different tasks to the virtual address space and avoid access conflicts or access errors.

Specifically, each page table item of the page table comprises a mapping relation between a virtual page and a physical page, and also comprises the access authority of the virtual page corresponding to the page table item, and the processor can perform authentication first after searching the corresponding page table item, and execute subsequent access actions after determining that the currently executed task has corresponding authority.

The first virtual address space configured through the TG1 field belongs to a high-order space in the virtual address space, the first n bits of an address in the high-order space are 1, n is an integer greater than 0 and less than 64, and the second virtual address space configured through the TG0 field belongs to a low-order space in the virtual address space, and the first n bits of the address in the low-order space are 0. Illustratively, n may be 16.

The processor can configure the access authority of the first sub-virtual address space as kernel mode task access, and the access authority of the second sub-virtual address space as kernel mode task and user mode task access.

In one possible implementation, as shown in fig. 4, the second virtual address space includes a third sub-virtual address space and a fourth sub-virtual address space, where the access right of the third sub-virtual address space is accessible to both kernel-mode tasks and user-mode tasks, and the access right of the fourth sub-virtual address space is accessible to the kernel-mode tasks.

Thus, in the specific example of fig. 4, the first sub-virtual address space and the fourth sub-virtual address space serve as kernel-mode address spaces (hereinafter, simply referred to as kernel spaces), and the second sub-virtual address space and the third sub-virtual address space serve as user-mode address spaces (hereinafter, simply referred to as user spaces).

Optionally, the processor may further configure the access right of the second sub-virtual address space to be only accessed by the user mode task, so as to avoid occupation of the second sub-virtual address space reserved for the user mode task by the kernel mode task.

According to the embodiment of the application, the first virtual address space of the high position and the second virtual address space of the low position are further divided, a part of the high position space and a part of the low position space are used as the kernel space together, and the other part of the high position space and the other part of the low position space are used as the user space together, so that physical pages with different sizes can be flexibly distributed according to the requirements of kernel-state tasks and user-state tasks.

It will be appreciated that the interval distribution shown in fig. 4 is merely exemplary and not limiting, and in a specific implementation, the second sub-virtual address space may be located before the first sub-virtual address space, or the first sub-virtual address space may be divided into two parts, and the fourth sub-virtual address space may be located in the same way.

Specifically, the processor may configure the access rights of the page table entries corresponding to the one or more page table base addresses in TTBR0 to be accessible to the kernel mode task, so that the address interval corresponding to the one or more page table base addresses is used as a fourth sub-virtual address space in the second virtual address space. Thus, when a smaller (e.g., 4 KB) physical page is needed for use by a driver module or other functional module in the kernel, the processor can allocate a second virtual page of a corresponding size for the corresponding task.

Similarly, the processor may configure access rights of page table entries corresponding to one or more page table base addresses in TTBR1 to be accessible to the user-mode task, such that an address interval corresponding to the one or more page table base addresses is a second sub-virtual address space in the first virtual address space. In this way, the processor may allocate a first virtual page for the application program, thereby increasing the hit rate of the TLB.

Optionally, the space size of the first sub-virtual address space is larger than the space size of the second sub-virtual address space, and the space size of the third sub-virtual address space is larger than the space size of the fourth sub-virtual address space. Therefore, the kernel mode task can be ensured to be allocated with large page memory more, and the kernel performance is improved.

It will be appreciated that in general, the virtual address space will be divided into two spaces, namely kernel space and user space, wherein the high-order space is reserved for operating system and hardware use and the low-order space is provided for application programs. Specifically, registers of hardware are typically mapped to high address areas of physical addresses, so that the kernel can access the hardware faster with the high order space in the virtual address space as kernel space, while it is more reasonable for programming convenience to allocate applications from low order addresses. The isolation of the kernel space and the user space can prevent the conflict between the user program and the kernel, and the kernel is better protected.

In the embodiment of the application, a more high-order first virtual address space is used as a kernel space, a more low-order second virtual address space is used as a user space, and the existing application programs, operating systems and hardware can be better compatible, after the configuration of a first virtual page of the first virtual address space is finished, a processor can map the first virtual page with a memory and input/output (IO) spaces of various hardware respectively, so that an operating system can call kernel codes stored in the memory and various hardware resources based on the first virtual address space.

Meanwhile, the kernel mode task can use more first virtual pages with larger page sizes and larger granularity, so that the memory allocation times can be reduced, and the kernel performance is improved.

Step 302, determining whether a task of the memory to be allocated belongs to a preset control group.

After completing the page configuration of the first virtual address space and the second virtual address space, step 302 may be performed when the processor detects that virtual memory needs to be allocated for the task. The task to be allocated with the memory refers to a task to be allocated with the virtual memory. Illustratively, when the processor maps an associated file of the task in an external memory of the computing device, such as a hard disk, to a virtual address space, the processor will allocate a virtual page in its virtual address space for the task and map the virtual page with the associated file.

The preset control group is used for controlling memory allocation for the task. The preset control group comprises a first control group and a second control group, wherein the first control group is used for controlling the allocation of a first virtual page for a preset kernel mode task, and the second control group is used for controlling the allocation of a first virtual page or a second virtual page for a preset user mode task.

The processor can determine whether the task is a kernel mode task or a user mode task, and then determine whether the task belongs to a control group for controlling the kernel mode task in the preset control group or belongs to a control group for controlling the user mode task in the preset control group.

Optionally, the second control group comprises a first sub-control group and a second sub-control group, wherein the first sub-control group is used for controlling the allocation of the first virtual page for the preset user mode task, and the second sub-control group is used for controlling the allocation of the second virtual page for the preset user mode task.

Optionally, the second control group is configured to control to allocate one of the first virtual page or the second virtual page to the preset user-mode task preferentially, and allocate the other one of the first virtual page or the second virtual page to the preset user-mode task when the preferentially allocated virtual page is insufficient.

Wherein the members of the control group are tasks. When the processor invokes the kernel code or the application code to execute the task, an operating system running on the processor may obtain an identification of the currently executing task, and then determine a control group to which the task belongs based on the identification. Specifically, the operating system may obtain a first identifier of the task of the memory to be allocated, and then traverse a second identifier of a member in the preset control group to determine whether the first identifier is matched with the second identifier, thereby determining whether the task belongs to the preset control group. For example, the first identifier and/or the second identifier may be information for uniquely identifying the task in a task_struct data structure of the corresponding task.

Step 303, if the task belongs to a preset control group, allocating a first virtual page or a second virtual page based on the control group to which the task belongs.

In the case that the task is determined to belong to the preset control group, the processor may allocate a virtual page for the task based on the memory usage rights or the memory usage priority set by the corresponding control group.

Specifically, the processor may first obtain the size of the virtual memory required by the task, and then allocate a corresponding number of first virtual pages or second virtual pages to the task based on the memory usage rights or the memory usage priorities set by the corresponding control group.

In one possible implementation, the processor may allocate a first virtual page for the task in the case where the task belongs to a first control group, that is, the task is a task in a preset kernel mode, and allocate a first virtual page or a second virtual page for the task in the case where the task belongs to a second control group, that is, the task is a task in a preset user mode.

Wherein, in the case that the task belongs to the first control group, the processor may allocate a first virtual page located in the first sub virtual address space for the task.

Alternatively, in the case where the task belongs to the second control group, the processor may allocate a first virtual page in the second sub-virtual address space for the task.

Optionally, the second virtual address space comprises a third sub-virtual address space, the third sub-virtual address space being a user space, and the processor allocates a second virtual page located in the third sub-virtual address space for the task in case the task belongs to the second control group.

In one possible implementation, the second control group includes a first sub-control group and a second sub-control group, the processor may allocate a first virtual page located in a second sub-virtual address space for the task in the case of the task belonging to the first sub-control group, and allocate a second virtual page located in a third sub-virtual address space for the task in the case of the task belonging to the second sub-control group.

In another possible implementation, the processor preferentially allocates a first virtual page in the second sub-virtual address space for the task in the case where the task belongs to the second control group, and allocates a second virtual page in the third sub-virtual address space for the task in the case where the first virtual page in the second sub-virtual address space is insufficient.

Step 304, if the task does not belong to the preset control group, a second virtual page is allocated to the task.

The virtual pages with the preset page sizes can be allocated to different tasks through the preset control group, and the virtual pages with the corresponding sizes can be allocated based on the actual demands of the different tasks, so that the tasks can use the physical pages with the corresponding sizes, and the use efficiency of the memory is higher. The method can be used for solving the problem that the task with high importance level, high operation requirement or high memory read-write requirement is divided into preset control groups by staff, and for the tasks which do not belong to the preset control groups, the processor can uniformly allocate second virtual pages with smaller granularity to the tasks, so that the tasks with low importance level, low operation requirement or low memory read-write requirement are prevented from occupying the first virtual pages.

In one possible implementation, the second virtual address space includes a third sub-virtual address space and a fourth sub-virtual address space, the third sub-virtual address space is used as a user space, the fourth sub-virtual address space is used as a kernel space, the processor can determine whether the task is a kernel-mode task or not first if the task does not belong to a preset control group, allocate a second virtual page located in the fourth sub-virtual address space to the task if the task is a kernel-mode task, and allocate a second virtual page located in the third sub-virtual address space to the task if the task is a user-mode task.

In the embodiment of the application, the two intervals with different page sizes and granularity are configured in the virtual address space, and the first virtual page or the second virtual page is allocated for different tasks based on the preset control group, so that the memory allocation with different page sizes and granularity can be realized, and more memory allocation requirements are met.

It can be understood that the user space of the task is described and managed by the task_struct data structure of the task, so in the embodiment shown in fig. 3, in the case that the user space and the kernel space both include a high-order address and a low-order address by adopting the division manner of the virtual address space shown in fig. 4, when the processor creates the task and switches the task, the task_struct data structure of the corresponding task needs to be correspondingly adjusted and updated to avoid access conflicts under the new access permission setting.

Specifically, after completing the configuration of the access rights of the virtual address space, the processor may update the task_struct data structure of the corresponding task and the page table entries in TTBR0, TTBR1 when creating the task or switching the task.

The task has five basic states, namely a new state, namely a state when a new task is created by a processor, a ready state, namely a state that the task is allocated with all necessary resources except the processor resources and can be operated after waiting for the system to allocate the processor resources, an operating state, namely a state that the task is being operated by the processor, a waiting state, namely a blocking state or a sleeping state, a state that the task does not have an operation condition to suspend operation and is waiting for the occurrence of an event, and a terminating state, namely a state that the task is normally ended after being completed, or is abnormally terminated due to the occurrence of an irrecoverable error, or a state that the task is terminated by an operating system and a process with a termination right.

Specifically, the processor may configure the task_struct data structure of the task after creating the task.

In one possible implementation, after configuring the page sizes of the first virtual address space and the second virtual address space, and the access rights of the respective sub-virtual address spaces, the processor may add a first page table entry in a task_struct data structure of the first task in response to creating the first task, and then add a second page table entry of the current task in the second page table base address register to the task_struct data structure of the first task.

Wherein the current task is the task being executed by the processor.

The first page table entry is used for indicating a page table base address of a second sub virtual address space, and the second page table entry is used for indicating a page table base address of a fourth sub virtual address space.

The computing device includes a first page table base address register corresponding to TTBR1 in the embodiment of FIG. 2, and a second page table base address register corresponding to TTBR0 in the embodiment of FIG. 2. For ease of description, the first page table base address register will be referred to hereinafter as TTBR1, and the second page table base address register will be referred to hereinafter as TTBR0.

Specifically, TTBR1 is used to store the page table base address of the first virtual address space, and TTBR0 is used to store the page table base address of the second virtual address space.

Each task is provided with a user space belonging to the task, when the processor creates the task, the processor divides the second virtual address space according to a TG0 field in a TCR_EL1 register to obtain a PGD of the second virtual address space of the task, then allocates a physical page to store the PGD, maps the physical address of the physical page with the head address of the PGD, and finally writes the PGD into a task_struct data structure of the task when configuring management information of the task. Thus, when executing the task, the processor may obtain the PGD from the task_struct data structure of the task, and load the PGD into TTBR0, so that the MMU may find the page table corresponding to the task through the page table base address in TTBR 0.

Since in this embodiment, the processor configures the access right of the second sub-virtual address space in the first virtual address space, and uses the second sub-virtual address space as a part of the user space, the processor may add the first page table entry for indicating the page table base address of the second sub-virtual address space of the task in the task_struct data structure of the newly-built state, so that the processor may synchronize the corresponding first page table entry to TTBR1 when executing the task, so that the processor can access the second sub-virtual address space of the currently-executed task through TTBR1, so as to avoid an access error.

The processor can acquire the PGD of the first virtual address space of the first task, acquire the first address of the second virtual address space from the PGD, allocate a physical page to the first task and map the first address of the second virtual address space, and finally write the mapping relation and the page table base address of the second virtual address space, namely the first page table entry, into the task_struct data structure of the first task.

In addition, in this embodiment, the processor uses the fourth sub-virtual address space as the kernel space by configuring the access right of the fourth sub-virtual address space of the second virtual address space, and each task shares the same kernel space but has an independent user space, so that it is necessary to keep the third sub-virtual address space of each task independent from each other, and the page table base addresses of the fourth sub-virtual address space are consistent. Because the PGD in the task_struct data structure of each task is used for managing the second virtual address space of the corresponding task, the processor can update the second page table item of the currently executed task in TTBR0 to the PGD in the task_struct data structure of the newly created first task, thereby maintaining the consistency of the kernel space of the processor under the condition of executing different tasks and avoiding the occurrence of exception or failure when the processor accesses the kernel space.

Specifically, the processor may write the second page table entry to the PGD, overwriting the page table entry in the PGD with the virtual address portion being the same.

And when the task is switched from the ready state or the waiting state to the running state, the processor needs to switch the related context so as to ensure the normal running of the task.

The context is a static description of the whole task execution activity process, the contents of executed task instructions and data in the relevant registers and stacks are called the above, the contents of executing instructions and data in the relevant registers and stacks are called the text, and the contents of instructions and data to be executed in the relevant registers and stacks are called the below. The context switch includes a switch of virtual address space to ensure that when a CPU accesses instructions and data when executing a task, it accesses the address space in memory belonging to the task.

In one possible implementation, the processor creates a first task and a second task and executes the first task, in response to switching the first task to the second task, the processor may update a corresponding page table entry in TTBR1 based on a first page table entry in a task_struct data structure of the second task, and then update a task_struct data structure of the second task based on a second page table entry of the first task in TTBR 0.

Wherein, in the process of switching the first task to the second task, the processor may switch the context of the first task to the context of the second task.

Therefore, when the first task is switched to the second task, the first page table item corresponding to the first task in the TTBR1 is required to be updated into the first page table item corresponding to the second task, so that the processor can access the user space of the processor through the TTBR 1.

Specifically, the processor may write the page table entry value of the first page table entry corresponding to the second task into TTBR1, covering the first page table entry corresponding to the first task.

The processor can acquire a second page table item of the first task in TTBR0, namely a page table base address of a fourth virtual address space of the first task, copy and write a PGD corresponding to the second task according to the second page table item corresponding to the first task, update the second page table item corresponding to the second task, and write the PGD of the second task into TTBR0 to keep the page table base address of the kernel space unchanged.

It will be appreciated that the processor may update the page table entry in TTBR1 before updating the page table entry in TTBR0, or may update the page table entry in TTBR0 before updating the page table entry in TTBR1, which is not particularly limited in the embodiment of the present application.

In another possible implementation, the processor may obtain a third page table entry in the PGD in the task_struct data structure of the second task, where the third page table entry is a page table base address for indicating a third sub-virtual address space of the second task, and update a page table entry corresponding to the third sub-virtual address space in TTBR0 according to the third page table entry.

The processor may keep the page table entry of the fourth sub-virtual address space in TTBR0 unchanged, and then update the third page table entry corresponding to the third sub-virtual address space as the user space to TTBR0.

Specifically, the processor may write the page table entry value of the third page table entry corresponding to the second task into TTBR0, covering the third page table entry corresponding to the first task in TTBR 0.

In another possible implementation, the processor may first obtain the second page table entry of the first task in TTBR0, then write the PGD in the task_struct data structure of the second task into TTBR0, and then update the second page table entry of the second task in TTBR0 according to the second page table entry corresponding to the first task.

By the configuration and updating actions when the task is created and switched, access conflict can be avoided and the safety of the kernel space can be improved under the condition that the user space and the kernel space both comprise high-order addresses and low-order addresses.

The memory allocation process in the embodiment of the present application will be further described below with reference to two application scenarios.

Referring to fig. 5, fig. 5 is a schematic diagram of a memory mapping process according to an embodiment of the present application, where the process is performed by a computing device, and the computing device includes an ARM architecture processor, and as shown in fig. 5, the memory mapping process includes steps 501 to 506.

Step 501, determining a task of the memory to be allocated as a target task.

The virtual address space distribution in this embodiment is shown in fig. 4.

The target task is a task for executing Memory Map (MMAP). After the processor newly builds a task, the processor needs to allocate a virtual page in the virtual address space for the task so as to map the related file of the task into the virtual address space of the task, and at this time, the processor can determine the task of the memory to be allocated as a target task. Specifically, when the task executes the MMAP, an MMAP request is sent to the operating system.

The MMAP request includes a start address of the file in the memory, and a mapping length, an offset (offset) of the mapping start address in the file.

In the process of executing the task by the processor, the processor may first determine whether the task is a target task if the task needs to allocate virtual memory, and in the event that the task is a target task, the processor may acquire the MMAP request and execute step 502.

In the case where the task is not a target task, steps 302 to 304 in the embodiment shown in fig. 3 may be performed to allocate virtual memory for the task.

Step 502, determining whether the task belongs to a second control group.

After acquiring the MMAP request, the processor may first determine whether the task is in a second control group. The second control group is a preset control group and is used for controlling the allocation of the first virtual page for the preset user mode task.

It will be appreciated that in the memory mapping scenario of the present embodiment, the processor will preferentially allocate the first virtual page for user mode tasks belonging to the second control group.

In some other possible implementations, the first control group is for controlling its group members to only use the first virtual page.

In this embodiment, the processor may execute step 506 if the first virtual page of the second sub-virtual address space is allocated or the first virtual page cannot be allocated temporarily.

If the task is in the second control group, step 503 is performed, and if the task is not in the second control group, step 506 is performed.

Step 503, determining whether the offset of the MMAP request corresponding to the task matches the page size of the first virtual page if the task belongs to the second control group.

Wherein upon determining that the task is in the second control group, the processor may further determine whether the offset in the MMAP request matches the page size of the first virtual page.

Specifically, the processor may determine whether the offset is an integer multiple of the page size of the first virtual page. If so, the processor may determine that the MMAP request meets the requirement for memory mapping using the first virtual page, execute step 504, and if not, the processor may determine that the MMAP request does not meet the requirement, execute step 506.

Step 504, determining whether the MMAP request is a fixed mapping and the mapping address range is in the third sub-virtual address space if the offset matches the page size of the first virtual page.

And after determining that the task belongs to the second control group, the processor needs to allocate a first virtual page for the task, determines that the offset of the MMAP request is matched with the page size of the first virtual page, and accords with the requirement of performing memory mapping by adopting the first virtual page, the processor can further determine whether the current memory mapping of the task particularly designates to use the second virtual page for mapping.

At this point, the processor may determine whether the MMAP request is a fixed map and the mapped address range is located in the third sub-virtual address space.

The processor may obtain a mapping function of the memory mapping request, and if the mapping function is a fixed mapping function map_fixed, determine that the memory mapping request is a fixed mapping, otherwise, determine that the memory mapping request is not a fixed mapping.

If the memory mapping request is a fixed mapping, the fixed mapping function designates a first head address mapped in the virtual address space, and the mapping address range can be obtained according to the first head address and the mapping length.

If the MMAP request is a fixed mapping and the mapped address range is located in the third sub-virtual address space, it is indicated that the current memory mapping of the task is specifically designated to use the second virtual page for mapping and the mapping request is legal, and the processor may execute step 506.

If the MMAP request is a fixed mapping and the mapped address range is not located in the second sub-virtual address space and the third sub-virtual address space, i.e., the mapped address range is located in kernel space (first sub-virtual address space or fourth sub-virtual address space), the processor may return a memory mapping failure, or a message without a right to map, to the task.

If the MMAP request is not a fixed mapping, or if the mapped address range of the fixed mapping is located in the second sub-virtual address space, then it is indicated that the request for memory mapping by the task using the first virtual page is legal, and the processor may execute step 505.

Step 505, in the case that the MMAP request is not a fixed mapping, or the mapping address range is located in the second sub-virtual address space, allocating a first virtual page located in the second sub-virtual address space for the task.

If the MMAP request is not fixed, the processor can acquire a second head address of the mapping, wherein the second head address is determined by the operating system according to the idle condition of the current second sub virtual address space, and then the first virtual page in the second sub virtual address space is allocated for the task from the head address.

If the MMAP request is a fixed mapping and the mapped address range is located in the second sub-virtual address space, the processor may allocate a first virtual page located in the second sub-virtual address space for the task starting from a first address specified in the MMAP request.

The processor may then map the relevant file for the task to the first virtual page assigned to the task.

Step 506, allocating a second virtual page in the third sub-virtual address space for the task.

If the task is not in the second control group, or the offset in the MMAP request does not match the page size of the first virtual page, the processor may obtain a mapped third first address, where the third first address is determined by the operating system according to the idle condition of the current third sub virtual address space, and then allocate a second virtual page for the task according to starting from the first address.

If the memory map request is a fixed map and the mapped address range is located in the third sub-virtual address space, the processor may allocate a second virtual page located in the third sub-virtual address space for the task based on the first address specified in the fixed map function.

The processor may then map the relevant file for the task to a second virtual page assigned to the task.

Referring to fig. 6, fig. 6 is a schematic diagram of a page fault handling process performed by a computing device including an ARM architecture processor according to an embodiment of the present application, and the page fault handling process includes steps 601 to 608 as shown in fig. 6. The virtual address space distribution in this embodiment is shown in fig. 4.

Step 601, determining a first physical page accessed by a task based on a target virtual page and a page table.

During the process of executing the task by the processor, the corresponding physical page loaded with the relevant file data of the task needs to be accessed through the virtual page in the user space of the task. At this time, the processor may obtain the virtual address of the target virtual page in the memory access request, and then determine the corresponding first physical page based on the page table entry of the page table.

It will be appreciated that after the mapping of a virtual page and the associated files or data corresponding to a task is established, the processor may not allocate a physical page corresponding to the virtual page for the task at a first time, but instead, when the task accesses the virtual page, may allocate a physical page for the task again by triggering a page fault handler.

Thus, in the event that a first physical page miss is determined, the processor may perform step 602.

Step 602, in response to the first physical page miss, determining whether the page size of the target virtual page matches the page size of the first virtual page.

In this embodiment, the page fault that occurs when the processor accesses the user space is taken as an example. When the processor executes the user mode task and accesses the memory through the second virtual address space or the third virtual address space, if the accessed target virtual page cannot find the corresponding first physical page in the TLB and the memory page table, the processor can determine that the first physical page is missing and a page error occurs.

After determining that the page fault occurs, the processor may first determine whether the page size of the target virtual page matches the page size of the first virtual page, thereby determining the page size of the first physical page.

The page size of the first virtual page is 64KB, the page size of the second virtual page is 4KB, the processor can determine that the page size of the target virtual page is matched with the page size of the first virtual page if the page size of the target virtual page is 64KB, and the processor can determine that the page size of the target virtual page is matched with the page size of the second virtual page if the page size of the target virtual page is 4 KB.

If the page size of the target virtual page matches the page size of the first virtual page, the processor performs step 603, and if the page size of the target virtual page matches the page size of the second virtual page, the processor performs step 605.

It will be appreciated that in this embodiment, the virtual page of the entire virtual address space includes the first virtual page and the second virtual page, that is, when the page size of the target virtual page does not match the page size of the first virtual page, the page size of the target virtual page matches the page size of the second virtual page.

In other embodiments, when the virtual address space includes virtual pages with more granularity, embodiments that are adapted to achieve the same effect based on the present embodiment may be adapted, and these embodiments are within the scope of the embodiments of the present application.

Step 603, determining whether the virtual address corresponding to the target virtual page is located in the second sub virtual address space if the page size of the target virtual page matches the page size of the first virtual page.

After determining the page size of the target virtual page, the processor may further determine a sub virtual address space in which the target virtual page is located to determine whether the access of the task is legal.

Specifically, when the page size of the target virtual page matches the page size of the first virtual page, the processor may further determine whether the target virtual page is in the second sub virtual address space.

If the target virtual page is in the second sub virtual address space, it indicates that the access target of the task is the first virtual page in the user space, and the processor has a corresponding access right when executing the task, so step 604 can be executed.

If the target virtual page is not in the second sub virtual address space, i.e. in the first sub virtual address space, it is indicated that the access target of the task is kernel space, and the processor does not have a corresponding access right when executing the task, at this time, the processor may execute step 608.

Step 604, allocating a second physical page for the task if the virtual address is in a second sub-virtual address space.

Wherein the second physical page is the same as the page size of the first virtual page.

In the event that a page miss is determined to occur and the access behavior of the task is legal, the processor may allocate a second physical page for the task that is the same size as the page of the first virtual page to map the second physical page with the target virtual page.

In one possible implementation, in the case that the page miss is a soft page miss, that is, the data content corresponding to the target virtual page has been loaded into the second physical page of the memory, the processor may allocate the second physical page to the task, and then execute step 607.

In another possible implementation, in the case that the page miss is a hard page miss, that is, the data content corresponding to the target virtual page is not loaded to the second physical page of the memory, the processor may determine an idle physical page having the same size as the first virtual page as the second physical page, load the data content of the task corresponding to the target virtual page to the second physical page, allocate the second physical page to the task, and then execute step 607.

Step 605, if the page size of the target virtual page does not match the page size of the first virtual page, determining whether the virtual address corresponding to the target virtual page is located in the third sub virtual address space.

The target virtual page is not the first virtual page, but the second virtual page, and the processor may determine whether the target virtual page is in the third sub virtual address space, so as to determine whether the access behavior is legal.

If the target virtual page is in the third sub virtual address space, it indicates that the access target of the task is the second virtual page corresponding to the user space, and the processor has a corresponding access right when executing the task, so that step 606 may be executed, and if the target virtual page is not in the third sub virtual address space, i.e. in the fourth sub virtual address space, it indicates that the access target of the user task is the kernel space, and the processor does not have a corresponding access right when executing the user task, at this time, the processor may execute step 608.

Step 606, allocating a third physical page for the task if the virtual address is in a third sub-virtual address space.

Wherein the third physical page is the same as the page size of the second virtual page.

It is understood that the specific embodiment of step 606 is similar to that of step 604, and the third physical page corresponds to the second physical page of step 604, and will not be described herein.

Step 607, adding the mapping relationship between the physical page allocated to the task and the target virtual page to the page table.

After allocating the physical page to the task, the processor may write the mapping relationship between the physical page and the target virtual page to a corresponding page table for subsequent re-access by the task.

Step 608, return access failure information.

When the processor determines that the access target of the current user mode task is the kernel space, a message of access failure or a message of insufficient access authority can be returned to the task.

In the embodiment of the application, the access behavior is authenticated when the occurrence of the page fault is detected, and the corresponding physical page allocation is performed when the access target is determined to be the user space, so that the security of the access behavior can be improved.

Referring to fig. 7, fig. 7 is a schematic structural diagram of a computing device according to an embodiment of the present application. As shown in fig. 7, a computing device 700 provided by an embodiment of the present application includes a processor 710 and a memory 720. The processor 710 is an ARM architecture processor.

Wherein processor 710 may include one or more processing cores. The processor 710 utilizes various interfaces and lines to connect various portions of the computing device 700 and performs the methods provided by any one or more of the embodiments described above by executing or executing instructions, programs, code sets, or instruction sets stored in the memory 720 and invoking data stored in the memory 720. Alternatively, the processor 710 may be implemented in at least one hardware form of Digital Signal Processing (DSP), field-programmable gate array (FPGA), programmable logic array (programmable logic array, PLA). The processor 710 may integrate one or a combination of a CPU, an image processor (graphics processing unit, GPU) and a modem. It will be appreciated that the modem may not be integrated into the processor 710 and may be implemented solely by a single communication chip.

The memory 720 may include random access memory (random access memory, RAM) or read-only memory (ROM). Optionally, memory 720 includes a non-transitory computer-readable medium (non-transitory computer-readable storage medium). Memory 720 may be used to store instructions, programs, code, sets of codes, or sets of instructions. Memory 720 may include a memory program area. The storage program area may store instructions for implementing an operating system, instructions for implementing at least one function (such as a touch function, a sound playing function, an image playing function, etc.), instructions for implementing a method of an embodiment of the present application, and so on.

Processor 710 and memory 720 are communicatively coupled via a bus within computing device 700, which may be a peripheral component interconnect standard (PERIPHERAL COMPONENT INTERCONNECT, PCI) bus, or an extended industry standard architecture (extended industry standard architecture, EISA) bus, or the like. The bus may be classified as an address bus, a data bus, a control bus, etc. For ease of illustration, only one thick line is shown in fig. 7, but not only one bus or one type of bus.

In another embodiment of the present application, there is also provided a computer-readable storage medium having stored therein computer-executable instructions that, when executed by at least one processor of a device, perform the method flow described in any of the embodiments of fig. 3, 5 or 6 above.

In another embodiment of the present application, there is also provided a computer program product comprising computer-executable instructions stored in a computer-readable storage medium, at least one processor of the apparatus being capable of reading the computer-executable instructions from the computer-readable storage medium, the at least one processor executing the computer-executable instructions causing the apparatus to perform the method flow described in any of the embodiments of fig. 3,5 or 6 above.

Those of ordinary skill in the art will appreciate that the various illustrative elements and algorithm steps described in connection with the embodiments disclosed herein may be implemented as electronic hardware, or combinations of computer software and electronic hardware. Whether such functionality is implemented as hardware or software depends upon the particular application and design constraints imposed on the solution. Skilled artisans may implement the described functionality in varying ways for each particular application, but such implementation decisions should not be interpreted as causing a departure from the scope of the embodiments of the present application.

It will be clear to those skilled in the art that, for convenience and brevity of description, specific working procedures of the above-described systems, apparatuses and units may refer to corresponding procedures in the foregoing method embodiments, and are not repeated herein.

In the embodiments provided in the present application, it should be understood that the disclosed system, apparatus and method may be implemented in other manners. For example, the apparatus embodiments described above are merely illustrative, e.g., the division of the units is merely a logical function division, and there may be additional divisions when actually implemented, e.g., multiple units or components may be combined or integrated into another system, or some features may be omitted or not performed. Alternatively, the coupling or direct coupling or communication connection shown or discussed with each other may be an indirect coupling or communication connection via some interfaces, devices or units, which may be in electrical, mechanical or other form.

The units described as separate units may or may not be physically separate, and units shown as units may or may not be physical units, may be located in one place, or may be distributed on a plurality of network units. Some or all of the units may be selected according to actual needs to achieve the purpose of the solution of this embodiment.

In addition, each functional unit in each embodiment of the present application may be integrated in one processing unit, or each unit may exist alone physically, or two or more units may be integrated in one unit.

The functions, if implemented in the form of software functional units and sold or used as a stand-alone product, may be stored in a computer-readable storage medium. Based on such understanding, the technical solution of the embodiments of the present application may be embodied in essence or a part contributing to the prior art or a part of the technical solution, in the form of a software product stored in a storage medium, including several instructions for causing a computer device (which may be a personal computer, a server, or a network device, etc.) to perform all or part of the steps of the method described in the embodiments of the present application. The storage medium includes a U disk, a removable hard disk, a Read-Only Memory (ROM), a random access Memory (Random Access Memory, RAM), a magnetic disk, an optical disk, or other various media capable of storing program codes.

Claims

1. A memory allocation method, characterized in that the memory allocation method is applied to a computing device of an ARM architecture; the method comprises:

Configuring a page size of a first virtual page of a first virtual address space and a page size of a second virtual page of a second virtual address space; wherein the page size of the first virtual page is larger than the page size of the second virtual page;

Determine whether the task to be allocated memory belongs to a preset control group; the preset control group includes a first control group and a second control group; wherein the first control group is used to control the allocation of the first virtual page to the preset kernel mode task; the second control group is used to control the allocation of the first virtual page or the second virtual page to the preset user mode task;

In the case where the task belongs to the preset control group, allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs;

The first virtual address space includes a second sub-virtual address space; the second virtual address space includes a fourth sub-virtual address space;

In response to creating a first task, a first page table entry is added to a task_struct data structure of the first task; the first page table entry is used to indicate a page table base address of the second sub-virtual address space, and the second sub-virtual address space is a user state address space;

The second page table entry in the second page table base address register of the current task is added to the task_struct data structure of the first task to maintain the consistency of the kernel space when the processor executes different tasks, and avoid exceptions or failures when the processor accesses the kernel space, wherein the second page table base address register is used to store the page table base address of the second virtual address space; the second page table entry is used to indicate the page table base address of the fourth sub-virtual address space, the fourth sub-virtual address space is the kernel space shared by each task, the current task is the task being executed, the first task is the task executed after the current task is completed, and the fourth sub-virtual address space is the kernel state address space.

2. The method according to claim 1, characterized in that the first virtual address space comprises a first sub-virtual address space and a second sub-virtual address space; wherein the first sub-virtual address space is a kernel state address space;

In the case where the task belongs to the preset control group, allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs includes:

In the case where the task belongs to the first control group, allocating a first virtual page located in the first sub-virtual address space to the task;

In a case where the task belongs to the second control group, a first virtual page located in the second sub-virtual address space is allocated to the task.

3. The method according to claim 1, characterized in that the first virtual address space includes a first sub-virtual address space, and the second virtual address space includes a third sub-virtual address space; wherein the first sub-virtual address space is a kernel state address space; and the third sub-virtual address space is a user state address space;

In a case where the task belongs to the second control group, a second virtual page located in the third sub-virtual address space is allocated to the task.

4. The method according to any one of claims 1 to 3, characterized in that the method further comprises:

When the task does not belong to the preset control group, the second virtual page is allocated to the task.

5. The method according to claim 4, characterized in that the second virtual address space includes a fourth sub-virtual address space;

When the task does not belong to the preset control group, allocating the second virtual page to the task includes:

In the case that the task does not belong to the preset control group, determining whether the task is a kernel state task;

In the case that the task is the kernel mode task, a second virtual page located in the fourth sub-virtual address space is allocated to the task.

6. The method according to claim 1, characterized in that the second control group is used to control the allocation of the first virtual page to the preset user mode task; the first virtual address space includes a second sub-virtual address space; the second virtual address space includes a third sub-virtual address space; wherein the second sub-virtual address space and the third sub-virtual address space are user mode address spaces;

Before determining whether the task to be allocated memory belongs to a preset control group, the method further includes:

Determine whether the task is a target task, wherein the target task is a task that performs memory mapping MMAP;

The step of determining whether the task to be allocated memory belongs to a preset control group includes:

In the case where the task is the target task, determining whether the task belongs to the second control group;

In a case where the task belongs to the second control group, determining whether an offset in the MMAP request corresponding to the task matches a page size of the first virtual page;

In a case where the offset matches the page size of the first virtual page, determining whether the MMAP request is a fixed mapping, and a mapping address range of the MMAP request is located in the third sub-virtual address space;

When the MMAP request is not a fixed mapping, or the mapping address range is located in the second sub-virtual address space, the first virtual page located in the second sub-virtual address space is allocated to the task.

7. The method according to claim 2, characterized in that after allocating the first virtual page or the second virtual page to the task based on the control group to which the task belongs, the method further comprises:

Determine a first physical page accessed by the task based on a target virtual page and a page table, wherein the target virtual page is a virtual page indicated by a virtual address in an access request of the task;

In response to the first physical page being missing, determining whether a page size of the target virtual page matches a page size of the first virtual page;

In a case where the page size of the target virtual page matches the page size of the first virtual page, determining whether the virtual address corresponding to the target virtual page is located in the second sub-virtual address space;

In a case where the virtual address corresponding to the target virtual page is located in the second sub-virtual address space, allocating a second physical page to the task, wherein the second physical page has the same page size as the first virtual page;

A mapping relationship between the second physical page and the target virtual page is added to the page table.

8. The method according to claim 1, characterized in that after adding the second page table entry of the current task in the second page table base address register to the task_struct data structure of the current task, the method further comprises:

In response to switching the current task to a first task, updating a corresponding page table entry in a first page table base address register according to a first page table entry in a task_struct data structure of the first task; wherein the first page table base address register is used to store a page table base address of the first virtual address space;

According to the second page table entry of the current task in the second page table base address register, the task_struct data structure of the first task is updated.

9. A computing device, characterized in that the computing device comprises a memory and a processor; wherein the processor is an ARM architecture;

The memory is coupled to the processor;

The memory is used to store computer program instructions;

The processor is used to call the computer program instructions to execute the memory allocation method as described in any one of claims 1-8.